A method, apparatus and computer program product for performing asynchronous tasks

Abstract

The present disclosure provides a method and apparatus for performing asynchronous tasks, which can be implemented in a computing device that can be included in a combined processing device that can also include a general-purpose interconnect interface and other processing devices. The computing device interacts with the other processing devices to collectively complete a user-specified computing operation. The combined processing device can also include a storage device that is connected to the computing device and the other processing devices, respectively, for data of the computing device and the other processing devices.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of computers, and more specifically, to serial and parallel execution of tasks. BACKGROUND

[0002] In the current deep network training process, in order to accelerate the convergence speed of network training, some or even all training tasks (including computing tasks, communication tasks, control logic tasks, etc.) are usually assigned to a dedicated acceleration chip (such as GPU, MLU, TPU, etc.) for execution.

[0003] Network training tasks are assigned to an acceleration card by a CPU in an asynchronous manner, and there is a concept of a task queue in the acceleration card. Tasks on the same queue are executed in turn according to the order of assignment, so there is a dependency relationship between tasks on the same queue, and tasks on different queues can be executed concurrently according to the idle condition of hardware resources. However, the current training tasks are usually assigned to execute in only one queue, which inevitably affects the execution efficiency of the tasks. SUMMARY

[0004] An object of the present disclosure is to overcome the defects in the prior art that communication or computing resources cannot be fully utilized and fault tolerance is low.

[0005] According to a first aspect of the present disclosure, a method for executing asynchronous tasks is provided, comprising: dividing a total task in a task queue into a plurality of sub-tasks, each sub-task being in a different sub-task queue; executing the plurality of sub-tasks in parallel; and in response to the sub-tasks being executed, causing the total task to be executed.

[0006] According to a second aspect of the present disclosure, an apparatus for executing asynchronous tasks is provided, comprising: a division unit configured to divide a total task in a task queue into a plurality of sub-tasks, each sub-task being in a different sub-task queue; a sub-task execution unit configured to execute the plurality of sub-tasks in parallel; and an end unit configured to, in response to the sub-tasks being executed, cause the total task to be executed.

[0007] According to a third aspect of the present disclosure, a chip is provided, comprising the apparatus as described above.

[0008] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising the chip as described above.

[0009] According to a fifth aspect of the present disclosure, an electronic device is provided, comprising: one or more processors; and a memory having computer-executable instructions stored therein, which, when executed by the one or more processors, cause the electronic device to perform the method as described above.

[0010] According to a sixth aspect of the present disclosure, a computer-readable storage medium is provided, comprising computer-executable instructions that, when executed by one or more processors, perform the method as described above.

[0011] The technical solution of the present disclosure can distribute one total task into different sub-task queues, thereby accelerating the execution of the total task. In addition, even if the execution of a certain sub-task queue is erroneous, there is no need to re-execute all sub-tasks, thereby reducing the cost of fault tolerance or retransmission of the task, reducing the burden of task execution, and enabling fault tolerance or retransmission processing of the task without the user's awareness. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and other objects, features and advantages of the disclosed example embodiments will be more apparent from the following detailed description read in conjunction with the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example, and wherein like reference numerals refer to like parts throughout the several views, in which:

[0013] Figure 1a A flow chart of a method of executing asynchronous tasks according to an embodiment of the present disclosure is shown;

[0014] Figure 1b A schematic diagram of a task dispatch queue and a task execution queue according to an embodiment of the present disclosure is shown;

[0015] FIG. 2 shows forming a serial instruction queue into a plurality of parallel program instruction queues corresponding to parallel modules according to an embodiment of the present disclosure;

[0016] Figure 2a A flow chart of dividing a total task in a task queue into a plurality of sub-tasks according to an embodiment of the present disclosure is shown;

[0017] Figure 2b A schematic diagram of inserting an identifier in a queue according to an embodiment of the present disclosure is shown;

[0018] Figure 3 A schematic diagram of a queue according to another embodiment of the present disclosure is shown;

[0019] Figure 4 A schematic diagram of inserting a second waiting identifier modified according to an embodiment of the present disclosure is shown;

[0020] Figure 5 A schematic diagram of an apparatus for executing asynchronous tasks according to an embodiment of the present disclosure is shown;

[0021] Figure 6 A combined processing apparatus is shown;

[0022] Figure 7 An example board card is shown. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0024] It should be understood that the terms "first", "second", "third", and "fourth" and the like in the claims, the specification and the drawings of the present disclosure are used to distinguish different objects, rather than to describe a particular order. The terms "include" and "contain" used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or sets thereof.

[0025] It should also be understood that the terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments, and are not intended to limit the present disclosure. As used in the specification and claims of the present disclosure, unless otherwise clear from the context, the singular forms "a", "an" and "the" are intended to include plural forms. It should be further understood that the term "and / or" used in the specification and claims of the present disclosure means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0026] The embodiments of the present disclosure are described in detail above, and the principles and implementation modes of the present disclosure are described by applying specific examples. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. Meanwhile, changes or deformations made by those skilled in the art according to the principles of the present disclosure, based on the specific implementation modes and application scope of the present disclosure, are within the scope of protection of the present disclosure. In summary, the content of the specification should not be understood as a limitation of the present disclosure.

[0027] The current mainstream framework (such as Tensorflow, Pytorch) only uses one special communication queue (comm_queue) to perform communication tasks. When the communication library responsible for the communication task obtains the task, it usually directly issues the task in the framework's comm_queue or the internal_queue of the communication library for execution. For example, the communication library NCCL is responsible for communication between GPUs. Currently, communication tasks are executed in a queue, and when a communication task fails, the communication task needs to be re-executed from the beginning, thereby reducing the overall communication efficiency.

[0028] In the present disclosure, communication and computing tasks are usually issued as asynchronous tasks to different task queues (queues) on the acceleration chip (such as GPU, MLU) for execution. Asynchronous tasks on the same queue are executed in series according to the order of task issuance, and tasks on different queues can be executed concurrently.

[0029] It should be understood that although the above takes the communication task as an example, the task in this paper is not limited to the communication task, but also involves various tasks such as neural network operation or training.

[0030] Figure 1a A method flowchart for executing asynchronous tasks according to an embodiment of the present disclosure is shown; Figure 1b A schematic diagram of a task issuance queue and a task execution queue according to an embodiment of the present disclosure is shown.

[0031] As shown in FIG. 1, the method of the present disclosure includes: in operation S110, dividing a total task in a task queue into a plurality of sub-tasks, each sub-task being in a different sub-task queue; in operation S120, executing the plurality of sub-tasks in parallel; and in operation S130, in response to the sub-tasks being executed, causing the total task to be executed.

[0032] The above method will be described in detail below in conjunction with Figure 1b

[0033] In Figure 1b ​The task queue includes two types of queues, i.e., a task distribution queue LQ and a task execution queue PQ. The task distribution queue LQ can receive multiple tasks, such as tasks A, B, and C, and the tasks A, B, and C are combined in series when entering the task distribution queue LQ, and the execution order is A, B, and C. That is, when the task A is executed, the tasks B and C need to wait, and the task B can be executed only after the task A is executed; and the task C needs to wait until the task B is executed. Such a task execution manner cannot fully utilize the parallel running resources of the system, especially when the execution time of a certain task is particularly long or the communication data volume is particularly large, the execution of other tasks is obviously blocked, and thus the system performance is affected.

[0034] The tasks in the task distribution queue LQ can be regarded as a total task, and the total task can be divided into multiple parallel execution sub-tasks and placed in the task execution queue PQ for execution. When a total task is divided into multiple sub-tasks for parallel execution, the execution efficiency of the task can be significantly improved.

[0035] In the present disclosure, taking a total task B as an example, the total task B can be divided into multiple sub-tasks b1, b2, and the like. Here, two sub-tasks b1 and b2 are taken as an example for description. It should be noted that the number of sub-tasks can be other numbers, which depends on the execution capability of the sub-tasks and / or the size of the total task. For example, if the execution capability of each sub-task is strong, the total task can be divided into a smaller number of sub-tasks; and in the case of the same execution capability, if a certain total task is large, the total task can be divided into a larger number of sub-tasks.

[0036] When the total task B is divided into the sub-tasks b1 and b2, and the sub-tasks are placed in different execution queues PQ1 and PQ2, the two sub-tasks b1 and b2 can be executed in parallel in the execution queues PQ1 and PQ2.

[0037] The execution of the total task B and the sub-tasks needs to satisfy the following rules: 1. When the total task B has not started execution, the sub-tasks b1 and b2 should also be in a non-starting state; 2. When the total task B starts execution, the sub-tasks b1 and b2 should also start execution; 3. Other tasks (such as C) in the task distribution queue LQ after the task B need to wait until the task B is executed; 4. When the sub-tasks b1 and b2 are all executed, the total task B should also be executed.

[0038] Figure 2a A flowchart of dividing a total task in a task queue into multiple sub-tasks according to an embodiment of the present disclosure is shown.

[0039] According to one embodiment of the present disclosure, dividing one total task in a task queue into a plurality of sub-tasks S110 comprises: inserting a first write identifier allowing the total task to start execution in the queue S1110; inserting a first wait identifier prohibiting the sub-task to start execution in the sub-task queue S1120; and executing the first wait identifier to prohibit the sub-task to start execution when the first write identifier is not executed S1130.

[0040] Figure 2b A schematic diagram of inserting an identifier in a queue according to one embodiment of the present disclosure is shown. The specific embodiments are described in detail below with reference to the accompanying drawings. Figure 2b Figure 2a

[0041] First, in order to control the execution of task B, a write identifier, here exemplarily denoted as F0, needs to be inserted before the task to be executed. Only when the write identifier F0 is executed, or when the write identifier F0 is changed to allow the execution of the following task, the subsequent task B starts to be executed. If the write identifier F0 is not executed, the corresponding task does not start to be executed. The write identifier can be inserted by an atomic operation. An atomic operation refers to an operation that cannot be interrupted by a thread scheduling mechanism; once the operation starts, it runs to the end without any context switching in between.

[0042] Correspondingly, a wait identifier f0 can be inserted before each sub-task, which indicates that the sub-task after the wait identifier is prohibited to be executed. It needs to be understood that, Figure 2b The first write identifier F0 and the wait identifier f0 in the above description are named differently, but the write identifier F0 and the wait identifier f0 refer to the same identifier, to detect whether the same identifier is changed.

[0043] According to one embodiment of the present disclosure, executing the plurality of sub-tasks in parallel comprises: in response to the first write identifier being executed, turning off the first wait identifier, so as to execute the plurality of sub-tasks in parallel.

[0044] The write identifier F0 before the total task and the wait identifier f0 before the sub-task present a correlation relationship. Only when the write identifier F0 allows the execution of the subsequent total task, the wait identifier f0 ends and the corresponding sub-task starts to be executed. If the write identifier F0 does not allow the execution of the subsequent total task, the wait identifier f0 also makes the execution of the sub-task to be in a waiting state.

[0045] Figure 3 A schematic diagram of a queue according to another embodiment of the present disclosure is shown. ​​

[0046] According to one embodiment of this disclosure, a second waiting flag may be inserted into the total task queue to prevent the execution of other tasks following the total task.

[0047] like Figure 3 As shown, in the total task queue, a second waiting flag can be inserted after the first write flag. When the execution reaches the second waiting flag, it indicates that other total tasks after the current total task need to be in a waiting state. Other total tasks cannot start executing before the current total task has been completed.

[0048] As can be seen from the above description, when the first write flag F0 is executed in the allocation queue, the main task B corresponding to the first write flag F0 begins to execute. That is, the sub-tasks b1 and b2 of the main task B end their waiting state and begin to execute. After that, when the second waiting flag F1 in the allocation queue is executed, the other tasks in the allocation queue after the main task B enter the waiting state and do not execute when the main task B is executed.

[0049] Figure 4 A schematic diagram showing the modification of the second waiting identifier for insertion according to one embodiment of the present disclosure is shown.

[0050] According to one embodiment of this disclosure, whenever a sub-task is completed, the second waiting flag F1 is modified until all sub-tasks are completed; and in response to the completion of all sub-tasks, the second waiting flag F1 is modified to a waiting end flag, thereby making the total task complete.

[0051] Next, as Figure 4 As shown, each sub-task b1 and b2 is executed in the execution queue PQ. Each time a sub-task b1 or b2 completes, the second waiting flag F1 can be modified accordingly, for example, by incrementing it by one. The number of times the second waiting flag F1 is modified is the same as the number of times the sub-task is completed. Therefore, the second waiting flag F1 can initially be set with a target value. As sub-tasks b1 or b2 complete, the second waiting flag F1 gradually approaches this target value. When the second waiting flag F1 reaches the preset target value, it means that all sub-tasks b1 and b2 have been completed. It should be understood that there are many ways to modify the second waiting flag F1, and it is not limited to simply "incrementing" as described above. For example, it can be decremented by one each time it is modified, until the second waiting flag F1 is less than a predetermined threshold. This disclosure does not impose any limitations on how the second waiting flag is modified.

[0052] The "second waiting identifier F1 reaches the target value" described above can also be understood as an end-of-waiting identifier, which means that the current total task B has been executed and other tasks can be executed.

[0053] When the total task is divided into multiple sub-tasks, there can be multiple division methods. The total task can be randomly divided into multiple sub-tasks; the total task can be divided into a fixed number of sub-tasks; the total task can be divided into a number of sub-tasks corresponding to the number of processors responsible for each execution queue PQ, and so on.

[0054] According to one preferred embodiment of the present disclosure, one total task in the task queue can be divided into multiple execution time equivalent sub-tasks.

[0055] The execution time equivalence described above does not mean that the size of each sub-task itself is the same. For example, for 100M of calculation data, there are 4 processing cores participating in the operation. In theory, each processing core can participate in 25M of operation, so that the 4 processing cores will complete the operation in the same time, thereby reducing the total operation time as much as possible. However, if a processing core is involved in other operation work and its processing capacity is lower than that of other processing cores, the respective processing capacities of the 4 processing cores should be considered to allocate the corresponding tasks, so that each processing core completes the operation in the same or substantially the same time, which will help to shorten the overall running time of the total task. Therefore, the principle of dividing the total task into multiple sub-tasks is to divide according to the capacity of the resource executing the task, so that multiple resources can be equivalent in processing time.

[0056] According to one embodiment of the present disclosure, in response to the data amount of the total task exceeding a certain threshold, the total task is divided into multiple sub-tasks. It should be understood that the division of the total task into multiple sub-tasks also needs to consider the total amount of data involved in each task. If the total amount of data involved in a certain task is small, and the processing time of the total task is already less than the time of transmitting the data generated by executing the total task, it will not be necessary to further divide the total task. Similarly, if the time of reading the data required by the total task constitutes a bottleneck, i.e., the time of reading the data is greater than the time of executing the total task, it is also unnecessary to further divide the total task.

[0057] According to one embodiment of the present disclosure, the method of the present disclosure further comprises: in response to one or more sub-tasks having errors, re-running the sub-tasks with errors.

[0058] When multiple sub-tasks are executed in the execution queue PQ, errors can occur, such as errors in the operation results of the execution process, errors in data throughput, errors in data transmission, and the like. In the conventional scheme, if the total task is not divided into multiple sub-tasks, once an error occurs in the execution process of the task, the entire total task needs to be re-executed, which can seriously waste processing capability and cause the overall performance of the system to decrease.

[0059] In the scheme of the present disclosure, since the multiple sub-tasks are in different execution queues, the execution queues run independently and do not interfere with each other, so even if an error occurs in the execution process of a sub-task, it will not affect the execution of other sub-tasks. Therefore, if an error occurs in the execution of a sub-task, only the sub-task with the error needs to be re-run, and the entire sub-tasks or total task does not need to be re-run. When running the sub-task with the error, other queues can be in an idle state, or other sub-tasks can be executed simultaneously. Therefore, the case of dividing a total task into multiple parallel sub-tasks in the present disclosure can improve the utilization of system processing resources and improve processing efficiency.

[0060] According to one embodiment of the present disclosure, in response to one or more sub-tasks having errors, the sub-tasks with errors are further divided into multiple sub-tasks for parallel execution.

[0061] When a sub-task has an error and needs to be re-executed, the sub-task with the error can be added to the task allocation queue LQ as a new total task, and the sub-task with the error is further divided into multiple sub-tasks, and the sub-task with the error is re-executed in multiple parallel execution queues PQ. Further dividing the sub-task with the error into multiple sub-tasks for re-execution further improves the running efficiency of the system, so that even if an error occurs in the execution of a sub-task, the time and processing resources spent to correct the error are greatly reduced.

[0062] The above-mentioned tasks can be of many kinds, such as calculation operation tasks, multiplication operation tasks, convolution calculation tasks, weight calculation tasks, communication tasks, and the like. Therefore, according to the different tasks, the allocation queue can be a communication queue used in a deep learning framework, such as a dedicated communication queue (Comm_queue) used in Tensorflow, Pytorch, and the execution queue can be an execution queue in a communication library, such as an internal execution queue (Internal_queue) in the NCCL communication library. Figure 5A schematic diagram of an apparatus for executing an asynchronous task is shown, according to an embodiment of the present disclosure, the apparatus comprising: a division unit M510 configured to divide a total task in a task queue into a plurality of sub-tasks, each sub-task being in a different sub-task queue; a sub-task execution unit M520 configured to execute the plurality of sub-tasks in parallel; and an ending unit M530 configured to respond to completion of the sub-tasks, thereby causing the total task to be executed.

[0063] The present disclosure also provides a chip comprising the apparatus as shown above. Figure 5 The present disclosure also provides an electronic device comprising the chip as described above.

[0064] The present disclosure also provides an electronic device comprising: one or more processors; and a memory having computer-executable instructions stored therein, which, when executed by the one or more processors, cause the electronic device to perform the method as described above.

[0065] The present disclosure also provides an electronic device comprising: one or more processors; and a memory having computer-executable instructions stored therein, which, when executed by the one or more processors, cause the electronic device to perform the method as described above.

[0066] The present disclosure also provides a computer-readable storage medium comprising computer-executable instructions, which, when executed by one or more processors, perform the method as described above.

[0067] The technical solutions of the present disclosure can be applied to the field of artificial intelligence and implemented in an artificial intelligence chip. The chip can exist independently or be included in a computing device.

[0068] Figure 6 A combined processing apparatus 600 is shown, which comprises the computing device 602 described above, a general-purpose interconnection interface 604, and another processing device 606. The computing device according to the present disclosure interacts with the other processing device to jointly complete a user-specified operation. Figure 6 A schematic diagram of the combined processing apparatus is shown.

[0069] The other processing device comprises one or more of the following processor types: a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor, and a general-purpose / special-purpose processor. The number of processors included in the other processing device is not limited. The other processing device serves as an interface for external data and control for the machine learning operation device, including data transfer and basic control such as starting and stopping the machine learning operation device; the other processing device can also cooperate with the machine learning operation device to jointly complete an operation task.

[0070] A general-purpose interconnection interface is used to transmit data and control instructions between a computing device (including, for example, a machine learning operation device) and other processing devices. The computing device obtains required input data from other processing devices, writes the data to a storage device on the computing device chip; can obtain control instructions from other processing devices and write the control instructions to a control cache on the computing device chip; and can also read data in the storage module of the computing device and transmit the data to other processing devices.

[0071] Optionally, the structure can further include a storage device 608 connected to the computing device and the other processing devices, respectively. The storage device is used to store data of the computing device and the other processing devices, and is particularly suitable for data that cannot be completely stored in the internal storage of the computing device or the other processing devices.

[0072] The combined processing device can be used as an SOC system-on-chip of a device such as a mobile phone, a robot, a drone, or a video monitoring device, effectively reducing the core area of the control part, improving the processing speed, and reducing the overall power consumption. In this case, the general-purpose interconnection interface of the combined processing device is connected to some components of the device. Some components are, for example, a camera, a display, a mouse, a keyboard, a network card, and a Wi-Fi interface.

[0073] In some embodiments, the disclosure further discloses a chip packaging structure including the chip.

[0074] In some embodiments, the disclosure further discloses a board card including the chip packaging structure. Referring to Figure 7 which provides an exemplary board card. In addition to the chip 702, the board card can further include other supporting components, including but not limited to: a memory device 704, an interface device 706, and a control device 708.

[0075] The memory device is connected to the chip in the chip packaging structure through a bus, and is used to store data. The memory device can include a plurality of groups of storage units 710. Each group of storage units is connected to the chip through a bus. It can be understood that each group of storage units can be a DDR SDRAM (English: Double Data Rate SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory).

[0076] DDR does not need to increase the clock frequency to double the speed of SDRAM. DDR allows reading data on the rising and falling edges of the clock pulse. The speed of DDR is twice that of standard SDRAM. In an embodiment, the storage device can include 4 groups of the storage units. Each group of the storage units can include a plurality of DDR4 particles (chips). In an embodiment, the chip can include 4 72-bit DDR4 controllers inside, of which 64 bits are used for data transmission and 8 bits are used for ECC check. In an embodiment, each group of the storage units includes a plurality of double data rate synchronous dynamic random access memories arranged in parallel. DDR can transmit data twice in one clock cycle. A controller for controlling DDR is arranged in the chip to control the data transmission and data storage of each of the storage units.

[0077] The interface device is electrically connected with the chip in the chip package structure. The interface device is used to realize data transmission between the chip and an external device 712 (such as a server or a computer). For example, in an embodiment, the interface device can be a standard PCIE interface. For example, the data to be processed is transmitted by the server to the chip through the standard PCIE interface to realize data transfer. In another embodiment, the interface device can also be other interfaces, and the disclosure does not limit the specific forms of the above-mentioned other interfaces, as long as the interface unit can realize the switching function. In addition, the calculation result of the chip is still transmitted back to the external device (such as a server) by the interface device.

[0078] The control device is electrically connected with the chip. The control device is used to monitor the state of the chip. Specifically, the chip and the control device can be electrically connected through an SPI interface. The control device can include a micro controller unit (MCU). As the chip can include a plurality of processing chips, a plurality of processing cores or a plurality of processing circuits, it can drive a plurality of loads. Therefore, the chip can be in different working states such as heavy load and light load. Through the control device, the working states of the plurality of processing chips, the plurality of processing and / or the plurality of processing circuits in the chip can be regulated.

[0079] In some embodiments, the disclosure also discloses an electronic device or apparatus including the above-mentioned board card.

[0080] The electronic device or apparatus includes a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a server, a cloud server, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a vehicle, a household appliance, and / or a medical device.

[0081] The vehicle includes an airplane, a ship and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric lamp, a gas stove, an oil smoke exhauster; the medical device includes a nuclear magnetic resonance instrument, a B-ultrasonic instrument and / or an electrocardiograph.

[0082] It should be noted that, for the foregoing method embodiments, the purposes of simple description, they are all described as a series of action combinations, but those skilled in the art should know that the disclosure is not limited to the order of the described actions, because according to the disclosure, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily necessary for the disclosure.

[0083] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0084] In several embodiments provided by the disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely schematic. The division of the units is only a logical function division. There can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, optical, acoustic, magnetic or other forms.

[0085] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0086] In addition, each functional unit in each embodiment of the disclosure can be integrated into a processing unit, or each unit can exist physically independently, or two or more units can be integrated into one unit. The integrated unit can be realized in the form of hardware or in the form of a software program module.

[0087] The integrated unit, if realized in the form of a software program module and sold or used as an independent product, can be stored in a computer readable memory. Based on such understanding, when the technical solution of the disclosure can be embodied in the form of a software product, the computer software product is stored in a memory, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in various embodiments of the disclosure. The aforementioned memory includes: a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store program codes.

[0088] The above detailed the embodiments of the disclosure, and the principles and implementation manners of the disclosure were described by applying specific examples. The above embodiment descriptions are only used to help understand the method of the disclosure and its core idea; meanwhile, for those skilled in the art, according to the idea of the disclosure, the specific implementation manner and application range will have changes, and the above description should not be understood as a limitation on the disclosure.

Claims

1. A method for performing asynchronous tasks, comprising: Divide a total task in the task queue into multiple sub-tasks, with each sub-task in a different sub-task queue; The multiple sub-tasks are executed in parallel; In response to the completion of the sub-tasks, the overall task is thus completed; Dividing a main task in the task queue into multiple sub-tasks includes: Insert a first write flag that allows the overall task to begin execution into the task queue; Insert a first waiting flag that prevents the sub-task from starting execution into the sub-task queue; When the first write flag is not executed, the first wait flag is executed to prevent the sub-task from starting execution, wherein executing the multiple sub-tasks in parallel includes: In response to the first write flag being executed, the first wait flag is turned off, thereby executing the multiple sub-tasks in parallel.

2. The method according to claim 1, further comprising: A second waiting flag is inserted into the total task queue to prevent the execution of other tasks following the total task.

3. The method according to claim 2, further comprising: Each time a sub-task is completed, the second waiting flag is modified until all sub-tasks are completed. In response to the completion of all sub-tasks, the second waiting flag is modified to the waiting completion flag, thereby completing the execution of the total task.

4. The method according to claim 1, wherein a total task in the task queue is divided into multiple sub-tasks with equivalent execution time.

5. The method according to claim 1, wherein, In response to the total data volume of the total task exceeding a certain threshold, the total task is divided into multiple sub-tasks.

6. The method of claim 1, further comprising: In response to errors in one or more subtasks, rerun the subtask that encountered the error.

7. The method of claim 1, wherein in response to an error occurring in one or more subtasks, the subtask that has an error is further divided into multiple subtasks for parallel execution.

8. The method according to any one of claims 1-7, wherein, The task queue is a communication task queue.

9. An apparatus for performing asynchronous tasks, comprising: The partitioning unit is configured to divide a total task in the task queue into multiple sub-tasks, with each sub-task located in a different sub-task queue; The task execution unit is configured to execute the multiple sub-tasks in parallel; The termination unit is configured to respond to the completion of the sub-task, thereby causing the total task to be completed. The partitioning unit includes: An insertion unit is configured to insert a first write identifier into the task queue that allows the total task to begin execution. The insertion unit is further configured to insert a first waiting flag that prevents the sub-task from starting execution into the sub-task queue; The execution unit is configured to execute the first wait flag to prevent the sub-task from starting execution when the first write flag is not executed, wherein... The sub-task execution unit is configured to turn off the first waiting flag in response to the first write flag being executed, thereby executing the multiple sub-tasks in parallel.

10. A chip comprising the apparatus of claim 9.

11. An electronic device comprising the chip as claimed in claim 10.

12. An electronic device, comprising: One or more processors; as well as A memory storing computer-executable instructions that, when executed by the one or more processors, cause the electronic device to perform the method as described in any one of claims 1-8.

13. A computer-readable storage medium comprising computer-executable instructions that, when executed by one or more processors, perform the method as described in any one of claims 1-8.

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