A data synchronization method, system and related equipment

Abstract

The present invention provides a data synchronization method, which is applied to a heterogeneous computer system. The method can use a write request to complete the function of confirming data writing, thereby saving link delay and bandwidth overhead.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a data synchronization method, system and related equipment. Background Art

[0002] In traditional computer systems, when the host accesses device memory, the bus order is usually disrupted during cross-protocol conversion. In order to meet the "producer-consumer" model, the host needs to add additional operations to ensure that the "consumer" can use the data generated by the "producer" after it takes effect.

[0003] The traditional processing method is to use a non-posted readback operation (memory read) specified by the PCIE protocol to read the previous write request. When the previously written value is read, it means that the previous write operation has been completed. However, the delay of a readback operation on the communication link is the round-trip time from request to completion, which will greatly reduce the performance of the host (Central Processing Unit, CPU). Summary of the invention

[0004] The present application provides a data synchronization method, which can use a write request to complete the function of confirming data writing, saving link delay and bandwidth overhead.

[0005] In a first aspect, the present application provides a data synchronization method, including: receiving a first write request and a second write request sent by a host; writing the first write request and the second write request into a reverse lookup table, recording the processing status of the first write request and the second write request in the reverse lookup table; when the processing status of the second write request is completed, determining that the processing status of at least one first write request before the second write request is completed.

[0006] In one possible implementation, writing data of a second write request into a flag storage space includes: the second write request includes a first tag, the first tag is used to determine whether the first write request is executed, and when the processing status of the second write request is updated to completion, writing the first tag into the flag storage space.

[0007] In a possible implementation, writing the first tag into the flag storage space includes: the second write request also includes offset position information of writing the first tag, and writing the first tag into a corresponding position in the flag storage space according to the offset position information.

[0008] In a possible implementation, the method further includes: when it is determined that the flag storage space stores the first tag, performing a calculation based on data written by a write operation corresponding to a first write request before the second write request.

[0009] In a possible implementation manner, the method includes: determining request attributes of the first write request and the second write request according to target write addresses of the first write request and the second write request, respectively.

[0010] In a possible implementation, a corresponding write operation is performed according to the first write request, data is written into a memory in the device, and the processing status of the first write request in the reverse lookup table is updated to completion.

[0011] In one possible implementation, the first write request and the second write request include the same second tag, and determining whether the first write request before the second write request is completed includes: determining the first write request before the second write request according to the second tag, and determining that the processing status of the first write request is completed.

[0012] In a second aspect, the present application provides a heterogeneous computer system, which includes a host and a device; the host is used to send at least one write request to the device, and the write request includes a first write request and a second write request; the device is used to: receive the first write request and the second write request sent by the host; write the first write request and the second write request into a reverse lookup table, and record the processing status of the first write request and the second write request in the reverse lookup table; when the processing status of the second write request is completed, it is determined that the processing status of at least one first write request before the second write request is completed.

[0013] In a third aspect, the present application provides a storage device comprising a memory and a processor; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory to implement the method described in the first aspect or any possible implementation of the first aspect.

[0014] In a fourth aspect, the present application provides a computer-readable storage medium, including a program or instruction, which, when executed on a computer device, implements the method described in the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of an application scenario provided for an embodiment of the present application;

[0016] Figure 2 A flowchart of a data synchronization method provided in an embodiment of the present application;

[0017] Figure 3 A schematic diagram of the structure of a data synchronization device provided in an embodiment of the present application;

[0018] Figure 4 A reverse query representation is provided for an embodiment of the present application;

[0019] Figure 5A schematic diagram of a request content structure of a second write request provided in an embodiment of the present application;

[0020] Figure 6 A structural diagram of a combined processing device provided in an embodiment of the present application;

[0021] Figure 7 A schematic diagram of the structure of a board provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] It should be noted that the terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms of "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0024] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0025] First, the application scenario of the embodiment of the present application is introduced, see Figure 1The computer system shown includes a host 110 and a device 120, and the device 120 is connected to the host 110 through a PCIE (Peripheral Component Interconnect Express, PCIE) interface to realize data transmission between the host 110 and the device 120. Generally, the host 110 adopts the PCIE protocol and the device 120 adopts the AXI (Advanced eXtensible Interface) protocol. Therefore, when data is transmitted between the host 110 and the device 120, conversion between the protocols is required. For example, the write request sent by the host 110 to the device 120 is a forwarding transaction (Posted TLP). After reaching the device 120 through the PCIE link, it will first be converted into a bus protocol (Advanced eXtensible Interface, AXI) message in the module responsible for protocol conversion, and then the device 120 accesses the memory 121 according to the AXI protocol.

[0026] Posted TLP does not require a completed TLP return. In this way, the PCIE bus can end the current transaction before the TLP reaches the final destination, and no TLP is returned to determine whether the transaction is completed. The reorder function of the AXI protocol executes the received write requests out of order, that is, not in the order in which they are received. This may cause the data to be used by the processor 122 before it is written to the memory 121, which can easily cause calculation errors. The traditional processing method is to refresh the previous write operation through a Non-Posted read back operation of the PCIE. When the previously written value is read, it means that the previous write operation has been completed. However, this method has a large delay and will reduce the performance of the host.

[0027] In order to solve the above-mentioned technical problems, the present invention provides a data synchronization method. Figure 1 The device 120 in the embodiment can execute the data synchronization method to achieve data synchronization at the device 120 end. Figure 2 , Figure 2 A flowchart of a data synchronization method provided in an embodiment of the present application.

[0028] S201. The device 120 receives a first write request and a second write request sent by a host.

[0029] like Figure 1As shown, when the host 110 and the device 120 perform data transmission, the host 110 may send several write requests to the device 120, and each write request may include write data and a write address. The write address in the write request may point to the address space of the memory 121 on the device, and the write data may be data transmitted by the host 110 to the device 120. Among them, the write request includes a first write request and a second write request, and the first write request and the second write request may have different request attributes. For example, the first write request may be to write write data to the first storage space of the memory 121 in the device 120, thereby moving the write data from the host 110 to the device 120. The second write request may be to write tag data to the second storage space of the memory 121 in the device 120, and the tag data is used to implement the data synchronization function on the device 120 end.

[0030] Specifically, the device 120 sets a second storage space on the memory 121 as a data write space for the second write request. The base address of the second storage space may be a special address SYNC_ADDR, which may be used as a matching address for the second write request. The second storage space may be set in advance by a driver.

[0031] Optionally, when receiving a write request sent by the host, the device 120 may determine the request attribute of the write request according to the write address carried in the write request. If the write address of the write request is an address in the second storage space, the write request is determined to be a second write request. If the write address of the write request is an address in the first storage space, the write request is determined to be a first write request. The number of the first write request may be at least one.

[0032] S202: The device 120 writes the first write request and the second write request into a reverse lookup table, and records the processing status of the first write request and the second write request in the reverse lookup table.

[0033] In the present application embodiment, Figure 3 As shown, the device 120 may include a protocol conversion module 310 and a synchronization module 320. The protocol conversion module 310 on the device 120 receives a write request and performs protocol conversion from the PCIE protocol to the AXI protocol on the received write request. The write request converted by the protocol conversion module 310 is sent to the synchronization module 320. The synchronization module is used to determine the processing status of the write request associated with the first write request according to the processing status of the second write request.

[0034] Optionally, the synchronization module 320 may include a reordering cache unit 321 and a synchronization unit 322. The reordering cache unit 321 is used to receive the write request after the protocol conversion, and reorder the received write request according to the AXI protocol so that the at least one write request can be executed out of order. Specifically, the reordering cache unit 321 may store a reverse lookup table. When the reordering cache unit 321 of the synchronization module 320 receives a write request, the write request may be written into the reverse lookup table. Figure 4 , Figure 4 A reverse lookup table is provided for an embodiment of the present application. The reverse lookup table may include at least one entry, and each entry may include an index, an original ID, a processing status, and a request content.

[0035] Among them, the index is a new identification ID of the write request, which is used for out-of-order issuance and execution of the write request. The original identification (Original ID) is the identification when the host sends a write request to the device 120, which can be used to ensure that the completion message is returned in order. In the embodiment of the present disclosure, the write request sent by the host to the device 120 can be at least one, and at least one write request has an original identification. The original identification of at least one write request can be the same or different. In this embodiment, some of the at least one write request can have the same Original ID. According to the requirements of the AXI protocol, write requests with the same Original ID need to ensure that the completion message is returned in the order of receipt. The reordering cache unit of the present disclosure can establish a linked list based on the Original ID. For example, a linked list is established between devices with the same original identification Original ID, such as Figure 4 As shown by the arrow in the middle, the association relationship between the write requests with the same original identifier can be determined according to the linked list.

[0036] The third column of each entry in the reverse lookup table is used to record the processing status of the write request, which may include completed and uncompleted. The fourth column of each entry in the reverse lookup table is used to record the request content, specifically for recording the request content of the second request. Optionally, the request content of the second write request may be flag data, which may be used to determine whether the associated write request before the second write request has been completed. For example, the flag data may be a flag value set by the user. For details, please refer to the description below.

[0037] Optionally, the device 120 may perform a corresponding write operation according to a write request sent by the host. For example, the device 120 may store the write data of the first write request sent by the host in the first storage space according to the write address of the first write request, and then update the processing status of the first write request to completion and record it in the reverse lookup table. For another example, the device 120 may record the request content of the second write request in the reverse lookup table according to the second write request sent by the host, and after the second write request is executed, update the processing status of the second write request in the reverse lookup table to completion. Optionally, the content of the second write request may include a flag value. When receiving the second write request, the reordering cache unit 321 may record the flag value in the second write request to the corresponding position of the fourth column of the reverse lookup table.

[0038] S203: When the processing status of the second write request is completed, the device 120 determines that the processing status of at least one first write request before the second write request is completed.

[0039] When the device 120 executes the second write request, it can search the reverse lookup table according to the index of the write request to determine whether the processing status of the first write request before the second write request is completed. If the processing status of the second write request of the device 120 is completed, it indicates that the processing status of at least one of the first write requests before the second write request is completed, so that the data synchronization of the device 120 can be completed through the second write request.

[0040] In a possible implementation, the first write request may include an associated write request, and the associated write request may have the same original identifier as the second write request. The reordering cache unit 321 of the synchronization module 320 may establish an association relationship between the write requests with the same original identifier. The association relationship may be in the form of Figure 4 The linked list shown is shown in Figure 2. Figure 4 As shown, index0, index2, index3, index5, index7 and index125 are write requests with the same original ID, wherein index0, index2 and index5 are associated write requests, and index3, index7 and index125 are second write requests.

[0041] The above method may further include: when the device 120 determines, according to the association relationship, that the execution of the association request before the second write request is completed, determining that the processing status of the second write request is completed.

[0042] Specifically, when the write request of a certain layer entry is completed, a completion message will be returned to the reverse lookup table of the reorder cache unit 321 for temporary storage, and then the execution status of the previous write request with the same Original ID needs to be searched forward according to the established linked list. If all the previous write requests with the same Original ID of the entry are completed, it means that the write request of the entry can return the completion message to the protocol conversion module 310, otherwise the write request needs to wait for the previous write request with the same Original ID to be completed.

[0043] See also Figure 4 , the associated write requests index0 and index2 are executed, and the processing status of the corresponding second write request index3 is updated to completed. The device 120 detects that the processing status of the second write request index3 is completed, indicating that the first write requests index0 and index2 before the second write request index3 are all completed.

[0044] As an implementation method, the content of the second write request may include a flag value, and a flag storage space for storing the flag value may be set on the device 120. When the device 120 reads that the flag value in the flag storage space is updated, it can be determined that the device 120 has received the data transmitted by the host.

[0045] Specifically, the method further includes: when the processing status of the second write request is updated to completion, writing the flag value into a flag storage space, wherein the flag storage space is used to store the flag value.

[0046] Specifically, when the synchronization unit 322 of the synchronization module 310 detects that the processing status of the second write request of a certain layer entry in the reverse lookup table is completed, it means that the associated write requests before the second write request have all been completed. At this time, the synchronization unit 322 of the synchronization module 320 can write the request content of the second request into the flag storage space according to the information recorded in the reverse lookup table. Optionally, the synchronization unit 322 can write the flag value recorded in the fourth column of the reverse lookup table into the specified position of the flag storage space.

[0047] Further optionally, the request content of the second write request may include offset position information flag_offset and flag value flag_value. For the request content structure of the second write request, see Figure 5 . Among them, flag_offset is the offset position information when writing data; flag_value can be custom data pre-set by the user. In the embodiment of the present disclosure, by carrying the offset position information in the second write request, multiple second write requests can be supported, thereby expanding the application scenario of the method of the present disclosure.

[0048] Optionally, the request content can be 32-bit data, the upper 16 bits are the offset position information of the written data, and the lower 16 bits are the flag value. The request content can also be extended to 64 bits or more, and the extended offset bits can be used to support writing more flag values ​​of the second write request in the flag storage space.

[0049] Specifically, a flag storage space can be set on the device 120, and the base address of the flag storage space can be FLAG_ADDR_BASE. The synchronization module 320 on the device 120 can determine the write position of the flag value according to the base address of the flag storage space and the above-mentioned offset position information, and write the flag value to the specific write position of the flag storage space.

[0050] For example, see Figure 4 , the processing status of the second write request index3 is completed, indicating that the associated write requests corresponding to index0 and index2 before the second write request index3 are all executed. According to the offset position information flag_offset in the request content of the second write request index3 and the base address of the flag storage space, the flag value flag_value of the second write request index3 is written to the corresponding position of the flag storage space.

[0051] As an implementation method, when the device 120 detects that the specified position in the flag storage space is updated to the flag value flag_value of the second write request, the device 120 can use the data written to the memory 121 by the first write request to perform calculations. Specifically, the processor of the device 120 can read the flag storage space periodically, such as accessing the flag storage space in a polling manner. When the processor on the device 120 determines that the specified position in the flag storage space is updated to the flag value flag_value of the second write request, it can indicate that the first write request associated with the second write request before the second write request has been executed, that is, the write data in the first write request associated with the second write request (that is, the associated write request mentioned above) has been stored in the first storage space of the memory 121, so that the processor on the device 120 can perform calculations based on the corresponding write data obtained from the first storage space.

[0052] Optionally, the processor on the device 120 may include a first processor and a second processor, the first processor may be a general-purpose processor (such as an ARM core, etc.), and the second processor may be a GPU or an artificial intelligence processor, etc. At this time, when the first processor detects that the specified position in the flag storage space is updated to the flag value flag_value of the second write request, it indicates that the write data in the first write request associated with the second write request (i.e., the associated write request above) has been stored in the first storage space of the memory 121, so that the second processor on the device 120 can perform operations based on the corresponding write data obtained from the first storage space.

[0053] By executing a second write request in the device to replace the original read-back operation, the completion of the first write request is determined, ensuring that the processor uses the data written into the memory 121 after the write operation corresponding to the first write request is completed, thereby saving link loss and bandwidth loss.

[0054] The above mainly introduces the scheme of the embodiment of the present application from the perspective of the execution process on the method side. It is understandable that, in order to realize the above functions, the electronic device includes a hardware structure and / or software module corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments provided herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

[0055] like Figure 1 As shown, an embodiment of the present disclosure provides a heterogeneous computer system, the system comprising a host and a device. The host is used to send at least one write request to the device, the write request comprising a first write request and a second write request. The device is used to: receive the first write request and the second write request sent by the host; write the first write request and the second write request into a reverse lookup table, and record the processing status of the first write request and the second write request in the reverse lookup table; and when the processing status of the second write request is completed, determine that the processing status of at least one of the first write requests before the second write request is completed.

[0056] See also Figure 3 The device 120 includes a protocol conversion module 310 and a synchronization module 320. The synchronization module 320 may include a reordering buffer unit 321 and a synchronization unit 322.

[0057] The protocol conversion module 310 is used to receive the first write request and the second write request sent by the host, and perform protocol conversion on the received write request and send it to the synchronization module 320. Specifically, the protocol conversion module 310 can send the write request after protocol conversion to the reordering buffer unit 321.

[0058] The reordering cache unit 321 is used to receive the write request after the protocol conversion, write the write request into a reverse lookup table, and reorder the received write request according to the AXI protocol so that at least one write request can be executed out of order. After the write request is executed, the reordering cache unit 321 receives the completion message of the write request, temporarily stores the completion message in the reverse lookup table, and records the processing status of the write request in the reverse lookup table. Specifically, the reordering cache unit 321 can store a reverse lookup table. When the reordering cache unit 321 of the synchronization module 320 receives a write request, the write request can be written into the reverse lookup table. Figure 4 , Figure 4 A reverse lookup table is provided for an embodiment of the present application. The reverse lookup table may include at least one entry, and each entry may include an index, an original ID, a processing status, and a request content.

[0059] Among them, the index is a new identification ID of the write request, which is used for out-of-order issuance and execution of the write request. The original identification (Original ID) is the identification when the host sends a write request to the device 120, which can be used to ensure that the completion message is returned in order. In the embodiment of the present disclosure, the write request sent by the host to the device 120 can be at least one, and at least one write request has an original identification. The original identification of at least one write request can be the same or different. In this embodiment, some of the at least one write request can have the same Original ID. According to the requirements of the AXI protocol, write requests with the same Original ID need to ensure that the completion message is returned in the order of receipt. The reordering cache unit of the present disclosure can establish a linked list based on the Original ID. For example, a linked list is established between devices with the same original identification Original ID, such as Figure 4 As shown by the arrow in the middle, the association relationship between write requests with the same original identifier can be determined based on the linked list. The third column of each entry in the reverse lookup table is used to record the processing status of the write request, which can include completed and uncompleted. The fourth column of each entry in the reverse lookup table is used to record the request content, specifically for recording the request content of the second request.

[0060] Optionally, the device 120 may perform a corresponding write operation according to a write request sent by the host. For example, the device 120 may store the write data of the first write request sent by the host in the first storage space according to the write address of the first write request, and then update the processing status of the first write request to completion and record it in the reverse lookup table. For another example, the device 120 may record the request content of the second write request in the reverse lookup table according to the second write request sent by the host, and after the second write request is executed, update the processing status of the second write request in the reverse lookup table to completion. Optionally, the content of the second write request may include a flag value. When receiving the second write request, the reordering cache unit 321 may record the flag value in the second write request to the corresponding position of the fourth column of the reverse lookup table.

[0061] The synchronization unit 322 is used to monitor that the processing status of the second write request of a certain layer entry in the reverse lookup table is completed, indicating that the associated write requests before the second write request have all been completed, and write the request content of the second request into the flag storage space according to the information recorded in the reverse lookup table.

[0062] As an implementation method, the content of the second write request may include a flag value, and a flag storage space for storing the flag value may be set on the device 120. When the device 120 reads that the flag value in the flag storage space is updated, it can be determined that the device 120 has received the data transmitted by the host.

[0063] Specifically, when the synchronization unit 322 of the synchronization module 310 detects that the processing status of the second write request of a certain layer entry in the reverse lookup table is completed, it means that the associated write requests before the second write request have all been completed. At this time, the synchronization unit 322 can write the request content of the second request into the flag storage space according to the information recorded in the reverse lookup table. Optionally, the synchronization unit 322 can write the flag value recorded in the fourth column of the reverse lookup table into the specified position of the flag storage space.

[0064] Further optionally, the request content of the second write request may include offset position information flag_offset and flag value flag_value. For the request content structure of the second write request, see Figure 5 . Among them, flag_offset is the offset position information when writing data; flag_value can be custom data pre-set by the user. In the embodiment of the present disclosure, by carrying the offset position information in the second write request, multiple second write requests can be supported, thereby expanding the application scenario of the method of the present disclosure.

[0065] Combined here Figure 1 and Figure 3, the device 120 also includes a processor and a memory. As an implementable embodiment, when the synchronization unit 322 detects that the specified position in the flag storage space is updated to the flag value flag_value of the second write request, the processor on the device 120 can use the data written to the memory 121 by the first write request to perform calculations. Specifically, the processor of the device 120 can read the flag storage space regularly, such as accessing the flag storage space in a polling manner. When the processor on the device 120 determines that the specified position in the flag storage space is updated to the flag value flag_value of the second write request, it can indicate that the first write request associated with the second write request has been executed, that is, the write data in the first write request associated with the second write request (that is, the associated write request above) has been stored in the first storage space of the memory 121, so that the processor on the device 120 can perform calculations based on the corresponding write data obtained from the first storage space.

[0066] Optionally, the processor on the device 120 may include a first processor and a second processor, the first processor may be a general-purpose processor (such as an ARM core, etc.), and the second processor may be a GPU or an artificial intelligence processor, etc. At this time, when the first processor detects that the specified position in the flag storage space is updated to the flag value flag_value of the second write request, it indicates that the write data in the first write request associated with the second write request (i.e., the associated write request above) has been stored in the first storage space of the memory 121, so that the second processor on the device 120 can perform operations based on the corresponding write data obtained from the first storage space.

[0067] The embodiment of the present application can divide the electronic device into functional units according to the above method example. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one processing unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units. It should be noted that the division of units in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0068] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute part or all of the steps of any method recorded in the above method embodiments.

[0069] The present application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute some or all of the steps of any method described in the above method embodiment. The computer program product may be a software installation package.

[0070] Figure 6 is a structural diagram showing a combined processing device 600 according to an embodiment of the present disclosure. Figure 6 As shown in FIG. 6 , the combined processing device 600 includes a computing processing device 604, an interface device 604, other processing devices 606, and a storage device 607. According to different application scenarios, the computing processing device may include one or more computing devices 610, which may be configured to execute the above-mentioned Figure 2 The combined processing device may be the above-mentioned device, and the combined processing device may be connected to the host through the interface device 604 .

[0071] In different embodiments, the computing and processing device disclosed herein may be configured to perform user-specified operations. In an exemplary application, the computing and processing device may be implemented as a single-core artificial intelligence processor or a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device may be implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core. When multiple computing devices are implemented as an artificial intelligence processor core or a partial hardware structure of an artificial intelligence processor core, with respect to the computing and processing device disclosed herein, it may be regarded as having a single-core structure or a homogeneous multi-core structure.

[0072] In an exemplary operation, the computing processing device of the present disclosure can interact with other processing devices through an interface device to jointly complete the operation specified by the user. Depending on the implementation, other processing devices of the present disclosure may include one or more types of processors in general and / or special processors such as a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence processor, etc. These processors may include but are not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, only with respect to the computing processing device of the present disclosure, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0073] In one or more embodiments, the other processing device can serve as an interface between the computing device disclosed herein (which can be embodied as an artificial intelligence such as a computing device related to neural network computing) and external data and control, and perform basic controls including but not limited to data handling, starting and / or stopping the computing device, etc. In other embodiments, the other processing device can also cooperate with the computing device to jointly complete computing tasks.

[0074] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it into a storage device (or memory) on the computing and processing device chip. Further, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them into a control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0075] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0076] In some embodiments, the present disclosure also discloses a neural network chip (e.g. Figure 7 In one implementation, the chip is a system on chip (SoC) and integrates one or more Figure 6 The chip can be connected to an external interface device (such as Figure 7 The external interface device 704 shown in the figure is connected to other related components. The related components may be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as a video codec) and / or interface modules (such as a DRAM interface) may be integrated on the chip. In some embodiments, the present disclosure further discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure further discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 6 The board is described in detail.

[0077] Figure 7 FIG. 2 is a schematic diagram showing the structure of a board 700 according to an embodiment of the present disclosure. Figure 7 As shown in , the board includes a storage device 704 for storing data, which includes one or more storage units 710. The storage device can be connected and data can be transmitted with the control device 707 and the chip 702 described above by means of, for example, a bus. Further, the board also includes an external interface device 706, which is configured for data relay or switching between the chip (or the chip in the chip packaging structure) and an external device 712 (such as a server or computer, etc.). For example, the data to be processed can be transmitted to the chip by the external device through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0078] In one or more embodiments, the control device in the disclosed board may be configured to regulate the state of the chip. To this end, in an application scenario, the control device may include a microcontroller unit (MCU) to regulate the working state of the chip.

[0079] According to the above combination Figure 6 and Figure 6 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0080] According to different application scenarios, the electronic equipment or device disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, IoT terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, transportation, household appliances, and / or medical equipment. The transportation includes airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging, ultrasound machines and / or electrocardiographs. The electronic equipment or device disclosed herein may also be applied to the Internet, IoT, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, and medical fields. Further, the electronic equipment or device disclosed herein may also be used in cloud, edge, and terminal applications related to artificial intelligence, big data, and / or cloud computing. In one or more embodiments, electronic devices or devices with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or devices with low power consumption can be applied to terminal devices and / or edge devices (such as smart phones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0081] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teaching of the present disclosure, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present disclosure may be regarded as optional embodiments, i.e., the actions or modules involved therein may not necessarily be necessary for the implementation of one or some of the schemes of the present disclosure. In addition, depending on the different schemes, the present disclosure also has different focuses on the description of some embodiments. In view of this, those skilled in the art may appreciate the parts that are not described in detail in a certain embodiment of the present disclosure, and may also refer to the relevant descriptions of other embodiments.

[0082] In terms of specific implementation, based on the disclosure and teaching of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented by other methods not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article divides them on the basis of considering logical functions, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. In terms of the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0083] In the present disclosure, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed on multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

[0084] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the scheme of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0085] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPU, GPU, FPGA, DSP and ASIC, etc. Further, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage medium or magneto-optical storage medium, etc.), which can be, for example, a variable resistive memory (Resistive Random Access Memory, RRAM), a dynamic random access memory (Dynamic Random Access Memory, DRAM), a static random access memory (Static Random Access Memory, SRAM), an enhanced dynamic random access memory (Enhanced Dynamic Random Access Memory, EDRAM), a high bandwidth memory (High Bandwidth Memory, HBM), a hybrid memory cube (Hybrid Memory Cube, HMC), ROM and RAM, etc.

[0086] In the above embodiments, the description of each embodiment has its own emphasis. For the part not described in detail in a certain embodiment, please refer to the relevant description of other embodiments. The technical features of the above embodiments can be combined arbitrarily. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The foregoing content can be better understood in accordance with the following terms:

[0088] Clause A1, a data synchronization method, characterized in that the method comprises:

[0089] receiving a first write request and a second write request sent by the host;

[0090] Writing the first write request and the second write request into a reverse lookup table, and recording the processing status of the first write request and the second write request in the reverse lookup table;

[0091] When the processing status of the second write request is completed, it is determined that the processing status of at least one of the first write requests before the second write request is completed.

[0092] Clause A2, according to the method described in Clause A1, the first write request includes an associated write request, the associated write request and the second write request have the same original identifier; the reverse lookup table records the association relationship between the associated write request and the second write request; the method further includes:

[0093] When it is determined according to the association relationship that the associated request before the second write request is completed, the processing status of the second write request is determined to be completed.

[0094] Clause A3, according to the method of clause A1 or A2, the second write request includes a flag value; the method further comprising:

[0095] When the processing status of the second write request is updated to completion, the flag value is written into a flag storage space, wherein the flag storage space is used to store the flag value.

[0096] Clause A4, according to the method of clause A3, the second write request also includes offset position information; and the writing the flag data into the flag storage space includes:

[0097] The mark data is written into a corresponding position in the mark storage space according to the offset position information.

[0098] Clause A5. A method according to clause A2 or A3, further comprising:

[0099] When it is determined that the flag storage space stores the flag value, an operation is performed based on the data written by the write operation corresponding to the associated write request before the second write request.

[0100] Clause A6. A method according to any one of clauses A1 to A4, further comprising:

[0101] According to the write addresses of the first write request and the second write request, it is determined whether the received write request is the first write request or the second write request.

[0102] Clause A7, a method according to clause A1, comprising:

[0103] The write data of the first write request is written into a memory in the device according to the first write request, and the processing status of the first write request in the reverse lookup table is updated to completion.

[0104] Clause B1, a heterogeneous computer system, the system comprising a host and a device;

[0105] The host is used to send at least one write request to the device, where the write request includes a first write request and a second write request;

[0106] The device is used for:

[0107] receiving a first write request and a second write request sent by the host;

[0108] Writing the first write request and the second write request into a reverse lookup table, and recording the processing status of the first write request and the second write request in the reverse lookup table;

[0109] When the processing status of the second write request is completed, it is determined that the processing status of at least one of the first write requests before the second write request is completed.

[0110] Clause C1, a device comprising a memory and a processor;

[0111] The memory is used to store computer programs;

[0112] The processor is used to execute a computer program stored in the memory to implement a method as described in any one of clauses A1-A7.

[0113] Item D1, a computer-readable storage medium comprising a program or instructions, which, when executed on a computer device, implements the method as described in any one of Items A1-A7.

[0114] The embodiments of the present disclosure are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present disclosure. At the same time, changes or deformations made by those skilled in the art based on the ideas of the present disclosure, the specific implementation methods and the scope of application of the present disclosure, all belong to the scope of protection of the present disclosure. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A data synchronization method, characterized in that: The method is applied to a heterogeneous computer system, the system comprising a host and a device, and the method comprises: receiving a first write request and a second write request sent by the host; Writing the first write request and the second write request into a reverse lookup table, and recording the processing status of the first write request and the second write request in the reverse lookup table; When the processing status of the second write request is completed, determining that the processing status of at least one of the first write requests before the second write request is completed; The second write request includes a flag value; and the method further includes: When the processing status of the second write request is updated to completed, the flag value is written into a flag storage space, wherein the flag storage space is used to store the flag value; the flag storage space stores the flag value of the second write request to indicate that the write data in the first write request associated with the second write request has been stored in the memory.

2. The method according to claim 1, characterized in that The first write request includes an associated write request, and the associated write request and the second write request have the same original identifier; The reverse lookup table records the association relationship between the associated write request and the second write request; The method further comprises: When it is determined according to the association relationship that the associated request before the second write request is completed, the processing status of the second write request is determined to be completed.

3. The method according to claim 1, characterized in that The second write request further includes offset position information; and the writing of the flag data into the flag storage space includes: The mark data is written into a corresponding position in the mark storage space according to the offset position information.

4. The method according to claim 1 or 2, characterized in that: The method further comprises: When it is determined that the flag storage space stores the flag value, an operation is performed according to the write data corresponding to the associated write request before the second write request.

5. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: According to the write addresses of the first write request and the second write request, it is determined whether the received write request is the first write request or the second write request.

6. The method according to claim 1, characterized in that include: The write data of the first write request is written into a memory in the device according to the first write request, and the processing status of the first write request in the reverse lookup table is updated to completion.

7. A heterogeneous computer system, characterized in that: The system includes a host and a device; The host is used to send at least one write request to the device, where the write request includes a first write request and a second write request; The device is used for: receiving a first write request and a second write request sent by the host; Writing the first write request and the second write request into a reverse lookup table, and recording the processing status of the first write request and the second write request in the reverse lookup table; When the processing status of the second write request is completed, determining that the processing status of at least one of the first write requests before the second write request is completed; The second write request includes a flag value; and the device is further configured to: When the processing status of the second write request is updated to completed, the flag value is written into a flag storage space, wherein the flag storage space is used to store the flag value; the flag storage space stores the flag value of the second write request to indicate that the write data in the first write request associated with the second write request has been stored in the memory.

8. A device, characterized in that including memory and processor; The memory is used to store computer programs; The processor is configured to execute a computer program stored in a memory to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The method comprises a program or an instruction, and when the program or the instruction is executed on a computer device, the method according to any one of claims 1 to 6 is implemented.

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