Chip input / output module arrangement method, device and storage medium

Abstract

A chip input / output module arrangement method, device, and storage medium are disclosed. The method first determines one or more connected areas at the chip's perimeter for arranging input / output modules, as well as solder bumps on the chip that require GPIO outputs. The method then automatically places the input / output modules within the connected areas, including placing module groups in a one-to-one correspondence with the solder bumps adjacent to the perimeter. The disclosed embodiments also provide a device for implementing the method. The disclosed embodiments can adaptively implement automatic arrangement of chip input / output modules, ensuring that the chip's input / output modules meet output rationality and signal integrity requirements, greatly improving arrangement efficiency.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, chip technology, and more specifically, to a chip input / output module arrangement method, device, and storage medium. Background Art

[0002] With the development of Moore's Law, the chip scale is further reduced, which puts higher requirements on chip design. The chip input and output module (IO: Input and Output) is an important component in chip design. It is mainly used to input the external signals required for chip operation and output the signals processed by the chip to the outside world. Some other modules are used to assist in completing this work. Common chip IO includes general purpose input and output modules (GPIO: General Purpose Input / Output), power supply modules, power control modules, termination modules, corner modules, general fill modules, etc. Since chip IO is usually placed at the edge of the chip, when the chip process develops to below 10nm, the space available for chip IO arrangement is further reduced, which brings challenges to the arrangement of chip IO. The difficulty of chip IO arrangement is further increased. The arrangement plan needs to be repeatedly adjusted, which is labor-intensive and prone to human errors. The design cost is high and the design cycle is long. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a chip input / output module arrangement method, including:

[0005] Determine one or more connectivity areas around the chip for arranging input and output modules, and the solder bumps on the chip that need to be routed through the GPIO.

[0006] Automatically placing input and output modules in the connected area includes: placing module groups in a one-to-one correspondence with the solder bumps of adjacent boundaries, wherein, in the process of sequentially placing the module groups along a set arrangement direction, by adding or reducing power supply modules in the module groups, the position deviation of the GPIO in each module group and the solder bump corresponding to the module group is maintained within an allowable range.

[0007] An embodiment of the present disclosure further provides a chip input-output module arrangement device, comprising a processor and a memory storing a computer program, wherein when the processor executes the computer program, it can implement the chip input-output module arrangement method as described in any embodiment of the present disclosure.

[0008] The chip input / output module arrangement method and apparatus of the above-mentioned embodiment of the present disclosure automatically places input / output modules in a connected area, wherein module groups are placed in a one-to-one correspondence with solder bumps on adjacent boundaries. By adding or reducing power supply modules within the module groups, the position deviation between the GPIO in each module group and the solder bump corresponding to the module group is kept within an allowable range. Automatic arrangement of chip input / output modules can be adaptively achieved, so that the chip input / output modules meet the requirements of line rationality and signal integrity, greatly improving arrangement efficiency and making it convenient and quick.

[0009] An embodiment of the present disclosure further provides a non-volatile computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, can implement the chip input-output module arrangement method as described in any embodiment of the present disclosure.

[0010] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to provide an understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation to the technical solutions of the present disclosure.

[0012] Figure 1 This is a flow chart of a chip input and output module arrangement method according to an embodiment of the present disclosure;

[0013] Figure 2 Schematic diagram of the arrangement of connected areas and input / output modules on a chip according to an embodiment of the present disclosure;

[0014] Figure 3 This is a schematic diagram of an arrangement result obtained according to the chip input and output module arrangement method of an embodiment of the present disclosure;

[0015] Figure 4 yes Figure 3 A partial enlarged view of

[0016] Figure 5 This is a flow chart of a chip input and output module arrangement method according to an embodiment of the present disclosure;

[0017] Figure 6 This is a schematic diagram of a chip input / output module arrangement device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure.

[0019] In the description of the present disclosure, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment described as "exemplary" or "for example" in the present disclosure should not be interpreted as being more preferred or advantageous than other embodiments. "And / or" in this article is a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. "Multiple" means at least two, including two or more than two. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present disclosure, words such as "first" and "second" are used to distinguish between identical or similar items with basically the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not limit them to be necessarily different.

[0020] When describing representative exemplary embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0021] An embodiment of the present disclosure provides a chip input and output module arrangement method, which can realize the automatic arrangement of input and output modules. Figure 1 As shown, the method includes:

[0022] Step 110, determining one or more connection areas at the periphery of the chip for arranging input and output modules, and solder bumps on the chip that need to be connected through GPIO output lines;

[0023] Step 120, automatically placing input and output modules in the connected area, includes: placing module groups in a one-to-one correspondence with the solder bumps of adjacent boundaries, wherein, in the process of placing the module groups sequentially along the set arrangement direction, by adding or reducing power supply modules in the module groups, the position deviation of the GPIO in each module group and the solder bump corresponding to the module group is kept within an allowable range.

[0024] In the embodiment of the present disclosure, after the chip size is determined, the remaining space is determined based on the estimated position and size of each functional module on the chip. Then, the chip IO is arranged at the chip boundary within the remaining space. Figure 2 In one example, a chip 100 has three functional modules: a first functional module 01, a second functional module 102, and a third functional module 103. These modules each occupy a portion of the perimeter of the chip's backside. Except for the perimeter areas occupied by the functional modules, all other areas can be used to arrange input and output modules. In this example, the perimeter of the chip is divided into three strip-shaped connected areas: a first connected area 104, a second connected area 105, and a third connected area 106. The first connected area 104 extends along the bottom and left edges of the chip, the second connected area 105 extends along the left and top edges of the chip, and the third connected area 106 extends along the top, right, and bottom edges of the chip. It should be noted that the placement of the functional modules on the chip can vary, and thus the number, shape, and size of the connected areas along the perimeter of the chip used to arrange the input and output modules can also vary, and this disclosure is not limited to this.

[0025] exist Figure 2 In the figure, the circles represent the solder bumps (Bumps) 4 of the chip pins, among which some bumps 4 that need to be routed out from the GPIO are cross-hatched. These bumps 4 that need to be routed out from the GPIO include the bumps 4 near the chip boundary, but not all bumps 4 near the chip boundary need to be routed out from the GPIO. There are three bumps 4 at the corners in the figure that do not need to be routed out. In the example shown in the figure, most of the bumps 4 are arranged in an array, among which the two rows of bumps 4 near the upper boundary and the two rows of bumps 4 near the lower boundary, except for the bumps 4 at the corners, need to be routed out from the GPIO. The two rows of bumps 4 near the left boundary and the two rows of bumps 4 near the right boundary, except for the bumps 4 at the corners, also need to be routed out from the GPIO. In other words, the bumps 4 that need to be routed out from the GPIO are located in two rows and two columns near the boundary, among which the two bumps 4 at the same position near the boundary overlap in the route direction, and the routes of these two bumps 4 need to be staggered and different GPIO routes. In other embodiments, the bumps required to be routed through the GPIO can also be arranged in three rows and three columns near the edge, or in one row and one column near the edge, and so on. This depends on the chip design requirements and is not limited in this disclosure. Unless otherwise specified, the bumps mentioned in the I / O module arrangement method refer to the bumps required to be routed through the GPIO.

[0026] This embodiment arranges the GPIO according to the position of the bump of the chip pin and the requirements for normal line output. In order to physically connect the GPIO and the bump, the signal inside the chip is transmitted to the bump through the GPIO, and then transmitted to the package and printed circuit board (PCB: Printed Circuit Board) without affecting other signals. At the same time, power supply modules need to be interspersed between the GPIOs to ensure that the GPIO power supply is normal. To this end, this embodiment places the module groups in a one-to-one correspondence with the bumps of adjacent boundaries. In the process of placing the module groups in sequence along the set arrangement direction, by adding or reducing the power supply modules in the module groups, the position deviation of the GPIO in each module group and the bump corresponding to the module group is kept within the allowable range, so that the bump of the chip can be connected from the nearest GPIO, meeting the requirements of line output rationality and signal integrity.

[0027] exist Figure 3 In the example shown, the position of a module group needs to meet the line requirements of two bumps 4, so a module group includes 2 GPIOs 3. In order to meet the GPIO power supply needs, a module group also includes a power supply module 2. The power supply module in the chip may have one level or multiple levels. This embodiment requires that the distance between power supply modules of the same level should be less than the set distance threshold to facilitate power supply. Therefore, in this embodiment, when the power supply module has multiple levels, the power supply modules of multiple levels are placed alternately in the connected area. Figure 3 In the example shown, the power supply modules have two levels. The first level power supply modules 21 and the second level power supply modules 22 are placed alternately in the connection area. The two levels of power supply modules in the figure are represented by different hatching lines. Figure 3 Taking the power supply modules arranged from right to left at the lower boundary as an example, they are placed in an alternating manner, namely, the second-level power supply module 22, the first-level power supply module 21, the second-level power supply module 22, the first-level power supply module 21, and so on. The same is true for the power supply modules in the module group corresponding to bump 4. The first module group includes two GPIOs 3 and one second-level power supply module 22, the second module group includes two GPIOs 3 and one first-level power supply module 21, and so on. It should be noted that the alternating manner of different power supply modules is not limited to this. For example, when there are two power supply modules A and B of different levels, they can be placed alternately in the above-mentioned ABABAB... manner (also called interleaved placement), or they can be placed alternately in the AA-BB-AA-BB... manner.

[0028] like Figure 2As shown, a strip-shaped connected region can include multiple edge regions extending in different directions. This article divides a connected region into multiple straight-band regions, each extending in one direction. In this example, these straight-band regions do not include corner regions. However, this is merely a convenient division; including corner regions in a straight-band region does not affect the layout of input and output modules and should be considered an equivalent transformation.

[0029] exist Figure 2 and Figure 3 In the example shown, the direction of arranging the input and output modules is counterclockwise, which is referred to as the arrangement direction. The arrangement direction will be different for different straight belt areas. For example, for the straight belt area on the lower boundary, the arrangement direction is from right to left; for the straight belt area on the left boundary, the arrangement direction is from bottom to top; for the straight belt area on the upper boundary, the arrangement direction is from left to right; for the straight belt area on the right boundary, the arrangement direction is from top to bottom. After the arrangement direction is determined, the position of the first bump can be determined according to the arrangement direction. For example, in Figure 2 、 Figure 3 In the example shown, the first bump in the left straight band of the two straight bands on the lower boundary is marked 41, and the same applies to the other straight bands. The position of a GPIO can be represented by its two coordinates: one in the arrangement direction and the other perpendicular to the arrangement direction. The positional deviation between a module group and its corresponding bump can be represented by the difference between the first coordinate of each GPIO in the module group in the arrangement direction and the second coordinate of the bump in the arrangement direction.

[0030] See also Figure 4 , taking the straight band area on the left side of the lower boundary as an example, the positional deviation between the GPIO in the first module group and the first bump 41 adjacent to the straight band area is represented by the difference between the coordinates of the GPIO in the arrangement direction and the coordinates of the bump. As an example, the position of the GPIO in the module group in the arrangement direction is represented by the coordinates of the center point of the first GPIO in the module group in the arrangement direction (the direction indicated by the arrow in the figure) and the coordinates of the center point of the second GPIO in the arrangement direction. The coordinates of these two GPIOs are both called first coordinates. The position of the first bump 41 in the arrangement direction is represented by the coordinates of the center point of the bump 41 in the arrangement direction, which are called second coordinates. However, this is only exemplary. For example, the position of the GPIO can be represented by the coordinates of any point on the GPIO (such as a point on the left boundary or the right boundary) in the arrangement direction, and the position of the bump can be represented by the coordinates of any point on the bump (such as the leftmost point or the rightmost point in the figure) in the arrangement direction, and so on. Figure 4 In the example shown, the coordinates of the center point of the first GPIO in the first module group and the center point of the first bump 41 in the arrangement direction (indicated by the arrow below the figure) are equal, and the two are aligned.

[0031] In this article, the arrangement length of an input / output module in a straight belt area refers to the size of the input / output module in the arrangement direction of the straight belt area after it is placed in the straight belt area, and the arrangement length of a module group is equal to the sum of the arrangement lengths of all input / output modules in the module group, see Figure 3 , Lm in the figure represents the arrangement length of a module group. Since the arrangement length of a module group is not exactly equal to the bump spacing, the absolute value of the position deviation between the GPIO and the corresponding bump will gradually increase with each placement of a module group. This will make the line distance between the GPIO and the corresponding bump longer. Figure 4 As shown in the figure, after being placed in the last module group in the figure, the position deviation between the first GPIO in the module group and the corresponding bump changes from 0 to d in the figure.

[0032] In the process of placing the module groups in sequence along the set arrangement direction, this embodiment increases or decreases the power supply modules in the module groups so that the position deviation between the GPIO in each module group and the solder bump corresponding to the module group is kept within an allowable range. In one example, keeping the position deviation within the allowable range means ensuring that the absolute value of the difference between the first coordinate and the second coordinate is less than or equal to half of the spacing D between the solder bumps, that is, D / 2. That is, the difference between the coordinates of the center point of the first GPIO in the module group in the arrangement direction and the coordinates of the center point of the bump corresponding to the module group in the arrangement direction is less than D / 2, and the difference between the coordinates of the center point of the second GPIO in the module group in the arrangement direction and the coordinates of the center point of the bump corresponding to the module group in the arrangement direction is also less than D / 2. In this way, the rationality of the output line and the requirements of signal integrity can be guaranteed.

[0033] If the chip IO layout is designed manually, it will take a lot of time and effort. Especially when the functional module floor plan of the chip has not yet been determined and needs to be iterated repeatedly, the layout plan needs to be repeatedly adjusted, which requires a huge workload. In addition, human errors are prone to occur, which brings unnecessary design costs to chip design and prolongs the design cycle. The chip input and output module arrangement method of this embodiment automatically places input and output modules in the connected area, wherein the module group is placed in a one-to-one correspondence with the solder bumps of the adjacent boundaries, and by adding or reducing the power supply modules in the module group, the position deviation between the GPIO in each module group and the solder bump corresponding to the module group is kept within the allowable range, thereby adaptively realizing the automatic arrangement of the chip input and output modules, and making the chip input and output modules meet the requirements of line rationality and signal integrity, thereby improving the arrangement efficiency.

[0034] In an exemplary embodiment of the present disclosure, automatically placing input and output modules in a connected area further includes automatically placing the input and output modules in accordance with some or all of the following methods:

[0035] a) In the case where the connected area includes the chip corners, place a corner module at each corner. Figure 2 As shown, the three connected areas all include chip corners, and a corner module 7 is placed at each of these chip corners.

[0036] b) Place terminal modules at both ends of the connected area. Figure 2 As shown, a termination module 1 is placed at both ends of each connected area. In this article, according to the arrangement direction, the end at the starting position of the connected area is called the head end of the connected area, and the end at the ending position of the connected area is called the end of the connected area. The same definition is also given to the head and end of the straight belt area. For the straight belt area, if the head end of the straight belt area is the head end of the connected area to which it belongs, a termination module 1 is placed at the head end of the straight belt area, such as the straight belt area on the lower left side of the figure. If the end of the straight belt area is the end of the connected area to which it belongs, a termination module 1 is placed at the end of the straight belt area, such as the straight belt area on the lower left side of the figure. In other examples, if the straight belt area is a complete connected area, a termination module 1 is placed at the head end and the end end of the straight belt area respectively. If the straight belt area does not include the head end and the end end of the connected area to which it belongs (such as the straight belt area on the right side of the figure), the straight belt area does not need to be placed with a termination module 1.

[0037] c) Place at least one power control module in the connected area. Figure 2As shown, each connected area constitutes a power domain. A power control module 6 is placed in each connected area to implement the power control function of this area. The straight belt area where the power control module is placed is referred to as the power control domain. When a connected area includes multiple straight belt areas, the power control module can be placed in any straight belt area. Figure 2 In the example shown, the power control module 6 is placed adjacent to the corner module 7 , but the present disclosure is not limited thereto.

[0038] d) Power supply modules placed in areas other than module groups, corner modules, terminal modules, and power control modules in the connectivity area. Figure 3 , power supply modules 21 and 22 are placed in areas other than the module group, corner module 7, power control module 6, and termination module 1. It should be noted that, similar to conventional placement, the input and output modules in this embodiment are placed immediately adjacent to each other, with no gaps between them. Placing power supply modules in this manner allows for as many power supply modules as possible to be placed in the connected area.

[0039] e) Place a common filler module in the gap between the power supply module and other input and output modules. Common filler modules can have different sizes, such as Figure 3 As shown, on the left side of the lower straight belt area, two types of common filler modules are placed between the power supply module 21 and the power control module 6: a relatively long common filler module 51 and a relatively short common filler module 52. In the left straight belt area, common filler module 52 is placed between the power supply module 21 and the termination module 1. Placing common filler modules allows all input and output modules in a connected area to be connected together.

[0040] An embodiment of the present disclosure provides a chip input and output module arrangement method, which places various input and output modules in sequence by dividing the front straight belt area into the front section, the back section and the middle section. Figure 3 , the front, back and middle sections of the straight belt area below are represented as B1, B2 and B3 respectively. The front, back and middle sections of the straight belt area on the left are represented as L1, L2 and L3 respectively. It should be noted that not all straight belt areas include the complete three sections, but may only include part of them. The following description of the input and output module arrangement method of the front, middle and back sections of the straight belt area is based on the straight belt area including the corresponding sections, and does not mean that all straight belt areas place input and output modules in a three-section manner.

[0041] The connected area is divided into one or more straight belt areas excluding the chip corners, and the input and output modules are placed in the front section of the straight belt area in the following manner:

[0042] Determine whether the head end of the straight belt area belongs to the head end of the connected area according to the arrangement direction;

[0043] If it is the head end of the connected area, place a termination module and K power supply modules in sequence from the head end to the end of the straight belt area until there is insufficient space between the last placed power supply module and the first bump adjacent to the straight belt area to place the next power supply module.

[0044] If it is not the beginning of the connected area, K power supply modules are placed sequentially from the beginning to the end of the straight belt area until there is insufficient space between the last placed power supply module and the first bump adjacent to the straight belt area to place the next power supply module.

[0045] Wherein, the arrangement direction is counterclockwise or clockwise, and K is a natural number.

[0046] In this embodiment, the position of the first bump adjacent to the straight band area is represented by the coordinates of the bump in the arrangement direction (referring to the arrangement direction of the straight band area adjacent to the bump), such as Figure 3 The position of the first bump 41 in the image may be represented by the x-coordinate of the center point of the bump 41 (in other examples, it may also be represented by the coordinates of points at other positions on the bump 41). Figure 3 In the example shown, a termination module and 10 power supply modules are placed in sequence starting from the head end of the front section (B1) of the straight belt area at the lower boundary.

[0047] In some cases, the area between the beginning of the straight belt area and the first bump adjacent to the straight belt area is not long enough to place a power supply module. In this case, K=0, that is, no power supply module is placed.

[0048] In one example of this embodiment, the middle section of the straight tape area is the area corresponding to the bump adjacent to the straight tape area. If a straight tape area does not have an adjacent bump, then the straight tape area does not have a middle section. As previously mentioned, in the middle section of the straight tape area, the module groups are placed in a one-to-one correspondence with the solder bumps adjacent to the boundary. In the process of placing the module groups in sequence along the set arrangement direction, by adding or reducing the power supply modules in the module groups, the position deviation between the GPIO in each module group and the solder bump corresponding to the module group is kept within an allowable range. If a straight tape area does not have an adjacent bump that needs to be routed out, then the straight tape area does not have a middle section, and there is no need to place input and output modules in the middle section.

[0049] In this example, the steps for mid-section module placement include:

[0050] In the middle section of the straight belt area, the module groups are placed in sequence along the arrangement direction starting from the last power supply module placed in the front section, and the first module group to be placed is the first module group including M GPIOs and N power supply modules;

[0051] After each module group is placed, the error between the arrangement length of the placed module group and i·D is calculated. If the error is less than an error threshold, a first module group is placed. If the error is greater than or equal to the error threshold, a second module group including M GPIOs and N' power supply modules is placed instead, so that the error is less than the error threshold. When the number of placed module groups equals the number of solder bumps adjacent to the straight strip area, the module group placement is terminated.

[0052] Wherein, i is the number of placed module groups, D is the spacing of the solder bumps, M and N are positive integers, M is the number of solder bumps passing through the GPIO output line in a module group, and the arrangement length of a single first module group is less than 1.5D and greater than 0.5D.

[0053] The module groups of this embodiment are divided into two types. One is a module group of normal size, namely the above-mentioned first module group. The arrangement length of the first module group is less than 1.5D and greater than 0.5D. In many cases, the arrangement length of the first module group is not exactly equal to D. Therefore, after placing multiple module groups, the position deviation between the module group and the corresponding bump will accumulate and gradually become larger. If it is not adjusted, it will be impossible to maintain the one-to-one placement between the module group and the bump. The position deviation is expressed as an error during actual arrangement. Therefore, when the error is greater than the error threshold, it is necessary to place a second module group for adjusting the position deviation. When the arrangement length of the first module group is greater than D, N' can be N-1, that is, one power supply module is reduced; when the arrangement length of the first module group is less than D, N' can be N+1, that is, one power supply module is added, so that the error becomes a value less than the error threshold. In other examples, more power supply modules can also be reduced or added to adjust the position deviation.

[0054] exist Figure 3In the example shown, a module group includes two GPIOs and a power supply module in the straight band area at the bottom edge of the chip. The center point of the first GPIO in the first module group in the middle section is substantially aligned with the center point of the first bump 41 adjacent to the straight band area in the arrangement direction. However, the positional deviation between the second GPIO in the module group and the first bump 41 is significant. The error can be represented by the difference between the coordinates of the left edge of the second GPIO in the group and the coordinates of the center point of bump 41 in the arrangement direction. The error threshold can be set as 0.5D. After placing multiple module groups, if this error accumulates to a value greater than or equal to the error threshold, indicating that the difference between the coordinates of the left edge of the second GPIO in the module group and the center point of the bump corresponding to the module group in the arrangement direction exceeds half the bump spacing, the power supply module in the next module group to be placed is removed to reduce the error. At the location indicated by the arrow in the figure, a power supply module is removed, and the GPIOs in the two module groups are placed consecutively to adjust the positional deviation. As shown in the figure, when the next module group is placed, the module group including 2 GPIOs and a power supply module is restored.

[0055] The error threshold depends on the location of the first bump adjacent to the straight band and the coordinates used to represent the error. For example, if the first bump's location is represented by the coordinates of the bump's center or the rightmost point on the bump, the error threshold can take different values. The error threshold should be set to ensure that the positional deviation between the GPIO within each module group and the corresponding solder bump of that module group remains within the allowable range.

[0056] In an example of this embodiment, automatically placing input and output modules in the connected area further includes: placing the input and output modules in the rear section of the straight belt area in the following manner:

[0057] Starting from the last module group placed in the middle section, L power supply modules are placed in sequence until there is insufficient space between the last power supply module and the power control module or the termination module or the end of the straight strip area to place the next power supply module, where L is a natural number;

[0058] If the end of the straight belt area is the end of the connected area, a termination module is placed at the end of the straight belt area; if the straight belt area is the power control domain of the connected area, a power control module is placed at the end of the straight belt area or adjacent to the termination module.

[0059] When there is a gap between the power supply module and other input / output modules placed in the rear section, a common filling module is placed in the gap.

[0060] As described above, some straight-belt areas require termination modules, while others do not. Some straight-belt areas require power control modules, while others do not. It is also possible that some straight-belt areas require neither termination modules nor power control modules. Therefore, when determining the number of power supply modules that can be placed, it is necessary to consider whether the straight-belt area requires both termination modules and power control modules. In this embodiment, when both termination modules and power control modules are required in the rear section of the straight-belt area, the termination modules are placed at the end of the straight-belt area, the power control modules are placed adjacent to the termination modules, and the power supply modules are placed in the remaining area between the last module group placed in the middle section and the power control modules. When only termination modules are required in the rear section of the straight-belt area, the termination modules are placed at the end of the straight-belt area, and the power supply modules are placed in the remaining area between the last module group placed in the middle section and the termination modules. When only power control modules are required in the rear section of the straight-belt area, the power control modules are placed at the end of the straight-belt area, and the power supply modules are placed in the remaining area between the last module group placed in the middle section and the power control modules. If the remaining area is insufficient to accommodate the power supply module, L=0, that is, the power supply module is not placed in the rear section of the straight belt area.

[0061] Before automatically placing the input and output modules in the connected area, this embodiment further includes: determining arrangement parameters of the input and output modules, wherein the arrangement parameters include some or all of the following:

[0062] The size of each input and output module can determine the arrangement length of the input and output modules arranged in the straight belt area according to the size of the input and output modules (such as length and width);

[0063] Solder bump pitch;

[0064] Information on the number of solder bumps that need to extend from the straight tape area; this number information can be the number of solder bumps adjacent to the straight tape area (i.e., the number of solder bumps that need to extend from the GPIO in a row or column of solder bumps adjacent to the straight tape area), or it can be the number of all solder bumps that need to extend from one straight tape area.

[0065] Position information of the first solder bump adjacent to the straight strip area;

[0066] The alternation frequency of different power supply modules in a module group. For example, when a module group contains two power supply modules A and B with different power levels, the power supply modules in multiple consecutive module groups can be alternated in the ABABABAB... pattern or in the AA-BB-AA-BB... pattern.

[0067] The number of power supply modules in the module group;

[0068] The type of power supply module to add or remove when adjusting position deviation. For example, if a module group contains two power supply modules, A and B, with different power levels and different layout lengths, you can set the power supply module to be added or removed to A or B.

[0069] In an example of this embodiment, after automatically placing the input and output modules in the connected area, the method further includes:

[0070] Check whether the arranged input and output modules meet the constraint rules, wherein the constraint rules include that the distance between power supply modules of the same power level does not exceed the set distance threshold;

[0071] If the constraint rules are not met, the parameters are adjusted and rearranged, and the adjusted parameters include at least one of the following: the alternating frequency of different power supply modules in the module group, the number of power supply modules in the module group, and the types of power supply modules added or reduced when adjusting the position deviation.

[0072] In one example of this embodiment, after the input and output modules are arranged in all connected areas on the chip, a table can be generated to represent the arrangement of the input and output modules, recording the type and position of each input and output module placed in the connected area. The table can be converted into a file that can be recognized by the chip design software, that is, a design file that forms the module arrangement order (Pad Order).

[0073] The chip input / output module arrangement method of the disclosed embodiment can adaptively realize automatic arrangement of chip input / output modules, so that the chip input / output modules meet the requirements of line rationality and signal integrity, greatly improving the arrangement efficiency and being convenient and fast.

[0074] An embodiment of the present disclosure also provides a method for arranging input and output modules in the straight tape area of ​​a chip, such as Figure 5 Shown, including:

[0075] Step 210, inputting layout parameters;

[0076] The layout parameters here include the design parameters of the chip, such as the size list of the input and output modules, the x coordinate x of the beginning of the straight belt area, and the x coordinate x of the beginning of the straight belt area. len or y coordinate y len , the x coordinate x of the first bump adjacent to the straight band area fp or y coordinate y fp The number of bumps that need to pass through the straight-band area (that is, the number of GPIOs that the straight-band area needs to include) n total , bump spacing p bumpThe arrangement parameters may also include some settings during arrangement, such as the alternation frequency of different power supply modules in the module group; the number of power supply modules in the module group; and the types of power supply modules to be added or removed when adjusting the position deviation.

[0077] under Figure 3 The arrangement process is described using the straight belt area at the lower boundary of the middle chip (including the front section B1, the middle section B2 and the back section B3) as an example. The arrangement direction of the input and output modules in the straight belt area is the x direction, and the x coordinate x of the beginning of the straight belt area is used. len , and the x coordinate x of the first bump adjacent to the straight band area fp .

[0078] Step 220: Place input and output modules in the front section of the straight belt area until they are adjacent to the first bump of the straight belt area.

[0079] Due to considerations of signal integrity and routing rationality, the GPIO needs to be as close to the bump as possible. Therefore, the empty space outside the first and last bumps adjacent to the straight strip area can be used to place the termination module that isolates the power domain and the power supply module that maintains stable power supply.

[0080] Calculate the number of power supply modules that can be placed

[0081]

[0082] Where x vdd is the x dimension of the power supply module. The bottom bracket indicates rounding. endcap is the x-dimension of the termination module.

[0083] At the same time, the x coordinate of the end position of the input and output module placed in the front section is obtained loc :

[0084]

[0085] This x coordinate will be used as the starting position for placing input and output modules in the middle section, that is, starting from the last module placed in the front section to place the input and output modules in the middle section.

[0086] When the power supply modules have two or more power level modes, this embodiment requires that the spacing between power supply modules of the same power level be less than a fixed value to ensure stable power supply. Therefore, power supply modules of two or more power levels are placed alternately.

[0087] Step 230 , placing module groups in sequence in the middle section of the straight belt area and accumulating errors;

[0088] The module group placed in the middle section corresponds one-to-one with the bumps adjacent to the straight band area. The distance from the GPIO in a module group to the corresponding bump of the module group is shorter than the distance to other bumps. The GPIO in a module group is basically aligned with the corresponding bump of the module group to ensure signal integrity and rationality of the output line. Since the GPIO requires a nearby power supply module to power it, and usually both level modes are required, this embodiment places n GPIOs and the power supply module as a group. Figure 3 The example shown uses 2 GPIOs and a power supply module.

[0089] In the process of placing the module groups in sequence along the arrangement direction, the error is accumulated. Because the arrangement length of a module group is not exactly equal to the bump spacing during the placement process, the resulting offset will continue to accumulate, and the bump at the rear may cause the line to not be able to be normally output. Therefore, after each module group is placed, the error needs to be accumulated, and the accumulated error is recorded as e a .

[0090] In this embodiment, an initial error is generated when placing the first module group. The error e a,1 It is equal to the difference between the x-coordinate of the left side of the second GPIO in the first module group (the left side is the side that serves as the end of the GPIO in the arrangement direction in the example; in other examples, the side can also be the upper side, the right side, etc.) and the x-coordinate of the center point of the first bump 41.

[0091] Before adjusting the position deviation, the module group includes n GPIOs and 1 power supply module. For each additional module group, the error e a The increase in is equal to the difference between the arrangement length of the module group (i.e., the first module group mentioned above) and the bump spacing, expressed as:

[0092] e=n*x gpio +x vdd -p bump

[0093] Where p bump Indicates bump spacing, x gpio represents the arrangement length of a GPIO, n is the number of GPIOs in a module group, and in this embodiment, n=2.

[0094] In this embodiment, when adjusting the position deviation, a module group including n GPIOs is placed. At this time, the error e a The increase is equal to the difference between the arrangement length of n GPIOs and the bump spacing. It is expressed as:

[0095] e′=n*x gpio-p bump

[0096] The accumulated error e after placing i module groups a,i for:

[0097] e a,i =e a,i-1 +n*x gpio -p bump

[0098] Where, e a,i-1 is the cumulative error after placing i-1 module groups. In the above embodiment, the cumulative error is expressed as the error between the length of the placed module groups and i·D, where i is the number of placed module groups and D is the bump spacing. The two representations are equivalent.

[0099] In this step, the coordinate x of the end of the placed module group is continuously updated after the current module group is placed. loc,i , until the number of GPIOs reaches n total :

[0100] x loc,i =x loc,i-1 -n*x gpio -x vdd

[0101] Where x loc,i-1 is the coordinate of the end of the placed module group after placing the i-th module group, x gpio The x size of the GPIO.

[0102] Step 240, determining whether the number of placed GPIOs reaches the number of GPIOs that need to be placed, if so, executing step 280, if not, executing step 250;

[0103] At this time, it is determined whether the number of GPIOs placed has reached the number of GPIOs that need to be placed. In other embodiments, it can also be determined whether the number of module groups placed has reached the number of module groups that need to be placed (the number of bumps in a row or column of bumps adjacent to the straight band area that need to pass through the GPIO output line). The two are equivalent.

[0104] Step 250: Determine whether the accumulated error is greater than or equal to the error threshold. If so, proceed to step 260; if not, proceed to step 270.

[0105] In this step, after placing the i-th module group, e a,i Compared with the set error threshold, the error threshold of this embodiment is set to 0.5*p bump ; then:

[0106] If ea,i ≥0.5*p bump , execute step 260; it should be noted that, Figure 3 In the example shown, the difference between the coordinates of the center point of the second GPIO in the i-th module group and the center point of the corresponding bump (i.e., the positional deviation between the GPIO in the module group and the bump corresponding to that module group) does not exceed the error threshold and remains within the allowable range. In other examples, if this would cause the positional deviation to exceed the allowable range, the error threshold or the placement of the first module group can be adjusted to keep the positional deviation within the allowable range.

[0107] If e a,i <0.5*p bump , execute step 270.

[0108] Step 260: The module group including two GPIOs and one power supply module is selected as the next module group to be placed, and the process returns to step 230 to continue placing module groups.

[0109] In this embodiment, the module group including 2 GPIOs and 1 power supply module is the first module group. In other embodiments, the number of GPIOs and the number of power supply modules included in the first module group can vary.

[0110] Step 270: The module group containing two GPIOs is selected as the next module group to be placed, and the process returns to step 230 to continue placing module groups.

[0111] In this embodiment, the module group containing two GPIOs is the second module group. Since the arrangement length of the first module group in this embodiment is greater than the bump spacing, adjusting the position deviation requires removing one power supply module from the module group. If the arrangement length of the first module group is less than the bump spacing, the position deviation can be adjusted by adding a power supply module to the module group.

[0112] After returning to step 230 to place the module group including 2 GPIOs, the accumulated error will be smaller than the error threshold, so the module group placed after adjustment will be the first module group.

[0113] Step 280 , placing input and output modules at the rear end of the straight belt area until the space of the straight belt area is fully occupied.

[0114] by Figure 3Taking the straight strip area at the lower boundary as an example, when the required number of GPIOs is reached, calculate the layout length occupied by the corner modules and the power control module. Subtract the layout length occupied by the corner modules and the power control module from the remaining layout length of the straight strip area, and divide the remaining length by the layout length of the power supply modules to obtain the maximum number of power supply modules that can be placed. Then, subtract the layout length occupied by the power supply modules from this portion, and divide the remaining length by the number of ordinary filler modules from the largest to the smallest. Iterate and solve until the smallest ordinary filler module can no longer fill the remaining space. This can be expressed as the following formula:

[0115]

[0116]

[0117]

[0118] In the formula The number of power supply modules placed in the back section, x corner is the x dimension of the corner module, x poc is the x-dimension of the power control module, is the number of larger filling modules, For the x-dimension of the larger filler module, For the smaller number of filling modules, The x-dimension of the smaller filler module.

[0119] This embodiment only takes two sizes of filling modules as an example. In practice, there are filling modules of various sizes that can be solved iteratively using similar formulas.

[0120] The above formula is based on the lower left corner of the chip as the coordinate origin. Although this example does not include the space occupied by the corner modules in the straight band area, the x-dimension of the corner modules is used when calculating the remaining space for the power supply modules in the subsequent stage.

[0121] Step 290, determine whether the placed input and output modules meet the constraint rules. If so, end. If not, execute step 300.

[0122] After completing one arrangement, it is checked whether the placed input and output modules meet the constraint rules. In one example, the constraint rules include but are not limited to: the distance between power supply modules of the same level does not exceed a set distance threshold.

[0123] Step 300: Adjust the arrangement parameters and return to step 220 to re-place the input and output modules in the straight belt area.

[0124] The layout parameters that can be adjusted in this step include, but are not limited to, at least one of the following: the alternating frequency of different power modules in the module group, the number of power modules in the module group, and the types of power modules added or removed when adjusting for position deviation. After adjusting the layout parameters, the input and output modules are re-arranged in the straight belt area, ultimately resulting in the chip's automatic IO layout, which can be converted into a corresponding design solution, namely, the pad order.

[0125] An example of the chip input and output module arrangement method of this embodiment is as follows Figure 3 As shown in the figure, a corner of the chip is selected as an example, including a straight band area at the bottom boundary and a straight band area at the left boundary. The three bumps at the chip corner do not require signal connections. After arrangement, the automatic placement of the input and output modules at the front, middle, and back ends of the straight band area is shown in the figure and explained in the figure. It can be seen that this automatic placement result effectively meets the expected design requirements and significantly reduces the time required for the entire process, greatly improving design efficiency.

[0126] The disclosed embodiment of the adaptive chip input and output module automatic arrangement method can quickly generate the IO layout design files required for chip design without human intervention. This method can quickly respond to design iterations, shorten the design cycle, and also has the advantages of wide compatibility and strong scalability. At the same time, the replacement of chip size and GPIO size has no effect on the solution. In the future, the introduction of new processes and new GPIO designs only requires changing input parameters and adjusting some function logic, which is well adapted to the rapid development of the integrated circuit industry.

[0127] The disclosed embodiment uses an adaptive algorithm to extract the information and rules required for the chip's IO layout into a data model, and uses software to perform automated calculations based on these rules and input parameters. The arrangement order of the most important GPIO and power management modules is determined by calculating the cumulative error method, making the arrangement result adaptive to meet the signal integrity and line rationality of the IO, thereby ensuring the normal operation of the IO.

[0128] The embodiments of the present disclosure can realize the automatic arrangement of input and output modules, so that the input and output modules of the chip meet the requirements of line rationality and signal integrity, greatly improving design efficiency, being convenient and fast, and can be used for the arrangement of input and output modules of all chip types and chip processes. The adaptive method of the present disclosure can adjust the arrangement logic for different input and output module lists.

[0129] like Figure 6As shown, an embodiment of the present disclosure further provides a chip input-output module arrangement device, including a processor 50 and a memory 60 storing a computer program. When the processor 50 executes the computer program, it can implement the chip input-output module arrangement method described in any embodiment of the present disclosure. The processor of this embodiment can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The various methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0130] An embodiment of the present disclosure further provides a non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the chip input-output module arrangement method as described in any embodiment of the present disclosure is implemented.

[0131] In any one or more of the above exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium and executed by a hardware-based processing unit. The computer-readable medium may include a computer-readable storage medium corresponding to a tangible medium such as a data storage medium, or a communication medium that facilitates the transfer of a computer program from one place to another, such as according to a communication protocol. In this manner, a computer-readable medium may generally correspond to a non-transitory tangible computer-readable storage medium or a communication medium such as a signal or carrier wave. The data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. A computer program product may include a computer-readable medium.

[0132] By way of example and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Furthermore, any connection may also be referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transient (transient) media, but rather refer to non-transient tangible storage media. As used herein, disk and optical disk include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, or Blu-ray disc, among others, where disks typically reproduce data magnetically, while optical discs use lasers to reproduce data optically. Combinations of the above should also be included within the scope of computer-readable media.

[0133] By way of example and not limitation, instructions may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor," as used herein, may refer to any of the aforementioned structures or any other structure suitable for implementing the techniques described herein. Additionally, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into a combined codec. Furthermore, the techniques may be fully implemented in one or more circuits or logic elements.

[0134] The technical solutions of the embodiments of the present disclosure can be implemented in a wide variety of devices or equipment, including wireless mobile phones, integrated circuits (ICs), or a group of ICs (e.g., chipsets). Various components, modules, or units are described in the embodiments of the present disclosure to emphasize the functional aspects of the devices configured to perform the described techniques, but they do not necessarily need to be implemented by different hardware units. Instead, as described above, the various units can be combined in a codec hardware unit or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware.

Claims

1. A chip input and output module arrangement method, comprising: Determine one or more connectivity areas around the chip for arranging input and output modules, and the solder bumps on the chip that need to be routed through the GPIO. Automatically placing input and output modules in the connected area includes: placing module groups in a one-to-one correspondence with the solder bumps of adjacent boundaries, wherein, in the process of sequentially placing the module groups along the arrangement direction, by adding or reducing power supply modules in the module groups, the position deviation of the GPIO in each module group and the solder bump corresponding to the module group is maintained within an allowable range.

2. The method according to claim 1, wherein: The automatic placement of input and output modules in the connected area further includes at least one of the following placement methods: In the case where the connected area includes chip corners, a corner module is placed at each corner; Place termination modules at both ends of the communication area respectively; At least one power control module is placed in the communication area; Power supply modules placed in other areas of the connected area except the module group, corner modules, terminal modules and power control modules; A common filling module is placed in the gap between the power supply module and other input and output modules.

3. The method according to claim 2, wherein: When the power supply modules have multiple levels, the power supply modules of the multiple levels are alternately placed in the communication area.

4. The method according to claim 1, wherein: The position deviation is determined based on the first coordinate of the center point of each GPIO in the module group in the arrangement direction and the second coordinate of the center point of the solder bump corresponding to the module group in the arrangement direction; the position deviation is kept within the allowable range, which means that the absolute value of the difference between the first coordinate and the second coordinate is less than or equal to half of the spacing between the solder bumps.

5. The method according to claim 1, wherein: The automatic placement of the input / output modules in the connected area includes: dividing the connected area into one or more straight strip areas excluding chip corners, and placing the input / output modules in the front section of the straight strip areas in the following manner: Determine whether the head end of the straight belt area belongs to the head end of the connected area according to the arrangement direction; If it is the head end of the connected area, place a termination module and K power supply modules in sequence from the head end to the end of the straight belt area until there is insufficient space between the last placed power supply module and the position of the first solder bump adjacent to the straight belt area to place the next power supply module; If it is not the beginning of the connected area, K power supply modules are placed sequentially from the beginning to the end of the straight belt area until there is insufficient space between the last placed power supply module and the first solder bump adjacent to the straight belt area to place the next power supply module. Wherein, the arrangement direction is counterclockwise or clockwise, and K is a natural number.

6. The method according to claim 5, wherein: The placing of the module groups in a one-to-one correspondence with the solder bumps adjacent to the boundary comprises: In the middle section of the straight belt area, the module groups are placed in sequence along the arrangement direction starting from the last power supply module placed in the front section, and the first module group to be placed is the first module group including M GPIOs and N power supply modules; After each module group is placed, the error between the arrangement length of the placed module group and i·D is calculated. If the error is less than an error threshold, a first module group is placed. If the error is greater than or equal to the error threshold, a second module group including M GPIOs and N' power supply modules is placed instead, so that the error is less than the error threshold. When the number of placed module groups equals the number of solder bumps adjacent to the straight strip area, the module group placement is terminated. Wherein, i is the number of placed module groups, D is the spacing of the solder bumps, M and N are positive integers, M is the number of solder bumps passing through the GPIO output line in a module group, and the arrangement length of a single first module group is less than 1.5D and greater than 0.5D.

7. The method according to claim 6, wherein: The automatic placement of input and output modules in the connected area further includes: placing the input and output modules in the rear section of the straight belt area in the following manner: Starting from the last module group placed in the middle section, L power supply modules are placed in sequence until there is insufficient space between the last power supply module and the power control module or the termination module or the end of the straight strip area to place the next power supply module, where L is a natural number; If the end of the straight belt area is the end of the connected area, a termination module is placed at the end of the straight belt area; if the straight belt area is the power control domain of the connected area, a power control module is placed at the end of the straight belt area or adjacent to the termination module. When there is a gap between the power supply module and other input / output modules placed in the rear section, a common filling module is placed in the gap.

8. The method according to claim 5, wherein: Before automatically placing the input and output modules in the connected area, the method further includes: determining arrangement parameters of the input and output modules, the arrangement parameters including: The size of each input and output module; Solder bump pitch; The number of solder bumps that need to be routed out of the straight tape area; Position information of the first solder bump adjacent to the straight strip area; The alternation frequency of different power supply modules in the module group; The number of power supply modules in the module group; The type of power supply module to be added or removed when adjusting position deviation.

9. The method according to claim 8, wherein: After automatically placing the input and output modules in the connected area, the method further includes: Check whether the arranged input and output modules meet the constraint rules, wherein the constraint rules include that the distance between power supply modules of the same power level does not exceed the set distance threshold; If the constraint rules are not met, the parameters are adjusted and rearranged, and the adjusted parameters include at least one of the following: the alternating frequency of different power supply modules in the module group, the number of power supply modules in the module group, and the types of power supply modules added or reduced when adjusting the position deviation.

10. A chip input / output module arrangement device, comprising a processor and a memory storing a computer program, characterized in that: When the processor executes the computer program, it can implement the chip input-output module arrangement method as described in any one of claims 1 to 8.

11. A non-transitory computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the chip input-output module arrangement method according to any one of claims 1 to 8 is implemented.

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