Display device and display apparatus having a plurality of display devices

Abstract

A display device and a display apparatus including a plurality of display devices are disclosed. The display device includes a first pixel circuit, a first scan signal line disposed at a side of the first pixel circuit, extending in a first direction, and transmitting a scan signal, a second pixel circuit disposed at an outermost side of the display device, and a first dummy wiring disposed at an outer side of the second pixel circuit and extending in the first direction. A width of the first dummy wiring is less than a width of the first scan signal line.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0173392, filed on December 11, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices and display apparatuses including multiple display devices, and more particularly, to a display device and a relatively large-sized display apparatus formed by attaching multiple display devices. Background Technology

[0004] A display device is a means for displaying images on a screen, and it can be a liquid crystal display (LCD), an organic light-emitting diode display (OLED), or a quantum dot display. Display devices can be used in or incorporated into various electronic devices (such as mobile phones, GPS devices, digital cameras, e-book readers, portable gaming devices, or various terminals).

[0005] Emitting-light display devices include light-emitting elements, such as organic light-emitting devices. Emitting-light display devices are self-emissive and, unlike LCDs, do not require a separate light source. Due to this characteristic, emitting-light display devices can be thinner and lighter than other types of display devices. Furthermore, emitting-light display devices offer superior features such as low power consumption, high brightness, and high response time.

[0006] It will be understood that this background section is intended to provide some useful context for understanding the art. However, this background section may also include concepts, ideas, or knowledge that were known or understood by a person skilled in the art prior to the corresponding valid application date, and are not related to the subject matter disclosed herein. Summary of the Invention

[0007] This disclosure provides a light-emitting display device and a large display device formed by attaching a plurality of light-emitting display devices, wherein the light-emitting display devices maintain a constant gap between pixels when the plurality of light-emitting display devices are attached to form a large display device.

[0008] In one embodiment, the display device may include: a first pixel circuit; a first scan signal line disposed on the side of the first pixel circuit, extending in a first direction, and transmitting a scan signal; a second pixel circuit disposed on the outermost side of the display device; and a first dummy wiring disposed on the outer side of the second pixel circuit and extending in the first direction. The width of the first dummy wiring may be smaller than the width of the first scan signal line.

[0009] The display device may include multiple sub-regions, and each of the multiple sub-regions may include: a scan signal application region for transmitting a scan signal in a first direction; and a dummy region in which dummy wiring is provided. The dummy wiring may include a first dummy wiring.

[0010] A voltage signal used to turn off a transistor can be applied to a dummy wiring.

[0011] A dummy wiring may also include a second dummy wiring, and the width of the second dummy wiring may be greater than the width of the first dummy wiring.

[0012] The second dummy wiring can be set on the side of the second pixel circuit where the first dummy wiring is not set.

[0013] The display device may further include a third pixel circuit between the first pixel circuit and the second pixel circuit. A second dummy wiring may be disposed on one side of the third pixel circuit.

[0014] The display device may further include a second scan signal line extending in a direction perpendicular to the first direction and transmitting scan signals. The second scan signal line may be electrically connected to the first scan signal line.

[0015] Multiple sub-regions can be configured as three sub-regions. Each of the three sub-regions may include a first scan signal line. A second scan signal line may extend into each of the three sub-regions. The second scan signal line may be electrically connected to the first scan signal line in each of the three sub-regions. The first scan signal line may transmit scan signals with the same timing.

[0016] The second scan signal line can be electrically connected to the gate electrode of the thin-film transistor included in the first pixel circuit and the gate electrode of the thin-film transistor included in the second pixel circuit.

[0017] The first pixel circuit and the second pixel circuit may each include: a driving transistor that generates an output current to a light-emitting diode; an input transistor that transmits a data voltage to the gate electrode of the driving transistor; a storage capacitor having a terminal connected to the gate electrode of the driving transistor; and an initialization transistor that initializes a terminal that outputs the output current from the driving transistor.

[0018] In an embodiment, the display device may include a plurality of display devices attached to each other. At least one of the plurality of display devices may include: a first pixel circuit; a first scan signal line disposed on the side of the first pixel circuit and extending in a first direction; a second pixel circuit disposed on the outermost side of the at least one display device; and an outermost dummy wiring disposed on the outer side of the second pixel circuit and extending in the first direction. The width of the outermost dummy wiring may be smaller than the width of the first scan signal line.

[0019] At least one display device may include a plurality of sub-regions, and each of the plurality of sub-regions may include: a scan signal application region for transmitting a scan signal in a first direction; and a dummy region in which dummy wiring is provided. The dummy wiring may include an outermost dummy wiring.

[0020] A voltage signal used to turn off a transistor can be applied to a dummy wiring.

[0021] A dummy wiring may also include a second dummy wiring, and the width of the second dummy wiring may be greater than the width of the outermost dummy wiring.

[0022] The second dummy wiring can be set on the side of the second pixel circuit where the outermost dummy wiring is not set.

[0023] The display device may also include a third pixel circuit disposed between the first pixel circuit and the second pixel circuit. A second dummy wiring may be disposed on one side of the third pixel circuit.

[0024] The display device may include a second scan signal line extending in a direction perpendicular to the first direction and transmitting scan signals. The second scan signal line may be electrically connected to the first scan signal line.

[0025] Multiple sub-regions can be configured as three sub-regions. Each of the multiple sub-regions may include a first scan signal line. Second scan signal lines may extend into the three sub-regions. The second scan signal lines may be electrically connected to the first scan signal lines in each of the three sub-regions, and the first scan signal lines may transmit scan signals with the same timing.

[0026] The second scan signal line can be electrically connected to the gate electrode of the thin-film transistor included in the first pixel circuit, and also electrically connected to the gate electrode of the thin-film transistor included in the second pixel circuit.

[0027] In one embodiment, the display device may include: a first pixel circuit; a pair of first scan signal lines disposed on the side of the first pixel circuit, extending in a first direction and transmitting scan signals; a second pixel circuit disposed on the outermost side of the display device; and dummy wiring disposed inside the second pixel circuit. Wiring may not be disposed outside the second pixel circuit.

[0028] According to the implementation, when the tolerance or allowance for manufacturing large display devices in processes such as laser beam cutting is considered by allowing a gap between the outermost pixel or wiring and the edge of the substrate equal to or greater than about 50 μm in the light-emitting display device, the pixel gaps of the completed large display device can correspond to each other, and the display quality of the large display device can be improved.

[0029] According to the implementation, when the narrowed wiring is used as a dummy wiring or when a cutoff voltage (Voff) is applied to the narrowed wiring, reducing the width of the wiring to adjust the width of the outermost area will not cause problems due to electrical load, and therefore will not degrade the display quality. Attached Figure Description

[0030] The above and other aspects and features of this disclosure will become clearer from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0031] Figure 1 A schematic layout diagram of a light-emitting display device according to an embodiment is shown;

[0032] Figure 2 A schematic diagram of the equivalent circuit of a pixel of a light-emitting display device according to an embodiment is shown;

[0033] Figure 3 A schematic top view of pixels disposed in the scanning signal application area of ​​a light-emitting display device according to an embodiment is shown;

[0034] Figure 4 and Figure 5 The light-emitting display device is shown relative to Figure 3 Schematic cross-sectional view of lines IV-IV and VV;

[0035] Figure 6 A schematic top view of a pixel disposed on the outermost left side of a light-emitting display device according to an embodiment is shown;

[0036] Figure 7 A schematic top view of pixels disposed in a dummy area of ​​a light-emitting display device according to an embodiment is shown;

[0037] Figure 8A schematic top view of a pixel disposed on the outermost right side of a light-emitting display device according to an embodiment is shown;

[0038] Figure 9 A schematic diagram of a light-emitting display device according to an embodiment is shown;

[0039] Figure 10 A schematic diagram of a large display device according to an embodiment is shown;

[0040] Figure 11 A schematic top view of pixels disposed in the scanning signal application area of ​​a light-emitting display device according to an embodiment is shown;

[0041] Figure 12 A schematic top view of a pixel disposed on the outermost left side of a light-emitting display device according to an embodiment is shown;

[0042] Figure 13 A schematic diagram of the equivalent circuit of a pixel of a light-emitting display device according to an embodiment is shown;

[0043] Figure 14 A schematic top view of a portion of a light-emitting display device according to an embodiment is shown; and

[0044] Figure 15 A schematic cross-sectional view of a light-emitting display device according to an embodiment is shown. Detailed Implementation

[0045] The present disclosure will now be described more fully below with reference to the accompanying drawings, which illustrate embodiments. However, the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0046] In the accompanying drawings, for ease of description and clarity, the dimensions, thickness, scale, and size of the components may be exaggerated. The same reference numerals denote the same components throughout.

[0047] For better understanding and ease of description, the dimensions and thicknesses of each configuration shown in the accompanying drawings are arbitrarily illustrated, but this disclosure is not limited thereto. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. For ease of illustration, the thicknesses of some layers and regions are exaggerated.

[0048] What will be understood is that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element, or there may be an intermediary element. Conversely, when an element is referred to as being “directly” on another element, there is no intermediary element. The word “on” or “above” means located on or below a portion of an object, and does not necessarily mean located on the upper side of the object based on the direction of gravity.

[0049] Unless explicitly stated otherwise, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply inclusion of the elements described, but not to exclude any other elements.

[0050] The phrase "in a plan view" means viewing a portion of an object from the top, and the phrase "in a sectional view" means viewing a section of an object cut vertically from the side.

[0051] Throughout the specification, when describing a part as "connected" to another part ("in contact" or "connected" to another part), the part may be directly connected to the other part, connected to the other part via a third part, or physically or electrically connected to the other part, and they may be represented by different names depending on their location or function, but essentially the various parts integrated into one body can be connected to each other.

[0052] It will be understood that the terms “connected to” or “linked to” can include physical or electrical connections, or physical or electrical connections.

[0053] In the specification and claims, for purposes of meaning and interpretation, the phrase “at least one of…” is intended to include the meaning of “at least one selected from the group of…”. For example, “at least one of A and B” can be understood to mean “A, B, or A and B”.

[0054] It will be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0055] For ease of description, the spatial relative terms “below,” “under,” “down,” “above,” “up,” etc., may be used herein to describe the relationship between one element or component and another element or component as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are intended to include different orientations of the device in use or operation. For example, in the case where the device shown in the figures is flipped, a device positioned “below” or “under” another device may be placed “above” another device. Therefore, the descriptive term “below” can include both a lower position and an upper position. The device may also be oriented in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0056] The term “overlapping” or “overlapping” means that the first object may be above or below the second object, or on one side of the second object, and that the second object may be above or below the first object, or on one side of the first object. Additionally, the term “overlapping” may include stacking, overlapping, facing or oriented towards, extending over, covering or partially covering, or may be any other suitable term as will be understood and appreciated by one of ordinary skill in the art.

[0057] As used herein, “about” or “approximately” includes the value as well as the average of the specific value within an acceptable range of variation, determined by a person skilled in the art considering the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0058] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted as having an idealized or overly formal meaning unless expressly so defined herein.

[0059] Embodiments of the light-emitting display device will now be described with reference to the accompanying drawings.

[0060] First, refer to Figure 1 Describe the schematic structure of the light-emitting display device.

[0061] Figure 1 A schematic layout diagram of a light-emitting display device according to an embodiment is shown.

[0062] according to Figure 1The light-emitting display device 10 of the embodiment includes a display area in which light-emitting diodes EDa, EDb and EDc are disposed, and a driving area disposed on the upper side of the display area and in which driving chips 20 and 30 are disposed.

[0063] In the display area, multiple sets of light-emitting diodes (EDa, EDb, and EDc) can be configured to display the three primary colors (such as red, green, and blue). (See reference...) Figure 1 The described embodiment of a group of light-emitting diodes EDa, EDb, and EDc can have a configuration in which corresponding light-emitting diodes (LEDs) positioned longitudinally in the x-axis direction are arranged parallel to each other in the y-axis direction. However, the embodiment is not limited to this, and the light-emitting diodes (LEDs) belonging to the group of light-emitting diodes EDa, EDb, and EDc can have the same configuration as the referenced one. Figure 1 The quantity or arrangement described is different from the quantity or arrangement.

[0064] According to the reference Figure 1 The described embodiment of the light-emitting display device 10 can be divided into three sub-regions 10-1, 10-2, and 10-3, and the corresponding sub-regions 10-1, 10-2, and 10-3 are separated and shown using dashed lines. The corresponding sub-regions 10-1, 10-2, and 10-3 may include a display area in which light-emitting diodes EDa, EDb, and EDc are disposed, and a driving area on the upper side of the display area in which driving chips 20 and 30 are disposed. (For reference...) Figure 1 The described embodiment of the light-emitting display device 10 has its driving region located on the upper side, and not on the right, left, or lower side. As a result, other light-emitting display devices 10 can be attached to the right, left, and lower sides to form a large display device (see reference). Figure 10 The driving area in the light-emitting display device 10 can be located on only one side of the display area.

[0065] A sub-region 10-1, 10-2, or 10-3 corresponds to a data driver 20 and a scan driver 30, and may be configured with multiple sets of light-emitting diodes EDa, EDb, and EDc that emit light when a data voltage is applied by the data driver 20.

[0066] Data driver 20 applies data voltage to the data line (reference). Figure 2 and Figure 3 Furthermore, the data driver 20 can be located within a chip mounted on a substrate. Although in Figure 1 Not shown, but the data driver 20 applies a data voltage to the corresponding data line that is electrically connected to the data line extending in the x-axis direction.

[0067] The scan driver 30 applies a scan signal to the scan signal line 151, and the scan driver 30 can be mounted as a chip on the substrate. Figure 1 The detailed connection structure of scan signal line 151 is shown. Scan signal line 151 generally includes a connecting scan signal line 151v (first scan signal line) and a main scan signal line 151h (second scan signal line), with the main scan signal line 151h extending in the y-axis direction and the connecting scan signal line 151v extending generally in the x-axis direction. The connecting scan signal line 151v is electrically connected to the scan driver 30 to receive scan signals. According to embodiments, additional connecting members (e.g., Figure 1 The wiring shown in Figure 31) is used to connect the scan signal line 151v and the scan driver 30.

[0068] The main scan signal line 151h is electrically connected to the connecting scan signal line 151v through an opening 151o. As a result, the scan signal output by the scan driver 30 is transmitted to the connecting scan signal line 151v and then to the main scan signal line 151h through the opening 151o. The connecting scan signal line 151v is located in one sub-region 10-1, 10-2, or 10-3 and does not extend to adjacent sub-regions 10-1, 10-2, or 10-3. Conversely, the main scan signal line 151h extends to adjacent sub-regions 10-1, 10-2, or 10-3 and is sequentially located in the three sub-regions 10-1, 10-2, and 10-3. One connecting scan signal line 151v is electrically connected to one main scan signal line 151h through an opening 151o in one of the sub-regions 10-1, 10-2, or 10-3. However, for the light-emitting display device 10 comprising three sub-regions 10-1, 10-2, and 10-3, a main scan signal line 151h is electrically connected to three connecting scan signal lines 151v through three openings 151o, respectively. As a result, the main scan signal line 151h receives three scan signals with the same timing. For example, in... Figure 1 In the diagram, the scan signal line 151, labeled as the first scan signal line G#1, includes a total of three connecting scan signal lines 151v and one main scan signal line 151h for each sub-region 10-1, 10-2, or 10-3. For example... Figure 1 As shown, the main scan signal lines 151h arranged in the x-axis direction are sequentially numbered G#1, G#2...G#540, and for each sub-region 10-1, 10-2, or 10-3, the connecting scan signal lines 151v arranged in the y-axis direction are sequentially numbered G#1, G#2...G#540. Scan signal lines 151 with the same number are electrically connected to each other and receive the same scan signal.

[0069] Typically, in a display device, the data driver 20 and the scan driver 30 are disposed on different sides of the display area, with a direction perpendicular to the main scan signal line 151h, and it is not necessary to connect the scan signal line 151v to the scan driver 30. However, in an embodiment, the driving area (having both the data driver 20 and the scan driver 30) can be disposed on one side of the display area, so as... Figure 3 As shown, the connection scan signal line 151v, which is set parallel to the data line, transmits the scan signal to the main scan signal line 151h, which is set perpendicular to the data line.

[0070] The light-emitting display device 10 may further include wirings 152 and 153 (hereinafter referred to as dummy wirings) arranged parallel to the connecting scan signal line 151v and extending in the x-axis direction. A constant voltage level (cutoff voltage (Voff)) in the scan signal for maintaining the transistor in the off state may be applied to the dummy wirings 152 and 153. According to embodiments, no voltage may be applied to the dummy wirings 152 and 153, so that they can float, or different voltages may be applied to the dummy wirings 152 and 153.

[0071] like Figure 1 As shown, dummy wirings 152 and 153 may not be electrically connected to the main scan signal line 151h. As a result, no opening 151o overlapping with dummy wirings 152 and 153 is provided.

[0072] Dummy wirings 152 and 153 may include two types of wires, including a first dummy wiring 152 (hereinafter, the outermost dummy wiring) having a wire width narrower than the wire width of the connecting scan signal line 151v, and a second dummy wiring 153 having the same wire width as the connecting scan signal line 151v. The first dummy wiring 152 may be disposed on the outermost (edge) of the light-emitting display device 10. A total of two first dummy wirings 152 may be disposed on the corresponding sides (edges) of the light-emitting display device 10. The other dummy wirings are disposed as second dummy wirings 153. Therefore, the first dummy wiring 152 may not be disposed on the boundaries of sub-regions 10-1, 10-2, and 10-3 (where the second dummy wiring 153 is disposed). The first dummy wiring 152 may be narrower than the second dummy wiring 153 or the connecting scan signal line 151v, so as to form a large display device (see reference) by attaching multiple light-emitting display devices 10 together. Figure 10When multiple light-emitting display devices 10 are attached, processes such as laser beam cutting are performed. The light-emitting display devices 10 can be provided for attachment after the laser beam cutting process (the light-emitting display devices 10 can be attached), and the narrow width of the first dummy wiring 152 allows for adjustment of tolerances or allowances so that the gap between light-emitting diodes EDa, EDb, and EDc can remain constant, even between light-emitting diodes EDa, EDb, and EDc in different light-emitting display devices 10. As a result, when a large display device is completed, the gap between light-emitting diodes EDa, EDb, and EDc can be constant and consistent throughout the large display device, and the display quality of the large display device can be improved.

[0073] like Figure 1 As shown, a number of second dummy wires 153 can be provided, and the implementation is not limited to a specific number of second dummy wires 153. The second dummy wires 153 can be the remaining wires after forming the necessary connection scan signal lines 151v and excluding the two first dummy wires 152 from the remaining wires.

[0074] refer to Figure 1 The enlarged portion shown, and referenced Figure 3 , Figure 6 , Figure 7 and Figure 8 Wiring extending in the x-axis direction (hereinafter, connecting wiring) is disposed on the corresponding sides of a group of light-emitting diodes EDa, EDb, and EDc, and can be used as connecting scan signal line 151v or dummy wirings 152 and 153. For the light-emitting diodes EDa, EDb, and EDc disposed on the outermost side, the wiring is configured as the first dummy wiring 152 on the outermost side, while the other wiring is configured as the second dummy wiring 153.

[0075] For example Figure 1 The light-emitting display device 10 shown has a resolution of 960×540 and may require 960×540 groups of light-emitting diodes EDa, EDb, and EDc. The required number of main scan signal lines 151h can be 540, and the required number of data lines can be 960×3. To apply the scan signal to the main scan signal line 151h, some of the connecting wiring is used to connect the scan signal line 151v, while other connecting wiring is used according to a reference... Figure 1The described implementation uses dummy wiring 152 and 153. Each of the corresponding sides of a group of LEDs EDa, EDb, and EDc can have a connection wiring arranged in the x-axis direction, so the number of connection wirings may need to be twice the number of LEDs EDa, EDb, and EDc arranged in the y-axis direction. Therefore, the total number of connection wirings can be 960 × 2. The scan signal can be applied to the main scan signal line 151h using 540 connection wirings out of the 960 × 2 wirings, and according to... Figure 1 In an embodiment with three sub-regions 10-1, 10-2, and 10-3, the number of connecting wires used to connect the scan signal lines 151v is 540 × 3, and the same scan signal as that applied to the corresponding main scan signal line 151h is applied to the connecting scan signal lines 151v. It is sufficient for the number of connecting scan signal lines 151v to be equal to or greater than the number of main scan signal lines 151h; however, in embodiments, the number of connecting scan signal lines 151v can be various multiples of the number of main scan signal lines 151h, such as two, three, or four times.

[0076] Once the number of connected scan signal lines 151v is determined, the remaining number of connected wirings, obtained by subtracting the number of connected scan signal lines 151v from the total number of connected wirings, is the number of dummy wirings 152 and 153. In the implementation, as... Figure 1 As shown, a total of 300 connection wires are used as dummy wires 152 and 153. Two of the 300 connection wires are first dummy wires 152, and the remaining 298 are second dummy wires 153. In one embodiment, the connection wires are disposed on the corresponding sides of a group of light-emitting diodes EDa, EDb, and EDc. In other embodiments, the connection wires may be formed only on one side of a group of light-emitting diodes EDa, EDb, and EDc.

[0077] In the following text, the area where the connection wiring close to a group of light-emitting diodes EDa, EDb, and EDc is used as the connection for the scan signal line 151v will be referred to as the scan signal application area (or central area), and the area where dummy wirings 152 and 153 are provided will be referred to as the dummy area (or side area). The scan signal application area (or central area) represents the area where the scan signal is transmitted in the x-axis direction via the connection for the scan signal line 151v.

[0078] Now refer to Figure 2 The circuit configuration of the pixels set in the light-emitting display device 10 is described.

[0079] Figure 2 A schematic diagram of the equivalent circuit of a pixel of a light-emitting display device according to an embodiment is shown.

[0080] Figure 2 A circuit diagram is shown for three pixels, including a set of light-emitting diodes EDa, EDb, and EDc.

[0081] like Figure 2 As shown, a pixel may include a first pixel PXa, a second pixel PXb, and a third pixel PXc. The first pixel PXa, the second pixel PXb, and the third pixel PXc each include transistors T1, T2, and T3, a storage capacitor Cst, and light-emitting diodes EDa, EDb, and EDc (which are light-emitting devices). Pixels PXa, PXb, and PXc can be divided into light-emitting diodes EDa, EDb, and EDc and pixel circuitry, and the pixel circuitry may include... Figure 2 The system contains multiple transistors T1, T2, and T3, as well as a storage capacitor Cst.

[0082] Transistors T1, T2, and T3 can be configured with one driving transistor T1 (first transistor) and two switching transistors T2 and T3, wherein the two switching transistors T2 and T3 include an input transistor T2 (second transistor) and an initialization transistor T3 (third transistor). Each of transistors T1, T2, and T3 may include a gate electrode, a first electrode, and a second electrode, and includes a semiconductor layer, so that current flows to or is cut off from the semiconductor layer depending on the voltage at the gate electrode. Depending on the voltage applied to transistors T1, T2, and T3, one of the first electrode and the second electrode may be a source electrode, and the other electrode may be a drain electrode.

[0083] The gate electrode of the driving transistor T1 can be electrically connected to the first terminal of the storage capacitor Cst and to the second electrode (the electrode on the output side) of the input transistor T2. The first electrode of the driving transistor T1 can be electrically connected to the driving voltage line 172 for transmitting the driving voltage QVDD, and the second electrode of the driving transistor T1 can be electrically connected to the anode of the light-emitting diodes EDa, EDb, and EDc, the second terminal of the storage capacitor Cst, and the first electrode of the initialization transistor T3. The driving transistor T1 can receive data voltages DVa, DVb, and DVc through its gate electrode according to the switching operation of the input transistor T2, and can provide driving current to the light-emitting diodes EDa, EDb, and EDc according to the voltage at its gate electrode. The storage capacitor Cst stores and maintains the voltage at the gate electrode of the driving transistor T1.

[0084] The gate electrode of the input transistor T2 can be electrically connected to the scan signal line 151 used to transmit the scan signal SC. Here, the scan signal line 151 shown as being electrically connected to the gate electrode of the input transistor T2 can be... Figure 1The main scan signal line 151h. The first electrode of the input transistor T2 can be electrically connected to data lines 171a, 171b, and 171c for transmitting data voltages DVa, DVb, and DVc, and the second electrode of the input transistor T2 can be electrically connected to the first terminal of the storage capacitor Cst and the gate electrode of the driving transistor T1. Data lines 171a, 171b, and 171c can transmit data voltages DVa, DVb, and DVc, each with different values, and the input transistors T2 of pixels PXa, PXb, and PXc can be electrically connected to separate data lines. The gate electrodes of the corresponding input transistors T2 of pixels PXa, PXb, and PXc can be electrically connected to the same scan signal line 151 and can receive scan signals SC with the same timing. When the input transistors T2 of pixels PXa, PXb, and PXc are simultaneously turned on according to the scan signals SC with the same timing, the data voltages DVa, DVb, and DVc are transmitted to the gate electrode of the driving transistor T1 of the corresponding pixels PXa, PXb, and PXc and the first terminal of the storage capacitor Cst.

[0085] The gate electrode of the initialization transistor T3 can be electrically connected to the scan signal line 151 used to transmit the scan signal SC. Here, the scan signal line 151 shown as being electrically connected to the gate electrode of the initialization transistor T3 can be... Figure 1 The main scan signal line 151h. The first electrode of the initialization transistor T3 is connected to the second terminal of the storage capacitor Cst, the second electrode of the driving transistor T1, and the anodes of the light-emitting diodes EDa, EDb, and EDc. The second electrode of the initialization transistor T3 is connected to the initialization voltage line 173 for transmitting the initialization voltage VINT. As a result, the initialization transistor T3 initializes the second electrode of the driving transistor T1 (the terminal for outputting the output current), and initializes the anodes of the light-emitting diodes EDa, EDb, and EDc, as well as the second terminal of the storage capacitor Cst.

[0086] According to the embodiment, the initialization voltage line 173 can be used as a sensing wiring by sensing the voltage at the anodes of the light-emitting diodes EDa, EDb, and EDc before applying the initialization voltage VINT. The sensing operation can confirm whether the voltage at the anodes is maintained at the target voltage. The sensing operation and the initialization operation for transmitting the initialization voltage VINT can be performed at different times, and the initialization operation can be performed after the sensing operation is performed.

[0087] The initialization transistor T3 can be turned on together with the input transistor T2 according to the scan signal SC, thereby transmitting the initialization voltage VINT to the anodes of the light-emitting diodes EDa, EDb and EDc and the second terminal of the storage capacitor Cst, and initializing the voltage at the second terminal of the storage capacitor Cst and the anodes of the light-emitting diodes EDa, EDb and EDc.

[0088] The first terminal of the storage capacitor Cst can be electrically connected to the gate electrode of the driving transistor T1 and the second electrode of the input transistor T2, and the second terminal is electrically connected to the first electrode of the initialization transistor T3 and the anode of the light-emitting diodes EDa, EDb and EDc. Figure 2 The accompanying diagram provides reference numerals for the first and second terminals of the storage capacitor Cst to indicate that... Figure 3 Which part corresponds to the storage capacitor Cst? The first end of the storage capacitor Cst corresponds to the gate electrodes 155a, 155b, and 155c of the driving transistor T1, and the second end of the storage capacitor Cst is disposed on the lower storage electrodes 125a, 125b, and 125c and the upper storage electrodes 175a, 175b, and 175c. Taking the first pixel PXa as an example, a cross-sectional structure of the storage capacitor Cst is shown with reference to the image. Figure 4 The lower storage electrode 125a is disposed below the gate electrode 155a of the driving transistor T1 and is insulated between the lower storage electrode 125a and the gate electrode 155a. The upper storage electrode 175a is disposed above the gate electrode 155a in an insulated manner. The insulating layers 120, 140, and 160 disposed between the three layers (lower storage electrode 125a, gate electrode 155a, and upper storage electrode 175a) serve as dielectric layers, and the lower storage electrode 125a and the upper storage electrode 175a are electrically connected to each other. The storage capacitor Cst for pixels PXb and PXc may include a similar structure.

[0089] The cathodes of LEDs EDa, EDb, and EDc can receive a common voltage QVSS, and LEDs EDa, EDb, and EDc can emit light according to the output current value of the driving transistor T1 to present grayscale in their color.

[0090] According to an embodiment, additional capacitors may be further included connected to the anode and cathode of the light-emitting diodes EDa, EDb, and EDc. The additional capacitors maintain the voltage at each terminal of the light-emitting diodes EDa, EDb, and EDc, enabling the light-emitting diodes EDa, EDb, and EDc to output a constant brightness.

[0091] Now we will describe having Figure 2 The operation of pixels in the circuit.

[0092] Figure 2The illustration shows an embodiment where transistors T1, T2, and T3 are n-type transistors and have the characteristic of being turned on when a high-level voltage is applied to their gate electrodes. However, according to the embodiment, the corresponding transistors T1, T2, and T3 can be p-type transistors.

[0093] Each frame can begin at the end of the transmit segment. A high-level scan signal SC can be provided, and input transistor T2 and initialization transistor T3 can be turned on.

[0094] When the input transistor T2 is turned on, programming operations can be performed. The data voltages DVa, DVb, and DVc from data lines 171a, 171b, and 171c are input to the gate electrode of the drive transistor T1 through the turned-on input transistor T2 and to the first terminal of the storage capacitor Cst (and stored by the storage capacitor Cst).

[0095] Optionally, an initialization operation can be performed when the initialization transistor T3 is turned on. The voltage at the second terminal of the storage capacitor Cst, the second electrode of the driving transistor T1, and the anode of the light-emitting diodes EDa, EDb, and EDc can be changed to the initialization voltage VINT transmitted by the initialization voltage line 173 to perform the initialization process.

[0096] Data voltages DVa, DVb, and DVc, along with the initialization voltage VINT, are applied to the corresponding terminals of the storage capacitor Cst. When the initialization transistor T3 is turned on, when an output current is generated from the driving transistor T1, the output current can be output to the outside through the initialization transistor T3 and the initialization voltage line 173, thus the output current is not input to the light-emitting diodes EDa, EDb, and EDc. According to the embodiment, for the programming section used to provide a high-level scan signal SC, the driving voltage QVDD can be applied as a low-level voltage, or the common voltage QVSS can be applied as a high-level voltage, thereby preventing current from being applied to the light-emitting diodes EDa, EDb, and EDc.

[0097] When the scan signal SC goes low, the normally high-level driving voltage QVDD and the low-level common voltage QVSS are applied to the pixel, thereby executing the emission segment through the gate voltage of the driving transistor T1 stored in the storage capacitor Cst, so that the driving transistor T1 generates an output current and the output current flows to the light-emitting diodes EDa, EDb and EDc, and the light-emitting diodes EDa, EDb and EDc emit light.

[0098] Now refer to Figures 3 to 8 Describing in conjunction with the light-emitting display device 10, such as Figure 2 The detailed structure of the pixel circuit of the pixel configured as shown is illustrated.

[0099] Figures 3 to 8The configuration of a pixel circuit including transistors T1, T2, and T3 and a storage capacitor Cst is shown. The anodes of light-emitting diodes EDa, EDb, and EDc are not shown.

[0100] In a group of light-emitting diodes EDa, EDb, and EDc, such as Figure 1 As shown, LEDs EDa, EDb, and EDc are arranged in parallel along the y-axis, and each pixel circuit is positioned along the y-axis. (Reference) Figure 3 The first pixel circuit belonging to the first pixel PXa is located at the top, the second pixel circuit belonging to the second pixel PXb is located below the first pixel PXa, and the third pixel circuit belonging to the third pixel PXc is located at the bottom. The first pixel circuit to the third pixel circuit are referred to as a group of pixel circuits.

[0101] Figures 3 to 5 The structure of the pixel circuit of the pixel disposed in the scan signal application area (central area) of the light-emitting display device 10 is shown, and Figures 6 to 8 The structure of a pixel circuit for a pixel located in a dummy region (side region) is shown.

[0102] Now refer to Figures 3 to 5 This describes the configuration of the pixel circuitry set in the scanning signal application area (central area).

[0103] Figure 3 A schematic top view of pixels disposed in the scanning signal application area of ​​a light-emitting display device according to an embodiment is shown, and Figure 4 and Figure 5 The light-emitting display device is shown relative to Figure 3 Sectional views of lines IV-IV and VV.

[0104] Now refer to Figure 4 The stacking structure of the light-emitting display device 10 according to the embodiment is described.

[0105] The light-emitting display device may include a substrate 110. The substrate 110 may include an insulating material such as glass or plastic, and may be flexible.

[0106] A first conductive layer, a first insulating layer 120, a semiconductor layer, a second insulating layer 140, a second conductive layer, a third insulating layer 160, a third conductive layer, and a fourth insulating layer 180 are sequentially disposed on a substrate 110. The first insulating layer 120 and the second insulating layer 140 may be inorganic insulating layers comprising inorganic insulating materials, and the third insulating layer 160 and the fourth insulating layer 180 may be organic insulating layers comprising organic insulating materials. According to an embodiment, the respective insulating layers may be made of multiple layers, and according to an embodiment, the third insulating layer 160 may be an inorganic insulating layer. The inorganic insulating material may include silicon nitride (SiN). x ), silicon oxide (SiO) x The conductive layer may contain silicon oxynitride (SiON) and organic insulating materials, including polyimide, acryloyl-based polymers, and siloxane-based polymers. Furthermore, the first, second, and third conductive layers may contain at least one metal selected from copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof. The first, second, and third conductive layers may be made of a single layer or multiple layers. For example, they may have a multilayer structure including a lower layer of titanium and an upper layer of copper. The semiconductor layer may include semiconductor materials such as amorphous silicon, polycrystalline silicon, or oxide semiconductors. In embodiments, semiconductor layers including oxide semiconductors will be described.

[0107] The scan signal line 151 may include a main scan signal line 151h and a connecting scan signal line 151v.

[0108] The main scan signal line 151h can extend in the y-axis direction, can be set for each group of pixel circuits, and can be formed as a single layer in the third conductive layer.

[0109] The connecting scan signal line 151v extends in the x-axis direction, and a pair of connecting scan signal lines 151vl and 151vr are on the left and right sides of each group of pixel circuits. The pair of connecting scan signal lines 151vl and 151vr includes a portion having a three-layer structure, and is deployed in the first conductive layer as the first connecting scan signal line 151-1vl and 151-1vr, in the second conductive layer as the second connecting scan signal line 151-2vl and 151-2vr, and in the third conductive layer as the third connecting scan signal line 151-3vl and 151-3vr. First connection scan signal lines 151-1vl and 151-1vr are continuously arranged in the x-axis direction, and second connection scan signal lines 151-2vl and 151-2vr and third connection scan signal lines 151-3vl and 151-3vr extend in the x-axis direction within a predetermined area and are electrically connected to the first connection scan signal lines 151-1vl and 151-1vr to reduce wiring resistance. (Reference) Figure 5 The first connection scan signal lines 151-1vl and 151-1vr are electrically connected to the third connection scan signal lines 151-3vl and 151-3vr through openings in the first insulating layer 120, the second insulating layer 140, and the third insulating layer 160. The third connection scan signal lines 151-3vl and 151-3vr are electrically connected to the second connection scan signal lines 151-2vl and 151-2vr through an opening in the third insulating layer 160. In an embodiment, the first connection scan signal lines 151-1vl and 151-1vr are not directly connected to the second connection scan signal lines 151-2vl and 151-2vr. However, according to an embodiment, the connection scan signal lines 151vl and 151vr can have various connection relationships, and they can have a double-layer or single-layer structure.

[0110] One of the scanning signal lines 151vl and 151vr is electrically connected to a main scanning signal line 151h, and according to reference... Figure 1 In the described embodiment, a main scan signal line 151h is electrically connected to three connecting scan signal lines 151v. At the portions where connecting scan signal lines 151vl and 151vr are electrically connected to the main scan signal line 151h, and at the portions where first connecting scan signal lines 151-1vl and 151-1vr are located, they are electrically connected to the main scan signal line 151h via openings 150ol and 150or. Openings 150ol and 150or are not limited to the portions where the first connecting scan signal lines 151-1vl and 151-1vr are located, and openings 150ol and 150or can be located within the portions electrically connected to the main scan signal line 151h. Figure 3Both openings 150ol and 150or are shown to illustrate their positions within the area where the scan signal is applied (central region). In other embodiments, only one of the two openings 150ol and 150or located on the respective side may be deployed, or both openings 150ol and 150or may be omitted.

[0111] The main scan signal line 151h is electrically connected to the second gate electrode 156 and the third gate electrode 157 through an opening. The scan signal controls the input transistor T2 and the initialization transistor T3, which are included in a set of pixel circuits, through the electrically connected gate electrodes 156 and 157.

[0112] Data lines 171a, 171b, and 171c extend in the x-axis direction and are disposed on one side of the pixel circuit. Data lines 171a, 171b, and 171c may include a portion with a three-layer structure: first data lines 171-1a, 171-1b, and 171-1c may be disposed in a first conductive layer; second data lines 171-2a, 171-2b, and 171-2c may be disposed in a second conductive layer; and third data lines 171-3a, 171-3b, and 171-3c may be disposed in a third conductive layer. First data lines 171-1a, 171-1b, and 171-1c are continuously arranged in the x-axis direction, and second data lines 171-2a, 171-2b, and 171-2c and third data lines 171-3a, 171-3b, and 171-3c extend in the x-axis direction within a predetermined area and are electrically connected to the first data lines 171-1a, 171-1b, and 171-1c to reduce wiring resistance. Similar to... Figure 5 The connection structure for connecting scan signal lines 151vl and 151vr, and the connection structure for the three layers of data lines 171a, 171b, and 171c, can be a structure where the first conductive layer is connected to the third conductive layer and the third conductive layer is connected to the second conductive layer. The three layers can be electrically connected to each other. The first data lines 171-1a, 171-1b, and 171-1c can be electrically connected to the third data lines 171-3a, 171-3b, and 171-3c through openings in the first insulating layer 120, the second insulating layer 140, and the third insulating layer 160, and the third data lines 171-3a, 171-3b, and 171-3c can be electrically connected to the second data lines 171-2a, 171-2b, and 171-2c through openings in the third insulating layer 160. In this implementation, the first data lines 171-1a, 171-1b, and 171-1c are not directly connected to the second data lines 171-2a, 171-2b, and 171-2c, but the implementation is not limited to this. The data lines 171a, 171b, and 171c can be connected in various ways, and they can have a double-layer or single-layer structure.

[0113] For data lines 171a, 171b and 171c, the first data lines 171-1a, 171-1b and 171-1c are electrically connected to the second semiconductors 132a, 132b and 132c respectively via connecting members 177a, 177b and 177c, wherein the connecting members 177a, 177b and 177c are disposed in a third conductive layer on the portions of which the first data lines 171-1a, 171-1b and 171-1c are disposed.

[0114] Therefore, although a single scan signal line 151 is connected to three pixels PXa, PXb, and PXc arranged in a column, different data voltages DVa, DVb, and DVc can be received via data lines 171a, 171b, and 171c. The corresponding light-emitting diodes EDa, EDb, and EDc of the respective pixels PXa, PXb, and PXc can output different levels of brightness.

[0115] The drive voltage line 172 used to transmit the drive voltage QVDD may include main drive voltage lines 172vl and 172vr and sub-drive voltage lines 172h-1 and 172h-2.

[0116] The main driving voltage lines 172vl and 172vr can extend in the x-axis direction, and a pair of main driving voltage lines 172vl and 172vr can be disposed on corresponding sides of the pixel circuit. The sub-driving voltage lines 172h-1 and 172h-2 can extend in the y-axis direction and can be formed in pairs on the top and bottom of each group of pixel circuits. The driving voltage lines 172 are wired in a grid structure in both the x-axis and y-axis directions to prevent voltage drop of the driving voltage QVDD in any area of ​​the display area.

[0117] The main drive voltage lines 172vl and 172vr may include a portion having a three-layer structure. The first main drive voltage lines 172-1vl and 172-1vr may be disposed in a first conductive layer, the second main drive voltage lines 172-2vl and 172-2vr may be disposed in a second conductive layer, and the third main drive voltage lines 172-3vl and 172-3vr may be disposed in a third conductive layer. The first main drive voltage lines 172-1vl and 172-1vr may be continuously disposed in the x-axis direction, and the second and third main drive voltage lines 172-2vl and 172-2vr and the third main drive voltage lines 172-3vl and 172-3vr may extend in the x-axis direction within a predetermined region and may be electrically connected to the first main drive voltage lines 172-1vl and 172-1vr to reduce wiring resistance. In the three-layer connection structure of the main drive voltage lines 172VL and 172VR, the first conductive layer can be connected to the third conductive layer, and the third conductive layer can be connected to the second conductive layer, similar to... Figure 5The three layers are electrically connected to each other in a manner similar to the connection structure of the connection scan signal lines 151vl and 151vr. The first main drive voltage lines 172-1vl and 172-1vr can be electrically connected to the third main drive voltage lines 172-3vl and 172-3vr through openings in the first insulating layer 120, the second insulating layer 140, and the third insulating layer 160, and the third main drive voltage lines 172-3vl and 172-3vr are electrically connected to the second main drive voltage lines 172-2vl and 172-2vr through an opening in the third insulating layer 160. In an embodiment, the first main drive voltage lines 172-1vl and 172-1vr are not directly connected to the second main drive voltage lines 172-2vl and 172-2vr. However, the embodiment is not limited to this, and the main drive voltage lines 172vl and 172vr can be electrically connected in various ways, and they can have a double-layer or single-layer structure.

[0118] Sub-driving voltage lines 172h-1 and 172h-2 are configured as a single layer in the third conductive layer.

[0119] The two main drive voltage lines 172Vl and 172Vr are electrically connected to the two sub-drive voltage lines 172H-1 and 172H-2. (Refer to...) Figure 3 In the described embodiment, the main driving voltage line 172vl disposed on the left side of the pixel circuit is electrically connected to the sub-driving voltage line 172h-1 disposed on the top side of the pixel circuit, and the main driving voltage line 172vr disposed on the right side of the pixel circuit is electrically connected to the sub-driving voltage line 172h-2 disposed on the bottom side of the pixel circuit. Regarding the connection relationship, the main driving voltage line 172vl and the sub-driving voltage line 172h-1 can be directly connected to the third conductive layer. The third main driving voltage line 172-3vl belonging to the main driving voltage line 172vl can extend in the y-axis direction to form the sub-driving voltage line 172h-1. Furthermore, the third main driving voltage line 172-3vr belonging to the main driving voltage line 172vr can extend in the y-axis direction and can be integrally formed with the sub-driving voltage line 172h-2.

[0120] The main driving voltage line 172vl, located on the left side of the pixel circuit, is electrically connected to the first semiconductors 131a, 131b, and 131c via a connecting member 172c. The connecting member 172c is disposed in a third conductive layer on a portion of which the first main driving voltage line 172-1vl is disposed in a first conductive layer. The first main driving voltage line 172-1vl is electrically connected to the connecting member 172c via an opening, and the connecting member 172c is electrically connected to the first semiconductors 131a, 131b, and 131c via an opening, thereby transmitting the driving voltage QVDD to the first semiconductors 131a, 131b, and 131c.

[0121] An initialization voltage line 173 for transmitting the initialization voltage VINT is disposed on the left side of the pixel circuit, extending in the x-axis direction, and may include a portion with a three-layer structure. A first initialization voltage line 173-1v may be disposed in a first conductive layer, a second initialization voltage line 173-2v may be disposed in a second conductive layer, and a third initialization voltage line 173-3v may be disposed in a third conductive layer. The first initialization voltage line 173-1v may be continuously disposed in the x-axis direction, and the second and third initialization voltage lines 173-2v and 173-3v may extend in the x-axis direction within a predetermined region and may be electrically connected to the first initialization voltage line 173-1v to reduce wiring resistance. In the three-layer connection structure of the initialization voltage line 173, the first conductive layer may be connected to the third conductive layer, and the third conductive layer may be connected to the second conductive layer, thus similar to the reference. Figure 5 The three layers are electrically connected to each other as described by the connection scan signal lines 151vl and 151vr. The first initialization voltage line 173-1v is electrically connected to the third initialization voltage line 173-3v through openings in the first insulating layer 120, the second insulating layer 140, and the third insulating layer 160, and the third initialization voltage line 173-3v is electrically connected to the second initialization voltage line 173-2v through an opening in the third insulating layer 160. In an embodiment, the first initialization voltage line 173-1v is not directly connected to the second initialization voltage line 173-2v. However, the embodiment is not limited to this, and the initialization voltage lines 173 can be electrically connected in various ways, and they can have a double-layer or single-layer structure.

[0122] An initialization voltage line 173 is electrically connected to third semiconductors 133a, 133b, and 133c via a connecting member 173c. The connecting member 173c is disposed in the third conductive layer on the portion of which the first initialization voltage line 173-1v is disposed in the first conductive layer. The first initialization voltage line 173-1v can be electrically connected to the connecting member 173c through an opening, and the connecting member 173c can be electrically connected to the third semiconductors 133a, 133b, and 133c through an opening, such that the initialization voltage VINT is transmitted to the third semiconductors 133a, 133b, and 133c.

[0123] Transistors T1, T2, and T3 may have the same stacked structure and include a gate electrode disposed in a second conductive layer, a channel disposed in a semiconductor layer, and a first region and a second region disposed on corresponding sides of the channel and doped to have the same / similar properties as the conductor. Here, the first region and the second region disposed in the semiconductor layer may correspond to a reference. Figure 2 The first and second electrodes are described.

[0124] The corresponding transistor will now be described in detail.

[0125] The driving transistor T1 includes a channel, a first region, and a second region disposed in first semiconductors 131a, 131b, and 131c on a first insulating layer 120, and the first and second regions are doped to have the same or similar conductivity characteristics as conductors. The first region of the first semiconductors 131a, 131b, and 131c is electrically connected to the main driving voltage line 172vl through an opening and a connection member 172c to receive the driving voltage QVDD. The second region of the first semiconductors 131a, 131b, and 131c is electrically connected to the upper storage electrodes 175a, 175b, and 175c disposed in a third conductive layer through an opening, and is electrically connected to the lower storage electrodes 125a, 125b, and 125c and the third semiconductors 133a, 133b, and 133c through additional openings disposed in the first conductive layer. The first semiconductors 131a, 131b, and 131c are covered by a second insulating layer 140, and gate electrodes 155a, 155b, and 155c are formed on the second insulating layer 140. In the plan view, a channel is formed in the portion of the first semiconductors 131a, 131b, and 131c that overlaps with the gate electrodes 155a, 155b, and 155c, and the channel is covered by the gate electrodes 155a, 155b, and 155c and is not doped. The gate electrodes 155a, 155b, and 155c are electrically connected to the second semiconductors 132a, 132b, and 132c through openings and connecting members 176a, 176b, and 176c. Here, the connecting members 176a, 176b, and 176c are disposed in the third conductive layer.

[0126] The input transistor T2 includes a channel, a first region, and a second region disposed on a first insulating layer 120 in second semiconductors 132a, 132b, and 132c, and the first and second regions are doped to have the same or similar conductivity characteristics as conductors. The first region of the second semiconductors 132a, 132b, and 132c is electrically connected to data lines 171a, 171b, and 171c through openings and connecting members 177a, 177b, and 177c to receive data voltages DVa, DVb, and DVc. The second region of the second semiconductors 132a, 132b, and 132c is electrically connected to gate electrodes 155a, 155b, and 155c through openings and connecting members 176a, 176b, and 176c. The connecting members 176a, 176b, and 176c extend toward the channel of the second semiconductors 132a, 132b, and 132c to cover the channel. Second semiconductors 132a, 132b, and 132c are covered by a second insulating layer 140, and a second gate electrode 156 is formed on the second insulating layer 140. In the plan view, a channel is formed in the portion of the second semiconductors 132a, 132b, and 132c that overlaps with the second gate electrode 156, and the channel is covered by the second gate electrode 156 and is not doped. The second gate electrode 156 extends to be electrically connected to the main scan signal line 151h through an opening.

[0127] The initialization transistor T3 includes a channel, a first region, and a second region in third semiconductors 133a, 133b, and 133c disposed on a first insulating layer 120, and the first and second regions are doped to have the same or similar conductivity characteristics as conductors. The first region of the third semiconductors 133a, 133b, and 133c is electrically connected to the upper storage electrodes 175a, 175b, and 175c disposed in the third conductive layer through an opening, and is also electrically connected to the lower storage electrodes 125a, 125b, and 125c disposed in the first conductive layer and the first semiconductors 131a, 131b, and 131c disposed in the second conductive layer through an additional opening. The second region of the third semiconductors 133a, 133b, and 133c is electrically connected to the initialization voltage line 173 through an opening and a connection member 173c and receives the initialization voltage VINT. The third semiconductors 133a, 133b, and 133c are covered by a second insulating layer 140, and a third gate electrode 157 is formed on the second insulating layer 140. In the plan view, the channel is formed in the portion of the third semiconductors 133a, 133b, and 133c that overlaps with the third gate electrode 157, and the channel is covered by the third gate electrode 157 and is not doped. The third gate electrode 157 extends to be electrically connected to the main scan signal line 151h through an opening.

[0128] like Figure 4As shown, the storage capacitor Cst includes a first storage capacitor Cst1 and a second storage capacitor Cst2.

[0129] The first storage capacitor Cst1 includes gate electrodes 155a, 155b, and 155c disposed in a second conductive layer, a third insulating layer 160 disposed on the gate electrodes 155a, 155b, and 155c, and upper storage electrodes 175a, 175b, and 175c disposed on the third insulating layer 160. The second storage capacitor Cst2 includes lower storage electrodes 125a, 125b, and 125c disposed in a first conductive layer, a first insulating layer 120 and a second insulating layer 140 disposed on the lower storage electrodes 125a, 125b, and 125c, and gate electrodes 155a, 155b, and 155c disposed on the first insulating layer 120 and the second insulating layer 140. As a result, a three-layer structure is provided, having storage electrodes (upper storage electrodes 175a, 175b and 175c that overlap each other in a plan view from top to bottom, and lower storage electrodes 125a, 125b and 125c) and common gate electrodes 155a, 155b and 155c.

[0130] The lower storage electrodes 125a, 125b and 125c are electrically connected to the upper storage electrodes 175a, 175b and 175c through openings, and the gate electrodes 155a, 155b and 155c are commonly included in the first storage capacitor Cst1 and the second storage capacitor Cst2. Therefore, the first storage capacitor Cst1 and the second storage capacitor Cst2 have a structure that is connected in parallel according to the circuit structure.

[0131] Upper storage electrodes 175a and 175b are integrally formed and may include anode connection members 179a and 179b extending on one side. Anode connection members 179a and 179b are electrically connected to the anodes (not shown) of light-emitting diodes EDa and EDb through openings 185a and 185b in the fourth insulating layer 180.

[0132] The upper storage electrode 175c does not include an extended anode connection member, and it is electrically connected to the anode (not shown) of the light-emitting diode EDc through an opening 185c provided in the upper portion of the upper storage electrode 175c.

[0133] According to the reference Figure 3 According to the described embodiment, in a set of light-emitting diodes EDa, EDb and EDc, the first light-emitting diode EDa is located on the left, the second light-emitting diode EDb is located on the right, and the third light-emitting diode EDc is located in the center.

[0134] LEDs EDa, EDb, and EDc include the anode (reference) Figure 15 191), emission layer (reference) Figure 15 370) and cathode (reference) Figure 15 (270), and the anode is disposed on the fourth insulating layer 180. Separator wall (reference) Figure 15 The 350) can be configured to separate the light-emitting diodes EDa, EDb and EDc (LED) from each other, and the separator wall can expose the anode, the emission layer can be formed through the exposed part, and the cathode can be disposed on the emission layer.

[0135] According to an embodiment, the emission layer can be located in an opening in the partition wall, and according to a reference... Figure 15 In the described embodiment, an emission layer 370 is formed on the exposed anode 191 and the partition wall 350. A cathode 270 is formed on the emission layer 370. According to the following... Figure 15 In one implementation, the emitter layer 370 and the cathode 270 can be integrally disposed without using a mask.

[0136] An encapsulation layer, color conversion layer, or color filter can be placed on the upper portion of the light-emitting diodes EDa, EDb, and EDc, which will be referred to later in the specification. Figure 15 Describe it.

[0137] Already referenced Figures 3 to 5 The configuration of the pixel circuitry set in the scanning signal application area (or central area) is described.

[0138] Now refer to Figures 6 to 8 This describes the configuration of pixel circuits for pixels set in a dummy region (or side region).

[0139] Now refer to Figure 6 This describes the configuration of the pixel circuitry located on the outermost left side in the dummy region (or side region).

[0140] Figure 6 A top view of a pixel disposed on the outermost left side of a light-emitting display device according to an embodiment is shown.

[0141] Reference Figure 3 Compared to the described configuration, in Figure 6In the outermost pixel circuit on the left, a first dummy wiring 152 is provided to replace the connecting scan signal line 151vl provided on the left side of the pixel circuit. The first dummy wiring 152 is a single layer and is provided in the first conductive layer. The first dummy wiring 152 is narrower than the connecting scan signal line 151vl, and as a result, the gap between the left edge of the substrate of the light-emitting display device 10 and the first dummy wiring 152 is equal to or greater than about 50 μm. The width of the first dummy wiring 152 is controlled such that the gap between the left edge of the substrate and the first dummy wiring 152 can be equal to or greater than about 50 μm. The width of the first dummy wiring 152 can be equal to or greater than about 5 μm and equal to or less than about 10 μm, and the width of the connecting scan signal line 151vl can be about 15 μm. According to the embodiment, the width of the wiring can be changed.

[0142] A cutoff voltage (Voff) in the scan signal used to keep the transistor in the off state can be applied to the first dummy wiring 152. The first dummy wiring 152 is narrow and can have a relatively large resistance. Therefore, the first dummy wiring 152 can have a large voltage drop value, so a voltage value that might cause errors when using a lower voltage value for the first dummy wiring 152 in the pixel circuit is not applied to it. Furthermore, according to embodiments, the first dummy wiring 152 can be floated without being energized, or other voltages can be applied to the first dummy wiring 152.

[0143] By forming the first dummy wiring 152 as narrow, the gap between the left edge of the substrate and the first dummy wiring 152 can be equal to or greater than about 50 μm, thereby providing sufficient tolerance or allowance in processes such as laser beam cutting when attaching another light-emitting display device 10 to the left to form a large display device. As a result, when the large display device is completed, the gap between the light-emitting diodes EDa, EDb, and EDc can remain constant, thereby improving the display quality of the large display device.

[0144] and Figure 3 Conversely, according to the reference Figure 6 In the described embodiment, a second dummy wiring 153r is provided to replace the connecting scan signal line 151vr provided on the right side of the pixel circuit. The second dummy wiring 153r is provided on one side of the pixel circuit located on the outermost left side, and on the side where the first dummy wiring 152 is not provided. The second dummy wiring 153r is a single layer and is provided in the first conductive layer. The second dummy wiring 153r may have the same width as the connecting scan signal line 151vr. The widths of the second dummy wiring 153r and the connecting scan signal line 151vr may be approximately 15 μm. According to the embodiment, the width of the wiring is variable.

[0145] Now refer to Figure 7 This describes the configuration of pixel circuits that are not set on the outermost side in a dummy region (or side region).

[0146] Figure 7 A schematic top view of pixels disposed in a dummy area of ​​a light-emitting display device according to an embodiment is shown.

[0147] and Figure 3 Compared to the configuration shown, the connection between scan signal lines 151vl and 151vr is not located on the corresponding side of the pixel circuit, and... Figure 7 In the pixel circuit shown, second dummy wirings 153l and 153r are used instead. The second dummy wirings 153l and 153r are configured as a single layer and disposed within the first conductive layer. The second dummy wirings 153l and 153r can have the same width as the connecting scan signal lines 151vl and 151vr. For example, the width of the second dummy wirings 153l and 153r, as well as the connecting scan signal lines 151vl and 151vr, can be approximately 15 μm. According to the embodiment, the width of the wiring is variable.

[0148] The cutoff voltage (Voff) in the scan signal used to keep the transistors in the off state can be applied to the second dummy wirings 153l and 153r. According to the embodiment, no voltage may be applied to the second dummy wirings 153l and 153r, so that they can float, or other voltages may be applied to the second dummy wirings 153l and 153r.

[0149] Now refer to Figure 8 Describes the configuration of the pixel circuitry set on the outermost right side in the dummy region (or side region).

[0150] Figure 8 A top view of a pixel disposed on the outermost right side of a light-emitting display device according to an embodiment is shown.

[0151] Reference Figure 3 Compared to the described configuration, in the settings Figure 8 In the outermost pixel circuit on the right, a first dummy wiring 152 is provided to replace the connecting scan signal line 151vr provided on the right side of the pixel circuit. Furthermore, a second dummy wiring 153l is provided to replace the connecting scan signal line 151vl provided on the left side of the pixel circuit. The second dummy wiring 153l is provided on one side of the outermost pixel circuit on the right, and on the side where the first dummy wiring 152 is not provided.

[0152] The first dummy wiring 152 is configured as a single layer and disposed within the first conductive layer. The first dummy wiring 152 is narrower than the connecting scan signal line 151vr, and as a result, the gap between the right edge of the substrate of the light-emitting display device 10 and the first dummy wiring 152 is equal to or greater than approximately 50 μm. The width of the first dummy wiring 152 is controlled such that the gap between the right edge of the substrate and the first dummy wiring 152 can be equal to or greater than approximately 50 μm. The width of the first dummy wiring 152 can be equal to or greater than approximately 5 μm and equal to or less than approximately 10 μm, and the width of the connecting scan signal line 151vr can be approximately 15 μm. According to an embodiment, the width of the wiring is variable.

[0153] A cutoff voltage (Voff) in the scan signal used to keep the transistor in the off state can be applied to the first dummy wiring 152. The first dummy wiring 152 is narrow and therefore has a relatively large resistance and a large voltage drop, so when the voltage value is reduced in the case of using the first dummy wiring 152 in pixel circuitry, a potentially faulty voltage can be avoided. According to embodiments, the first dummy wiring 152 may not be energized, allowing it to float, or other voltages may be applied to the first dummy wiring 152.

[0154] By forming the first dummy wiring 152 as narrow, the gap between the right edge of the substrate and the first dummy wiring 152 can be equal to or greater than about 50 μm, thereby providing sufficient tolerance or allowance in processes such as laser beam cutting when attaching another light-emitting display device 10 to the right side of the light-emitting display device 10 to form a large display device. As a result, when the large display device is completed, the gap between the light-emitting diodes EDa, EDb, and EDc can remain constant, thereby improving the display quality of the large display device.

[0155] The second dummy wiring 153l is a single layer and is disposed within the first conductive layer. The second dummy wiring 153l may have the same width as the connecting scan signal line 151vl. For example, the width of the second dummy wiring 153l and the connecting scan signal line 151vl may be approximately 15 μm. According to the embodiment, the width of the wiring is variable.

[0156] when Figure 6 and Figure 8 When the LEDs are positioned on the outermost left and outermost right sides to attach other light-emitting display devices 10 to the left and right sides of the light-emitting display device 10, the gap between the LEDs EDa, EDb and EDc can remain constant.

[0157] refer to Figure 1On the underside of the light-emitting display device 10, the width of the wiring is not reduced, and this is because the gap between the lower edge of the substrate and the pixel circuit is equal to or greater than about 50 μm. Therefore, another light-emitting display device 10 can be attached to the underside of the light-emitting display device 10, and the gap between the light-emitting diodes EDa, EDb, and EDc can remain constant.

[0158] refer to Figure 1 The driving area is located on the upper side of the light-emitting display device 10 and has a width equal to or greater than about 50 μm.

[0159] Already referenced Figure 1 A light-emitting display device 10 in which the driving region is disposed on the upper side is described, and according to an embodiment, the driving region may be disposed on the lower side. Reference will now be made to... Figure 9 Describe a light-emitting display device in which the driving area is disposed on the lower side.

[0160] Figure 9 A schematic diagram of a light-emitting display device according to an embodiment is shown.

[0161] like Figure 9 As shown, for the light-emitting display device 10', the driving region is disposed on the lower side, and the data driver 20 and the scan driver 30 can be disposed on the lower side and can be mounted on the substrate in the form of chips.

[0162] Figure 9 Sub-regions in the light-emitting display device 10' are not shown, and for ease of explanation, a data driver 20 and a scan driver 30 are shown, with sub-regions omitted. However, according to embodiments, the light-emitting display devices 10 and 10' may each include a data driver 20 and a scan driver 30.

[0163] Figure 9 The positions of corresponding portions in the light-emitting display device 10' are indicated by letters. L represents the left non-display area of ​​the light-emitting display device 10', and R represents the right non-display area of ​​the light-emitting display device 10'. U represents the upper region, and D represents the lower region. LU represents the upper region of the left non-display area, and RD represents the lower region of the right non-display area. LL represents the central region on the left, and RR represents the central region on the right. Here, the left non-display area refers to the region from the left edge of the substrate to the outermost left pixel circuit, and the right non-display area refers to the region from the right edge of the substrate to the outermost right pixel circuit.

[0164] Figure 9 The width of the non-display area on the outer side is shown according to an embodiment. For Figure 9The light-emitting display device 10' shown has a gap of approximately 50 μm between the outermost pixel circuit on the corresponding side and the edge of the substrate, and on the upper side where no driving region is provided, the gap between the pixel circuit and the edge of the substrate is approximately 50 μm. Other light-emitting display devices can be attached to the top, right, and left sides of the light-emitting display device 10', and the gap between the light-emitting diodes EDa, EDb, and EDc can remain constant.

[0165] refer to Figure 9 The center line between adjacent pixel circuits on the right and left sides is shown as a solid line, and the gap from one pixel circuit to the center line is set to approximately 40.2 μm. Therefore, when there is no... Figure 6 and Figure 8 When the first dummy wiring 152 is set as shown, the gap to the right and left edges of the substrate becomes approximately 40.2 μm, which can be less than the approximately 50 μm required to provide sufficient tolerance or allowance for cutting and attaching other light-emitting display devices. When another light-emitting display device is attached to the right or left side, the gap between the light-emitting diodes EDa, EDb, and EDc may become different and degrade the quality of the displayed image.

[0166] However, in an implementation, a narrow first dummy wiring 152 can be provided, and the gap between the edge of the substrate and the pixel circuit can be controlled to be equal to or greater than about 50 μm, which is required to provide sufficient tolerance or margin, so as to display accurate images when manufacturing large display devices.

[0167] Reference Figure 10 Describe the configuration of a large display device according to the implementation method.

[0168] Figure 10 A schematic diagram of a large display device according to an embodiment is shown.

[0169] according to Figure 10 The large display device of the embodiment shown can be manufactured by attaching four light-emitting display devices 10 or 10'.

[0170] For the corresponding light-emitting display devices 10 and 10', the driving area and the display area are distinguished and shown by solid lines, and as shown in the figure. Figure 9 As shown, only one data driver 20 and one scan driver 30 are shown for each of the light-emitting display devices 10 and 10', and no sub-regions are shown. Although Figure 10 The illustrations of the light-emitting display devices 10 and 10' have been simplified, but as... Figure 1 As shown, the light-emitting display devices 10 and 10' may include multiple sub-regions, multiple data drivers 20, and multiple scan drivers 30.

[0171] refer to Figure 10 The driving region can be disposed on the lateral sides of the two light-emitting display devices 10 on the upper side, attached to each other in the y-axis direction. A narrow first dummy wiring 152 can be disposed on the lateral sides where the two light-emitting display devices 10 are attached. Before attaching the two light-emitting display devices 10 to their lateral sides, the gap between the first dummy wiring 152 and the edge of the substrate can be equal to or greater than approximately 50 μm. Figure 10 As shown, after attaching the two light-emitting display devices 10 to their lateral sides, the gap between the two first dummy wirings 152 can be adjusted to... Figure 9 The gap shown is twice that of approximately 40.2 μm. As a result, the gap between pixel circuits or light-emitting diodes EDa, EDb, and EDc that are adjacent to each other on two different light-emitting display devices 10, but after the two different light-emitting display devices 10 are attached, becomes the same as the gap between other pixels in each of the light-emitting display devices 10.

[0172] For two light-emitting display devices 10' whose driving region can be disposed on the lower side, a narrow first dummy wiring 152 can be disposed on the lateral side that is attached to each other in the y-axis direction. For the two light-emitting display devices 10' before the lateral side can be attached, the gap between the first dummy wiring 152 and the edge of the substrate is equal to or greater than about 50 μm. Figure 10 After the two light-emitting display devices 10' are attached to each other as shown, the gap between the two first dummy wires 152 can be adjusted to... Figure 9 The gap shown is twice that of approximately 40.2 μm. As a result, the gap between the pixel circuits or light-emitting diodes EDa, EDb, and EDc that are adjacent to each other on two different light-emitting display devices 10' but after the two different light-emitting display devices 10' are attached becomes the same as the gap between other pixels in each of the light-emitting display devices 10'.

[0173] For the portions of the light-emitting display device 10 in which the driving region can be disposed on the upper side and the light-emitting display device 10' in which the driving region is disposed on the lower side, which are attached to each other in the x-axis direction, the space gap disposed on the edge portion of the substrate has an edge equal to or greater than about 50 μm, so that when attached after a process such as laser beam cutting, the gap between adjacent pixel circuits or light-emitting diodes EDa, EDb and EDc is the same as that of other portions.

[0174] Now refer to Figure 11 and Figure 12 Describe the implementation method of the modification.

[0175] Now refer to Figure 11This describes an implementation with a modified configuration of the drive voltage line 172 used to transmit the drive voltage QVDD.

[0176] Figure 11 A top view is shown of pixels disposed in the scanning signal application area of ​​a light-emitting display device according to an embodiment.

[0177] Reference Figure 11 In the described implementation, compared with the reference Figure 3 The described implementations differ, and in order to reduce the resistance of the drive voltage line 172, additional wiring (drive voltage line extension 172e, and additional drive voltage lines 172-1e and 172-2e) may be included.

[0178] Now we will describe it in more detail with Figure 3 Different configurations of drive voltage line 172.

[0179] In the main driving voltage line 172vl located on the left side of the pixel circuit, the first main driving voltage line 172-1vl located in the first conductive layer also includes a driving voltage line extension 172e that protrudes to the right in the y-axis direction below the main scan signal line 151h and the sub-driving voltage line 172h-2.

[0180] The drive voltage line extension 172e also includes a first additional drive voltage line 172-1e that protrudes from and extends downward from the first main drive voltage line 172-1vl in the y-axis direction. A second additional drive voltage line 172-2e disposed in the second conductive layer is disposed on the two first additional drive voltage lines 172-1e of the drive voltage line extension 172e.

[0181] In the plan view, the first additional driving voltage line 172-1e and the second additional driving voltage line 172-2e overlap each other and are electrically connected to each other through an opening. However, according to an embodiment, it may further include a third additional driving voltage line disposed in a third conductive layer, and it may be as follows: Figure 5 The diagram shows the connection of three layers.

[0182] The first additional driving voltage line 172-1e extends in the x-axis direction and can be connected to the sub-driving voltage line 172h-1 disposed in the third conductive layer through an opening.

[0183] As mentioned above, in such Figure 11 In the illustrated embodiment, including the drive voltage line extension 172e and the additional drive voltage lines 172-1e and 172-2e reduces the resistance in the wiring for applying the drive voltage QVDD without increasing the area of ​​the pixel circuit, because the additional components (drive voltage line extension 172e and additional drive voltage lines 172-1e and 172-2e) are disposed in the pixel circuit. Figure 3 In the implementation method, the unused space.

[0184] In other embodiments, additional voltage wiring can be formed to further reduce wiring resistance by adding components.

[0185] Figure 12 An embodiment is shown in which the gap between the edge of the substrate and the pixel circuitry can be less than a margin of about 50 μm, and the width of the first dummy wiring 152 is reduced.

[0186] Figure 12 A schematic top view of a pixel disposed on the outermost left side of a light-emitting display device according to an embodiment is shown.

[0187] Figure 12 The outermost pixel circuit is shown, and... Figure 6 In contrast to the implementation described herein, it shows an implementation in which the first dummy wiring 152 may not be provided.

[0188] Figure 12 The outermost pixel circuit and Figure 3 The pixel circuits shown are located in the scanning signal application area (central region) and have differences.

[0189] refer to Figure 3 A pair of connecting scan signal lines 151V (first scan signal lines) can be positioned on the corresponding sides of the pixel circuit within the scan signal application area (central area). However, in Figure 12 In the middle, the second dummy wiring 153 can be set to the right side of the outermost pixel circuit to replace... Figure 3 The connection to the 151V scan signal line (first scan signal line) can be omitted on the left side of the outermost pixel circuit, instead of using a different wiring method. Figure 3 The connection is to scan signal line 151V (first scan signal line). (Reference) Figure 12 The leftmost wiring of the outermost pixel circuit does not have to be the first dummy wiring 152, but can be the initialization voltage line 173. (See reference) Figure 1 There are many dummy wires 152 and 153, and the same voltage (e.g., cutoff voltage (Voff)) is applied to dummy wires 152 and 153, so there is no problem when dummy wire 152 can be removed.

[0190] In addition, in reference Figure 12 In the described implementation, the gap between the edge of the substrate and the pixel circuit can be equal to or greater than a margin of about 50 μm, so the gap can be adjusted and images can be accurately displayed when manufacturing large display devices.

[0191] According to one embodiment, the first dummy wiring 152 can be removed from the outermost pixel on the right. In an embodiment where the first dummy wiring 152 is not formed on the outermost pixel on the right, the wiring disposed on the rightmost side of the outermost pixel circuit can be the main drive voltage line 172vr disposed on the right.

[0192] Now refer to Figure 13 and Figure 14 The description has reference Figure 2 The description describes different implementations of the circuit configuration.

[0193] Figure 13 A circuit diagram of a pixel of a light-emitting display device according to an embodiment is shown.

[0194] and Figure 2 compared to, Figure 13 An embodiment is shown in which the gate electrode of the initialization transistor T3 receives a scan signal that is different from the gate electrode of the input transistor T2.

[0195] The following will describe Figure 13 and Figure 2 The differences.

[0196] In each of pixels PXa, PXb, and PXc, the gate electrode of initialization transistor T3 can be connected to the second scan line 151-1 for transmitting the second scan signal SS. The first electrode of initialization transistor T3 can be electrically connected to the second terminal of storage capacitor Cst, the second electrode of driving transistor T1, and the anode of light-emitting diodes EDa, EDb, and EDc, and the second electrode of initialization transistor T3 can be electrically connected to the initialization voltage line 173 for transmitting the initialization voltage VINT. Initialization transistor T3 is turned on by the second scan signal SS to transmit the initialization voltage VINT to the anode of light-emitting diodes EDa, EDb, and EDc and the second terminal of storage capacitor Cst, and thus initializes the voltage at the anode of light-emitting diodes EDa, EDb, and EDc. Furthermore, according to an embodiment, the voltage at the anode of light-emitting diodes EDa, EDb, and EDc is sensed to determine whether the target voltage of the previous frame is maintained before transmitting the initialization voltage VINT to the anode of light-emitting diodes EDa, EDb, and EDc.

[0197] exist Figure 13 In the implementation described herein, the sections used to turn on the initialization transistor T3 and the input transistor T2 can be separated, so that the programming operation performed by the input transistor T2 and the initialization operation performed by the initialization transistor T3 can be performed at different times.

[0198] exist Figure 14 The text shows that it has the same characteristics as... Figure 13The pixel circuit configuration of a light-emitting display device with the same circuit configuration.

[0199] Figure 14 A schematic top view of a portion of a light-emitting display device according to another embodiment is shown.

[0200] Figure 14 It shows the relationship with Figure 6 The corresponding pixel circuit on the left has a first dummy wiring 152.

[0201] Now will describe Figure 14 The configuration of the pixel circuit and Figure 6 The differences.

[0202] and Figure 6 different, Figure 14 A second scan line 151-1 disposed in the third conductive layer is also shown. The second scan line 151-1 extends in the y-axis direction and is electrically connected to the third gate electrode 157 of the initialization transistor T3 through an opening.

[0203] The two scan lines 151 and 151-1 are separated from each other, so they can transmit scan signals with different timings and independently control the conduction time of the input transistor T2 and the initialization transistor T3.

[0204] For a light-emitting display device, a light-emitting diode (LED) comprising an anode, an emitting layer, and a cathode can be formed on a fourth insulating layer, and an encapsulation layer, a color conversion layer, or a color filter can be additionally disposed on the LED. Reference will now be made to... Figure 15 Describe the detailed cross-sectional configuration of the entire light-emitting display device.

[0205] Figure 15 A cross-sectional view of a light-emitting display device according to an embodiment is shown.

[0206] Figure 15 The pixel circuit is omitted from the configuration of the light-emitting display device according to the embodiment, and the anode 191 constituting the light-emitting diodes EDa, EDb and EDc is shown.

[0207] like Figure 15 As shown, an anode 191 is provided on the substrate 110 for the corresponding pixels PXa, PXb, and PXc. The configuration of the pixel circuitry, such as the transistors and insulating layer disposed between the substrate 110 and the anode 191, is omitted. These components are... Figures 3 to 5 As shown in the image.

[0208] A partition wall 350 may be formed on the anode 191 and may include an opening 351 that exposes a portion of the anode 191.

[0209] According to one embodiment, an emitting layer 370 can be formed on the anode 191 and the partition wall 350, and the emitting layer 370 is disposed throughout the entire area. The emitting layer 370 can emit light of a first color, wherein the first color light can be blue light. According to one embodiment, the emitting layer 370 can be formed separately with respect to the opening 351 of the respective pixels PXa, PXb, and PXc, and the emitting layers of the respective pixels PXa, PXb, and PXc can emit light of different colors. A cathode 270 can be formed on the entire emitting layer 370.

[0210] An encapsulation layer 380, including insulating layers 381, 382, ​​and 383, may be disposed on the cathode 270. Insulating layers 381 and 383 may include inorganic insulating materials, and the insulating layer 382 between insulating layers 381 and 383 may include organic insulating materials.

[0211] A filler layer 390, including filler material, can be disposed on the encapsulation layer 380. A capping layer 400, including insulating material, color conversion layers 430a and 430b, and a transmissive layer 430c can be disposed on the filler layer 390.

[0212] The transmissive layer 430c can transmit incident light. The transmissive layer 430c can transmit a first color light (which may be blue light). The transmissive layer 430c may include a polymer material for transmitting the first color light. The region where the transmissive layer 430c is disposed may correspond to a light-emitting region for emitting blue light, and the transmissive layer 430c may not include semiconductor nanocrystals and may transmit the incident first color light.

[0213] Color conversion layers 430a and 430b may include different types of semiconductor nanocrystals. For example, a first color light input to color conversion layer 430a can be converted into a second color light, and then released by the semiconductor nanocrystals included in color conversion layer 430b. A first color light input to color conversion layer 430b can be converted into a third color light, and then released by the semiconductor nanocrystals included in color conversion layer 430b.

[0214] Semiconductor nanocrystals may include at least one of fluorescent materials and quantum dot materials for converting incident first-color light into second-color light or third-color light.

[0215] The nucleus of a quantum dot can be selected from group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, or combinations thereof.

[0216] Group II-VI compounds may be selected from: binary compounds, including CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS or mixtures thereof; and ternary compounds, selected from AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnS, CdZnS nSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS or mixtures thereof; or quaternary compounds selected from HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe or mixtures thereof.

[0217] III-V group compounds may be selected from: binary compounds, including GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb or mixtures thereof; ternary compounds, selected from GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb or mixtures thereof; and quaternary compounds, selected from GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, GaAlNP or mixtures thereof.

[0218] Group IV-VI compounds may be selected from: binary compounds, including SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; ternary compounds, selected from SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; and quaternary compounds, selected from SnPbSSe, SnPbSeTe, SnPbSTe, and mixtures thereof. Group IV elements may be selected from Si, Ge, and mixtures thereof. Group IV compounds may be binary compounds selected from SiC, SiGe, and mixtures thereof.

[0219] Binary, ternary, or quaternary compounds can exist in particles at a uniform concentration or in the same particles at different concentration distributions. The color conversion medium layer can have a core / shell structure with one quantum dot surrounding another. The boundary between the core and shell can have a concentration gradient, such that the concentration of the element present in the shell gradually decreases near the center of the quantum dot.

[0220] In some embodiments, quantum dots may have a core-shell structure, comprising a core containing nanocrystals as described above, and a shell surrounding the core. The shell of the quantum dot can serve as a protective layer for maintaining semiconductor properties by preventing chemical denaturation of the core, and / or as a charging layer for providing electrophoretic properties to the quantum dot. The shell may be a single layer or may include multiple layers. The boundary between the core and the shell may have a concentration gradient, such that the concentration of the element present in the shell gradually decreases near the center. Examples of shells for quantum dots include metal or non-metal oxides, semiconductor compounds, or combinations thereof.

[0221] For example, metal or non-metal oxides may include: binary compounds, such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4 or NiO; or ternary compounds, such as MgAl2O4, CoFe2O4, NiFe2O4 or CoMn2O4, and the embodiments are not limited thereto.

[0222] Semiconductor compounds may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, and AlSb, and the embodiments are not limited thereto.

[0223] Quantum dots can have a full width at half maximum (FWHM) of emission wavelengths less than about 45 nm, for example less than about 40 nm, or less than about 30 nm, and can improve color purity or color reproducibility within this range. Furthermore, light emitted through quantum dots is output in all directions, thereby improving the viewing angle.

[0224] The implementation method is not limited to the form of quantum dots, and quantum dots can be formed into spherical, conical, multi-armed or cubic nanoparticles, nanotubes, nanowires, nanofibers and nanoplate particles.

[0225] Quantum dots can control the color of light output based on the size of the particles, and therefore, quantum dots can have a variety of emission colors, such as blue, red, and green.

[0226] Insulating layer 440 can be disposed on color conversion layers 430a and 430b and transmissive layer 430c, and color filters 450a, 450b and 450c and light blocking member 460 can be disposed on these components.

[0227] Color filter 450a can output a second color light, color filter 450b can display a third color light, and color filter 450c can display a first color light.

[0228] The light-blocking component 460 can be disposed between adjacent color filters 450a, 450b and 450c.

[0229] Substrate 210 can be formed on color filters 450a, 450b and 450c and light blocking member 460. Color conversion layers 430a and 430b and color filters 450a, 450b and 450c can be disposed between substrate 110 and substrate 210.

[0230] According to another embodiment, the emitting layer 370 may include quantum dots in place of the color conversion layers 430a and 430b and the transmissive layer 430c.

[0231] Substrates 110 and 210 may comprise the same material. An encapsulation layer 380 may be disposed on substrate 110, and color filters 450a, 450b, and 450c, a light-blocking member 460, an insulating layer 440, color conversion layers 430a and 430b, a transmission layer 430c, and a capping layer 400 may be formed on substrate 210. Substrate structures at the upper and lower sides can be attached using a filler layer 390. The substrate structures at the upper and lower sides can be attached by further including a sealant inside or outside the filler layer 390.

[0232] Embodiments have been disclosed herein, and although terminology is used, it is used in a general and descriptive sense only and will be interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, unless otherwise expressly indicated, features, characteristics, and / or elements described in connection with embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: First pixel circuit; A first scan signal line is disposed on the side of the first pixel circuit, extends in a first direction, and transmits a scan signal; The second pixel circuit is disposed outside the first pixel circuit and at the outermost position of the display device. The first dummy wiring is disposed outside the second pixel circuit and extends in the first direction; as well as The second dummy wiring is disposed on the side of the second pixel circuit where the first dummy wiring is not disposed. Wherein, the width of the first dummy wiring is smaller than the width of the first scan signal line, and The width of the second dummy wiring is greater than the width of the first dummy wiring.

2. The display device according to claim 1, further comprising: Multiple sub-regions, each of the multiple sub-regions including: A scanning signal application area for transmitting the scanning signal in the first direction; and A virtual region is provided in which virtual wiring is provided, the virtual wiring including the first virtual wiring and the second virtual wiring.

3. The display device according to claim 2, further comprising: The third pixel circuit is disposed between the first pixel circuit and the second pixel circuit. The second dummy wiring is located on one side of the third pixel circuit.

4. The display device according to claim 2, further comprising: A second scan signal line extends in a direction perpendicular to the first direction and transmits the scan signal, wherein the second scan signal line is electrically connected to the first scan signal line, and in: The multiple sub-regions are set as three sub-regions. Each of the three sub-regions includes the first scan signal line. The second scan signal line extends in the three sub-regions. The second scan signal line is electrically connected to the first scan signal line in each of the three sub-regions, and The first scan signal line transmits scan signals with the same timing.

5. Display devices, including: Multiple display devices are attached to each other, among which, At least one of the plurality of display devices includes: First pixel circuit; A first scan signal line is disposed on the side of the first pixel circuit and extends in a first direction; The second pixel circuit is disposed outside the first pixel circuit and at the outermost position of the at least one display device. The outermost dummy wiring is disposed outside the second pixel circuit and extends in the first direction; and The second dummy wiring is disposed on the side of the second pixel circuit where the outermost dummy wiring is not disposed, and The width of the outermost dummy wiring is less than the width of the first scan signal line, and The width of the second dummy wiring is greater than the width of the outermost dummy wiring.

6. The display device according to claim 5, wherein, The at least one display device includes multiple sub-regions, and Each of the plurality of sub-regions includes: The scanning signal application area is used to transmit the scanning signal in the first direction, and A virtual region is provided in which virtual wiring is provided, the virtual wiring including the outermost virtual wiring and the second virtual wiring.

7. The display device according to claim 6, further comprising: The third pixel circuit is disposed between the first pixel circuit and the second pixel circuit. The second dummy wiring is located on one side of the third pixel circuit.

8. The display device according to claim 6, further comprising: A second scan signal line extends in a direction perpendicular to the first direction and transmits the scan signal, wherein the second scan signal line is electrically connected to the first scan signal line; in: The multiple sub-regions are set as three sub-regions. Each of the three sub-regions includes the first scan signal line. The second scan signal line extends in the three sub-regions. The second scan signal line is electrically connected to the first scan signal line in each of the three sub-regions, and The first scan signal line transmits scan signals with the same timing.

Images