Semiconductor memory device and method of operating a semiconductor memory device

Abstract

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a failure address register, and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The scrub control circuit generates a scrub address for performing a scrub operation on a first memory cell row based on a refresh row address for refreshing the memory cell row. The control logic circuit controls the ECC circuit such that the ECC circuit performs error detection and correction operations on a plurality of sub-pages in the first memory cell row during a first interval to count a number of error occurrences, and determines a sub-operation in a second interval in the scrub operation based on the number of error occurrences in the first memory cell row.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0185741, filed on December 29, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments relate to memory, and more specifically to semiconductor memory devices and methods of operating semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices can be classified into non-volatile memory devices such as flash memory and volatile memory devices such as DRAM. The high-speed operation and cost-efficiency of DRAM make it suitable for use as system memory. However, due to the continuous shrinking of DRAM manufacturing design rules, bit errors in DRAM cells can increase rapidly, and DRAM yields can decrease. Therefore, there is a need for higher reliability in semiconductor memory devices. Summary of the Invention

[0005] Some example embodiments provide semiconductor memory devices with enhanced reliability and performance.

[0006] Some example embodiments provide methods for operating semiconductor memory devices with enhanced reliability and performance.

[0007] According to various example embodiments, a semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, and control logic circuitry. The memory cell array includes multiple rows of memory cells, and each of the multiple rows includes volatile memory cells coupled to multiple bit lines. A cleanup control circuit generates a cleanup address for performing a cleanup operation on a first selected memory cell row from the multiple rows of memory cells, based on a refresh row address used to refresh the memory cell row. The control logic circuitry is configured to control the ECC circuit and the cleanup control circuitry. The control logic circuitry controls the ECC circuit such that, during a first interval in the cleanup operation, the ECC circuit performs error detection and correction operations on multiple codewords of multiple subpages in the first memory cell row in codeword units to count the number of errors; performs a row fault detection operation based on the number of errors in the first memory cell row to selectively store the row address of the first memory cell row as a row fault address in the fault address register; and determines a sub-operation in the cleanup operation in a second interval after the first interval based on the number of errors in the first memory cell row.

[0008] According to various example embodiments, a method is provided for operating a semiconductor memory device including a memory cell array, the memory cell array including a plurality of memory cell rows, and each of the plurality of memory cell rows including a plurality of volatile memory cells. According to the method, a first memory cell row is selected from the plurality of memory cell rows based on a refresh row address for refreshing memory cells connected to the memory cell row; error detection and correction operations for multiple codewords of multiple subpages in the first memory cell row are performed by an error correction code (ECC) circuit on a codeword basis during a first interval of a cleanup operation to count the number of errors occurring; and sub-operations are determined based on the number of errors occurring during a second interval of the cleanup operation. The sub-operations include one of: writing back the corrected codeword to the corresponding subpage in the first memory cell row, or the error detection and correction operations for a second memory cell row of the plurality of memory cell rows different from the first memory cell row.

[0009] According to various example embodiments, a semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit, a fault address register, and control logic circuitry. The memory cell array includes multiple rows of memory cells, and each of the multiple rows includes volatile memory cells coupled to multiple bit lines. A cleanup control circuit generates a cleanup address for performing a cleanup operation on a first selected memory cell row from the multiple rows of memory cells, based on a refresh row address used to refresh the memory cell row. The control logic circuitry is configured to control the ECC circuit and the cleanup control circuitry. The control logic circuitry controls the ECC circuit such that, during a first interval in the cleanup operation, the ECC circuit performs error detection and correction operations on multiple codewords of multiple subpages in the first memory cell row in codeword units to count the number of errors; performs a row fault detection operation based on the number of errors in the first memory cell row to selectively store the row address of the first memory cell row as a row fault address in the fault address register; and determines a sub-operation in a second interval in the cleanup operation based on the number of errors in the first memory cell row. The control logic circuit controls the ECC circuit to perform the error detection and correction operation on multiple sub-pages in a second storage cell row selected from the plurality of storage cell rows that are different from the first storage cell row, in response to the error occurrence count being zero in the first storage cell row. The sub-operation includes one of the following: writing the corrected codeword back to the corresponding sub-page in the first storage cell row, or performing the error detection and correction operation on the second storage cell row that is different from the first storage cell row.

[0010] Accordingly, the semiconductor memory device includes an ECC circuit, a cleanup control circuit, and a fault address register. The ECC circuit can quickly perform a cleanup operation during the initial interval after power is applied to the semiconductor memory device, and memory cell rows with row faults can be quickly detected. Attached Figure Description

[0011] The exemplary embodiments will now be described in more detail with reference to the accompanying drawings.

[0012] Figure 1 A block diagram illustrating a storage system according to various example embodiments.

[0013] Figure 2 To illustrate the various example embodiments Figure 1 A block diagram of semiconductor memory devices.

[0014] Figure 3 Show Figure 2 An example of a first bank array in a semiconductor memory device.

[0015] Figure 4 To illustrate the various example embodiments Figure 2 A block diagram of a refresh control circuit in a semiconductor memory device.

[0016] Figure 5 To illustrate the various example embodiments in Figure 4 The circuit diagram shown is an example of a refresh clock generator.

[0017] Figure 6 To illustrate the various example embodiments in Figure 4 The circuit diagram shown is another example of a refresh clock generator.

[0018] Figure 7 To illustrate the various example embodiments Figure 2 A block diagram of an example scrubbing control circuit in a semiconductor memory device.

[0019] Figure 8 To illustrate the various example embodiments Figure 7 Block diagram of the cleanup address generator in the cleanup control circuit.

[0020] Figure 9 To illustrate the various example embodiments Figure 1 A block diagram of another example of a semiconductor memory device.

[0021] Figure 10 A circuit diagram illustrating interference between memory cells in a semiconductor memory device.

[0022] Figure 11To illustrate the various example embodiments Figure 9 A block diagram illustrating an example of a victim address detector in a semiconductor memory device.

[0023] Figure 12 To show Figure 11 A block diagram of the interference detector in the sacrificial address detector.

[0024] Figure 13 To illustrate the various example embodiments Figure 9 A block diagram of an example of a cleanup control circuit in a semiconductor memory device.

[0025] Figure 14 To illustrate the various example embodiments Figure 13 Block diagram of the cleanup address generator in the cleanup control circuit.

[0026] Figure 15 Examples of various embodiments are shown. Figure 13 The weak codeword address generator in the cleanup control circuit.

[0027] Figure 16 Showing in the write operation Figure 2 or Figure 9 The semiconductor memory device portion.

[0028] Figure 17 This is shown in refresh or read operations. Figure 2 or Figure 9 The semiconductor memory device portion.

[0029] Figure 18 Examples of various embodiments are shown. Figure 2 or Figure 9 An example of a fault address register in a semiconductor memory device.

[0030] Figure 19 To illustrate the various example embodiments Figure 2 or Figure 9 A block diagram of an example ECC circuit in a semiconductor memory device.

[0031] Figure 20 Examples of various embodiments are shown. Figure 19 An example of an ECC encoder in an ECC circuit.

[0032] Figure 21 Examples of various embodiments are shown. Figure 19 An example of an ECC decoder in an ECC circuit.

[0033] Figure 22A The following examples illustrate the implementation of the various exemplary embodiments. Figure 2 or Figure 9Normal refresh and cleanup operations are performed in semiconductor memory devices.

[0034] Figure 22B The following examples illustrate the implementation of the various exemplary embodiments. Figure 2 or Figure 9 Normal refresh operations and accelerated cleanup operations are performed in semiconductor memory devices.

[0035] Figure 23 Shown in Figure 2 or Figure 9 Perform a cleanup operation on the semiconductor memory device.

[0036] Figure 24 A flowchart illustrating the cleaning operation according to various example embodiments is provided.

[0037] Figure 25A and Figure 25B Each example embodiment is shown separately. Figure 2 or Figure 9 Normal refresh operations and accelerated cleanup operations are performed in semiconductor memory devices.

[0038] Figure 26A and Figure 26B Shown separately in Figure 2 or Figure 9 Refresh and cleanup operations performed in semiconductor memory devices.

[0039] Figure 27 A block diagram illustrating a semiconductor memory device according to various example embodiments.

[0040] Figure 28 A flowchart illustrating a method of operating a semiconductor memory device according to various example embodiments.

[0041] Figure 29 A diagram illustrating a semiconductor package including stacked memory devices according to various example embodiments. Detailed Implementation

[0042] Various example embodiments will be described more fully below with reference to the accompanying drawings, which illustrate example embodiments.

[0043] Figure 1 A block diagram illustrating a storage system according to various example embodiments.

[0044] refer to Figure 1 The storage system 20 may include a storage controller 100 and a semiconductor storage device 200.

[0045] The storage controller 100 can control the overall operation of the storage system 20. The storage controller 100 can control the overall data exchange between the external host and the semiconductor storage device 200. For example, the storage controller 100 can write data to or read data from the semiconductor storage device 200 in response to a request from the host.

[0046] In addition, the memory controller 100 can send operation commands for controlling the semiconductor memory device 200 to the semiconductor memory device 200.

[0047] In some example embodiments, the semiconductor memory device 200 is a memory device that includes dynamic memory cells, such as dynamic random access memory (DRAM), double data rate 4 (DDR4) synchronous DRAM (SDRAM), DDR5 SDRAM, low power DDR4 (LPDDR4) SDRAM, LPDDR5 SDRAM, or LPDDR6 DRAM.

[0048] The memory controller 100 sends the clock signal CLK, command CMD and address (signal) ADDR to the semiconductor memory device 200 and exchanges master data MD with the semiconductor memory device 200.

[0049] Semiconductor storage device 200 includes a memory cell array (MCA) 300 for storing master data MD and parity data, an error correction code (ECC) circuit 400, a control logic circuit 210, a cleanup control circuit 500, and a fault address register (FAR) 580.

[0050] The ECC circuit 400 can perform ECC encoding on the write data to be stored in the target page of the memory cell array 300 under the control of the control logic circuit 210, and can perform ECC decoding or decoding on the codewords read from the target page.

[0051] When a refresh operation is performed on multiple rows of memory cells included in the memory cell array 300, the cleanup control circuit 500 can generate a cleanup address whenever a refresh operation is performed on N rows of memory cells, thereby performing a cleanup operation on the first row of memory cells in the multiple rows of memory cells. Here, N is a natural number equal to or greater than three. In accelerated cleanup mode, the cleanup control circuit 500 can generate a cleanup address whenever a refresh operation is performed on a row of memory cells with fewer than N rows of memory cells.

[0052] The cleanup operation may include: error detection and correction operations performed during the first interval of the cleanup operation and sub-operations performed during the second interval of the cleanup operation.

[0053] Control logic circuit 210 can control ECC circuit 400, such that during a first interval in the cleanup operation, ECC circuit 400 performs error detection and correction operations on multiple subpages in the first memory cell row in units of codewords to count the number of errors, and performs row fault detection operations based on the number of errors in the first memory cell row to selectively store the row address of the first memory cell row as a row fault address in fault address register 580. Control logic circuit 210 can determine sub-operations in a second interval of the cleanup operation based on the number of errors in the first memory cell row. Sub-operations may include one of the following: a writing-back correction codeword (C_CW), and error detection and correction operations on a second memory cell row different from the first memory cell row.

[0054] Control logic circuit 210 can, in response to the number of errors being less than a reference value, control ECC circuit 400 to write the corrected codeword back to the corresponding subpage in the first memory cell row. Control logic circuit 210 can, in response to the number of errors being equal to or greater than the reference value, control ECC circuit 400 not to write the corrected codeword back to the corresponding subpage in the first memory cell row. During the second interval of the cleanup operation, control logic circuit 210 can control ECC circuit 400 to perform error detection and correction operations on the second memory cell row.

[0055] After the row address of the first storage cell row is stored in the fault address register 580 as the row fault address, when the access address is associated with a read command from the storage controller 100 and the access address matches the row fault address, the control logic circuit 210 can control the ECC circuit 400 not to perform ECC decoding on the storage cell row specified by the access address.

[0056] Figure 2 To illustrate the various example embodiments Figure 1 A block diagram of semiconductor memory devices.

[0057] refer to Figure 2 The semiconductor memory device 200 may include control logic circuitry 210, address register 220, memory bank control logic 230, refresh control circuitry 385, row address multiplexer (RA MUX) 240, column address (CA) latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, input / output (I / O) gate circuitry 290, ECC circuitry 400, cleanup control circuitry 500, data I / O buffer 295, fault address register 580, address comparator 590, and fuse circuitry 595.

[0058] The memory cell array 300 may include a plurality of memory bank arrays 310a to 310s. The row decoder 260 may include a plurality of memory bank row decoders 260a to 260s respectively coupled to the plurality of memory bank arrays 310a to 310s, the column decoder 270 may include a plurality of memory bank column decoders 270a to 270s respectively coupled to the plurality of memory bank arrays 310a to 310s, and the sense amplifier unit 285 may include a plurality of sense amplifiers 285a to 285s respectively coupled to the plurality of memory bank arrays 310a to 310s.

[0059] Multiple memory bank arrays 310a to 310s, multiple memory bank row decoders 260a to 260s, multiple memory bank column decoders 270a to 270s, and multiple sense amplifiers 285a to 285s can form multiple memory banks. Each memory bank array in the multiple memory bank arrays 310a to 310s may include multiple volatile memory cells MC formed at the intersection of multiple word lines WL and multiple bit lines BTL.

[0060] Address register 220 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from memory controller 100. Address register 220 can provide the received bank address BANK_ADDR to memory control logic 230, the received row address ROW_ADDR to row address multiplexer 240, and the received column address COL_ADDR to column address latch 250.

[0061] The memory bank control logic 230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. The memory bank row decoders 260a to 260s corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal, and the memory bank column decoders 270a to 270s corresponding to the memory bank address BANK_ADDR can also be activated in response to the memory bank control signal.

[0062] Row address multiplexer 240 can receive row address ROW_ADDR from address register 220 and refresh row address REF_ADDR from refresh control circuit 385. Row address multiplexer 240 can selectively output row address ROW_ADDR or refresh row address REF_ADDR as row address RA. Row address RA output from row address multiplexer 240 can be applied to multiple memory bank row decoders 260a to 260s.

[0063] The refresh control circuit 385 can respond to the first refresh control signal IREF1 or the second refresh control signal IREF2 from the control logic circuit 210 and sequentially output the refresh row address REF_ADDR.

[0064] When the command CMD from the storage controller 100 corresponds to the automatic refresh command, whenever the control logic circuit 210 receives the automatic refresh command, the control logic circuit 210 can apply the first refresh control signal IREF1 to the refresh control circuit 385.

[0065] When the command CMD from the memory controller 100 corresponds to a self-refresh enter command, the control logic circuit 210 can apply the second refresh control signal IREF2 to the refresh control circuit 385. The second refresh control signal IREF2 is activated from the time the control logic circuit 210 receives the self-refresh enter command to the time the control logic circuit 210 receives the self-refresh exit command. The refresh control circuit 385 can sequentially increment or decrement the refresh row address REF_ADDR in response to receiving the first refresh control signal IREF1 or during the activation of the second refresh control signal IREF2.

[0066] The memory bank row decoders 260a to 260s, activated by the memory bank control logic 230, can decode the row address RA output from the row address multiplexer 240 and can activate the word line corresponding to the row address RA. For example, the activated memory bank row decoder can apply a word line drive voltage to the word line corresponding to the row address RA.

[0067] Column address latch 250 can receive column address COL_ADDR from address register 220 and temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, column address latch 250 can generate a column address COL_ADDR' incremented from the received column address COL_ADDR. Column address latch 250 can apply the temporarily stored or generated column address COL_ADDR' to multiple memory bank column decoders 270a to 270s.

[0068] The active memory bank column decoder among the multiple memory bank column decoders 270a to 270s can activate the sense amplifier corresponding to the memory bank address BANK_ADDR and column address COL_ADDR' through the I / O gate circuit 290.

[0069] I / O gating circuit 290 may include a circuit system for gating input / output data, and may also include input data mask logic, a read data latch for storing data output from multiple memory bank arrays 310a to 310s, and a write driver for writing data to the multiple memory bank arrays 310a to 310s.

[0070] A codeword CW read from one of the multiple memory arrays 310a to 310s can be sensed by a sense amplifier coupled to that memory array from which data is to be read, and stored in a read data latch of the I / O gate circuit 290. After ECC decoding of the codeword CW by the ECC circuit 400, the codeword CW stored in the read data latch can be provided to the memory controller 100 via the data I / O buffer 295.

[0071] The master data MD to be written to one of the multiple memory arrays 310a to 310s can be provided from the memory controller 100 to the data I / O buffer 295, and from the data I / O buffer 295 to the ECC circuit 400. The ECC circuit 400 can perform ECC encoding on the master data MD to generate parity data. The ECC circuit 400 can provide the master data MD and parity data to the I / O gating circuit 290, and the I / O gating circuit 290 can write the master data MD and parity data to a subpage of a target page of a memory array via a write driver.

[0072] The data I / O buffer 295 can provide the master data MD from the memory controller 100 to the ECC circuit 400 during a write operation of the semiconductor memory device 200 based on the clock signal CLK, and can also provide the master data MD from the ECC circuit 400 to the memory controller 100 during a read operation of the semiconductor memory device 200.

[0073] ECC circuit 400 can perform ECC decoding on codewords read from subpages of the target page, and can provide error generation signal EGS to control logic circuit 210 when at least one error bit is detected in the codeword.

[0074] The cleanup control circuit 500 can count the sequentially changing refresh row addresses REF_ADDR, and output a normal cleanup address SCADDR whenever the cleanup control circuit 500 has counted N refresh row addresses. Here, N is a natural number equal to or greater than three. The normal cleanup address SCADDR may include a cleanup row address SRA and a cleanup column address SCA. The cleanup control circuit 500 can provide the cleanup row address SRA and the cleanup column address SCA to the row decoder 260 and the column decoder 270, respectively.

[0075] Control logic circuit 210 can control the operation of semiconductor memory device 200. For example, control logic circuit 210 can generate control signals for semiconductor memory device 200 to perform write or read operations. Control logic circuit 210 includes command decoder 211 and mode register 212. Command decoder 211 decodes commands (CMD) received from memory controller 100, and mode register 212 sets the operating mode of semiconductor memory device 200.

[0076] The control logic circuit 210 may further include a counter 214 that counts the error generation signal EGS. The counter 214 can count the error generation signal EGS during the cleanup operation of the first memory cell row. The control logic circuit 210 can compare the number of errors (i.e., the counted error generation signals) with a reference value VTH, and can provide an error threshold flag ETF to the ECC circuit 400 when the number of errors is equal to or greater than the reference value VTH.

[0077] Control logic circuit 210 can store the row address of the first memory cell row as the row fault address RF_ADDR in fault address register 580 in response to the number of errors occurring in the first memory cell row being equal to or greater than the reference value VTH. When the number of errors occurring in the first memory cell row is equal to or greater than the reference value VTH, control logic circuit 210 can stop the operation of counter 214. Control logic circuit 210 may include a comparator that compares the number of errors occurring with the reference value VTH and outputs an error threshold flag ETF that is activated when the number of errors occurring is equal to or greater than the reference value VTH. The reference value VTH can be K, and K is a natural number equal to or greater than 2.

[0078] In addition, the command decoder 211 can generate control signals corresponding to the command CMD by decoding the write enable signal, row address strobe signal, column address strobe signal, chip select signal, etc.

[0079] The control logic circuit 210 can generate a first control signal CTL1 for controlling the I / O gate circuit 290, a second control signal CTL2 for controlling the ECC circuit 400, and a third control signal CTL3 for controlling the cleanup control circuit 500. Additionally, the control logic circuit 210 can provide a mode signal MS associated with the refresh period to the refresh control circuit 385. The control logic circuit 210 can generate the mode signal MS based on a temperature signal (not shown) representing the operating temperature of the semiconductor memory device 200.

[0080] The fuse 595 can store a reference value VTH and can provide the reference value VTH to the control logic circuit 210. The reference value VTH can be changed by programming the fuse 595.

[0081] Address comparator 590 compares the row address ROW_ADDR of the access address ADDR from memory controller 100 with the row fault address RF_ADDR stored in fault address register 580, and provides a match signal MTS to control logic circuit 210 based on the comparison result (e.g., when row address ROW_ADDR matches row fault address RF_ADDR). Control logic circuit 210 can control ECC circuit 400 not to perform ECC decoding on the memory cell row specified by row address ROW_ADDR in response to the match signal MTS.

[0082] Figure 3 Show Figure 2 An example of a first memory bank array in a semiconductor memory device.

[0083] refer to Figure 3 The first memory bank array 310a includes multiple word lines WL0 to WLm-1 (m is a natural number greater than 2), multiple bit lines BTL0 to BTLn-1 (n is a natural number greater than 2), and multiple volatile memory cells MC arranged at the intersections between the word lines WL0 to WLm-1 and the bit lines BTL0 to BTLn-1. Each memory cell MC includes a cell transistor coupled to each word line WL0 to WLm-1 and each bit line BTL0 to BTLn-1, and a cell capacitor coupled to the cell transistor. Each memory cell MC may have a DRAM cell structure. The bit lines BTL0 to BTLn-1 extend in a first direction D1, and the word lines WL0 to WLm-1 extend in a second direction D2.

[0084] Figure 4 To illustrate the various example embodiments Figure 2 A block diagram of an example refresh control circuit in a semiconductor memory device.

[0085] refer to Figure 4 The refresh control circuit 385 may include a refresh clock generator 390 and a refresh counter 397.

[0086] The refresh clock generator 390 can generate a refresh clock signal RCK in response to a first refresh control signal IREF1, a second refresh control signal IREF2, and a mode signal MS. The mode signal MS can determine the refresh time period of the refresh operation. As described above, the refresh clock generator 390 can generate the refresh clock signal RCK whenever it receives the first refresh control signal IREF1 or during the activation of the second refresh control signal IREF2.

[0087] The refresh counter 397 can generate refresh row addresses REF_ADDR that sequentially specify memory cell rows by performing a counting operation during the refresh clock signal RCK.

[0088] Figure 5 To illustrate the various example embodiments in Figure 4 The circuit diagram shown is an example of a refresh clock generator.

[0089] refer to Figure 5 The refresh clock generator 390a may include multiple oscillators 391, 392, and 393, a multiplexer 394, and a decoder 395a. The decoder 395a decodes the first refresh control signal IREF1, the second refresh control signal IREF2, and the mode signal MS to output a clock control signal RCS1. The oscillators 391, 392, and 393 generate refresh clock signals RCK1, RCK2, and RCK3 with different periods from each other. The multiplexer 394, in response to the clock control signal RCS1, selects one of the refresh clock signals RCK1, RCK2, and RCK3 to provide the refresh clock signal RCK.

[0090] Figure 6 To illustrate the various example embodiments in Figure 4 The circuit diagram shown is another example of a refresh clock generator.

[0091] refer to Figure 6 The refresh clock generator 390b may include a decoder 395b, a bias unit 396a, and an oscillator 396b. The decoder 395b decodes the first refresh control signal IREF1, the second refresh control signal IREF2, and the mode signal MS to output a clock control signal RCS2. The bias unit 396a generates a control voltage VCON in response to the clock control signal RCS2. The oscillator 396b generates a refresh clock signal RCK with a variable period based on the control voltage VCON.

[0092] Figure 7 To illustrate the various example embodiments Figure 2 A block diagram of an example of a cleanup control circuit in a semiconductor memory device.

[0093] refer to Figure 7 The cleanup control circuit 500 may include a counter 505 and a cleanup address generator 510.

[0094] Counter 505 counts the refresh row address REF_ADDR and generates an internal cleanup signal ISRB. The ISRB is activated during a first interval when counter 505 counts to the refresh row address REF_ADDR to the number specified by the count control signal CCS. The first interval may correspond to the time interval used to refresh one memory cell row. Counter 505 may change the number specified by the count control signal CCS in response to a cleanup acceleration signal SAS. For example, when SAS indicates accelerated cleanup mode, counter 505 may decrement the number specified by the count control signal CCS.

[0095] The cleanup address generator 510 generates a normal cleanup address SCADDR in response to the internal cleanup signal ISRB, which is associated with the normal cleanup operation for the codeword in each memory cell row. The normal cleanup address SCADDR changes gradually in the first cleanup mode.

[0096] The normal cleanup address SCADDR includes a cleanup row address (SRA) and a cleanup column address (SCA). The cleanup row address (SRA) specifies a page in a memory array, and the cleanup column address (SCA) specifies one of the codewords in that page. The cleanup address generator 510 provides the cleanup row address (SRA) to the corresponding row decoder and the cleanup column address (SCA) to the corresponding column decoder.

[0097] The cleanup operation performed based on the normal cleanup address SCADDR can be called a normal cleanup operation because the cleanup operation performed based on the normal cleanup address SCADDR is performed on all codewords included in the memory cell array 300.

[0098] Figure 8 To illustrate the various example embodiments Figure 7 Block diagram of the cleanup address generator in the cleanup control circuit.

[0099] refer to Figure 8 The cleanup address generator 510 may include a page segment (SG) counter 511 and a row counter 513.

[0100] In response to the internal cleanup signal, page segment counter 511 increments the cleanup column address SCA by 1 while the internal cleanup signal ISRB is activated, and activates the maximum address detection signal MADT, which is reset whenever the cleanup column address SCA reaches its maximum value. Page segment counter 511 provides the maximum address detection signal MADT to row counter 513.

[0101] In response to the internal cleanup signal ISRB, row counter 513 begins counting once it initially receives the internal cleanup signal ISRB, and increments the cleanup row address SRA by 1 each time the active maximum address detection signal MADT is received. Since the internal cleanup signal ISRB is activated during the first interval of performing a refresh operation on a memory cell row, page segment counter 511 can generate a cleanup column address SCA associated with a codeword in a page during the first interval.

[0102] Figure 9 To illustrate the various example embodiments Figure 1 A block diagram of another example of a semiconductor memory device.

[0103] Figure 9 Semiconductor memory device 200a and Figure 2 The difference between the semiconductor memory device 200 and the semiconductor memory device 200a is that the semiconductor memory device 200a also includes a sacrificial address detector 560 and a cleanup control circuit 500a, which outputs a weak codeword address WCADDR in the second cleanup mode.

[0104] refer to Figure 9 The control logic circuit 210a can also generate a fourth control signal CTL4 for controlling the sacrificial address detector 560.

[0105] The sacrificial address detector 560 can count the number of accesses to a first memory region in the memory cell array 300 during a reference interval, and generate at least one sacrificial address VCT_ADDR when the counted number of accesses to the first memory region reaches a reference number. The at least one sacrificial address VCT_ADDR specifies at least one adjacent memory region adjacent to the first memory region. The sacrificial address VCT_ADDR can be stored in the address memory table of the cleanup control circuit 500a.

[0106] In a first cleanup mode, the cleanup control circuit 500a can provide the cleanup row address SRA and the cleanup column address SCA to the row decoder 260 and the column decoder 270, respectively. In a second cleanup mode, the cleanup control circuit 500a can output the address of the codeword associated with the sacrifice address VCT_ADDR stored in the address storage table as the weak codeword address WCADDR. The weak codeword address WCADDR may include the weak codeword row address WCRA and the weak codeword column address WCCA. In the second cleanup mode, the cleanup control circuit 500a can provide the weak codeword row address WCRA and the weak codeword column address WCCA to the row decoder 260 and the column decoder 270, respectively.

[0107] Figure 10 A circuit diagram illustrating interference between memory cells in a semiconductor memory device.

[0108] refer to Figure 10 A portion of the semiconductor memory device 200a includes memory cells 51, 52 and 53 and a bit line sense amplifier 60.

[0109] Assume that memory cells 51, 52, and 53 are all connected to the same bit line BTL. Additionally, memory cell 51 is connected to the word line WL. <g-1>Storage unit 52 is connected to word line WL <g>And storage unit 53 is connected to word line WL<g+1> .like Figure 10 As shown, the word line WL <g-1>and WL<g+1> Located at the WL line <g>Adjacent to each other. Memory cell 51 includes an access transistor CT1 and a cell capacitor CC1. The gate of access transistor CT1 is connected to word line WL. <g-1>One end of the memory cell 52 is connected to the bit line BTL. The memory cell 52 includes an access transistor CT2 and a cell capacitor CC2. The gate of the access transistor CT2 is connected to the word line WL. <g>One end of it is connected to the bit line BTL. Furthermore, memory cell 53 includes an access transistor CT3 and a cell capacitor CC3. The gate of access transistor CT3 is connected to the word line WL.<g+1> And one end of it is connected to the bit line BTL.

[0110] Bit line sensing amplifier 60 may include an N-sensing amplifier for discharging low-level bit lines in bit lines BTL and BTLB, and a P-sensing amplifier for charging high-level bit lines in bit lines BTL and BTLB.

[0111] During a refresh operation, the bit line sense amplifier 60 rewrites the stored data into the selected memory cell via an N-sensor amplifier or a P-sensor amplifier. During a read or write operation, a selection voltage (e.g., Vpp) is provided to the word line WL. <g>Then, due to the effects of capacitive coupling, even when the selection voltage is not applied to the adjacent word line WL... <g-1>and WL<g+1> At that time, adjacent word lines WL <g-1>and WL<g+1> The voltage continues to rise. This capacitive coupling is indicated by parasitic capacitances Ccl1 and Ccl2.

[0112] During non-refresh operations, when the word line WL <g>When accessed repeatedly, connect to word line WL <g-1>and WL<g+1> The charge stored in the cell capacitors CC1 and CC3 of memory cells 51 and 53 may gradually leak. In this case, the reliability of logic "0" stored in cell capacitor CC1 and the reliability of logic "1" stored in cell capacitor CC3 may not be guaranteed. Therefore, a cleanup operation of the memory cells is required at appropriate times.

[0113] Figure 11 To illustrate the various example embodiments Figure 9 A block diagram of an example of a sacrificial address detector in a semiconductor memory device.

[0114] refer to Figure 11 The sacrificial address detector 560 may include an interference detector 570 and a sacrificial address generator 577.

[0115] Interference detector 570 can count the number of accesses to a first memory region (e.g., at least one memory cell row) based on row address ROW_ADDR during a reference (or predetermined) interval, and can generate a first detection signal DET1 when the counted number of accesses reaches a reference value.

[0116] The sacrificial address generator 577 can generate at least one of sacrificial addresses VCT_ADDR1 and VCT_ADDR2 in response to the first detection signal DET1. At least one of the sacrificial addresses VCT_ADDR1 and VCT_ADDR2 can be a row address specifying a second or third memory region located adjacent to the first memory region. The sacrificial address generator 577 can provide at least one of the sacrificial addresses VCT_ADDR1 and VCT_ADDR2 to the address storage table in the cleanup control circuit 500a.

[0117] Figure 12 To show Figure 11 A block diagram of the interference detector in the sacrificial address detector.

[0118] refer to Figure 12 The interference detector 570 may include an access counter 571, a threshold register 573, and a comparator 575.

[0119] Access counter 571 can count the number of accesses to a specific address (or a specific memory region) based on the row address ROW_ADDR. For example, access counter 571 can count the number of accesses to a specific word line. It can count the number of accesses to a specific word line or a group of word lines comprising at least two word lines. Furthermore, the counting of accesses can be performed by a specific block cell, bank cell, or chip cell.

[0120] Threshold register 573 can store the maximum interference occurrence count that guarantees the reliability of data in a specific word line or memory cell. For example, the threshold (or reference value) for a word line can be stored in threshold register 573. Alternatively, the threshold for a group of word lines, a block, a memory cell, or a chip cell can be stored in threshold register 573.

[0121] Comparator 575 compares a reference value stored in threshold register 573 with the number of accesses to a specific memory region counted by access counter 571. If a memory region has an access count that reaches the reference value, comparator 575 generates a first detection signal DET1. Comparator 575 provides the first detection signal DET1 to sacrificial address generator 577.

[0122] Figure 13 To illustrate the various example embodiments Figure 9 A block diagram of an example of a cleanup control circuit in a semiconductor memory device.

[0123] refer to Figure 13 The cleanup control circuit 500a may include a counter 505, a cleanup address generator 510a, and a weak code word address generator 520a.

[0124] The operation of counter 505 and cleanup address generator 510a is basically similar. Figure 7 The operation of counter 505 and cleanup address generator 510 is described. Cleanup address generator 510a also receives cleanup mode signal SMS and generates normal cleanup address SCADDR in the first cleanup mode.

[0125] The weak codeword address generator 520a, in response to the internal cleanup signal ISRB and the cleanup mode signal SMS, generates a weak codeword address WCADDR associated with a weak cleanup operation in a second cleanup mode. This weak cleanup operation is associated with weak codewords in the memory bank array. The weak codeword address WCADDR includes the weak codeword row address WCRA and the weak codeword column address WCCA.

[0126] The cleanup mode signal SMS indicates a first cleanup mode when it has a first logic level, and indicates a second cleanup mode when it has a second logic level. The cleanup mode signal SMS may be included in the third control signal CTL3. The weak codeword address generator 520a provides the weak codeword row address WCRA to the corresponding row decoder and the weak codeword column address WCCA to the corresponding column decoder.

[0127] The weak codeword address generator 520a may include an address storage table, which can store the addresses of codewords associated with the sacrifice address VCT_ADDR. The cleanup operation performed based on the weak codeword address WCADDR can be called a target cleanup operation because the cleanup operation is performed on the weak codeword.

[0128] Figure 14 To illustrate the various example embodiments Figure 13 Block diagram of the cleanup address generator in the cleanup control circuit.

[0129] refer to Figure 14 The cleanup address generator 510a may include a page segment counter 511a and a line counter 513a.

[0130] Page segment counter 511a responds to the internal cleanup signal ISRB and the cleanup mode signal SMS. In the first cleanup mode, while the internal cleanup signal ISRB is activated, it increments the cleanup column address SCA by 1 and activates the maximum address detection signal MADT, which is reset whenever the cleanup column address SCA reaches its maximum value. Page segment counter 511a provides the maximum address detection signal MADT to row counter 513a.

[0131] The row counter 513a responds to the internal cleanup signal ISRB and the cleanup mode signal SMS. It begins counting once the internal cleanup signal ISRB is initially received, and increments the cleanup row address SRA by 1 whenever the active maximum address detection signal MADT is received.

[0132] Figure 15 Examples of various embodiments are shown. Figure 13 The weak codeword address generator in the cleanup control circuit.

[0133] refer to Figure 15 The weak codeword address generator 520a may include a table pointer 521, an address storage table 530, and a sensing unit 540.

[0134] Address storage table 530 stores the address information of weak codewords WCRA1 to WCRAv and WCCA1 to WCCAw (w is a natural number greater than v) included in storage cell array 300.

[0135] A weak codeword can be all or some of the pages in the storage array of a storage cell array, including weak pages with a number of error bits greater than a reference value. Additionally, a weak codeword can be the codeword of an adjacent page near a densely accessed storage region.

[0136] In the second cleanup mode, pointer 521 can generate a pointer signal TPS in response to the internal cleanup signal ISRB and the cleanup mode signal SMS during the first interval, and provide the pointer signal TPS to the address memory table 530. The pointer signal TPS provides location information for the address memory table 530. The address memory table 530 may include a non-volatile storage device. Figure 11 At least one of the sacrifice addresses VCT_ADDR1 and VCT_ADDR2 provided by the sacrifice address generator 577 can be stored in the address storage table 530.

[0137] The pointer signal TPS gradually increases a predetermined number of times during the first interval, and each time the pointer signal TPS is applied, the address storage table 530 can output the weak codeword address stored at the location (indicated by the pointer signal TPS) via the sensing unit 540 as the weak codeword row address WCRA and the weak codeword column address WCCA. The sensing unit 540 provides the weak codeword row address WCRA to the corresponding row decoder and the weak codeword column address WCCA to the corresponding column decoder.

[0138] The control logic circuit 210a can apply different refresh cycles to some memory cell rows based on the number of error bits detected by the cleanup operation for each memory cell row.

[0139] Figure 16 Showing in the write operation Figure 2 Semiconductor memory device 200 or Figure 9 Part of the semiconductor memory device 200a.

[0140] exist Figure 16 The diagram shows control logic circuit 210, first memory array 310a, I / O gate circuit 290, and ECC circuit 400.

[0141] refer to Figure 16 The first memory array 310a includes a normal cell array (NCA) and a redundant cell array (RCA). The normal cell array (NCA) includes multiple first memory blocks MB0 to MB15, i.e., 311 to 313, and the redundant cell array (RCA) includes at least a second memory block 314. The first memory blocks 311 to 313 are memory blocks that determine the storage capacity of the semiconductor memory device 200. The second memory block 314 is used for ECC and / or redundancy repair. Because the second memory block 314 used for ECC and / or redundancy repair is used for ECC, data line repair, and block repair (EDB) to repair "defective" cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block. In each of the first memory blocks 311 to 313, multiple first memory cells are arranged in rows and columns. In the second memory block 314, multiple second memory cells are arranged in rows and columns. The first memory cell connected to the intersection of the word line WL and the bit line BTL can be a dynamic memory cell. The second memory cell connected to the intersection of word line WL and bit line RBTL can be a dynamic memory cell.

[0142] I / O gating circuitry 290 includes multiple switching circuits 291a to 291d connected to the first memory blocks 311 to 313 and the second memory block 314, respectively. In the semiconductor memory device 200, multiple bit lines corresponding to burst length (BL) data can be accessed simultaneously to support the BL, which indicates the maximum number of accessible column locations. For example, BL can be set to 8.

[0143] ECC circuit 400 can be connected to switching circuits 291a to 291d via first data line GIO and second data line EDBIO. Control logic circuit 210 can receive command CMD and address ADDR and can decode command CMD to generate a first control signal CTL1 for controlling switching circuits 291a to 291d and a second control signal CTL2 for controlling ECC circuit 400.

[0144] When the command CMD is a write command, the control logic circuit 210 can provide the second control signal CTL2 to the ECC circuit 400, and the ECC circuit 400 can perform ECC encoding on the master data MD to generate parity data associated with the master data MD, and provide the codeword CW, which includes the master data MD and the parity data, to the I / O gating circuit 290. The control logic circuit 210 can provide the first control signal CTL1 to the I / O gating circuit 290, so that the codeword CW will be stored in a subpage of the target page in the first memory array 310a.

[0145] Figure 17 This is shown in refresh (cleanup) or read operations. Figure 2 Semiconductor memory device 200 or Figure 9 Part of the semiconductor memory device 200a.

[0146] exist Figure 17 The diagram shows control logic circuit 210, first memory array 310a, I / O gate circuit 290, ECC circuit 400, fault address register 580, and address comparator 590.

[0147] refer to Figure 17 When the command CMD is a refresh command specifying a refresh operation, the cleanup control circuit 500 can generate a cleanup address based on the refresh row address count, and the control logic circuit 210 can provide the first control signal CTL1 to the I / O gate circuit 290, so that the read codeword RCW stored in each subpage of the target page in the first memory array 310a is sequentially provided to the ECC circuit 400. For example, the read codeword RCW may include first parity data and first master data.

[0148] ECC circuit 400 can perform error detection and correction operations on the read codeword RCW during the first interval of the cleanup operation, and can provide an error generation signal EGS to control logic circuit 210 in response to detected error bits. Control logic circuit 210 can count the error generation signal EGS (number of errors) for a page, and can determine whether a row fault has occurred in the target page based on a comparison of the number of errors and a reference value VTH. When the number of errors is equal to or greater than the reference value VTH, control logic circuit 210 can provide ECC circuit 400 with an error threshold flag ETF with a high level and can store the row address of the target page in fault address register 580.

[0149] The control logic circuit 210 can write back the corrected codeword C_CW to the corresponding subpage based on a comparison of the number of errors and the reference value VTH, or it can perform error detection and correction operations on a second storage cell row different from the first storage cell row. For example, the corrected codeword C_CW may include second parity data and second main data. For example, the control logic circuit 210 can control the ECC circuit 400 not to write back the corrected codeword C_CW to the corresponding subpage in response to the number of errors being equal to or greater than the reference value VTH. For example, during the second interval of the cleanup operation, the control logic circuit 210 can control the ECC circuit 400 to write back the corrected codeword C_CW to the corresponding subpage in response to the number of errors being greater than zero and less than the reference value VTH. For example, the control logic circuit 210 can control the ECC circuit 400 to perform error detection and correction operations on multiple subpages in a second storage cell row different from the first storage cell row in response to the number of errors in the first storage cell row being zero. The control logic circuit 210 can quickly perform cleanup operations on the memory cell rows because the number of errors in most memory cell rows is zero.

[0150] When the command CMD corresponds to a read command, the ECC circuit 400 can provide the corrected master data C_MD to the data I / O buffer 295 without writing back the corrected codeword C_CW. For example, the corrected master data C_MD may include third master data.

[0151] After the row fault address RF_ADDR is stored in the fault address register 580, when the command CMD corresponds to a read command, the address comparator 590 can compare the row address ROW_ADDR and the row fault address RF_ADDR, and can provide a match signal MTS indicating the comparison result to the control logic circuit 210. When the match signal MTS indicates that the row address ROW_ADDR matches the row fault address RF_ADDR, the control logic circuit 210 can control the ECC circuit 400 not to perform ECC decoding on the memory cell row specified by the row address ROW_ADDR.

[0152] Figure 18 Examples of various embodiments are shown. Figure 2 Semiconductor memory device 200 or Figure 9 An example of a fault address register in a semiconductor memory device 200a.

[0153] refer to Figure 18 Each index (e.g., entry) Idx11, Idx12, ..., Idx1u (u being a natural number greater than 2) in the fault address register 580 may include information about the row fault address RF_ADDR of each row fault memory cell row determined to have a row fault during the first interval of the cleanup operation. The fault address register 580 includes multiple columns 581 and 583.

[0154] Column 581 stores the row fault address RF_ADDR for each row of failed memory cells, and column 583 stores the number of errors (ECNT) for each row of failed memory cells. The row fault address RF_ADDR may include the bank group address ("BGA"), bank address ("BA"), and row address ("RA") for each row of failed memory cells.

[0155] exist Figure 18 In this context, it is assumed that when the number of errors detected during the first interval is equal to or greater than 3 (ECNT), the storage cell row is determined to have a row fault.

[0156] Figure 2 The control logic circuit 210 can perform soft packaged repair (PPR) on at least some row faulty memory cell rows by referring to the fault address register 580. The control logic circuit 210 can perform soft PPR on at least some row faulty memory cell rows by storing (moving) the data stored in at least some row faulty memory cell rows in a redundant area of ​​the cell array 300. The row fault address RF_ADDR of at least some row faulty memory cell rows that have undergone soft PPR is reset in the fault address register 580, and the row fault address of the new row faulty memory cell row can be stored in the fault address register 580.

[0157] Figure 19 To illustrate the various example embodiments Figure 2 or Figure 9 A block diagram of an example of an ECC circuit in a semiconductor memory device 200.

[0158] refer to Figure 19 The ECC circuit 400 may include an ECC encoder 410, an ECC decoder 430, and an (ECC) memory 415. The memory 415 may store ECC 421. The ECC 421 may be a single error correction (SEC) code or a single error correction / double error detection (SECDED) code.

[0159] ECC encoder 410 can use ECC 421 to generate parity data PRT associated with write data WMD to be stored in the normal cell array NCA of the first memory array 310a. The parity data PRT can be stored in the redundant cell array RCA of the first memory array 310a.

[0160] ECC decoder 430 can use ECC 421 to perform ECC decoding on read data RMD based on read data RMD and parity data PRT read from the first memory array 310a. As a result of ECC decoding, when read data RMD includes at least one error bit, ECC decoder 430 can provide an error generation signal EGS to control logic circuit 210, selectively correcting the error bit in read data RMD, and can write back the corrected codeword C_CW in a cleanup operation and output the corrected master data C_MD in a read operation.

[0161] Figure 20 Examples of various embodiments are shown. Figure 19 An example of an ECC encoder in an ECC circuit.

[0162] refer to Figure 20 The ECC encoder 410 may include a parity generator 420. The parity generator 420 may receive write data WMD and bias bit BB, and may generate parity data PRT by performing, for example, an XOR array operation.

[0163] Figure 21 Examples of various embodiments are shown. Figure 19 An example of an ECC decoder in ECC circuit 400.

[0164] refer to Figure 21 The ECC decoder 430 may include a checksum generation circuit 440, an error locator 460, a data corrector 470, a data latch 480, a multiplexer 485, and a demultiplexer 490. The checksum generation circuit 440 may include a check bit generator 441 and a checksum generator 443.

[0165] The parity bit generator 441 can generate the parity bit CHB based on the read data RMD by performing an XOR array operation, and the parity sub-generator 443 can generate the parity sub-SDR by comparing the corresponding bits of the parity data PRT with the parity bit CHB.

[0166] When all bits of the checksum SDR are not all "zero", the error locator 460 can generate an error position signal EPS indicating the location of the error bit in the read data RMD, and provide the error position signal EPS to the data corrector 470. Additionally, when the read data RMD includes an error bit, the error locator 460 can provide an error generation signal EGS to the control logic circuit 210.

[0167] In response to the Operation Mode Signal (OMS) and the Data Control Signal (DCS), the data latch 480 can receive a page data PDT including multiple read data RMDs during a cleanup operation, can provide read data RMDs including correctable error bits to the data corrector 470 and multiplexer 485 during a cleanup operation, or can provide read data RMDs to the data corrector 470 without considering error bits during a read operation. The Operation Mode Signal (OMS) can specify one of the cleanup operation and the read operation. The Operation Mode Signal (OMS) and the Data Control Signal (DCS) can be included in... Figure 2 In the second control signal CTL2.

[0168] Data corrector 470 can receive read data RMD, correct error bits in read data RMD based on error position signal EPS when the read data RMD includes error bits, and output corrected master data C_MD.

[0169] Multiplexer 485 can select one of read data RMD and corrected master data C_MD in response to an error threshold flag ETF, and can provide the selected data to demultiplexer 490. For example, when the error threshold flag ETF indicates that the number of errors is equal to or greater than the reference value VTH, multiplexer 485 can provide read data RMD to demultiplexer 490. For example, when the error threshold flag ETF indicates that the number of errors is less than the reference value VTH, multiplexer 485 can provide corrected master data C_MD to demultiplexer 490.

[0170] In response to the Operation Mode Signal OMS, the demultiplexer 490 can provide the output of the multiplexer 485 to the I / O gate circuit 290 during a cleanup operation, and can provide the output of the multiplexer 485 to the data I / O buffer 295 during a read operation.

[0171] Figure 22A The following examples illustrate the implementation of the various exemplary embodiments. Figure 2 Semiconductor memory device 200 or Figure 9 Normal refresh and cleanup operations are performed in the semiconductor memory device 200a.

[0172] exist Figure 22A In this context, tRFC represents the refresh cycle and refers to the time it takes to refresh one row of memory cells, while tREFI represents the refresh interval and refers to the interval between two consecutive refresh commands. tREFI can be the "average" interval between two consecutive refresh commands, and tRFC can be the "minimum" delay between a refresh command and the next valid command. The next valid command can include consecutive refresh commands.

[0173] refer to Figure 22A It should be noted that whenever a normal refresh operation NREF is performed N times on a storage cell row in response to a refresh command, the cleanup control circuit 500 specifies at least one storage cell row, and the ECC circuit performs a cleanup operation SCRB S times on that at least one storage cell row. S is a natural number less than N.

[0174] The cleanup operation SCRB for a storage cell row includes: M cleanup error detection and correction operations SCD1 to SCDM during the first interval INT11, and one of the cleanup write-back operation SCWC for corrected data and the cleanup non-write-back operation SCW-NC for non-corrected data during the second interval INT12 of the cleanup operation.

[0175] The ECC circuit 400 in semiconductor memory device 200 or 200a can sequentially read data corresponding to codewords from each of the M subpages in the memory cell row during the first interval INT11 of the cleanup operation, perform error detection and correction operations on the M codewords to count the number of errors, and can write back and forth the corrected codewords or not write back the corrected codewords based on the number of errors during the second interval INT12 of the cleanup operation.

[0176] When the number of errors counted is equal to or greater than the reference value VTH, the cell row containing the number of errors equal to or greater than the reference value VTH has a high probability of experiencing a row failure. Writing the corrected codeword back to the subpage of the cell row that experienced the row failure will result in a miscorrected error in the cell row that experienced the row failure, and a correctable error in the cell row may change into an uncorrectable error.

[0177] Figure 22B The following examples illustrate the implementation of the various exemplary embodiments. Figure 2 Semiconductor memory device 200 or Figure 9 Normal refresh operations and accelerated cleanup operations are performed in the semiconductor memory device 200a.

[0178] Figure 22B and Figure 22A The difference lies in the cleanup operation SCRB'.

[0179] refer to Figure 22B The cleanup operation SCRB' includes: M cleanup error detection and correction operations SCD1 to SCDM for one storage cell row (e.g., the first storage cell row) during the first interval INT11', and M cleanup error detection and correction operations SCD1 to SCDM for another storage cell row (e.g., the second storage cell row) during the second interval INT12'. When the number of errors counted in the M cleanup error detection and correction operations SCD1 to SCDM for one storage cell row (e.g., the first storage cell row) during the first interval INT11' is equal to zero, M cleanup error detection and correction operations SCD1 to SCDM are performed for another storage cell row (e.g., the second storage cell row) during the second interval INT12', thus the cleanup operation for the storage cell row can be performed quickly.

[0180] Figure 23 Shown in Figure 2 Semiconductor memory device 200 or Figure 9 A cleanup operation is performed in the semiconductor memory device 200a.

[0181] exist Figure 23 In the code, RMW is the signal that identifies the first and second intervals of the cleanup operation, ECC_ON represents the ECC decoding operation associated with the write-back correction data, ETF is the signal that indicates the number of errors that have occurred is equal to or greater than the reference value, and RFD_NO_ERR is the signal that no errors were detected in a storage cell row.

[0182] refer to Figure 2 and Figure 23 In the first interval INT21 of the cleanup operation, the ECC circuit 400 performs error detection and correction operations on multiple sub-pages in a memory cell row to count the number of errors. When the counted number of errors is zero, the signal RFD_NO_ERR goes high. When an error is detected in the first interval INT21 and the counted number of errors is greater than zero and less than the reference value VTH, the signal RFD_NO_ERR goes low and the signal ECC_ON goes high in the second interval INT22 because the corrected data is written back in the second interval INT22.

[0183] Because no error was detected during the error detection and correction operation on another storage cell row in the first interval INT31, the second interval INT32 is very short, and error detection and correction operations can be performed on yet another storage cell row during the third interval INT33.

[0184] Because in Figure 23 During each interval, the error threshold flag ETF is low, so the decoded row address DRA is not stored as a row fault address in the fault address register 580.

[0185] Figure 24 A flowchart illustrating the cleaning operation according to various example embodiments is provided.

[0186] refer to Figure 2 and Figure 24 The ECC circuit 400 performs error detection and correction operations on the first memory cell row in units of codewords (operation S110) to determine whether an error has occurred in the first memory cell row (operation S120). When no error has occurred in the first memory cell row ("No" in operation S120), the control logic circuit 210 increments the row address by 1 and the ECC circuit 400 performs error detection operations on the second memory cell row.

[0187] When an error occurs in the first memory cell row ("Yes" in operation S120), the control logic circuit 210 determines whether the number of errors is equal to or greater than the reference value VTH (operation S130). When the number of errors is equal to or greater than the reference value VTH ("Yes" in operation S130), the ECC circuit 400 performs a cleanup operation by writing back the corrected codeword (operation S140). When the number of errors is less than the reference value VTH ("No" in operation S130), the ECC circuit 400 performs a cleanup operation by writing back the corrected codeword (operation S150).

[0188] Figure 25A and Figure 25B Each example embodiment is shown separately. Figure 2 Semiconductor memory device 200 or Figure 9 Normal and accelerated cleanup operations are performed in the semiconductor memory device 200a.

[0189] refer to Figure 25A , Figure 2 The cleaning control circuit 500 or Figure 13 The cleaning control circuit 500a in the middle activates the internal cleaning signal ISRB during the refresh period tRFC corresponding to the interval between the continuous refresh command REF.

[0190] Control logic circuit 210 or control logic circuit 210a can control column decoder 270 to continuously generate read column select signals SCRB_RCSL for selecting a portion of the bit lines of the target page associated with the cleanup operation in a first cycle INT41. After a time tRCD elapsed from the time point from receiving the first refresh command REF, column decoder 270 activates the first read column select signal SCRB_RCSL. Control logic circuit 210 or control logic circuit 210a can control column decoder 270 to activate write column select signals SCRB_WCSL for continuously selecting a portion of the bit lines of the target page associated with the write-back operation, such that after a time interval tWR elapsed from the activation of each write column select signal SCRB_WCSL, each read column select signal SCRB_RCSL is activated.

[0191] refer to Figure 25B , Figure 2 The cleaning control circuit 500 or Figure 13 The cleanup control circuit 500a in the middle activates the internal cleanup signal ISRB during the refresh cycle tRFC corresponding to the interval between the continuous refresh command REF.

[0192] Control logic circuit 210 or 210a can control column decoder 270 to continuously generate read column select signals SCRB_RCSL for selecting a portion of the bit lines of the target page associated with the cleanup operation at a second cycle INT42. After time tRCD has elapsed since the first refresh command REF was received, column decoder 270 activates the first read column select signal SCRB_RCSL. Control logic circuit 210 or 210a can also control column decoder 270 not to generate write column select signals SCRB_WCSL for continuously selecting a portion of the bit lines of the target page associated with the write-back operation.

[0193] exist Figure 25A and Figure 25B In this context, the first period INT41 can be G times the second period INT42, and G is a natural number equal to or greater than 2. In some examples, G can be a positive integer greater than 1.

[0194] Because in Figure 25B The write column select signal SCRB_WCSL is not generated, so the ECC circuit 400 can perform cleanup operations on more codewords (approximately two times or more codewords) while the internal cleanup signal ISRB is activated.

[0195] Figure 25B The cleanup operation can be performed quickly during the initial interval after power is applied to the semiconductor memory device 200 or 200a, and memory cell rows with row faults can be detected quickly. For example, the initial interval can be predetermined.

[0196] Figure 26A and Figure 26B Shown separately in Figure 2 Semiconductor memory device 200 or Figure 9 Refresh and cleanup operations performed in the semiconductor memory device 200a.

[0197] refer to Figure 26A It should be noted that the cleanup control circuit 500 specifies that the ECC circuit 400 performs cleanup operations SCRB S times on the memory cell row, and whenever a normal refresh operation NREF is performed N times on the memory cell row in response to a refresh command, a refresh operation FREF is performed L times on the adjacent memory region corresponding to the sacrificed address VCT_ADDR. Here, L is a natural number less than N and S is a natural number less than L.

[0198] refer to Figure 26B It should be noted that the cleanup control circuit 500 specifies that the ECC circuit 400 performs cleanup operations SCRB S times on the memory cell rows, and in the accelerated cleanup operation, whenever a normal refresh operation NREF is performed on the memory cell row in response to a refresh command, a refresh operation FREF is performed L / 4 times on the adjacent memory region corresponding to the sacrifice address VCT_ADDR. The control logic circuit 210 can control the cleanup control circuit 500 to generate cleanup addresses during the cleanup operation at a period shorter than the normal period defined in the specification of the semiconductor memory device 200 or 200a during an initial interval (e.g., a predetermined time interval) after power is applied to the semiconductor memory device 200 or 200a.

[0199] Figure 26B The cleanup operation is performed rapidly during an initial interval (e.g., a predetermined interval) after power is applied to the semiconductor memory device 200 or 200a, and memory cell rows with row faults can be detected quickly. In some examples, Figure 26B The accelerated cleanup operation can be performed in response to a specific control signal during the normal cleanup operation.

[0200] exist Figure 25B and Figure 26B In the middle, the control logic circuit 210 can control the ECC circuit 400 to perform background write operations in the initial interval to write default data into the storage cell row and perform cleanup operations on the default data.

[0201] Figure 27 A block diagram illustrating a semiconductor memory device according to various example embodiments.

[0202] refer to Figure 27 The semiconductor memory device 600 may include a buffer die 610 and a set of dies 620 arranged in a stacked chip structure to provide soft error analysis and correction functions.

[0203] The set of dies 620 may include multiple memory dies 620-1 to 620-p stacked on buffer die 610 and transmitting data through multiple through-substrate paths (e.g., through-silicon paths (TSV)) lines.

[0204] At least one of the memory dies 620-1 to 620-p may include: a cell core 621 containing an array of memory cells, an ECC circuit 622 that generates transmission parity data based on transmission data to be sent to buffer die 611, a refresh control circuit (RCC) 624, a cleanup control circuit (SCC) 623, and a fault address register (FAR) 625. The ECC circuit 622 may be referred to as the "cell core ECC circuit". The ECC circuit 622 may employ... Figure 2 or Figure 9 The ECC circuit 400. The refresh control circuit 624 can be used. Figure 4 The refresh control circuit 385. The cleaning control circuit 623 can be adopted. Figure 7 Cleaning control circuit 500 or Figure 13 The cleaning control circuit 500a.

[0205] When a refresh operation is performed on a row of memory cells, the ECC circuit 622 and the cleanup control circuit 623 can perform a cleanup operation on the rows of memory cells in the memory die. During a first interval of the cleanup operation, the ECC circuit 622 performs error detection and correction operations on the first row of memory cells to count the number of errors. When the counted number of errors equals zero, error detection and correction operations can be performed on the second row of memory cells during a second interval of the cleanup operation. Therefore, the ECC circuit 622 can perform cleanup operations on rows of memory cells quickly.

[0206] The buffer die 610 may include a path ECC circuit 612 that, when a transmission error is detected from the transmitted data received via the TSV line, corrects the transmission error using transmitted parity data and generates error-corrected data.

[0207] Semiconductor memory device 600 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals via TSV lines. TSV lines may also be referred to as "through electrodes".

[0208] The data TSV line group 632 formed in at least one of the memory dies 620-1 to 620-p may include TSV lines L1 to Lp, and the parity TSV line group 634 may include TSV lines L10 to Lq.

[0209] The TSV lines L1 to Lp of the data TSV line group 632 and the parity TSV lines L10 to Lq of the parity TSV line group 634 can be connected to the microbumps MCB correspondingly formed between the storage dies 620-1 to 620-p.

[0210] At least one of the memory dies 620-1 to 620-p may include a DRAM cell, each including at least one access transistor and a storage capacitor.

[0211] Semiconductor memory device 600 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with the host via data bus B10. Buffer die 610 may be connected to memory controller 100 via data bus B10.

[0212] The path ECC circuit 612 can determine whether a transmission error has occurred in the transmitted data received via the data TSV line group 632 based on the transmitted parity data received via the parity TSV line group 634. When a transmission error is detected, the path ECC circuit 612 can use the transmitted parity data to correct the transmission error. When the transmission error is uncorrectable, the path ECC circuit 612 can output information indicating that an uncorrectable data error has occurred.

[0213] Figure 28 A flowchart illustrating a method of operating a semiconductor memory device according to various example embodiments.

[0214] refer to Figures 1 to 21 , Figure 22A , Figure 22B , Figure 23 , Figure 24 , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figure 27 and Figure 28 In a method of operating a semiconductor memory device including a memory cell array 300 (the memory cell array 300 includes multiple memory cell rows, and each of the multiple memory cell rows includes multiple volatile memory cells), a memory cell row for performing a cleanup operation is selected from the memory cell rows based on a refresh row address (operation S210). That is, the cleanup control circuit 500 or 500a can generate a cleanup address by counting refresh row addresses.

[0215] In the first interval of the cleanup operation, the ECC circuit 400 performs error detection and correction operations on multiple subpages in the selected memory cell row to count the number of errors (operation S230). The ECC circuit 400 can determine the sub-operation to be performed in the second interval of the cleanup operation based on the count of errors in the first interval (operation S250).

[0216] Control logic circuit 210 may, in the second interval, not write back the correction codeword in response to the count of errors being equal to or greater than a reference value. Control logic circuit 210 may, in the second interval, write back the correction codeword in the corresponding sub-page in response to the count of errors being less than the reference value but greater than zero. Control logic circuit 210 may, in the second interval, perform error detection and correction operations on multiple sub-pages in the second memory cell row in response to the count of errors being zero.

[0217] Figure 29 A diagram illustrating a semiconductor package including stacked memory devices according to various example embodiments.

[0218] refer to Figure 29 The semiconductor package 900 may include one or more stacked memory devices 910 and a graphics processing unit (GPU) 920. The GPU 920 may include a memory controller (CONT) 925.

[0219] Stacked memory devices 910 and GPU 920 can be mounted on interposer 930, and the interposer on which the stacked memory devices 910 and GPU 920 are mounted can be mounted on package substrate 940. Package substrate 940 can be mounted on solder balls 950. Memory controller 925 can be adopted... Figure 1 The storage controller 100 in the middle.

[0220] Each stacked memory device 910 can be implemented in various forms and can be a high-bandwidth memory (HBM) memory device in the form of multiple stacked layers. Accordingly, each stacked memory device 910 may include buffer dies and multiple memory dies. As previously described, each memory die may include a memory cell array, ECC circuitry, cleanup control circuitry, and a fault address register.

[0221] Multiple stacked storage devices 910 may be mounted on an interposer layer 930, and a GPU 920 may communicate with the multiple stacked storage devices 910. For example, each stacked storage device 910 and GPU 920 may include a physical region, and communication may be performed between the stacked storage devices 910 and GPU 920 through the physical region.

[0222] As mentioned above, according to various example embodiments, the semiconductor memory device includes an ECC circuit, a cleanup control circuit, and a fault address register. During a first interval of the cleanup operation, the ECC circuit sequentially performs error detection and correction operations on the codewords in the memory cell row specified by the cleanup address provided from the cleanup control circuit to count the number of errors occurring, and can determine sub-operations in a second interval of the cleanup operation based on the counted number of errors. Therefore, the ECC circuit can rapidly perform the cleanup operation during the initial interval after power is applied to the semiconductor memory device, and memory cell rows with row faults can be quickly detected.

[0223] Various aspects of this invention can be applied to systems using semiconductor memory devices employing ECC circuitry. For example, various aspects of this invention can be applied to systems using semiconductor memory devices as working memory, such as smartphones, navigation systems, laptop computers, desktop computers, and game consoles.

[0224] The foregoing descriptions of exemplary embodiments are not intended to be limiting. While some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of this disclosure as defined by the appended claims. < / g> < / g> < / g> < / g> < / g>

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A storage cell array, the storage cell array comprising a plurality of storage cell rows, each of the plurality of storage cell rows comprising volatile storage cells coupled to a plurality of bit lines; Error correction code circuit, also known as ECC circuit; Fault address register; A cleanup control circuit, configured to: generate a cleanup address for performing a cleanup operation on a first storage cell row selected from the plurality of storage cell rows, based on a refresh row address used to refresh the storage cell rows; and A control logic circuit configured to control the ECC circuit and the cleanup control circuit. The control logic circuit is further configured as follows: The ECC circuit is controlled such that during the first interval of the cleanup operation, the ECC circuit performs error detection and correction operations on multiple codewords of multiple subpages in the first storage cell row in units of codewords to count the number of errors. Based on the number of errors occurring in the first storage cell row, a row fault detection operation is performed to selectively store the row address of the first storage cell row as the row fault address in the fault address register; and The sub-operation in the cleanup operation, located in the second interval following the first interval, is determined based on the number of errors occurring in the first storage cell row.

2. The semiconductor memory device according to claim 1, wherein, The control logic circuit is further configured to, in response to the number of errors occurring in the first storage cell row being zero, control the ECC circuit such that the ECC circuit performs the error detection and correction operation on multiple sub-pages in a second storage cell row selected from the plurality of storage cell rows, the second storage cell row being different from the first storage cell row, and The determined sub-operations include: error detection and correction operations on the plurality of sub-pages in the second storage cell row.

3. The semiconductor memory device according to claim 1, wherein, The control logic circuit is further configured to, in response to the number of errors being greater than zero and less than a reference value, control the ECC circuit such that the ECC circuit writes the corrected codeword back to the corresponding subpage of the first memory cell row during the second interval of the cleanup operation, and The determined sub-operation includes: writing the corrected codeword back to the corresponding sub-page of the first storage cell row.

4. The semiconductor memory device according to claim 1, wherein, The control logic circuit is further configured to, in response to the number of errors being equal to or greater than a reference value, control the ECC circuit such that the ECC circuit does not write back the corrected codeword to the corresponding subpage of the first memory cell row during the second interval of the cleanup operation, and The determined sub-operation includes: not writing the corrected codeword back to the corresponding sub-page of the first storage cell row.

5. The semiconductor memory device according to claim 1, further comprising: A column decoder configured to, in normal mode, continuously generate column selection signals for selecting a subset of the bit lines in response to a column address for a first cycle. The control logic circuit is further configured to control the column decoder such that, during an initial interval after power is applied to the semiconductor memory device, the column decoder generates a read column selection signal at a second period less than the first period, the read column selection signal being associated with a read operation performed during the first interval of the cleanup operation, and The initial interval is a predetermined interval.

6. The semiconductor memory device according to claim 5, wherein, The control logic circuit is further configured to control the column decoder such that the column decoder does not generate a write column selection signal associated with the write operation corresponding to the read operation during the first interval of the cleanup operation.

7. The semiconductor memory device according to claim 5, wherein, The first period is G times the second period, and G is a natural number equal to or greater than 2.

8. The semiconductor memory device according to claim 5, wherein, The interval at which the cleanup operation is performed is determined based on the continuous refresh commands received from outside the semiconductor memory device.

9. The semiconductor memory device according to claim 1, wherein, In the cleanup operation, the control logic circuit is further configured to control the cleanup control circuit such that, during an initial interval after power is applied to the semiconductor memory device, the cleanup control circuit generates the cleanup address at a second cycle less than a first cycle defined in the specification of the semiconductor memory device, and The initial interval is a predetermined interval.

10. The semiconductor memory device according to claim 9, wherein, The control logic circuit is further configured to control the ECC circuit such that the ECC circuit: A background write operation is performed during the initial interval to write default data to the storage cell row; and Perform the cleanup operation on the default data.

11. The semiconductor memory device according to claim 1, wherein, The control logic circuit is further configured to: in response to the number of errors detected in the first storage cell row during the first interval being equal to or greater than K, store the row address of the first storage cell row as the row fault address in the fault address register, where K is a natural number equal to or greater than 2.

12. The semiconductor memory device according to claim 1, wherein, The cleaning control circuit includes: A counter configured to count the refresh row addresses to generate an internal cleanup signal, wherein the counter activates the internal cleanup signal whenever the counter has counted N refresh row addresses, where N is a natural number equal to or greater than 2; A cleanup address generator, configured to generate a normal cleanup address associated with a normal cleanup operation of the first memory cell row in a first cleanup mode, in response to the internal cleanup signal and the cleanup mode signal; and A weak codeword address generator is configured to generate, in response to the internal cleanup signal and the cleanup mode signal, a weak codeword address associated with a weak cleanup operation in a second cleanup mode, the weak cleanup operation being associated with a weak codeword in the first storage cell row.

13. The semiconductor memory device according to claim 12, in, The normal cleanup address includes the cleanup row address specifying a storage cell row and the cleanup column address specifying one of the codewords included in the storage cell row, and The cleanup address generator includes: A page segment counter, configured to increment the cleanup column address by 1 during the activation of the internal cleanup signal; and A row counter is configured to increment the cleanup row address by 1 whenever the cleanup column address reaches its maximum value.

14. The semiconductor memory device according to claim 12, wherein, The weak codeword address generator includes: An address storage table, configured to store the address information of the weak codeword; and A table pointer, configured to generate a pointer signal that provides location information for the address storage table in response to the internal cleanup signal.

15. The semiconductor memory device according to claim 1, wherein, The ECC circuit includes an ECC decoder, which is configured to perform the error detection and correction operations on multiple codewords. The ECC decoder includes: A data latch, configured to store the plurality of codewords; A checksum generation circuit, configured to generate a checksum based on the master data and parity check data of each of the plurality of codewords; An error locator, configured to generate an error location signal based on the checksum indicating the location of at least one error bit in the master data; and A data corrector configured to receive codewords selected from the plurality of codewords stored in the data latch, and configured to correct erroneous bits in each selected codeword.

16. The semiconductor memory device according to claim 1, wherein, The control logic circuit is further configured to perform soft encapsulation and repair on the storage cell row corresponding to the row fault address by storing the data stored in the storage cell row corresponding to the row fault address in the redundant area of ​​the storage cell array.

17. The semiconductor memory device of claim 1, further comprising: At least one buffer die; as well as Multiple memory dies are stacked on the at least one buffer die and transmit data via multiple through-silicon vias. Wherein, at least one of the plurality of memory dies includes the memory cell array, the ECC circuit, the cleanup control circuit, and the refresh control circuit that generates the refresh row address.

18. A method of operating a semiconductor memory device including an array of memory cells, the array of memory cells including a plurality of rows of memory cells, each of the plurality of rows of memory cells including a plurality of volatile memory cells, the method comprising: A first storage cell row is selected from the plurality of storage cell rows based on the refresh row address used to refresh the storage cells connected to the storage cell row; During the first interval of the cleanup operation, error detection and correction operations are performed on multiple codewords of multiple subpages in the first storage unit row, in units of codewords, using an error correction code circuit to count the number of errors; and Based on the number of errors, determine the sub-operations in the cleanup operation within the second interval following the first interval. The sub-operations include one of the following: writing the corrected codeword back to the corresponding sub-page in the first storage cell row, or the error detection and correction operation for the second storage cell row of the plurality of storage cell rows that is different from the first storage cell row.

19. The method according to claim 18, further comprising: A row fault detection operation is performed based on the number of errors occurring in the first storage cell row to selectively store the row address of the first storage cell row as a row fault address in the fault address register.

20. A semiconductor memory device, the semiconductor memory device comprising: A storage cell array, the storage cell array comprising a plurality of storage cell rows, each of the plurality of storage cell rows comprising volatile storage cells; Error correction code circuit; Fault address register; Cleaning control circuit, the cleaning control circuit being configured as follows: Generate cleanup address, Based on the refresh row address used to refresh the storage cell row, a cleanup operation is performed on the first storage cell row selected from the plurality of storage cell rows; and Control logic circuit, wherein the control logic circuit is configured as follows: Control the ECC circuit so that the ECC circuit: During the first interval of the cleanup operation, error detection and correction operations are performed on multiple codewords of multiple subpages in the first storage unit row in units of codewords to count the number of errors. In response to the fact that the number of errors occurring in the first storage cell row is zero. The error detection and correction operation is performed on multiple subpages in a second storage cell row that is different from the first storage cell row. Based on the number of errors occurring in the first storage cell row, a row fault detection operation is performed to selectively store the row address of the first storage cell row as the row fault address in the fault address register; and The sub-operation in the cleanup operation, located in the second interval after the first interval, is determined based on the number of errors occurring in the first storage cell row. The sub-operations include one of the following: writing the corrected codeword back to the corresponding sub-page in the first storage cell row, or the error detection and correction operation for a second storage cell row that is different from the first storage cell row.

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