Memory device and operating method of a memory device

Abstract

Embodiments of the present disclosure relate to a memory device and an operating method of a memory device. The present disclosure relates to an electronic device. A memory device according to the present disclosure includes a memory block coupled to a plurality of local word lines, a peripheral circuit configured to couple the plurality of local word lines to a plurality of global word lines and configured to perform an operation on the memory block, and a control logic configured to control the peripheral circuit to cause or increase a leakage current of a transmission switch circuit to discharge a potential level of the plurality of local word lines when the memory device enters a ready state after the operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0185074, filed on December 28, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention generally relate to electronic devices, and more specifically to the operation of memory devices and semiconductor devices. Background Technology

[0004] Storage devices are configured to store data in response to control from host devices such as computers or smartphones. Storage devices may include memory devices that store data and memory controllers that control the memory devices. Memory devices can be categorized as volatile memory devices and non-volatile memory devices.

[0005] Volatile memory devices can retain data as long as power is supplied, but may lose stored data if power is unavailable. Types of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), and others.

[0006] Even in the absence of a power supply, non-volatile memory devices may not lose data. Types of non-volatile memory devices can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), and flash memory. Summary of the Invention

[0007] According to an embodiment, the memory device may include: a memory block coupled to a plurality of local word lines; peripheral circuitry configured to couple the plurality of local word lines to a plurality of global word lines via a transmission switch circuitry and configured to perform operations on the memory block; and control logic configured to control the peripheral circuitry to cause or increase the leakage current of the transmission switch circuitry to discharge the potential levels of the plurality of local word lines when the memory device enters a ready state after operation.

[0008] According to an embodiment, a method of operating a memory device may include: performing operations on a memory block coupled to a plurality of local word lines; and when the memory device enters a ready state, causing or increasing the leakage current of a transmission switch circuit that couples the plurality of local word lines to a plurality of global word lines, and discharging the potential levels of the plurality of local word lines.

[0009] According to an embodiment, the memory device may include: a memory block coupled to a plurality of local word lines; and peripheral circuitry configured to couple the plurality of local word lines to a plurality of global word lines via a plurality of transfer transistors, configured to perform a read operation on the memory block, and configured to discharge the potential levels of the plurality of local word lines by pre-charging or floating the body regions of the plurality of transfer transistors when the memory device enters a ready state after the read operation. Pre-charging or floating the body regions causes or increases the leakage current of the plurality of transfer transistors. Attached Figure Description

[0010] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure;

[0011] Figure 2 It's a diagram. Figure 1 A diagram illustrating the structure of a memory device;

[0012] Figure 3 It's a diagram. Figure 2 A diagram illustrating the structure of a memory cell array;

[0013] Figure 4 It's a diagram. Figure 2 A diagram illustrating another embodiment of a memory cell array;

[0014] Figure 5 It's a diagram. Figure 4 The circuit diagram of one of the memory blocks (BLKa) from BLK1 to BLKz is shown;

[0015] Figure 6 It's a diagram. Figure 4 The circuit diagram of another memory block (BLKb) in memory blocks BLK1 to BLKz is shown;

[0016] Figure 7 This is a diagram illustrating global and local character lines;

[0017] Figure 8 It's a diagram. Figure 7 The diagram shows the transmission switch circuit.

[0018] Figure 9 It's a diagram. Figure 8 A diagram showing the transmission transistor;

[0019] Figure 10 This is a diagram illustrating the negative boost of the channel voltage during a read operation;

[0020] Figure 11 This is a timing diagram illustrating the operation of a memory device according to an embodiment of the present disclosure;

[0021] Figure 12 This is a timing diagram illustrating the operation of a memory device according to an embodiment of the present disclosure; and

[0022] Figure 13 This is a timing diagram illustrating the operation of a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions of examples of embodiments of the concepts disclosed in this specification are illustrated to illustrate examples of embodiments of the concepts, and examples of embodiments of the concepts may be implemented in various forms, but the description is not limited to the examples of embodiments described in this specification.

[0024] Various embodiments may relate to a memory device with improved read / recovery performance and a method of operating the memory device.

[0025] Figure 1 This is a diagram illustrating a storage device 50 according to an embodiment of the present disclosure.

[0026] Reference Figure 1 Storage device 50 may include memory device 100 and memory controller 200, the memory controller 200 controlling the operation of memory device 100. Storage device 50 may be configured to store data in response to host control. Examples of storage device 50 may include cellular phones, smartphones, MP3 players, laptops, desktop computers, game consoles, TVs, tablet PCs, or in-vehicle infotainment systems.

[0027] Storage device 50 can be manufactured as one of various types of storage devices according to a host interface corresponding to the communication method with the host. For example, storage device 50 can be configured as any of the following types of storage devices: solid-state drives (SSDs), multimedia cards in the form of MMC, eMMC, RS-MMC and micro-MMC, secure digital cards in the form of SD, mini-SD and micro-SD, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, PCMCIA card storage devices, peripheral component interconnect (PCI) card storage devices, PCI rapid (PCI-E) card storage devices, compact flash (CF) cards, smart media cards and memory sticks.

[0028] The storage device 50 can be manufactured in any of a variety of packages. For example, the storage device 50 can be manufactured in any of a variety of package types, such as POP, SIP, SOC, MCP, COB, WFP, and WSP.

[0029] The memory device 100 can store data. The memory device 100 can operate in response to the control of the memory controller 200. The memory device 100 may include a memory cell array, which includes a plurality of memory cells for storing data.

[0030] Each memory cell in the memory unit can be a single-level cell (SLC) that stores 1 bit of data, a multi-level cell (MLC) that stores 2 bits of data, a three-level cell (TLC) that stores 3 bits of data, or a four-level cell (QLC) that stores 4 bits of data.

[0031] The memory cell array may include multiple memory blocks. Each memory block may include multiple memory cells. Each memory block may include multiple pages. According to an embodiment, a page may be a unit for storing data in the memory device 100 or retrieving data stored in the memory device 100.

[0032] A memory block can be a unit used to erase data. According to embodiments, examples of memory device 100 may include Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR) SDRAM, Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory Device, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM). For ease of explanation, it is assumed that memory device 100 is NAND Flash Memory.

[0033] Memory device 100 can receive commands and addresses from memory controller 200 and access regions selected in response to addresses in the memory cell array. That is, memory device 100 can perform operations corresponding to commands on regions selected in response to addresses. For example, memory device 100 can perform write operations (programming operations), read operations, and erase operations. During a programming operation, memory device 100 can program data into the region selected in response to an address. During a read operation, memory device 100 can read data from the region selected by the address. During an erase operation, memory device 100 can erase data from the region selected by the address.

[0034] The memory controller 200 can control the overall operation of the storage device 50.

[0035] When power is applied to storage device 50, memory controller 200 can execute firmware. When storage device 100 is a flash memory device, memory controller 200 can execute firmware such as flash translation layer (FTL) to control communication between the host and storage device 100.

[0036] According to an embodiment, the memory controller 200 can receive data and a logical block address (LBA) from a host and convert the logical block address (LBA) into a physical block address (PBA), which indicates the address of the memory cell in which the data included in the memory device 100 is stored.

[0037] In response to a request from the host, the memory controller 200 can control the memory device 100 to perform programming, reading, or erasing operations. During a programming operation, the memory controller 200 can provide the memory device 100 with a write command, a physical block address, and data. During a read operation, the memory controller 200 can provide the memory device 100 with a read command and a physical block address. During an erasing operation, the memory controller 200 can provide the memory device 100 with an erase command and a physical block address.

[0038] According to an embodiment, regardless of the request from the host, the memory controller 200 can generate commands, addresses, and data and transmit them to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100 to perform background operations, such as programming operations for wear leveling and programming operations for garbage collection.

[0039] According to an embodiment, the memory controller 200 can control at least two memory devices 100. The memory controller 200 can control the memory devices 100 according to an interleaving scheme to improve operational performance. The interleaving scheme can refer to an operational scheme in which the operating cycles of at least two memory devices 100 overlap.

[0040] The host can communicate with the storage device 50 using at least one of a variety of communication methods, such as Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCIe, Non-Volatile Memory Fast (NVMe), Universal Flash (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Depleted DIMM (LRDIMM).

[0041] Figure 2 It's a diagram. Figure 1 A diagram illustrating the structure of the memory device 100.

[0042] Reference Figure 2 The memory device 100 may include a memory cell array 110, peripheral circuitry 120, and control logic 130. The control logic 130 may be implemented as hardware, software, or a combination of both. For example, the control logic 130 may be control logic circuitry operating according to an algorithm and / or a processor executing control logic code.

[0043] The memory cell array 110 may include multiple memory blocks, namely, first memory block BLK1 to z-th memory block BLKz. The multiple memory blocks BLK1 to BLKz may be coupled to address decoder 121 via row lines RL. The memory blocks BLK1 to BLKz may be coupled to read and write circuitry 123 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. According to an embodiment, the multiple memory cells may be non-volatile memory cells. Among the multiple memory cells, memory cells coupled to the same word line may be defined as a page. In other words, the memory cell array 110 may include multiple pages. According to an embodiment, each of the multiple memory blocks BLK1 to BLKz included in the memory cell array 110 may include multiple dummy cells. One or more dummy cells may be coupled in series between a drain select transistor and a memory cell, and between a source select transistor and a memory cell.

[0044] Each memory cell in the memory cell of the memory device 100 may include a single-level cell (SLC) that stores a single data bit, a multi-level cell (MLC) that stores two data bits, a three-level cell (TLC) that stores three data bits, and a four-level cell (QLC) that stores four data bits.

[0045] The peripheral circuit 120 may include an address decoder 121, a voltage generator 122, a read and write circuit 123, a data input / output circuit 124, and a sensing circuit 125.

[0046] The peripheral circuitry 120 can drive the memory cell array 110. For example, the peripheral circuitry 120 can drive the memory cell array 110 to perform programming operations, read operations, and erase operations.

[0047] Address decoder 121 can be coupled to memory cell array 110 via row lines RL. Row lines RL may include drain select lines, word lines, source select lines, and common source lines. According to embodiments of this disclosure, word lines may include normal word lines and dummy word lines. According to embodiments, row lines RL may also include pipe select lines.

[0048] Address decoder 121 can be configured to operate in response to control of control logic 130. Address decoder 121 can receive address ADDR from control logic 130.

[0049] Address decoder 121 can be configured to decode the block address of the received address ADDR. Address decoder 121 can select at least one memory block from memory blocks BLK1 to BLKz based on the decoded block address. Address decoder 121 can be configured to decode the row address from the received address ADDR. Address decoder 121 can select at least one word line from the word lines of the selected memory block based on the decoded row address. Address decoder 121 can apply an operating voltage Vop provided from voltage generator 122 to the selected word line.

[0050] During programming operations, address decoder 121 can apply a programming voltage to the selected word line and a programming pass voltage with a lower voltage level than the programming voltage to the unselected word line. During programming verification operations, address decoder 121 can apply a verification voltage to the selected word line and a verification pass voltage with a higher voltage level than the verification voltage to the unselected word line.

[0051] During a read operation, the address decoder 121 can apply a read voltage to the selected word line and apply a read pass voltage with a voltage level greater than the read voltage to the unselected word line.

[0052] According to embodiments of this disclosure, memory device 100 can perform an erase operation on each memory block. During the erase operation, the address ADDR input to memory device 100 may include a block address. Address decoder 121 can decode the block address and select at least one memory block from the memory blocks based on the decoded block address. During the erase operation, address decoder 121 may apply a ground voltage to the word line input to the selected memory block.

[0053] According to an embodiment, address decoder 121 can be configured to decode the column address of the transmitted address ADDR. The decoded column address can be transmitted to read and write circuitry 123. For example, address decoder 121 may include components such as row decoder, column decoder, and address buffer.

[0054] Voltage generator 122 can be configured to generate multiple operating voltages Vop by using an external power supply voltage supplied to memory device 100. Voltage generator 122 can be controlled by control logic 130.

[0055] According to an embodiment, voltage generator 122 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 122 can be used as the operating voltage for memory device 100.

[0056] According to an embodiment, voltage generator 122 can generate multiple voltages Vop by using an external power supply voltage or an internal power supply voltage. Voltage generator 122 can be configured to generate various voltages required by memory device 100. For example, voltage generator 122 can generate multiple erase voltages, multiple programming voltages, multiple pass voltages, multiple selected read voltages, and multiple unselected read voltages.

[0057] The voltage generator 122 may include a plurality of pump capacitors that receive an internal power supply voltage to generate a plurality of operating voltages Vop with various voltage levels, and the plurality of operating voltages Vop can be generated by selectively activating the plurality of pump capacitors in response to control of control logic 130.

[0058] Multiple operating voltages Vop can be provided to the memory cell array 110 by the address decoder 121.

[0059] The read and write circuitry 123 may include first page buffers PB1 through m-th page buffers PBm. First page buffers PB1 through m-th page buffers PBm may be coupled to the memory cell array 110 via first bit lines BL1 through m-th bit lines BLm, respectively. First page buffers PB1 through m-th page buffers PBm may operate in response to control logic 130.

[0060] Page buffers PB1 through PBm (page m) can transfer data DATA with data input / output circuit 124. During programming operations, page buffers PB1 through PBm can receive the data DATA to be stored via data input / output circuit 124 and data line DL.

[0061] During programming operations, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the m-th page buffer PBm can transmit data DATA received through the data input / output circuit 124 to the selected memory cell via bit lines BL1 to BLm. The memory cell of the selected page can be programmed based on the transmitted data DATA. Memory cells coupled to bit lines to which a programming enable voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of memory cells coupled to bit lines to which a programming disable voltage (e.g., power supply voltage) is applied can be maintained. During programming verification operations, the first page buffer PB1 to the m-th page buffer PBm can read the data DATA stored in the memory cell from the selected memory cell via bit lines BL1 to BLm.

[0062] During a read operation, the read and write circuit 123 can read data DATA from the memory cell of the selected page via the bit line BL and output the read data DATA to the data input / output circuit 124.

[0063] During an erase operation, the read and write circuitry 123 can float the bit line BL. According to an embodiment, the read and write circuitry 123 may include a column selector.

[0064] The data input / output circuit 124 is coupled to the first page buffer PB1 to the m-th page buffer PBm via the data line DL. The data input / output circuit 124 can operate in response to the control logic 130.

[0065] The data input / output circuit 124 may include multiple input / output buffers (not shown) for receiving input data DATA. During programming operations, the data input / output circuit 124 may receive data DATA to be stored from an external controller (not shown). During reading operations, the data input / output circuit 124 may output data DATA transferred from the first page buffer PB1 to the m-th page buffer PBm included in the read and write circuit 123 to the external controller.

[0066] The sensing circuit 125 can generate a reference current in response to the enable bit signal VRYBIT generated by the control logic 130, and can compare the sensed voltage VPB received from the read and write circuit 123 with the reference voltage generated by the reference current to output a pass signal or a failure signal during a read operation or a verification operation.

[0067] Control logic 130 can be coupled to address decoder 121, voltage generator 122, read and write circuitry 123, data input / output circuitry 124, and sensing circuitry 125. Control logic 130 can be configured to control the overall operation of memory device 100. Control logic 130 can operate in response to commands (CMD) transmitted from external devices.

[0068] Control logic 130 can control peripheral circuitry 120 by generating various signals in response to command CMD and address ADDR. For example, control logic 130 can output operation signal OPSIG, address ADDR, read and write control signal PBSIGNALS, and enable bit VRYBIT in response to command CMD and address ADDR. Control logic 130 can output operation signal OPSIG to voltage generator 122, address ADDR to address decoder 121, read and write control signal to read and write circuit 123, and enable bit VRYBIT to sensing circuit 125. Additionally, control logic 130 can determine whether the verification operation passed or failed in response to pass / fail signal PASS / FAIL output by sensing circuit 125.

[0069] According to an embodiment, the address decoder 121 may include a transmission switch circuit, the coupling of which will be referred to below. Figure 7 The global word line and local word line are described. The operating voltage Vop generated by voltage generator 122 can be applied to the global word line. The local word line can be coupled to the memory block. Figure 2 The local word lines shown may include line lines RL.

[0070] Address decoder 121 can apply a block select signal to the transfer switch circuit based on the address ADDR received from control logic 130. When the transfer switch circuit is turned on in response to the applied block select signal, the operating voltage Vop applied to the global word line can be transferred to the local word line.

[0071] According to an embodiment, the peripheral circuit 120 may include a transmission switch circuit coupled with multiple local word lines and multiple global word lines, and may perform read operations on memory blocks. During a word line discharge operation (as described below)... Figure 13During the read operation described, when the channel potential of the memory block that has been boosted to a negative voltage is restored to the ground voltage level, the peripheral circuit 120 can discharge the potential levels of multiple local word lines to the ground voltage level.

[0072] When memory device 100 enters a ready state after a read operation, control logic 130 can control peripheral circuitry 120 to discharge the potential levels of multiple local word lines by increasing the leakage current of the transmission switch circuit. Memory device 100 can be in a busy state during a read operation or in a ready state when the read operation is completed.

[0073] The transfer switching circuit may include multiple transfer transistors, each coupled to multiple local word lines and multiple global word lines. The transfer switching circuit can increase the leakage current of the transfer transistors by pre-charging the body regions of the multiple transfer transistors to a positive voltage or by floating the body regions of the transfer transistors.

[0074] When the memory device 100 enters the ready state, the transfer switching circuit can apply a block select signal with a low voltage level to the gate of each of the multiple transfer transistors, and can apply a positive voltage to the body region of the multiple transfer transistors or float the body region of the multiple transfer transistors.

[0075] Figure 3 It's a diagram. Figure 2 A diagram illustrating the structure of the memory cell array 110.

[0076] Reference Figure 3 The first memory block BLK1 to the z-th memory block BLKz can be jointly coupled to the first bit line BL1 to the m-th bit line BLm. Figure 3 For ease of explanation, the components included in the first memory block BLK1 of the multiple memory blocks BLK1 to BLKz are illustrated, and the components included in the second memory blocks BLK2 to BLKz can be omitted. Each of the remaining memory blocks BLK2 to BLKz can be configured in substantially the same way as the first memory block BLK1.

[0077] The first memory block BLK1 may include multiple first unit strings CS1_1 to m-th unit strings CS1_m, where m is a positive integer. Each unit string from the first unit strings CS1_1 to the m-th unit strings CS1_m may be coupled to bit lines BL1 to BLm respectively. Each unit string from the first unit strings CS1_1 to the m-th unit strings CS1_m may include a drain selection transistor DST, multiple memory cells MC1 to MCn coupled in series, and a source selection transistor SST, where n is a positive integer.

[0078] The gate terminal of the drain-select transistor DST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m can be coupled to the first drain-select line DSL1. The gate terminal of the first memory cell MC1 to the n-th memory cell MCn included in each of the first unit strings CS1_1 to the m-th unit string CS1_m can be coupled to the first word line WL1 to the n-th word line WLn, respectively. The gate terminal of the source-select transistor SST included in each of the first unit strings CS1_1 to the m-th unit string CS1_m can be coupled to the source-select line SSL1.

[0079] For ease of explanation, the structure of the unit strings is described based on the first unit string CS1_1 among multiple unit strings CS1_1 to CS1_m. However, it should be understood that each of the remaining unit strings CS1_2 to CS1_m can be configured in the same way as the first unit string CS1_1.

[0080] The drain terminal of the drain select transistor DST included in the first unit string CS1_1 can be coupled to the first bit line BL1. The source terminal of the drain select transistor DST included in the first unit string CS1_1 can be coupled to the drain terminal of the first memory cell MC1 included in the first unit string CS1_1. The first memory cells MC1 to the nth memory cell MCn can be coupled in series with each other. The drain terminal of the source select transistor SST included in the first unit string CS1_1 can be coupled to the source terminal of the nth memory cell MCn included in the first unit string CS1_1. The source terminal of the source select transistor SST included in the first unit string CS1_1 can be coupled to the common source line CSL. According to an embodiment, the common source line CSL can be connected together to the first memory block BLK1 to the zth memory block BLKz.

[0081] Drain select line DSL1, first word lines WL1 to nth word lines WLn, and source select line SSL1 can be included Figure 2 In the row line RL shown, the drain select line DSL1, the first word lines WL1 to the nth word lines WLn, and the source select line SSL1 can be controlled by the address decoder 121. The common source line CSL can be controlled by the control logic 130. The first bit line BL1 to the mth bit line BLm can be controlled by the read and write circuit 123.

[0082] Figure 4 It's a diagram. Figure 2 A diagram illustrating another embodiment of the memory cell array 110.

[0083] Reference Figure 4The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include multiple memory cells stacked on a substrate. The multiple memory cells may be arranged in the +X, +Y, and +Z directions. The structure of each memory block will be referenced... Figure 5 and Figure 6 describe.

[0084] Figure 5 It's a diagram. Figure 4 The circuit diagram shown is for one of the memory blocks (BLKa) from BLK1 to BLKz.

[0085] Reference Figure 5 The memory block BLKa may include multiple cell strings CS11 to CS1m and CS21 to CS2m. According to an embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m may be formed in a 'U' shape. In the memory block BLKa, 'm' cell strings may be arranged in the row direction (i.e., the +X direction). Figure 5 The illustration shows two unit strings arranged in the column direction (i.e., the +Y direction). However, it should be understood that three or more unit strings can be arranged in the column direction.

[0086] According to an embodiment, a memory block may include multiple sub-blocks. A sub-block may include a string of cells arranged in a 'U' shape in a row.

[0087] Each of the cell strings CS11 to CS1m and CS21 to CS2m may include at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0088] Each of the source-select transistor (SST) and drain-select transistor (DST), and each of the memory cells MC1 to MCn, may have a structure similar to each other. According to an embodiment, each of the source-select transistor (SST), drain-select transistor (DST), and memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a barrier insulating layer. According to an embodiment, pillars for providing the channel layer may be provided in each cell string. According to an embodiment, pillars for providing at least one of the channel layer, tunneling insulating layer, charge storage layer, and barrier insulating layer may be provided in each cell string.

[0089] The source selection transistor SST of each cell string can be coupled between the common source line CSL and the first memory cell MC1 to the nth memory cell MCn.

[0090] According to an embodiment, source selection transistors in cell strings arranged in the same row can be coupled to source selection lines extending in the row direction, and source selection transistors in cell strings arranged in different rows can be coupled to different source selection lines. Figure 5 In the first row, the source selection transistors SST of cell strings CS11 to CS1m can be coupled to the first source selection line SSL1. In the second row, the source selection transistors SST of cell strings CS21 to CS2m can be coupled to the second source selection line SSL2.

[0091] According to another embodiment, the source selection transistors SST of cell strings CS11 to CS1m and CS21 to CS2m can be co-coupled to a single source selection line.

[0092] The first memory cell MC1 to the nth memory cell MCn of each cell string can be coupled between the source selection transistor SST and the drain selection transistor DST.

[0093] The first memory cells MC1 to the nth memory cell MCn can be divided into first memory cells MC1 to the pth memory cells MCp and (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first memory cells MC1 to the pth memory cells MCp can be arranged sequentially in the direction opposite to the +Z direction and can be coupled in series between the source selection transistor SST and the drain selection transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn can be arranged sequentially in the +Z direction and can be coupled in series between the drain selection transistor PT and the drain selection transistor DST. The first memory cells MC1 to the pth memory cells MCp and the (p+1)th memory cells MCp+1 to the nth memory cells MCn can be coupled through the drain transistor PT. The gates of the first memory cells MC1 to the nth memory cells MCn in each cell string can be coupled to the first word line WL1 to the nth word line WLn, respectively.

[0094] The gate of the pipe transistor PT in each unit string can be coupled to the pipe line PL.

[0095] The drain select transistor (DST) of each cell string can be coupled between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction can be coupled to drain select lines extending along the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row can be coupled to the first drain select line DSL1. The drain select transistors (DST) of cell strings CS21 to CS2m in the second row can be coupled to the second drain select line DSL2.

[0096] A string of cells arranged in the column direction can be coupled to a bit line extending along the column direction. Figure 5 In the first column, the cell strings CS11 and CS21 can be coupled to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column can be coupled to the m-th bit line BLm.

[0097] Memory cells coupled to the same word line in a cell string arranged in the row direction can form a single page. For example, memory cells coupled to the first word line WL1 in cell strings CS11 to CS1m in the first row can form a single page. Memory cells coupled to the first word line WL1 in cell strings CS21 to CS2m in the second row can form another page. A cell string arranged in a row direction can be selected when one of the drain select lines DSL1 and DSL2 is selected. A page can be selected from the selected cell string when one of the word lines WL1 to WLn is selected.

[0098] According to another embodiment, even-numbered bit lines and odd-numbered bit lines can replace the first bit line BL1 to the m-th bit line BLm. Additionally, even-numbered cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be coupled to even-numbered bit lines, and odd-numbered cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction can be coupled to odd-numbered bit lines.

[0099] According to an embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, one or more dummy memory cells can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, one or more dummy memory cells can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. When more dummy memory cells are provided, the operational reliability of the memory block BLKa can be improved, while the size of the memory block BLKa may be increased. On the other hand, when the number of dummy memory cells decreases, the size of the memory block BLKa can be reduced, and the operational reliability of the memory block BLKa may be reduced.

[0100] To efficiently control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on some or all of the dummy memory cells before or after an erase operation on the memory block BLKa. When the erase operation is performed after the programming operation, the dummy memory cell can have a desired threshold voltage by controlling the voltage applied to the dummy word line coupled to the corresponding dummy memory cell.

[0101] Figure 6 It's a diagram. Figure 4 The circuit diagram of another memory block (BLKb) in memory blocks BLK1 to BLKz is shown.

[0102] Reference Figure 6 The memory block BLKb may include multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may extend in the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' may include at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST, which are stacked on a substrate (not shown) under the memory block BLK1'.

[0103] According to an embodiment, a memory block may include multiple sub-blocks. A sub-block may include a string of cells arranged in an 'I' shape in a row.

[0104] The source select transistor (SST) of each cell string can be coupled between a common source line CSL and the first memory cell MC1 to the nth memory cell MCn. Source select transistors of cell strings arranged in the same row can be coupled to the same source select line. The source select transistors (SST) of cell strings CS11' to CS1m' arranged in the first row can be coupled to the first source select line SSL1. The source select transistors (SST) of cell strings CS21' to CS2m' arranged in the second row can be coupled to the second source select line SSL2. According to another embodiment, the source select transistors (SST) of cell strings CS11' to CS1m' and CS21' to CS2m' can be jointly coupled to a single source select line.

[0105] The first memory cell MC1 to the nth memory cell MCn in each cell string can be coupled in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn can be coupled to the first word line WL1 to the nth word line WLn, respectively.

[0106] The drain select transistor (DST) of each cell string can be coupled between the corresponding bit line and memory cells MCp+1 to MCn. The drain select transistors of cell strings arranged in the row direction can be coupled to drain select lines extending along the row direction. The drain select transistors (DST) of cell strings CS11' to CS1m' in the first row can be coupled to the first drain select line DSL1. The drain select transistors (DST) of cell strings CS21' to CS2m' in the second row can be coupled to the second drain select line DSL2.

[0107] Therefore, in addition to removing the pipe transistor PT from each cell string of the memory block BLKb, Figure 6 The memory block BLKb shown can have the same characteristics as... Figure 5 The equivalent circuit is similar to the memory block BLKa shown.

[0108] According to another embodiment, even-numbered bit lines and odd-numbered bit lines can replace the first bit line BL1 to the m-th bit line BLm. Additionally, even-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be coupled to even-numbered bit lines respectively, and odd-numbered cell strings arranged in the row direction CS11' to CS1m' or CS21' to CS2m' can be coupled to odd-numbered bit lines respectively.

[0109] According to an embodiment, at least one of the first memory cells MC1 to the nth memory cell MCn can be used as a dummy memory cell. For example, one or more dummy memory cells can be provided to reduce the electric field between the source selection transistor SST and the first memory cells MC1 to the nth memory cells MCn. Alternatively, one or more dummy memory cells can be provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. When more dummy memory cells are provided, the operational reliability of the memory block BLKb can be improved, while the size of the memory block BLKb may be increased. On the other hand, when fewer memory cells are provided, the size of the memory block BLKb can be reduced, while the operational reliability of the memory block BLKb may be reduced.

[0110] To efficiently control one or more dummy memory cells, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on some or all of the dummy memory cells before or after an erase operation on the memory block BLKb. When the erase operation is performed after the programming operation, the dummy memory cell can have a desired threshold voltage by controlling the voltage applied to the dummy word line coupled to the corresponding dummy memory cell.

[0111] Figure 7This is a diagram illustrating global and local character lines.

[0112] Reference Figure 7 A local word line group may include multiple local word lines coupled to a memory block. A global word line group may include multiple global word lines coupled to multiple local word lines via a transfer switching circuit.

[0113] The first local word line group LWL_G1 may include local word lines coupled to the first memory block BLK1. The second local word line group LWL_G2 may include local word lines coupled to the second memory block BLK2. The third local word line group LWL_G3 may include local word lines coupled to the third memory block BLK3. The fourth local word line group LWL_G4 may include local word lines coupled to the fourth memory block BLK4.

[0114] Local word lines can be coupled to global word lines via a transmission switch circuit.

[0115] The first local word line group LWL_G1 can be coupled to the first global word line group GWL_G1 through the first transmission switch circuit PSC1. The second local word line group LWL_G2 can be coupled to the first global word line group GWL_G1 through the second transmission switch circuit PSC2. The third local word line group LWL_G3 can be coupled to the second global word line group GWL_G2 through the third transmission switch circuit PSC3. The fourth local word line group LWL_G4 can be coupled to the second global word line group GWL_G2 through the fourth transmission switch circuit PSC4.

[0116] Voltages associated with memory operations can be applied to active global word lines. Memory operations can include read operations, program operations, erase operations, etc. The voltages associated with memory operations applied to the active global word line group can be transmitted to the corresponding local word line group via corresponding transfer switch circuits.

[0117] exist Figure 7 In this process, the first global word line group GWL_G1 can be activated, and the second global word line group GWL_G2 can be deactivated. Voltages associated with memory operations can be applied to the first global word line group GWL_G1. Conversely, voltages associated with memory operations may not be applied to the second global word line group GWL_G2.

[0118] Block selection signals can be applied to the transmission switch circuits. The first block selection signal BLKWL_1 can be applied to the first transmission switch circuit PSC1 and the third transmission switch circuit PSC3. The second block selection signal BLKWL_2 can be applied to the second transmission switch circuit PSC2 and the fourth transmission switch circuit PSC4.

[0119] The first selection signal BLKWL_1 can be activated, and the second selection signal BLKWL_2 can be deactivated, enabling the first transmission switch circuit PSC1 and the third transmission switch circuit PSC3 to be turned on, and the second transmission switch circuit PSC2 and the fourth transmission switch circuit PSC4 to be turned off. In an embodiment, the first selection signal BLKWL_1 can be turned on, and the second selection signal BLKWL_2 can be turned off, enabling the first transmission switch circuit PSC1 and the third transmission switch circuit PSC3 to be turned on, and the second transmission switch circuit PSC2 and the fourth transmission switch circuit PSC4 to be turned off.

[0120] With the first transmission switch circuit PSC1 turned on, the memory operation-related voltage applied to the first global word line group GWL_G1 can be transmitted to the first local word line LWL_G1. The first memory block BLK1 coupled to the first local word line group LWL_G1 can be a selected memory block (Sel).

[0121] Because the second transmission switch circuit PSC2 is turned off, the first global word line group GWL_G1 and the second local word line group LWL_G2 can be disconnected from each other. The second memory block BLK2, coupled to the second local word line group LWL_G2, can be an unselected memory block.

[0122] Although the third transmission switch circuit PSC3 is turned on, the second global word line group GWL_G2 can be deactivated. Therefore, the third memory block BLK3, coupled to the third local word line group LWL_G3, can be a shared memory block.

[0123] Because the fourth transmission switch circuit PSC4 is turned off, the second global word line group GWL_G2 and the fourth local word line group LWL_G4 can be disconnected from each other. The fourth memory block BLK4, coupled to the fourth local word line group LWL_G4, can be an unselected memory block.

[0124] Figure 8 It's a diagram. Figure 7 The diagram shows the transmission switch circuit.

[0125] Reference Figure 8 A memory block may include a memory string. However, the number of memory strings included in a memory block is not limited to this.

[0126] A memory string may include multiple memory cells coupled in series between a drain-select transistor and a source-select transistor. A drain-select line DSL may be coupled to the gate of the drain-select transistor. A source-select line SSL may be coupled to the gate of the source-select transistor. Multiple local word lines LWL1 to LWLn may be coupled to the gates of multiple memory cells, where n is a natural number of 1 or greater.

[0127] The transmission switch circuit may include multiple transmission transistors PT1 to PTn, which are respectively coupled to multiple local word lines LWL1 to LWLn and multiple global word lines GWL1 to GWLn. A block select signal BLKWL may be applied to the gates of the multiple transmission transistors PT1 to PTn.

[0128] When the block select signal BLKWL is in the 'on' state, the voltages applied to the multiple global word lines GWL1 to GWLn can be transmitted to the multiple local word lines LWL1 to LWLn respectively. When the block select signal BLKWL is in the 'off' state, the voltages applied to the multiple global word lines GWL1 to GWLn can be prevented from being transmitted to the multiple local word lines LWL1 to LWLn respectively. In an embodiment, when the block select signal BLKWL is in the 'on' state (i.e., activated), the voltages applied to the multiple global word lines GWL1 to GWLn can be transmitted to the multiple local word lines LWL1 to LWLn respectively. When the block select signal BLKWL is in the 'off' state (i.e., deactivated), the voltages applied to the multiple global word lines GWL1 to GWLn can be prevented from being transmitted to the multiple local word lines LWL1 to LWLn respectively.

[0129] Figure 9 It's a diagram. Figure 8 The diagram shows the transmission transistor.

[0130] Reference Figure 9 The transfer transistor can be an nMOSFET transistor. In another embodiment, the transfer transistor can be a pMOSFET transistor.

[0131] The block select signal BLKWL can be applied to the gate terminal of the transfer transistor. The local word line LWL can be coupled to the drain terminal of the transfer transistor. The global word line GWL can be coupled to the source terminal of the transfer transistor. The body of the transfer transistor can be a P-well.

[0132] When the block select signal BLKWL is in the 'off' state (i.e., inactive), the global word line GWL and the local word line LWL can be disconnected from each other. Therefore, leakage current can flow from the drain terminal coupled to the local word line LWL to the source terminal coupled to the global word line GWL. The amount of leakage current can vary depending on the threshold voltage of the transfer transistor. When the threshold voltage of the transfer transistor is lowered, the leakage current can increase.

[0133] When a transistor has a P-well body, a positive voltage applied to the body region can cause a body effect, potentially lowering the transistor's threshold voltage. Because the body effect lowers the threshold voltage, the transistor's leakage current may increase.

[0134] Body effects can also occur when the body region is floating. When a local word line coupled to the drain terminal and in a floating state is boosted to a positive voltage, the floating body region can be increased to a positive voltage due to the coupling effect. Therefore, body effects may occur.

[0135] See below for reference. Figure 12 As described, the potential of a local word line can be boosted to a positive voltage after a read operation. When the potential of a local word line is boosted to a positive voltage, stress can be applied to memory cells with low threshold voltages (e.g., erase cells). Therefore, it may not be necessary to discharge the potential of the local word line to ground level to reduce stress.

[0136] According to an embodiment, by applying a positive voltage to the body region of the transfer transistor or by floating the body region of the transfer transistor, the memory device can increase the leakage current of the transfer transistor. By increasing the leakage current of the transfer transistor, the memory device can discharge the boost potential level of the local word line to the ground voltage level and can reduce the stress on the memory cells. Figure 9 In the diagram, the N-well of the transmission transistor is illustrated as shown.

[0137] Figure 10 This is a diagram illustrating the negative boost of the channel voltage during a read operation.

[0138] Reference Figure 10 The read operation may include a read voltage application operation and a word line discharge operation. During the read voltage application operation, a read voltage can be applied to a selected word line from a plurality of word lines, and an unselected word line can be applied via a voltage Vpass. During the word line discharge operation, a ground voltage can be applied to a plurality of word lines.

[0139] When a word line discharge operation is performed, the current can be cut off at different times, thus varying according to the threshold voltage of the memory cell. For example, a memory cell with a high threshold voltage can be cut off before a memory cell with a low threshold voltage.

[0140] exist Figure 10 In this context, assuming the memory cell is a three-level cell, a memory cell with a high threshold voltage can be programmed to the seventh programming state PV7, which is the highest programming state. A memory cell with a low threshold voltage can be erased to the erase state Era, which is the lowest programming state.

[0141] When a discharge operation is performed to apply a ground voltage to word lines WL1 through WL8, memory cells A, B, and C, coupled to word lines WL1, WL4, and WL7 respectively, can be turned off first (transistor (Tr.) turn off). The channel region between the turned-off memory cells A, B, and C can be partially floated. The voltages applied to word lines WL2, WL3, WL5, and WL6 can be reduced to the ground voltage level. The potential level of the partially floated channel region can be boosted to a negative voltage.

[0142] In an embodiment, PV can indicate a programming state defined by a programming verification voltage level. For example, a three-level cell (TLC) can be programmed into one of several programming states (Era, PV1 to PV7). The programming verification voltage level corresponding to the first programming state (PV1) is the lowest. The programming verification voltage level corresponding to the seventh programming state (PV7) is the highest.

[0143] In an embodiment, local negative boost can mean boosting the potential level of a locally floating channel region to a negative voltage.

[0144] Figure 11 This is a timing diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0145] Reference Figure 11 During the time period from t1 to t2, a read voltage (i.e., Vread) application operation can be performed. During the read voltage application operation, the read voltage can be applied to the selected word line (i.e., Sel WL), and the pass voltage (i.e., Vpass) can be applied to the unselected word line (i.e., Unsel WL).

[0146] During the time period from t2 to t3, a word line discharge operation can be performed. When the word line discharge operation is performed, equalization can be performed to reduce the interference caused by the voltage difference between the selected word line and its adjacent unselected word line. As a result of equalization, the potential level of the selected word line can be raised to the same pass voltage as the potential level of the unselected word line, and then it can be discharged to the ground voltage level together with the unselected word line.

[0147] As referenced above Figure 10 The described negative boost voltage, where the potential in the channel region is reduced to a negative voltage, may be caused by word line discharge operation.

[0148] During the time interval from t3 to t4, the potential of the negative boost channel region can be restored to the ground voltage level. The potential of the channel region can be restored by the current flowing through the bit line or common source line. When the potential of the channel region recovers from negative voltage to ground voltage level, the floating word line can be boosted to positive voltage due to the coupling effect with the channel region.

[0149] During the period from t4 to t5, the word line can be floated while being boosted to a positive voltage. Therefore, due to the positive voltage boosted to the word line, stress may be applied to memory cells with low threshold voltages. For example, due to the continuously applied positive voltage, memory cells in the erase state may be slightly programmed. Therefore, the potential of the word line boosted to a positive voltage after a read operation may need to be discharged.

[0150] When a read operation is performed during the time period from t1 to t3, the block select signal BLKWL can be activated (i.e., turned on), and the read / busy signal R / B can also be activated. While a read operation is being performed on the memory device, the read / busy signal R / B may go low, indicating a busy state (i.e., busy). When the read operation on the memory device is complete, the read / busy signal R / B may go high, indicating a ready state (i.e., ready). A ground voltage level can be applied to the body region (P-well) of the transfer transistor.

[0151] Figure 12 This is a timing diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0152] Reference Figure 12 The read operation can be performed in accordance with the above reference. Figure 11 The same method described is executed between t1 and t3.

[0153] During the time interval from t3 to t4, a positive voltage can be applied to the body region (P-well) of the transmission transistor, or the body region of the transmission transistor can be left floating. When the potential of the channel region that has been negatively boosted to a negative voltage is restored to the ground voltage level, the potential of the word line can be positively boosted to a positive voltage.

[0154] During the period from t4 to t5, as referred above... Figure 9 As described, the memory device can apply a positive voltage to the body region (P-well) of the transfer transistor or float the body region (P-well) of the transfer transistor. By applying a positive voltage to the body region (P-well) of the transfer transistor or floating the body region (P-well) of the transfer transistor, the body effect may cause or increase the leakage current of the transfer transistor, and the potential of the word line can be discharged to the ground voltage level.

[0155] According to an embodiment, when the potential of the word line is discharged to the ground voltage level after a read operation, the programming stress applied to the memory cell with a low threshold voltage can be reduced.

[0156] Figure 13 This is a timing diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0157] Reference Figure 13 In step S1301, the memory device can perform a read operation.

[0158] In step S1303, the memory device can determine whether it is in a ready state. When a read operation is completed, the memory device can determine the ready state, and the processing flow can proceed to step S1305. On the other hand, when a read operation is being performed, the memory device can determine the busy state, and the processing flow can proceed to step S1301. In an embodiment, the ready state is a state in which the memory device is not performing operations such as programming, reading, writing, or erasing. In an embodiment, the busy state is a state in which the memory device is performing operations such as programming, reading, writing, or erasing.

[0159] In step S1305, the memory device can increase the leakage current of the transmission switch circuits that couple multiple local word lines and multiple global word lines, so that the memory device can discharge the potential of multiple local word lines to the ground voltage level.

[0160] According to this disclosure, a memory device with improved read / write performance and a method of operating the memory device with improved read / write performance can be provided.

Claims

1. A memory device, comprising: The memory block is coupled to multiple local word lines; The peripheral circuitry is configured to couple the plurality of local word lines to a plurality of global word lines via a transmission switch circuit, and is configured to perform a read operation on the memory block; as well as The control logic is configured to, when the memory device enters a ready state after the read operation, control the peripheral circuitry to cause or increase the leakage current of the transmission switch circuit, and use the leakage current of the transmission switch circuit to discharge the potential levels of the plurality of local word lines.

2. The memory device of claim 1, wherein the transfer switching circuit includes a plurality of transfer transistors, the plurality of transfer transistors respectively coupling the plurality of local word lines to the plurality of global word lines, and the transfer switching circuit precharges the body regions of the plurality of transfer transistors to a positive voltage or floats the body regions of the plurality of transfer transistors to induce or increase the leakage current.

3. The memory device of claim 2, wherein the control logic controls the peripheral circuitry to perform the read operation, the read operation including a read voltage application operation and a word line discharge operation. The read voltage application operation includes: A read voltage is applied to a selected local word line among the plurality of local word lines, and a pass voltage is applied to an unselected local word line among the plurality of local word lines. The word line discharge operation includes applying a ground voltage to the plurality of local word lines.

4. The memory device of claim 3, wherein the memory device is in a busy state when the read operation is being performed, and When the read operation is completed, the memory device is in the ready state.

5. The memory device of claim 4, wherein when the memory device enters the ready state, the transfer switching circuit applies a block select signal having a low level to the gate of the plurality of transfer transistors and applies a positive voltage to the body region of the plurality of transfer transistors, or floats the body region of the plurality of transfer transistors.

6. The memory device of claim 3, wherein as the channel potential of the memory block, which has been boosted to a negative voltage, is restored to a ground voltage level, the peripheral circuit discharges the potential level of the plurality of local word lines, which have been boosted to the positive voltage, to the ground voltage level.

7. The memory device of claim 6, wherein as the leakage current of the plurality of transmission transistors is caused or increased, the potential level of the plurality of local word lines is discharged to the ground voltage level.

8. The memory device of claim 7, wherein each of the plurality of local word lines is coupled to the drain terminal of each of the plurality of transfer transistors, and Each of the plurality of global word lines is coupled to at least two source terminals of the plurality of transmission transistors.

9. The memory device of claim 2, wherein each of the plurality of transfer transistors is a negative metal-oxide-semiconductor (NMOS) transistor or a positive metal-oxide-semiconductor (PMOS) transistor.

10. A method of operating a memory device, the method comprising: Perform a read operation on a memory block coupled to multiple local word lines; as well as When the memory device enters a ready state, leakage current is caused or increased in the transmission switch circuit that couples the plurality of local word lines to the plurality of global word lines, and the leakage current of the transmission switch circuit is used to discharge the potential level of the plurality of local word lines.

11. The method of claim 10, wherein the execution of the read operation comprises: Perform a read voltage application operation that applies a read voltage to a selected local word line among the plurality of local word lines and applies a pass voltage to an unselected local word line among the plurality of local word lines; as well as Perform a word line discharge operation that applies a ground voltage to the plurality of local word lines.

12. The method of claim 11, wherein the transmission switch circuit comprises a plurality of transmission transistors, the plurality of transmission transistors respectively coupling the plurality of local word lines to the plurality of global word lines.

13. The method of claim 12, wherein the inducing or increasing of the leakage current comprises: The body regions of the plurality of transmission transistors are precharged to a positive voltage, or the body regions of the plurality of transmission transistors are floated.

14. The method of claim 13, further comprising: The memory device is set to a busy state while the read operation is being performed, and the memory device is set to the ready state when the read operation is completed.

15. The method of claim 14, wherein the induction or increase of the leakage current comprises: When the memory device enters the ready state, a block select signal with a low level is applied to the gate of the plurality of transfer transistors; as well as The positive voltage is applied to the body region of the plurality of transmission transistors, or the body region of the plurality of transmission transistors is floated.

16. The method of claim 12, wherein the discharge of the potential levels of the plurality of local word lines comprises: When the channel potential of the memory block, which has been boosted to a negative voltage through the word line discharge operation, is restored to the ground voltage level, the potential levels of the plurality of local word lines, which have been boosted to a positive voltage, are discharged to the ground voltage level.

17. The method of claim 16, wherein as the leakage current of the plurality of transmission transistors is caused or increased, the potential level of the plurality of local word lines is discharged to the ground voltage level.

18. The method of claim 17, wherein each of the plurality of local word lines is coupled to the drain terminal of each of the plurality of transmission transistors, and Each of the plurality of global word lines is coupled to at least two source terminals of the plurality of transmission transistors.

19. The method of claim 12, wherein each of the plurality of transmission transistors is a negative metal-oxide-semiconductor (NMOS) transistor or a positive metal-oxide-semiconductor (PMOS) transistor.

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