Integrated circuit, pixel sensor and method of forming the same

Abstract

An integrated circuit, a pixel sensor, and a method of forming the same. The pixel sensor includes a substrate having a front side opposite a back side. An image sensor element includes an active layer disposed within the substrate, where the active layer includes germanium. An anti-reflective coating (ARC) structure is overlying the back side of the substrate. The ARC structure includes a first dielectric layer overlying the back side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer. A first refractive index of the first dielectric layer is less than a second refractive index of the second dielectric layer and a third refractive index of the third dielectric layer is less than the first refractive index.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated circuit, a pixel sensor, and a method of forming the same, particularly to an integrated circuit and a pixel sensor comprising a dielectric structure superimposed on an image sensor element for improving quantum efficiency, and a method of forming the same. Background Technology

[0002] Many modern electronic devices (such as digital cameras, optical imaging devices, etc.) include image sensors. Image sensors convert optical images into digital data that can be represented as digital images. An image sensor contains an array of pixel sensors, which are unit devices used to convert optical images into digital data. Some types of pixel sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors (CIS). Compared to CCD pixel sensors, CIS is favored due to its lower power consumption, smaller size, faster data processing, direct data output, and lower manufacturing cost. Summary of the Invention

[0003] According to some embodiments, a pixel sensor includes a substrate, an image sensor element, and an anti-reflective coating structure. The substrate has a front side opposite a back side, and the image sensor element includes an active layer disposed within the substrate, wherein the active layer includes germanium. An anti-reflective coating structure is applied to the back side of the substrate, wherein the anti-reflective coating structure includes a first dielectric layer applied to the back side of the substrate, a second dielectric layer applied to the first dielectric layer, and a third dielectric layer applied to the second dielectric layer, wherein a first refractive index of the first dielectric layer is less than a second refractive index of the second dielectric layer, and wherein a third refractive index of the third dielectric layer is less than the first refractive index.

[0004] According to some embodiments, an integrated circuit includes a first integrated circuit die, a second integrated circuit die, a plurality of image sensor elements, a mesh structure, and an anti-reflective coating structure. The first integrated circuit die includes a first substrate and a first interconnect structure overlying the first substrate. The second integrated circuit die is overlying the first integrated circuit die, wherein the second integrated circuit die includes a second substrate and a second interconnect structure beneath the second substrate, wherein the first integrated circuit die and the second integrated circuit die are in contact at a bonding interface between the first interconnect structure and the second interconnect structure. Image sensor elements are disposed within the second substrate, and the mesh structure is overlying the plurality of image sensor elements, wherein each of the image sensor elements is laterally spaced between the sidewalls of the mesh structure. The anti-reflective coating structure is disposed between the second substrate and the mesh structure, wherein the anti-reflective coating structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, each having a different refractive index than the others, wherein the second dielectric layer is overlying the first dielectric layer, and the third dielectric layer is overlying the second dielectric layer, wherein the first dielectric layer comprises a first metal oxide, and the second dielectric layer comprises a second metal oxide different from the first metal oxide.

[0005] According to some embodiments, a method for forming a pixel sensor includes at least the following steps: forming a first isolation structure in the front side of a substrate; forming an image sensor element within the substrate such that the image sensor element includes an active layer laterally spaced between sidewalls of the first isolation structure; wherein the substrate includes a first material; the active layer includes a second material different from the first material; forming an interconnect structure along the front side of the substrate; and forming an anti-reflective coating structure over the back side of the substrate such that the anti-reflective coating structure includes a first dielectric layer overlying the back side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer, wherein a first refractive index of the first dielectric layer is less than a second refractive index of the second dielectric layer, and wherein a third refractive index of the third dielectric layer is less than the first refractive index. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 Cross-sectional views of some embodiments of a pixel sensor with an anti-reflective coating structure overlying an image sensor element are shown, wherein the anti-reflective coating structure is configured to enhance the quantum efficiency of the image sensor element.

[0008] Figures 2A to 2F Showing according to Figure 1 Cross-sectional views of some alternative embodiments of the pixel sensor.

[0009] Figure 3 Cross-sectional views of some embodiments of an integrated circuit including a first IC die beneath a second integrated circuit (IC) die are shown, wherein the second IC die includes an anti-reflective coating structure overlaid on a plurality of image sensor elements.

[0010] Figures 4 to 11 Cross-sectional views of some embodiments of a method for forming a pixel sensor having an anti-reflective coating structure overlying an image sensor element are shown.

[0011] Figure 12 The flowchart illustrates methods for forming some embodiments of a pixel sensor having an anti-reflective coating structure overlying an image sensor element.

[0012] Explanation of icon numbers

[0013] 100: Pixel sensor;

[0014] 102: Interconnection structure;

[0015] 104: Interconnect dielectric structure;

[0016] 106: Conductive wire;

[0017] 108: Through hole;

[0018] 110: Substrate;

[0019] 110b: Dorsal side;

[0020] 110f: Front side;

[0021] 112, 112a, 112b: Image sensor elements;

[0022] 114: Active layer;

[0023] 116: First isolation structure;

[0024] 118: Anti-reflective coating structure;

[0025] 120: First dielectric layer;

[0026] 122: Second dielectric layer;

[0027] 124: Third dielectric layer;

[0028] 126: Grid structure;

[0029] 128: Upper dielectric layer;

[0030] 130: Electromagnetic radiation;

[0031] 130a: Arrowhead;

[0032] 132: First normal;

[0033] 134: Second normal;

[0034] 140: Circle;

[0035] 200a, 200b, 200c, 200d, 200e, 200f: Pixel sensors;

[0036] 202: Second isolation structure;

[0037] 204: Passivation layer;

[0038] 206: Conductive trench layer;

[0039] 208: Reflector;

[0040] 209: Buffer layer;

[0041] 210: The second deepest well;

[0042] 212: First doped region;

[0043] 214: The First Deep Well;

[0044] 216: Doped region;

[0045] 218: Filter;

[0046] 220: Microlens;

[0047] 300: Integrated Circuits;

[0048] 301: The first integrated circuit die;

[0049] 302: Lower substrate;

[0050] 303: Second integrated circuit die;

[0051] 305: Semiconductor devices;

[0052] 307: Lower interconnect structure;

[0053] 308: First joint structure;

[0054] 310: Joint etching termination layer;

[0055] 312: Bonded dielectric structure;

[0056] 313: Rewire via;

[0057] 314: Rewiring;

[0058] 316: Second joint structure;

[0059] 321: First mesh layer;

[0060] 322: Second grid layer;

[0061] 328: Upper joint pad structure;

[0062] 330: Upper etching termination layer;

[0063] 336: Opening;

[0064] 400, 500, 600, 700, 800, 900, 1000, 1100: Sectional view;

[0065] 702: Deep trench isolation opening;

[0066] 1200: Method;

[0067] 1202, 1204, 1206, 1208, 1210, 1212, 1214: Actions;

[0068] t1: First thickness;

[0069] t2: Second thickness;

[0070] t3: Third thickness;

[0071] Ti, Ts: thickness;

[0072] θ1: Angle of incidence;

[0073] θ2: First angle of refraction;

[0074] θ3: Second angle of refraction. Detailed Implementation

[0075] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0076] Additionally, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" are used herein to describe the relationship between one element or feature and another element or feature as shown in the diagrams. Besides the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0077] Furthermore, for ease of description, the terms "first," "second," "third," etc., may be used herein to distinguish different elements of a diagram or a series of diagrams. "First," "second," "third," etc., are not intended to describe corresponding elements, but are merely general identifiers. For example, the "first dielectric layer" described in connection with the first figure may not necessarily correspond to the "first dielectric layer" described in connection with some embodiments, but may instead correspond to the "second dielectric layer" in other embodiments.

[0078] CMOS image sensors (CIS) typically comprise an array of pixel regions, each having an image sensor element disposed within a substrate. An anti-reflective coating (ARC) is structurally applied to the image sensor element and configured to prevent the reflection of incident light away from the substrate. After receiving light, the image sensor element is configured to generate an electrical signal corresponding to the received light. The electrical signal from the image sensor element can be processed by a signal processing unit to determine the image captured by the CIS. Quantum efficiency (QE) is the ratio of the number of photons contributing to the electrical signal generated by the image sensor element within the pixel region to the number of photons incident on the pixel region. It is understood that the ARC structure enhances the QE of the CIS by preventing the reflection of incident light away from the underlying image sensor element.

[0079] One challenge of the aforementioned pixel sensor is the reflection of incident radiation away from the underlying image sensor element. In some embodiments, the ARC structure includes a first dielectric layer disposed above the underlying image sensor element and a second dielectric layer overlying the first dielectric layer. The first dielectric layer has a first refractive index greater than the second refractive index of the second dielectric layer (e.g., the first refractive index is about 2 and the second refractive index is about 1.44), such that the difference between the first and second refractive indices is relatively small (e.g., less than about 0.6). Due to the difference between the first and second refractive indices, incident light traveling from the second dielectric layer to the first dielectric layer bends toward a line perpendicular to the upper surface of the first dielectric layer, thereby guiding the light toward the underlying image sensor element. However, because the difference between the first and second refractive indices is relatively small (e.g., less than about 0.6), the incident light is not sufficiently bent toward the line. This may cause the incident light to travel to adjacent image sensor elements and / or be reflected away from the underlying image sensor element, thereby reducing the QE of the pixel sensor, increasing crosstalk, and degrading the overall performance of the pixel sensor.

[0080] In some embodiments, this invention pertains to a pixel sensor having an anti-reflective coating (ARC) structure overlying an image sensor element and configured to improve the QE of the pixel sensor. For example, the pixel sensor includes an image sensor element disposed within a substrate. The ARC structure is overlying the back side of the substrate and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is overlying the back side of the substrate, the second dielectric layer is overlying the first dielectric layer, and the third dielectric layer is overlying the second dielectric layer. The first dielectric layer includes a first refractive index, the second dielectric layer includes a second refractive index greater than the first refractive index, and the third dielectric layer includes a third refractive index less than the second refractive index (e.g., the second refractive index is about 2.43 and the third refractive index is about 1.44). Therefore, the difference between the second and third refractive indices is relatively large (e.g., greater than about 0.6). Due to the relatively large difference between the second and third refractive indices, incident light transmitted from the third dielectric layer to the second dielectric layer is sufficiently bent toward a line perpendicular to the upper surface of the second dielectric layer, thereby sufficiently guiding the incident light toward the underlying image sensor element. Therefore, incident light directed towards adjacent image sensor elements and / or reflected away from underlying image sensor elements is reduced. This improves the QE of the image sensor elements and reduces crosstalk, thereby improving the overall performance of the pixel sensor.

[0081] Figure 1 Cross-sectional views of some embodiments of a pixel sensor 100 having an anti-reflective coating (ARC) structure 118 overlying a substrate 110 are shown. In some embodiments, circle 140 shows an enlarged view of a region of the pixel sensor 100 to show details of the ARC structure 118 more clearly.

[0082] Pixel sensor 100 includes interconnect structure 102 disposed along the front side 110f of substrate 110. Image sensor element 112 is disposed within substrate 110. Image sensor element 112 is configured to convert electromagnetic radiation 130 (e.g., photons) into electrical signals (e.g., to generate electron-hole pairs from electromagnetic radiation 130). In some embodiments, electromagnetic radiation 130 is back-side illuminated (BSI) on pixel sensor 100. In some embodiments, image sensor element 112 may be configured, for example, to generate electrical signals from near infrared (NIR) radiation (e.g., electromagnetic radiation with wavelengths in the range of about 700 nanometers (nm) to about 3,000 nanometers).

[0083] In some embodiments, the substrate 110 is made of a first material (e.g., silicon). Additionally, the image sensor element 112 includes an active layer 114 disposed within the substrate 110. In other embodiments, the active layer 114 includes a second material (e.g., germanium) different from the first material. A first isolation structure 116 is disposed within the substrate 110 and provides electrical isolation between the image sensor element 112 and other devices and / or doped regions disposed within / on the substrate 110. The first isolation structure 116 may laterally enclose the image sensor element 112. The active layer 114 may include, for example, photodetector regions and / or photodetector layers configured to convert electromagnetic radiation 130 (e.g., photons) into electrical signals and / or facilitate the readout of these electrical signals, such as charge storage regions, floating nodes, surface pinning regions, contact regions, guard rings, etc. The second material of the active layer 114 is selected to ensure a high QE for NIR radiation and / or infrared radiation (IR). For example, a second material (e.g., germanium) in the active layer 114 helps the active layer 114 absorb IR radiation, thereby improving the QE of the image sensor element 112.

[0084] Interconnect structure 102 extends along the front side 110f of substrate 110 and is configured to electrically couple the doped regions of substrate 110 and / or active layer 114 to pixel devices (e.g., transfer transistors, source-follower transistors, row-select transistors, etc.). Interconnect structure 102 includes interconnect dielectric structure 104, multiple conductive lines 106, and multiple vias 108. Additionally, ARC structure 118 is disposed along the back side 110b of substrate 110. ARC structure 118 includes a first dielectric layer 120 having a first refractive index, a second dielectric layer 122 having a second refractive index, and a third dielectric layer 124 having a third refractive index. Furthermore, grid structure 126 is overlaid on ARC structure 118. Grid structure 126 may include, for example, a metallic grid structure and / or a dielectric grid structure. Grid structure 126 is configured to guide electromagnetic radiation 130 to the underlying image sensor element 112. In some embodiments, when the mesh structure 126 comprises a metal mesh structure (e.g., aluminum, copper, tungsten, or a combination thereof), electromagnetic radiation 130 may be reflected from the sidewalls of the metal mesh structure to the underlying image sensor element 112, rather than traveling to adjacent image sensor elements (not shown). In such embodiments, the mesh structure 126 may reduce crosstalk between adjacent image sensor elements, thereby improving the QE of the image sensor element 112. Furthermore, an upper dielectric layer 128 is disposed above the mesh structure 126 and the ARC structure 118.

[0085] In various embodiments, electromagnetic radiation 130 is disposed on ARC structure 118 and includes a first range of wavelengths. In some embodiments, the first dielectric layer 120 may be, for example, or include tantalum oxide (e.g., Ta2O5), another dielectric material, or any combination thereof, and / or the first refractive index may be about 2, about 2.06, in the range of about 2 to 2.1, or another suitable value. In some embodiments, if the first range of wavelengths is in the range of about 400 nm to about 700 nm (e.g., visible light), then the first refractive index may be in the range of about 2.11 to about 2.25 or another suitable value. In other embodiments, if the first range of wavelengths is in the range of about 700 nm to about 3,000 nm (e.g., NIR radiation), then the first refractive index may be in the range of about 2.01 to 2.11 or another suitable value. In various embodiments, if the first range of wavelengths is in the range of about 1,400 nm to about 1,600 nm, then the first refractive index may be in the range of about 2.056 to about 2.062 or another suitable value.

[0086] In various embodiments, the second dielectric layer 122 may be, for example, or include titanium oxide (e.g., TiO2), silicon carbide, another suitable dielectric material, or any combination thereof, and / or the second refractive index may be about 2.43, in the range of about 2.4 to 2.6, or another suitable value. In some embodiments, if the first wavelength range is in the range of about 400 nm to about 700 nm (e.g., visible light), then the second refractive index may be in the range of about 2.55 to about 2.88, or another suitable value. In other embodiments, if the first wavelength range is in the range of about 700 nm to about 3,000 nm (e.g., NIR radiation), then the second refractive index may be in the range of about 2.37 to 2.55, or another suitable value. In various embodiments, if the first wavelength range is in the range of about 1,400 nm to about 1,600 nm, then the second refractive index may be in the range of about 2.43 to about 2.46, or another suitable value.

[0087] In some embodiments, the third dielectric layer 124 may be, for example, silicon dioxide (e.g., SiO2), another oxide, high-density plasma oxide, another suitable dielectric material, or any combination thereof, and / or the third refractive index may be about 1.44, about 1.438, about 1.53, in the range of about 1.438 to 1.53, or another suitable value. In some embodiments, if the first wavelength range is in the range of about 400 nm to about 700 nm (e.g., visible light), then the third refractive index may be in the range of about 1.46 to about 1.49 or another suitable value. In other embodiments, if the first wavelength range is in the range of about 700 nm to about 3,000 nm (e.g., NIR radiation), then the third refractive index may be in the range of about 1.42 to 1.46 or another suitable value. In various embodiments, if the first wavelength range is in the range of about 1,400 nm to about 1,600 nm, then the third refractive index may be in the range of about 1.443 to about 1.446 or another suitable value. In various embodiments, the second refractive index is greater than the first refractive index, and the third refractive index is less than the first refractive index. This partially reduces the reflection of electromagnetic radiation away from the image sensor element 112, thereby improving the QE of the pixel sensor 100.

[0088] In some embodiments, arrow 130a illustrates some non-limiting examples of the path of electromagnetic radiation 130 as it travels through ARC structure 118. When electromagnetic radiation 130 crosses the boundary between the third dielectric layer 124 and the second dielectric layer 122, it bends toward the first normal 132. Because the third refractive index is substantially smaller than the second refractive index (i.e., the difference between the second and third refractive indices is greater than about 0.6), the first angle of refraction θ2 is substantially smaller than the corresponding angle of incidence θ1, thereby focusing electromagnetic radiation 130 toward image sensor element 112. This reduces reflections of electromagnetic radiation 130 away from image sensor element 112 and / or reduces crosstalk, thereby improving the QE of pixel sensor 100. Additionally, when electromagnetic radiation 130 crosses the boundary between the second dielectric layer 122 and the first dielectric layer 120, it bends away from the second normal 134. Because the first refractive index is relatively smaller than the second refractive index (i.e., the difference between the second and first refractive indices is less than about 0.5), the second angle of refraction θ3 is slightly larger than the first angle of refraction θ2. Because the difference between the second and first refractive indices is relatively small, reflection of electromagnetic radiation away from the image sensor element 112 is reduced. Finally, in some embodiments, the refractive index of the substrate 110 is greater than the first refractive index (e.g., the refractive index of the substrate 110 is in the range of about 3.42 to 3.48 or another suitable value), such that when electromagnetic radiation is transmitted from the first dielectric layer 120 to the substrate 110, it bends toward a line perpendicular to the back side 110b of the substrate 110. This directs the electromagnetic radiation 130 toward the image sensor element 112 and reduces reflection of the electromagnetic radiation 130 away from the image sensor element 112 and / or reduces crosstalk, thereby improving the QE of the pixel sensor 100. Therefore, the ARC structure 118 is configured to improve the performance of the pixel sensor 100. In some embodiments, the first normal 132 is perpendicular to the upper surface of the second dielectric layer 122 (the interface between the third dielectric layer 124 and the second dielectric layer 122), and the second normal 134 is perpendicular to the upper surface of the first dielectric layer 120 (the interface between the second dielectric layer 122 and the first dielectric layer 120) and / or the first normal 132 and the second normal 134 are parallel to each other.

[0089] Figure 2A Showing according to Figure 1 Cross-sectional views of some embodiments of pixel sensor 200a, which are some alternative embodiments of pixel sensor 100.

[0090] Pixel sensor 200a includes an interconnect structure 102 disposed along the front side 110f of substrate 110 and an ARC structure 118 disposed along the back side 110b of substrate 110. In some embodiments, substrate 110 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, p-doped silicon, or another suitable material. Thus, substrate 110 includes a first material such as silicon. Interconnect structure 102 includes interconnect dielectric structure 104, a plurality of conductive lines 106, and a plurality of vias 108. In other embodiments, interconnect dielectric structure 104 may be, for example, or include silicon dioxide, a low-k dielectric material, another suitable dielectric material, or any combination thereof. In yet another embodiment, conductive lines 106 and / or vias 108 may be, for example, aluminum, copper, ruthenium, tungsten, titanium nitride, tantalum nitride, another suitable material, or any combination thereof. The interconnect structure 102 is configured to electrically couple doped regions and / or semiconductor devices disposed within the pixel sensor 200a to each other.

[0091] Image sensor element 112 is disposed within substrate 110 and includes an active layer 114. Image sensor element 112 is configured, for example, to generate an electrical signal from near-infrared (NIR) radiation (e.g., electromagnetic radiation having wavelengths in the range of about 700 nanometers (nm) to about 3,000 nanometers). It should be understood that image sensor element 112 configured to generate electrical signals from other frequency wavelength values ​​is also within the scope of this disclosure. A first isolation structure 116 is disposed within substrate 110 and laterally encloses image sensor element 112. The first isolation structure 116 extends from the front side 110f of substrate 110 to a point above the front side 110f of substrate 110. The first isolation structure 116 is configured to electrically isolate image sensor element 112 from other devices disposed on and / or within substrate 110. In some embodiments, the first isolation structure 116 is configured as a shallow trench isolation (STI) structure or another suitable isolation structure. In other embodiments, the first isolation structure 116 may be, for example, an oxide, such as silicon dioxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination thereof.

[0092] Additionally, the second isolation structure 202 extends from the back side 110b of the substrate 110 to a point below the back side 110b of the substrate 110. In some embodiments, the bottom surface of the second isolation structure 202 may contact the top surface of the first isolation structure 116. The second isolation structure 202 laterally surrounds the image sensor element 112 and is configured to electrically isolate the image sensor element 112 from other devices disposed within and / or on the substrate 110. In some embodiments, the second isolation structure 202 is configured as a deep trench isolation (DTI) structure or another suitable isolation structure. Additionally, in some embodiments, the second isolation structure 202 may be, for example, or include a dielectric material (e.g., silicon dioxide, silicon nitride, silicon carbide, another dielectric material, or any combination thereof), a metallic material (e.g., tungsten, copper, aluminum, another metal, or any combination thereof), another suitable material, or any combination thereof. In other embodiments, the second isolation structure 202 may be configured to direct incident electromagnetic radiation to the image sensor element 112. For example, when the second isolation structure 202 comprises a metallic material (e.g., aluminum, copper, tungsten, etc.), electromagnetic radiation can be reflected from the sidewalls of the metallic material to the underlying image sensor element 112, rather than traveling to adjacent image sensor elements (not shown). In such embodiments, the second isolation structure 202 can reduce crosstalk between adjacent image sensor elements, thereby improving the QE of the image sensor element 112.

[0093] The ARC structure 118 is disposed along the back side 110b of the substrate 110. The ARC structure 118 includes a first dielectric layer 120 having a first refractive index, a second dielectric layer 122 having a second refractive index, and a third dielectric layer 124 having a third refractive index. In some embodiments, the first dielectric layer 120 may be, for example, or include tantalum oxide (e.g., Ta2O5), another dielectric material, or any combination thereof, and / or the first refractive index may be about 2, about 2.06, in the range of about 2 to 2.16, or another suitable value. In other embodiments, the second dielectric layer 122 may be, for example, or include titanium oxide (e.g., TiO2), silicon carbide, another suitable dielectric material, or any combination thereof, and / or the second refractive index may be about 2.43, in the range of about 2.4 to 2.6, or another suitable value. In other embodiments, the third dielectric layer 124 may be, for example, or include silicon dioxide (e.g., SiO2), another oxide, high-density plasma oxide, another suitable dielectric material, or any combination thereof, and / or the third refractive index may be about 1.44, about 1.438, about 1.53, in the range of about 1.438 to 1.53, or another suitable value. In various embodiments, the second refractive index is greater than the first refractive index and / or the third refractive index is less than the first refractive index. This partially reduces the reflection of electromagnetic radiation away from the image sensor element 112, thereby improving the QE of the pixel sensor 200a.

[0094] A first dielectric layer 120 has a first thickness t1, a second dielectric layer 122 has a second thickness t2, and a third dielectric layer 124 has a third thickness t3. In some embodiments, the first thickness t1 is, for example, about 1,100 angstroms, in the range of about 900 angstroms to 1,300 angstroms, or another suitable thickness value. In other embodiments, the second thickness t2 is, for example, about 200 angstroms, in the range of about 10 angstroms to 1,000 angstroms, or another suitable thickness value. In still other embodiments, the third thickness t3 is, for example, about 1,300 angstroms, in the range of about 1,100 angstroms to 1,500 angstroms, or another suitable thickness value. In various embodiments, the first thickness t1 is greater than the second thickness t2, and the first thickness t1 is less than the third thickness t3.

[0095] In some embodiments, image sensor element 112 is configured to generate an electrical signal from a first range of NIR radiation, wherein the first range of NIR radiation contains wavelengths in the range of about 1400 nm to 1600 nm, however other values ​​of the first range of NIR radiation are within the range of this disclosure. In some embodiments, if the second thickness t2 is less than about 10 angstroms, the reflectivity of incident electromagnetic radiation in the first range of NIR radiation increases, thereby reducing the performance of pixel sensor 200a. In yet another embodiment, if the second thickness t2 is equal to or greater than about 200 angstroms, the reflectivity of incident electromagnetic radiation in the first range of NIR radiation decreases, thereby improving the performance of pixel sensor 200a. In yet another embodiment, if the first range of NIR radiation has a wavelength of about 1550 nm and the second thickness t2 is approximately 200 angstroms, the reflectivity of incident electromagnetic radiation in the first range of NIR radiation can be reduced from about 15% to about 6.2%. In this type of embodiment, the reflectivity of the incident electromagnetic radiation in the first range of NIR radiation is approximately 15%, which corresponds to an embodiment that omits the second dielectric layer 122 (e.g., the second thickness t2 is 0 angstroms) (not shown in the figure). Therefore, the second dielectric layer 122 improves the overall performance of the pixel sensor 200a.

[0096] Furthermore, the mesh structure 126 overlays the ARC structure 118. The mesh structure 126 may, for example, comprise a metallic mesh structure and / or a dielectric mesh structure. Additionally, an upper dielectric layer 128 is disposed above the mesh structure 126 and the ARC structure 118. In some embodiments, the upper dielectric layer 128 may be, for example, an oxide, such as silicon dioxide, another suitable dielectric material, or any combination thereof. In yet another embodiment, the upper dielectric layer 128 comprises the same material as the third dielectric layer 124.

[0097] Figure 2B Showing according to Figure 2A Cross-sectional views of some alternative embodiments of pixel sensor 200a and some embodiments of pixel sensor 200b.

[0098] In some embodiments, the second isolation structure 202 includes a passivation layer 204 and a conductive trench layer 206. The passivation layer 204 may be, for example, or comprise a dielectric material, such as silicon dioxide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination thereof. Additionally, the passivation layer may extend continuously along the back side 110b of the substrate 110. The passivation layer 204 is disposed between the conductive trench layer 206 and the substrate 110, thereby electrically isolating the conductive trench layer 206 from the substrate 110. In other embodiments, the conductive trench layer 206 may be, for example, or comprise aluminum, tungsten, copper, another suitable conductive material, or any combination thereof. Furthermore, the conductive trench layer 206 may be configured to reduce crosstalk between adjacent image sensor elements disposed within the substrate 110. This further improves the performance of the pixel sensor 200b in part. In other embodiments, the thickness of the passivation layer 204 may be less than a first thickness t1, a second thickness t2, and / or a third thickness t3. In other embodiments, the refractive index of the passivation layer 204 may be equal to the third refractive index of the third dielectric layer 124. In various embodiments, the refractive index of the passivation layer 204 may be less than the first refractive index of the first dielectric layer 120 and / or less than the second refractive index of the second dielectric layer 122.

[0099] Figure 2C Showing according to Figure 2A Cross-sectional views of some alternative embodiments of pixel sensor 200a and some embodiments of pixel sensor 200c.

[0100] Reflector 208 is located beneath image sensor element 112 and is separated from the front side 110f of substrate by interconnect dielectric structure 104. In some embodiments, reflector 208 comprises a metallic material (e.g., aluminum, tungsten, copper, another metallic material, or any combination thereof). Reflector 208 is configured to reflect incident electromagnetic radiation disposed on the back side 110b of substrate 110 that passes through the front side 102f of substrate 110 back to image sensor element 112. This further improves the QE of image sensor element 112, thereby improving the performance of pixel sensor 200c. In yet another embodiment, reflector 208 may comprise a first metallic material different from the second metallic material comprised of conductive line 106.

[0101] Figure 2D Showing according to Figure 2A Cross-sectional views of some alternative embodiments of pixel sensor 200a and some embodiments of pixel sensor 200d.

[0102] The substrate 110 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, P-doped silicon, N-doped silicon, or another suitable material. In some embodiments, the substrate 110 is lightly doped with a first conductivity type (e.g., P-type). In various embodiments, the image sensor element 112 is configured as a single-photon avalanche diode (SPAD) capable of detecting incident radiation with extremely low intensity (e.g., a single photon). In other embodiments, the image sensor element 112 may be used, for example, in near-IR (NIR) direct-time-of-flight (D-TOF) applications. In some embodiments, the active layer 114 includes a second material (e.g., germanium) lightly doped with a first conductivity type. The active layer 114 may include a first deep well 214 having a first conductivity type and a first heavily doped region 212 having a second conductivity type (e.g., N-type) opposite to the first conductivity type. The first deep well 214 is disposed above the first heavily doped region 212. A multiplication junction region is formed at the interface between the first heavily doped region 212 and the first deep well 214. In some embodiments, the first deep well 214 and the first heavily doped region 212 (not shown) are vertically spaced apart, such that the multiplication junction region is formed at the interface between the first heavily doped region 212 and the active layer 114.

[0103] In some embodiments, the image sensor element 112 further includes a second deep well 210 heavily doped with a dopant of a first conductivity type. The second deep well 210 extends from the front side 110f of the substrate to a point above the first heavily doped region 212. In some embodiments, the second deep well 210 is configured as a guard ring to prevent premature edge breakdown of the image sensor element 112 in a SPAD configuration. Additionally, a buffer layer 209 is disposed between the active layer 114 and the substrate 110. The buffer layer 209 may include the same dopant and doping concentration as the active layer 114. In some embodiments, the buffer layer 209 is omitted, allowing the active layer 114 to directly contact the substrate 110 (not shown). In some embodiments, the first conductivity type dopant is p-type (e.g., boron, some other suitable p-type dopant, or any combination thereof), and the second conductivity type dopant is n-type (e.g., arsenic, phosphorus, some other suitable n-type dopant, or any combination thereof) or vice versa.

[0104] In some embodiments, during operation in a SPAD configuration, image sensor element 112 is reverse biased above its breakdown voltage, and incident photons (e.g., wavelengths in the near-infrared (NIR) radiation range) strike image sensor element 112 to generate charge carriers. The charge carriers generated by the photons move to the multiplication junction region and trigger a breakdown current, which amplifies the photon-generated signal to make it easier to detect. In some embodiments, the doping type and / or concentration of the first deep well 214 may be configured to adjust the breakdown voltage of image sensor element 112 in a SPAD configuration. In yet another embodiment, conductive features within interconnect structure 102 (e.g., vias 108 and / or conductive lines 106) are electrically coupled to doped regions within active layer 114 to facilitate readout of the photon-generated signal.

[0105] The selection of a second material (e.g., germanium) for the active layer 114 enables the image sensor element 112 to exhibit high sensitivity to electromagnetic radiation with wavelengths in the NIR radiation range. This improves the quantum efficiency (QE) of the image sensor element 112 when receiving wavelengths within the NIR radiation range. However, the QE of the image sensor element 112 may decrease as the wavelength of the incident electromagnetic radiation increases. For example, if the wavelength of the incident electromagnetic radiation is approximately 940 nm, 1310 nm, and / or 1550 nm, then the QE of the image sensor element 112 may be approximately 86%, 50%, and / or 32%, respectively. Additionally, in some embodiments, to mitigate harm to the human eye, the wavelength of the incident electromagnetic radiation transmitted by the NIR light source for D-TOF applications may be limited to wavelengths within a first range comprising approximately 1400 nm to approximately 2600 nm. Therefore, the ARC structure 118 is configured to reduce reflections away from the image sensor 112 at wavelengths within a first range of the received wavelength, thereby mitigating the impact of the lower QE of the image sensor element 112 and improving the overall performance of the pixel sensor 200d in D-TOF applications.

[0106] Figure 2E Showing according to Figure 2A Cross-sectional views of some alternative embodiments of pixel sensor 200a and some embodiments of pixel sensor 200e.

[0107] In some embodiments, the image sensor element 112 includes a doped region 216 of a substrate 110. In various embodiments, regions of the substrate 110 adjacent to and / or in contact with the doped region 216 include a first doping type (e.g., p-type dopant), and the doped region 216 includes a second doping type (e.g., n-type) different from the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. The image sensor element 112 is configured to generate an electrical signal from electromagnetic radiation within a frequency range. In some embodiments, the frequency range may include, for example, visible light (e.g., electromagnetic radiation with wavelengths in the range of about 400 nm to about 700 nm). It should be understood that image sensor elements 112 configured to generate electrical signals from other frequency wavelength values ​​are also within the scope of this disclosure.

[0108] Figure 2F Showing according to Figure 2A Cross-sectional views of some alternative embodiments of pixel sensor 200a and some embodiments of pixel sensor 200f.

[0109] A filter 218 (e.g., a color filter, an infrared (IR) filter, etc.) is overlaid on the ARC structure 118 and laterally disposed between the sidewalls of the grid structure 126. The filter 218 is configured to transmit incident radiation of a specific wavelength. For example, the filter 218 may transmit radiation with wavelengths in a first range while blocking radiation with wavelengths in a second range different from the first range. Additionally, a plurality of microlenses 220 are disposed above the filter 218 and the grid structure 126. The microlenses 220 are configured to focus incident electromagnetic radiation toward the substrate 110, thereby improving the QE of the image sensor element 112. In yet another embodiment, the image sensor element 112 may be configured as... Figure 2E The image sensor element 112 of the pixel sensor 200e.

[0110] Figure 3 Cross-sectional views of some embodiments of an integrated circuit (IC) 300 including a first IC die 301 beneath a second IC die 303 are shown, wherein the second IC die 303 includes an ARC structure 118 overlying a plurality of image sensor elements 112a to image sensor elements 112b.

[0111] like Figure 3As shown, the first IC die 301 includes a lower interconnect structure 307 overlying a lower substrate 302. The lower substrate 302 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, P-doped silicon, N-doped silicon, another suitable material, or any combination thereof. The lower interconnect structure 307 includes an interconnect dielectric structure 104, a plurality of conductive lines 106, and a plurality of vias 108. The lower interconnect structure 307 is configured to electrically couple semiconductor devices 305 disposed on and / or within the lower substrate 302 to each other, other devices (e.g., image sensor elements 112a to 112b), and / or doped regions disposed within the lower substrate 302. In some embodiments, the semiconductor devices 305 may be configured as transistors, pixel devices (e.g., source follower transistors, row select transistors, reset transistors, etc.), capacitors, other semiconductor devices, or any combination thereof. In yet another embodiment, the first IC die 301 is configured as an application-specific integrated circuit (ASIC), wherein the semiconductor device 305 is configured as an ASIC device.

[0112] The first IC die 301 and the second IC die 303 are bonded at the bonding interface between the first bonding structure 308 and the second bonding structure 316. The first bonding structure 308 and the second bonding structure 316 each include a bonding dielectric structure 312, a bonding etch stop layer 310, a redistribution via 313, and a redistribution 314. The first bonding structure 308 and the second bonding structure 316 are configured to facilitate bonding the second IC die 303 to the first IC die 301 and electrically coupling the interconnect structure 102 to the lower interconnect structure 307. This partially facilitates the electrical coupling of image sensor elements 112a to 112b to the semiconductor device 305 through the interconnect structure 102 and the lower interconnect structure 307.

[0113] Additionally, the second IC die 303 includes a plurality of image sensor elements 112a to 112b disposed within the substrate 110 and laterally offset from the upper bonding pad structure 328. In some embodiments, each of the image sensor elements 112a to 112b includes an active layer 114 and is configurable to Figure 1 , Figures 2A to 2D or Figure 2F Image sensor element 112. In yet another embodiment, each of image sensor elements 112a to 112b may be configured to... Figure 2E The image sensor elements 112, such that each image sensor element 112a to image sensor element 112b includes a doped region ( Figure 2E(216). The ARC structure 118 is overlaid on the back side 110b of the substrate 110 and configured to improve the QE of the image sensor elements 112a to 112b. In some embodiments, the ARC structure 118 includes a passivation layer 204 disposed between the back side 110b of the substrate 110 and the first dielectric layer 120. In yet another embodiment, the passivation layer 204 is disposed between the substrate 110 and the second isolation structure 202 (not shown) (see, for example, see...). Figure 2B ).

[0114] A mesh structure 126 is overlaid on the ARC structure 118. In some embodiments, the mesh structure 126 may include a first mesh layer 321 and a second mesh layer 322 overlaid on the first mesh layer 321. The first mesh layer 321 and the second mesh layer 322 may each be, for example, a conductive material, such as tungsten, aluminum, copper, a combination thereof, or the like. In other embodiments, the first mesh layer 321 and the second mesh layer 322 may be, for example, a conductive material or a dielectric material. For example, the first mesh layer 321 may be, for example, a conductive mesh structure (e.g., including tungsten, aluminum, copper, another conductive material, etc.) configured to guide incident radiation from image sensor element 112a to image sensor element 112b, and the second mesh layer 322 may be, for example, a dielectric mesh structure configured to achieve total internal reflection (TIR) ​​with the upper dielectric layer 128, and vice versa. This can improve the QE of image sensor elements 112a to image sensor element 112b. Multiple filters 218 are overlaid on the mesh structure 126, and multiple microlenses are overlaid on the multiple filters 218. An upper etch stop layer 330 liner exposes an opening 336 on the upper surface of the upper bonding pad structure 328. In some embodiments, the upper etch stop layer 330 may be, for example, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination thereof. In some embodiments, bonding pads (not shown) are disposed within the opening 336 and overlaid on the upper bonding pad structure 328. The bonding pads are configured to electrically couple a first IC die 301 and / or a second IC die 303 to another integrated circuit (not shown).

[0115] Figures 4 to 11 Cross-sectional views 400 to 1100 illustrate some embodiments of a method for forming a pixel sensor having an anti-reflective coating (ARC) structure overlying an image sensor element according to the present disclosure. Although the method is described with reference to the method description... Figures 4 to 11 The cross-sectional views 400 to 1100 are shown in the figures, but it should be understood that... Figures 4 to 11 The structures illustrated herein are not limited to the method described and can actually be used independently of the method. Furthermore, although... Figures 4 to 11The description is a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments and the disclosed methods are also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted entirely or in part.

[0116] like Figure 4 As shown in cross-sectional view 400, a substrate 110 is provided and a first isolation structure 116 is formed within the substrate 110. In some embodiments, the substrate 110 may be, for example, a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, or some other suitable substrate. In other embodiments, the first isolation structure 116 may be formed by selectively etching the substrate 110 to form trenches in the substrate 110, and then filling the trenches with a dielectric material (e.g., by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition or growth process). In yet another embodiment, the substrate 110 may be selectively etched by forming a mask layer (not shown) over the front side 110f of the substrate 110, and then exposing the substrate 110 to one or more etchants configured to selectively remove unmasked portions of the substrate 110. In various embodiments, the dielectric material may be, for example, an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), another suitable dielectric material, or any combination thereof.

[0117] like Figure 5 As shown in cross-sectional view 500, an image sensor element 112 is formed within a substrate 110. In some embodiments, the process for forming the image sensor element 112 includes: selectively etching the substrate 110 to define an opening extending into a front side 110f of the substrate 110; depositing an active material (e.g., germanium) within the opening; and performing a planarization process (e.g., chemical mechanical planarization (CMP)) on the active material, thereby forming an active layer 114 within the substrate 110. In other embodiments, prior to forming the active layer 114, a buffer layer (not shown) is selectively grown within the opening, such that the buffer layer is disposed between the active layer 114 and the substrate 110 (see, for example, [link to previous embodiment]). Figure 2DThe buffer layer 209). In other embodiments, the buffer layer and / or active material may be formed, for example, by molecular-beame epitaxy (MBE), vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), some other suitable epitaxial process, some other suitable deposition or growth process, or any combination thereof. Furthermore, one or more formation processes (e.g., including selective ion implantation or other suitable processing steps) may be performed to define well regions, doped regions, or other suitable regions and / or structures within the active layer 114. For example, one or more formation processes may be performed to form in the active layer 114 Figure 2D The second deep well 210, the first heavily doped region 212 and / or the first deep well 214.

[0118] In another alternative embodiment, the process for forming the image sensor element 112 may include performing a selective ion implantation process on the substrate 110 to form a doped region (not shown) within the substrate 110 (see, for example, see...). Figure 2E The doped regions 216 may be laterally disposed between the sidewalls of the first isolation structure 116. In such embodiments, the substrate 110 includes a first doping type (e.g., p-type) laterally adjacent to the doped regions, wherein the doped regions include a second doping type (e.g., n-type) opposite to the first doping type. In such embodiments, the active layer 114 is omitted, and the image sensor element 112 is configured as follows: Figure 2E Image sensor element 112.

[0119] In addition, such as Figure 5 As shown in cross-sectional view 500, after forming the image sensor element 112, a thinning process is performed on the back side 110b of the substrate 110 to reduce the initial thickness Ti of the substrate 110 to a thickness Ts. The thickness Ts is defined between the front side 110f of the substrate 110 and the back side 110b of the substrate 110. In some embodiments, the thinning process may include performing a mechanical polishing process, a CMP process, another suitable thinning process, or any combination thereof.

[0120] like Figure 6As shown in cross-sectional view 600, an interconnect structure 102 is formed above the front side 110f of the substrate 110. The interconnect structure 102 includes an interconnect dielectric structure 104, a plurality of conductive lines 106, a plurality of vias 108, and a reflector 208. In some embodiments, the interconnect dielectric structure 104 may be, for example, an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), a low-k dielectric material, another suitable dielectric material, or any combination thereof. The interconnect dielectric structure 104 may be formed by one or more deposition processes (e.g., CVD, PVD, ALD, or another suitable deposition or growth process). The plurality of conductive lines 106 and / or the plurality of vias 108 may be formed, for example, by a single damascene process, a dual damascene process, or another suitable formation process. Additionally, the reflector 208 may be formed simultaneously with at least one layer of the conductive lines 106 and / or the vias 108. In some embodiments, the conductive line 106 and / or the via 108 may, for example, be or comprise aluminum, copper, titanium nitride, tantalum nitride, ruthenium, another suitable conductive material, or any combination thereof. In yet another embodiment, the reflector 208 may, for example, be or comprise aluminum, tungsten, copper, another metallic material, or any combination thereof.

[0121] As by Figure 7 As shown in the cross-sectional view 700, Figure 6 The structure is flipped and a patterning process is performed on the back side 110b of the substrate 110, thereby forming a deep trench isolation (DTI) opening 702. In some embodiments, the patterning process includes: forming a mask layer (not shown) over the back side 110b of the substrate 110, exposing an unmasked area of ​​the substrate 110 to one or more etchants, thereby forming the DTI opening 702, and performing a removal process to remove the mask layer.

[0122] As by Figure 8 As shown in the cross-sectional view 800, a second isolation structure 202 is formed above the back side 110b of the substrate 110, thereby filling the DTI opening ( Figure 7 702). In various embodiments, the second isolation structure 202 may be configured as a DTI structure and / or may include a passivation layer 204 and a conductive trench layer 206. In some embodiments, the process for forming the second isolation structure 202 includes: depositing a passivation layer 204 over a substrate 110 (e.g., by CVD, PVD, ALD, or another suitable deposition or growth process), wherein the passivation layer 204 covers the back side 110b of the substrate 110 and lined with a DTI opening ( ). Figure 7 702), a conductive material is deposited on the back side 110b of the substrate 110 (e.g., by CVD, PVD, electroless plating, sputtering, electroplating, or another suitable deposition or growth process), wherein the conductive material covers the substrate 110 and fills the DTI openings ( Figure 7The conductive trench layer 206 and the second isolation structure 202 are formed by performing a planarization process (e.g., CMP process) on the conductive material and / or passivation layer 204. In some embodiments, the passivation layer 204 may be, for example, or include a dielectric material, such as silicon dioxide, silicon oxynitride, silicon oxycarbide, another suitable dielectric material, or any combination thereof. In other embodiments, the conductive trench layer 206 may be, for example, or include aluminum, tungsten, copper, another suitable conductive material, or any combination thereof.

[0123] As by Figure 9 As shown in cross-sectional view 900, an anti-reflective coating (ARC) structure 118 is formed over the back side 110b of the substrate 110. In some embodiments, the ARC structure 118 includes a first dielectric layer 120, a second dielectric layer 122, and a third dielectric layer 124. In other embodiments, the process for forming the ARC structure 118 includes: depositing the first dielectric layer 120 over the substrate 110 (e.g., by CVD, PVD, ALD, or another suitable deposition or growth process); depositing the second dielectric layer 122 over the first dielectric layer 120 (e.g., by CVD, PVD, ALD, or another suitable deposition or growth process); and depositing the third dielectric layer 124 over the second dielectric layer 122 (e.g., by CVD, PVD, ALD, or another suitable deposition or growth process), thereby forming the ARC structure 118. In some embodiments, the third dielectric layer 124 is formed by a plasma-enhanced CVD process, an ALD process, a high-density plasma CVD process, or another suitable growth or deposition process.

[0124] The first dielectric layer 120 has a first refractive index, the second dielectric layer 122 has a second refractive index, and the third dielectric layer 124 has a third refractive index. In some embodiments, the first dielectric layer 120 may be, for example, or include tantalum oxide (e.g., Ta2O5), another dielectric material, or any combination thereof, and / or the first refractive index may be about 2, about 2.06, in the range of about 2 to 2.16, or another suitable value. In other embodiments, the second dielectric layer 122 may be, for example, or include titanium oxide (e.g., TiO2), silicon carbide, another suitable dielectric material, or any combination thereof, and / or the second refractive index may be about 2.43, in the range of about 2.4 to 2.6, or another suitable value. In other embodiments, the third dielectric layer 124 may be, for example, or include silicon dioxide (e.g., SiO2), another oxide, high-density plasma oxide, another suitable dielectric material, or any combination thereof, and / or the third refractive index may be about 1.44, about 1.438, about 1.53, in the range of about 1.438 to 1.53, or another suitable value. In various embodiments, the second refractive index is greater than the first refractive index and / or the third refractive index is less than the first refractive index. This partially reduces the reflection of electromagnetic radiation away from the image sensor element 112, thereby improving the QE of the image sensor element 112.

[0125] In some embodiments, the first dielectric layer 120 is formed to a first thickness t1, for example, about 1,100 angstroms, in the range of about 900 angstroms to 1,300 angstroms, or for another suitable thickness value. In other embodiments, the second dielectric layer 122 is formed to a second thickness t2, for example, about 200 angstroms, in the range of about 10 angstroms to 1,000 angstroms, or for another suitable thickness value. In still other embodiments, the third dielectric layer 124 is formed to a third thickness t3, for example, about 1,300 angstroms, in the range of about 1,100 angstroms to 1,500 angstroms, or for another suitable thickness value. In various embodiments, the first thickness t1 is greater than the second thickness t2, and the first thickness t1 is less than the third thickness t3.

[0126] As by Figure 10 As shown in cross-sectional view 1000, a mesh structure 126 and an upper dielectric layer 128 are formed over the ARC structure 118. In some embodiments, the mesh structure 126 may include a metallic mesh structure and / or a dielectric mesh structure. In other embodiments, the metallic mesh structure and / or dielectric mesh structure may be formed by, for example, CVD, PVD, ALD, sputtering, electroless plating, electroplating, or another suitable growth or deposition process. Additionally, after depositing the metallic mesh structure and / or dielectric mesh structure, a patterning process may be performed on the metallic mesh structure and / or dielectric mesh structure to define openings. Subsequently, the upper dielectric layer 128 may be formed within the openings and over the ARC structure 118.

[0127] As by Figure 11As shown in cross-sectional view 1100, a filter 218 is formed above an upper dielectric layer 128, and a microlens 220 is formed above the filter 218. The filter 218 is formed of a material that allows the transmission of incident electromagnetic radiation (e.g., light) having a specific wavelength range while blocking incident wavelengths having another wavelength outside the specified range. In other embodiments, the filter 218 can be formed by CVD, PVD, ALD, sputtering, etc., and / or can be planarized after formation (e.g., via chemical mechanical planarization (CMP)). Additionally, in some embodiments, the microlens 220 can be formed by depositing a lens material on the filter 218 (e.g., by CVD, PVD, etc.). A lens template (not shown) having a curved upper surface is patterned over the lens material. The microlens 220 is then formed by selectively etching the lens material according to the lens template.

[0128] Figure 12 A method 1200 for forming a pixel sensor according to the present disclosure having an anti-reflective coating (ARC) structure overlying an image sensor element is illustrated. Although method 1200 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the shown order or actions. Therefore, in some embodiments, actions may be performed in a different order than shown and / or simultaneously. Additionally, in some embodiments, the shown actions or events may be subdivided into multiple actions or events, which may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted and other actions or events not shown may be included.

[0129] At action 1202, a first isolation structure is formed in the front side of the substrate, wherein the substrate includes a first material. Figure 4 A cross-sectional view 400 is shown corresponding to some embodiments of action 1202.

[0130] At action 1204, an image sensor element is formed in the substrate, wherein the image sensor element has an active layer comprising a second material different from the first material. Figure 5 Cross-sectional view 500 is shown corresponding to some embodiments of action 1204.

[0131] At action 1206, an interconnect structure is formed along the front side of the substrate. Figure 6 A cross-sectional view 600 is shown corresponding to some embodiments of action 1206.

[0132] At action 1208, a second isolation structure is formed in the back side of the substrate, wherein the second isolation structure extends from the back side of the substrate to the first isolation structure. Figure 7 and Figure 8Cross-sectional views 700 and 800 are shown corresponding to some embodiments of action 1208.

[0133] At operation 1210, an anti-reflective coating (ARC) structure is formed above the back side of the substrate. The ARC structure includes: a first dielectric layer having a first refractive index overlying the substrate, a second dielectric layer having a second refractive index overlying the first dielectric layer, and a third dielectric layer having a third refractive index overlying the second dielectric layer. Furthermore, the second refractive index is greater than the third refractive index. Figure 9 A cross-sectional view 900 is shown corresponding to some embodiments of action 1210.

[0134] At action 1212, a mesh structure and an upper dielectric layer are formed above the ARC structure. Figure 10 Cross-sectional view 1000 is shown corresponding to some embodiments of action 1212.

[0135] At action 1214, a filter is formed above the upper dielectric layer, and a microlens is formed above the filter. Figure 11 Cross-sectional view 1100 is shown corresponding to some embodiments of action 1214.

[0136] Therefore, in some embodiments, this disclosure relates to an anti-reflective coating (ARC) structure overlaid on an image sensor element, wherein the ARC structure comprises: a first dielectric layer having a first refractive index overlaid on the image sensor element, a second dielectric layer having a second refractive index overlaid on the first dielectric layer, and a third dielectric layer having a third refractive index overlaid on the second dielectric layer. The second refractive index is greater than the first refractive index, and the first refractive index is greater than the third refractive index.

[0137] In some embodiments, this invention provides a pixel sensor comprising: a substrate having a front side opposite to a back side; an image sensor element including an active layer disposed within the substrate, wherein the active layer includes germanium; and an anti-reflective coating (ARC) structure overlying the back side of the substrate, wherein the ARC structure includes a first dielectric layer overlying the back side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer, wherein a first refractive index of the first dielectric layer is less than a second refractive index of the second dielectric layer, and wherein a third refractive index of the third dielectric layer is less than a first refractive index.

[0138] In some embodiments, the first dielectric layer, the second dielectric layer, and the third dielectric layer each comprise different dielectric materials. In some embodiments, the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer, wherein the thickness of the third dielectric layer is greater than the thickness of the first dielectric layer. In some embodiments, the image sensor element is configured to generate an electrical signal from near-infrared radiation. In some embodiments, the first dielectric layer comprises tantalum oxide, the second dielectric layer comprises titanium oxide or silicon carbide, and the third dielectric layer comprises silicon dioxide. In some embodiments, the pixel sensor further comprises an isolation structure disposed within the substrate, wherein the isolation structure extends from the back side of the substrate to the front side of the substrate, wherein the image sensor elements are laterally spaced between the sidewalls of the isolation structure. In some embodiments, the pixel sensor further comprises an interconnect structure and a reflector, the interconnect structure being disposed along the front side of the substrate, wherein the interconnect structure includes an interconnect dielectric structure, a plurality of vias, and a plurality of conductive lines, and the reflector being disposed within the interconnect dielectric structure and directly below the image sensor element. In some embodiments, the pixel sensor further comprises a mesh structure overlying the anti-reflective coating structure, a filter overlying the mesh structure, and a microlens overlying the filter.

[0139] In some embodiments, this invention provides an integrated circuit (IC) comprising: a first IC die including a first substrate and a first interconnect structure overlying the first substrate; a second IC die overlying the first IC die, wherein the second IC die includes a second substrate and a second interconnect structure beneath the second substrate, wherein the first IC die and the second IC die are in contact at a bonding interface between the first interconnect structure and the second interconnect structure; a plurality of image sensor elements disposed within the second substrate; a mesh structure overlying the plurality of image sensor elements, wherein each image sensor element is laterally spaced between the sidewalls of the mesh structure; and an anti-reflective coating (ARC) structure disposed between the second substrate and the mesh structure, wherein the ARC structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer each having a different refractive index from each other, wherein the second dielectric layer overlying the first dielectric layer and the third dielectric layer overlying the second dielectric layer, wherein the first dielectric layer includes a first metal oxide, and the second dielectric layer includes a second metal oxide different from the first metal oxide.

[0140] In some embodiments, the first metal oxide is tantalum oxide and the second metal oxide is titanium oxide. In some embodiments, the first refractive index of the first dielectric layer is less than the second refractive index of the second dielectric layer, wherein the third refractive index of the third dielectric layer is less than the second refractive index. In some embodiments, the antireflective coating structure further includes a passivation layer disposed between the first dielectric layer and the second substrate, wherein the refractive index of the passivation layer is equal to the third refractive index. In some embodiments, the thickness of the third dielectric layer is greater than the thickness of the second dielectric layer, wherein the thickness of the second dielectric layer is greater than the thickness of the passivation layer. In some embodiments, the second refractive index is in the range of about 2.4 to 2.6, and the third refractive index is less than about 1.55. In some embodiments, the integrated circuit further includes a first isolation structure and a second isolation structure, the first isolation structure extending from a front surface of the second substrate to a first point above the front surface, wherein each of the image sensor elements is laterally spaced between the sidewalls of the first isolation structure, and the second isolation structure extending from a back surface of the second substrate to a second point below the back surface, wherein the second point is below the first point, such that the second isolation structure contacts the first isolation structure.

[0141] In some embodiments, this invention provides a method for forming a pixel sensor, the method comprising: forming a first isolation structure in the front side of a substrate; forming an image sensor element in the substrate such that the image sensor element includes an active layer laterally spaced between sidewalls of the first isolation structure, wherein the substrate includes a first material and the active layer includes a second material different from the first material; forming an interconnect structure along the front side of the substrate; and forming an anti-reflective coating (ARC) structure over the back side of the substrate such that the ARC structure includes a first dielectric layer overlying the back side of the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer, wherein a first refractive index of the first dielectric layer is less than a second refractive index of the second dielectric layer, and wherein a third refractive index of the third dielectric layer is less than a first refractive index.

[0142] In some embodiments, forming the image sensor element includes patterning the front side of the substrate to form an opening extending into the front side of the substrate; depositing the second material within the opening; and performing a planarization process on the second material, thereby forming the active layer. In some embodiments, the method for forming a pixel sensor further includes patterning the back side of the substrate to form an opening extending into the back side of the substrate; depositing a passivation layer over the substrate such that the passivation layer liner the opening, wherein the passivation layer is disposed between the substrate and the first dielectric layer; and forming a conductive trench layer within the opening such that the passivation layer is disposed between the conductive trench layer and the substrate. In some embodiments, the refractive index of the passivation layer is less than the first refractive index and the second refractive index.

[0143] The foregoing summary outlines the features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A pixel sensor, comprising: Substrate, having a front side opposite to the back side; An image sensor element includes an active layer disposed within the substrate, wherein the active layer comprises germanium; as well as An anti-reflective coating structure is applied to the back side of the substrate, wherein the anti-reflective coating structure includes a first dielectric layer applied to the back side of the substrate, a second dielectric layer applied to the first dielectric layer, and a third dielectric layer applied to the second dielectric layer, wherein the first refractive index of the first dielectric layer is less than the second refractive index of the second dielectric layer, and wherein the third refractive index of the third dielectric layer is less than the first refractive index.

2. The pixel sensor according to claim 1, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer each comprise different dielectric materials.

3. The pixel sensor according to claim 1, wherein the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer, and wherein the thickness of the third dielectric layer is greater than the thickness of the first dielectric layer.

4. The pixel sensor of claim 1, wherein the image sensor element is configured to generate an electrical signal from near-infrared radiation.

5. The pixel sensor according to claim 1, wherein the first dielectric layer comprises tantalum oxide, the second dielectric layer comprises titanium oxide or silicon carbide, and the third dielectric layer comprises silicon dioxide.

6. The pixel sensor according to claim 1, further comprising: An isolation structure is disposed within the substrate, wherein the isolation structure extends from the back side of the substrate to the front side of the substrate, wherein the image sensor elements are laterally spaced between the sidewalls of the isolation structure.

7. The pixel sensor according to claim 1, further comprising: An interconnect structure is disposed along the front side of the substrate, wherein the interconnect structure includes an interconnect dielectric structure, a plurality of vias, and a plurality of conductive lines; as well as A reflector is disposed within the interconnect dielectric structure and directly beneath the image sensor element.

8. The pixel sensor according to claim 1, further comprising: A mesh structure is applied over the anti-reflective coating structure; A filter is applied over the mesh structure; as well as Microlenses are applied over the filter.

9. The pixel sensor of claim 1, wherein the substrate comprises a first material different from germanium.

10. An integrated circuit, comprising: The first integrated circuit die includes a first substrate and a first interconnect structure covered by the first substrate; A second integrated circuit die is overlaid on the first integrated circuit die, wherein the second integrated circuit die includes a second substrate and a second interconnect structure under the second substrate, wherein the first integrated circuit die and the second integrated circuit die are in contact at a bonding interface between the first interconnect structure and the second interconnect structure; Multiple image sensor elements are disposed within the second substrate; A mesh structure is overlaid on the plurality of image sensor elements, wherein each of the image sensor elements is laterally spaced between the sidewalls of the mesh structure; as well as An anti-reflective coating structure is disposed between the second substrate and the mesh structure. The anti-reflective coating structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, each having a different refractive index. The second dielectric layer is overlaid on the first dielectric layer, and the third dielectric layer is overlaid on the second dielectric layer. The first dielectric layer includes a first metal oxide, and the second dielectric layer includes a second metal oxide different from the first metal oxide. The first refractive index of the first dielectric layer is less than the second refractive index of the second dielectric layer, and the third refractive index of the third dielectric layer is less than the second refractive index.

11. The integrated circuit according to claim 10, wherein the first metal oxide is tantalum oxide and the second metal oxide is titanium oxide.

12. The integrated circuit of claim 10, wherein the first thickness of the first dielectric layer is greater than the second thickness of the second dielectric layer, and the first thickness is less than the third thickness of the third dielectric layer.

13. The integrated circuit according to claim 10, further comprising a passivation layer disposed between the first dielectric layer and the second substrate, wherein the refractive index of the passivation layer is equal to the third refractive index.

14. The integrated circuit of claim 13, wherein the thickness of the third dielectric layer is greater than the thickness of the second dielectric layer, and the thickness of the second dielectric layer is greater than the thickness of the passivation layer.

15. The integrated circuit of claim 10, wherein the second refractive index is in the range of 2.4 to 2.6, and the third refractive index is less than 1.

55.

16. The integrated circuit of claim 10, further comprising: A first isolation structure extends from the front surface of the second substrate to a first point above the front surface, wherein each of the image sensor elements is laterally spaced between the sidewalls of the first isolation structure. as well as A second isolation structure extends from the back surface of the second substrate to a second point below the back surface, wherein the second point is below the first point, such that the second isolation structure contacts the first isolation structure.

17. A method for forming a pixel sensor, the method comprising: The first isolation structure is formed in the front side of the substrate; An image sensor element is formed within the substrate, such that the image sensor element includes an active layer laterally spaced between the sidewalls of the first isolation structure, wherein the substrate comprises a first material and the active layer comprises a second material different from the first material; An interconnect structure is formed along the front side of the substrate; as well as An anti-reflective coating structure is formed above the back side of the substrate, such that the anti-reflective coating structure includes a first dielectric layer covering the back side of the substrate, a second dielectric layer covering the first dielectric layer, and a third dielectric layer covering the second dielectric layer, wherein the first refractive index of the first dielectric layer is less than the second refractive index of the second dielectric layer, and wherein the third refractive index of the third dielectric layer is less than the first refractive index.

18. The method for forming a pixel sensor according to claim 17, wherein forming the image sensor element comprises: The front side of the substrate is patterned to form an opening extending into the front side of the substrate; Depositing the second material within the opening; and A planarization process is performed on the second material to form the active layer.

19. The method for forming a pixel sensor according to claim 17, further comprising: The back side of the substrate is patterned to form an opening extending into the back side of the substrate; A passivation layer is deposited over the substrate such that the passivation layer liner the opening, wherein the passivation layer is disposed between the substrate and the first dielectric layer; as well as A conductive trench layer is formed within the opening, such that the passivation layer is disposed between the conductive trench layer and the substrate.

20. The method for forming a pixel sensor according to claim 19, wherein the refractive index of the passivation layer is less than the first refractive index and the second refractive index.

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