Epitaxial structure of semiconductor device and preparation method thereof, semiconductor device

Abstract

Embodiments of the present invention disclose an epitaxial structure of a semiconductor device, a method for fabricating the same, and a semiconductor device. The epitaxial structure includes a substrate and a semiconductor layer located on one side of the substrate. The semiconductor layer includes at least a buffer layer disposed on one side of the substrate. The buffer layer includes a first buffer section and a second buffer section connected to each other, extending from a source predetermined region to a drain predetermined region. The vertical projection of the first buffer section on the substrate overlaps with the vertical projection of the source predetermined region on the substrate, and the vertical projection of the second buffer section on the substrate overlaps with the vertical projections of the gate predetermined region and the drain predetermined region on the substrate. Ions are implanted into the buffer layer, and the ion implantation concentration in the second buffer section is greater than the ion implantation concentration in the first buffer section. A semiconductor device utilizing this epitaxial structure exhibits high breakdown voltage, low leakage current, and high electrostatic protection capabilities.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to an epitaxial structure of a semiconductor device and a preparation method thereof, and a semiconductor device. Background Art

[0002] The semiconductor material gallium nitride has become a current research hotspot due to its characteristics such as large bandgap, high electron saturation drift velocity, high breakdown field strength, and good thermal conductivity. For example, it is used to prepare gallium nitride high electron mobility transistor (GaNHEMT) devices.

[0003] Reducing leakage and improving electrostatic discharge (ESD) protection are important directions for optimizing GaN HEMT devices. In the prior art, doping or ion implantation is usually performed in the buffer layer during the epitaxial growth process to increase the resistivity of the buffer layer, thereby achieving a higher breakdown voltage and lower leakage. However, from the perspective of improving electrostatic protection, it is necessary to reduce the resistivity of the buffer layer between the gate and the source. Therefore, if the above-mentioned scheme for reducing leakage is adopted, the entire buffer layer will have the same higher resistivity, which makes the increase in resistivity run counter to the goal of improving ESD protection.

[0004] How to improve the electrostatic protection capability of semiconductor devices while achieving higher breakdown voltage and lower leakage is an urgent problem to be solved. Summary of the Invention

[0005] An embodiment of the present invention provides an epitaxial structure of a semiconductor device, a preparation method thereof, and a semiconductor device. The semiconductor device using the epitaxial structure has high breakdown voltage, low leakage current, and high electrostatic protection capability.

[0006] In a first aspect, an embodiment of the present invention provides an epitaxial structure of a semiconductor device, comprising:

[0007] substrate;

[0008] A semiconductor layer located on one side of a substrate; the semiconductor layer at least includes a buffer layer arranged on one side of the substrate; along the direction from the source preset region to the drain preset region, the buffer layer includes a first buffer section and a second buffer section connected to each other, the vertical projection of the first buffer section on the substrate overlaps with the vertical projection of the source preset region on the substrate, and the vertical projection of the second buffer section on the substrate overlaps with the vertical projections of the gate preset region and the drain preset region on the substrate; ions are injected into the buffer layer, and the ion injection concentration in the second buffer section is greater than the ion injection concentration in the first buffer section; the gate preset region is located between the source preset region and the drain preset region.

[0009] Optionally, the ion implantation concentration C1 in the first buffer sub-section satisfies C1=0; the resistivity ρ1 of the first buffer sub-section satisfies 0.1Ω·cm≤ρ1≤100Ω·cm;

[0010] The ion implantation concentration C2 in the second buffer section satisfies 1×10 17 cm -3 ≤C2≤5×10 18 cm -3 ; The resistivity ρ2 of the second buffer section satisfies 10 5 Ω·cm≤ρ2≤10 10 Ω·cm.

[0011] Optionally, the semiconductor layer further includes a barrier layer, the barrier layer is located on a side of the buffer layer away from the substrate, and the band gap width of the barrier layer is greater than the band gap width of the buffer layer;

[0012] Along the direction from the source preset region to the drain preset region, the blocking layer includes a first blocking sub-section and a second blocking sub-section connected to each other, a vertical projection of the first blocking sub-section on the substrate overlaps with a vertical projection of the source preset region on the substrate, and a vertical projection of the second blocking sub-section on the substrate overlaps with a vertical projection of the gate preset region and a vertical projection of the drain preset region on the substrate;

[0013] Ions are implanted into the barrier layer, and the ion implantation concentration in the second barrier sub-section is greater than the ion implantation concentration in the first barrier sub-section.

[0014] Optionally, the ion implantation concentration C3 in the first blocking sub-section satisfies C3=0; the resistivity ρ3 of the first blocking sub-section satisfies 0.1Ω·cm≤ρ3≤100Ω·cm;

[0015] The ion implantation concentration C4 in the second blocking section satisfies 1×10 15 cm -3 ≤C4≤5×10 16 cm -3 ; The resistivity ρ4 of the second barrier section satisfies 10 5 Ω·cm≤ρ4≤10 10 Ω·cm.

[0016] Optionally, the semiconductor layer further includes a nucleation layer, and the nucleation layer is located between the substrate and the buffer layer;

[0017] Along the direction from the source preset region to the drain preset region, the nucleation layer includes a first nucleation subsection and a second nucleation subsection connected to each other, the first nucleation subsection is located between the first buffer subsection and the substrate, and the second nucleation subsection is located between the second buffer subsection and the substrate;

[0018] Ions are implanted into the nucleation layer, and the ion implantation concentration in the second nucleation subsection is greater than the ion implantation concentration in the first nucleation subsection.

[0019] Optionally, the ions include at least one of boron ions, arsenic ions, helium ions, beryllium ions, magnesium ions, argon ions, aluminum ions, phosphorus ions, nitrogen ions, oxygen ions, carbon ions, and iron ions.

[0020] In a second aspect, an embodiment of the present invention further provides a method for preparing an epitaxial structure of a semiconductor device, which is used to prepare the epitaxial structure provided in the above aspect, and the preparation method includes:

[0021] providing a substrate;

[0022] A semiconductor layer is prepared on one side of a substrate; the semiconductor layer includes at least a buffer layer arranged on one side of the substrate; along the direction from the source preset region to the drain preset region, the buffer layer includes a first buffer section and a second buffer section connected to each other, the vertical projection of the first buffer section on the substrate overlaps with the vertical projection of the source preset region on the substrate, and the vertical projection of the second buffer section on the substrate overlaps with the vertical projections of the gate preset region and the drain preset region on the substrate; ions are injected into the buffer layer, and the ion injection concentration in the second buffer section is greater than the ion injection concentration in the first buffer section; the gate preset region is located between the source preset region and the drain preset region.

[0023] Optionally, the semiconductor layer further includes a barrier layer, wherein the band gap width of the barrier layer is greater than the band gap width of the buffer layer; along the direction from the source preset region to the drain preset region, the barrier layer includes a first barrier sub-section and a second barrier sub-section connected to each other, wherein a vertical projection of the first barrier sub-section on the substrate overlaps with a vertical projection of the source preset region on the substrate, and a vertical projection of the second barrier sub-section on the substrate overlaps with a vertical projection of the gate preset region and a vertical projection of the drain preset region on the substrate;

[0024] The method comprises preparing a semiconductor layer on one side of the substrate, comprising:

[0025] A buffer layer and a barrier layer are sequentially prepared on one side of the substrate;

[0026] Ions are injected into the barrier layer and the buffer layer on a side of the barrier layer away from the substrate, the ion injection concentration in the second barrier section is greater than the ion injection concentration in the first barrier section, and the ion injection concentration in the second barrier section is less than the ion injection concentration in the second buffer section.

[0027] Optionally, the semiconductor layer further includes a nucleation layer; along a direction from the source preset region to the drain preset region, the nucleation layer includes a first nucleation subsection and a second nucleation subsection connected to each other, the first nucleation subsection is located between the first buffer subsection and the substrate, and the second nucleation subsection is located between the second buffer subsection and the substrate;

[0028] The method comprises preparing a semiconductor layer on one side of the substrate, comprising:

[0029] A nucleation layer and a buffer layer are sequentially prepared on one side of the substrate;

[0030] Ions are implanted into the buffer layer and the nucleation layer at a side of the buffer layer away from the substrate, and the ion implantation concentration in the second nucleation portion is greater than the ion implantation concentration in the first nucleation portion.

[0031] In a third aspect, an embodiment of the present invention further provides a semiconductor device, comprising the epitaxial structure provided in the first aspect;

[0032] The semiconductor device also includes a heterojunction structure located on the side of the epitaxial structure away from the substrate, and a gate, a source and a drain located on the side of the heterojunction structure away from the substrate. The gate is set in a gate preset area, the source is set in a source preset area, and the drain is set in a drain preset area.

[0033] In the epitaxial structure of the semiconductor device provided by the embodiment of the present invention, the ion implantation concentrations in different regions of the buffer layer are different. Since the ion implantation concentration of the buffer layer between the gate preset region and the drain preset region (i.e., the second buffer division) is relatively high, the resistivity of the second buffer division can be increased. Thus, when this epitaxial structure is applied to a semiconductor device, the breakdown voltage of the semiconductor device can be increased and the leakage of the semiconductor device can be reduced. At the same time, since the ion concentration of the buffer layer between the gate preset region and the source preset region (i.e., the first buffer division) is relatively low (even zero), the resistivity of the first buffer division can be maintained at a relatively low level. Thus, when this epitaxial structure is applied to a semiconductor device, the electrostatic protection capability of the semiconductor device can be improved, so that the semiconductor device using this epitaxial structure has high breakdown voltage, low leakage, and high electrostatic protection capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 1 is a schematic structural diagram of an epitaxial structure of a semiconductor device provided by an embodiment of the present invention;

[0035] Figure 2 is a schematic structural diagram of an epitaxial structure of another semiconductor device provided by an embodiment of the present invention;

[0036] Figure 3 is a schematic structural diagram of an epitaxial structure of another semiconductor device provided by an embodiment of the present invention;

[0037] Figure 4 is a schematic structural diagram of an epitaxial structure of another semiconductor device provided by an embodiment of the present invention;

[0038] Figure 5 This is a schematic flow chart of a method for preparing an epitaxial structure of a semiconductor device provided by an embodiment of the present invention;

[0039] Figure 6It is a schematic flow chart of another method for preparing an epitaxial structure of a semiconductor device provided by an embodiment of the present invention;

[0040] Figure 7 It is a schematic flow chart of another method for preparing an epitaxial structure of a semiconductor device provided by an embodiment of the present invention;

[0041] Figure 8 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0042] Figure 9 It is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0044] Figure 1 is a schematic diagram of the epitaxial structure of a semiconductor device provided by an embodiment of the present invention, see Figure 1 The epitaxial structure 10 of the semiconductor device provided by the embodiment of the present invention includes a substrate 1 and a semiconductor layer 2 located on one side of the substrate 1; the semiconductor layer 2 includes at least a buffer layer 22 arranged on one side of the substrate 1; along the direction from the source preset region 3 to the drain preset region 5, the buffer layer 22 includes a first buffer section 221 and a second buffer section 222 connected to each other, the vertical projection of the first buffer section 221 on the substrate 1 overlaps with the vertical projection of the source preset region 3 on the substrate 1, and the vertical projection of the second buffer section 222 on the substrate 1 overlaps with the vertical projections of the gate preset region 4 and the drain preset region 5 on the substrate 1; ions are implanted in the buffer layer 22, and the ion implantation concentration in the second buffer section 222 is greater than the ion implantation concentration in the first buffer section 221; the gate preset region 4 is located between the source preset region 3 and the drain preset region 5.

[0045] The epitaxial structure 10 provided in the embodiment of the present invention is used to manufacture semiconductor devices. Specifically, the semiconductor device can be manufactured by secondary growth on the epitaxial structure 10 to form a heterojunction structure, and forming a gate, source, and drain on the side of the heterojunction structure away from the substrate. The source is disposed in the aforementioned source preset region 3, the gate is disposed in the aforementioned gate preset region 4, and the drain is disposed in the aforementioned drain preset region 5.

[0046] For semiconductor devices, the highest voltage needs to be withstood between the gate and the drain. Therefore, a high-resistivity region needs to be formed in the semiconductor layer on the gate-to-drain side, while the semiconductor layer between the gate and the source needs to maintain a low resistivity to obtain better electrostatic protection capabilities. Therefore, in order to enable semiconductor devices to have high breakdown voltage, low leakage, and high electrostatic protection capabilities, an embodiment of the present invention provides an epitaxial structure. By performing ion implantation on the buffer layer 22 in different regions, the buffer layer 22 in different regions has different resistivities, thereby enabling semiconductor devices using this epitaxial structure to have high breakdown voltage, low leakage, and high electrostatic protection capabilities.

[0047] Specifically, because the ion implantation concentration in the second buffer subsection 222 is greater than that in the first buffer subsection 221, the resistivity of the second buffer subsection 222 is greater than that of the first buffer subsection 221. The first buffer subsection 221 corresponds to the region between the predetermined gate region 4 and the predetermined source region 3, thereby meeting the requirement for high electrostatic protection capability and low resistivity between the predetermined gate region 4 and the predetermined source region 3. The second buffer subsection 222 corresponds to the region between the predetermined gate region 4 and the predetermined drain region 5, thereby meeting the requirement for high resistivity and high breakdown voltage and low leakage.

[0048] Illustratively, the boundary line between the first buffer sub-portion 221 and the second buffer sub-portion 222 may be located at a preset distance from the gate preset region 4 toward the source preset region 3 . Illustratively, the distance between the boundary line and the gate preset region 4 may be 0 nm to 100 nm.

[0049] It should be noted that low-concentration ion implantation may be performed in the first buffer portion 221 , or ion implantation may not be performed, as long as the electrostatic protection capability of the semiconductor device is not affected.

[0050] It should also be noted that Figure 1 In the same film layer in subsequent figures, the filled portion indicates that ion implantation has been performed, and the unfilled portion indicates that ion implantation has not been performed.

[0051] Optionally, the material of the substrate 1 can be a combination of one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing group III nitrides.

[0052] In the epitaxial structure of the semiconductor device provided by the embodiment of the present invention, the ion implantation concentrations in different regions of the buffer layer are different. Since the ion implantation concentration of the buffer layer between the gate preset region and the drain preset region (i.e., the second buffer division) is relatively high, the resistivity of the second buffer division can be increased. Thus, when this epitaxial structure is applied to the semiconductor device, the breakdown voltage of the semiconductor device can be increased and the leakage of the semiconductor device can be reduced. At the same time, since the ion concentration of the buffer layer between the gate preset region and the source preset region (i.e., the first buffer division) is relatively low (even zero), the resistivity of the first buffer division can be maintained at a relatively low level. Thus, when this epitaxial structure is applied to the semiconductor device, the electrostatic protection capability of the semiconductor device can be improved, so that the semiconductor device has both high breakdown voltage, low leakage and high electrostatic protection capability.

[0053] Based on the above embodiments, the structure of the epitaxial structure is further described in detail below.

[0054] Optionally, the ion implantation concentration C1 in the first buffer sub-section 221 satisfies C1=0; the resistivity ρ1 of the first buffer sub-section 221 satisfies 0.1Ω·cm≤ρ1≤100Ω·cm; the ion implantation concentration C2 in the second buffer sub-section 222 satisfies 1×10 17 cm -3 ≤C2≤5×10 18 cm -3 The resistivity ρ2 of the second buffer portion 222 satisfies 10 5 Ω·cm≤ρ2≤10 10 Ω·cm.

[0055] In this embodiment, the first buffer division 221 is not ion-implanted, so that the first buffer division 221 can maintain its original low resistivity and have better electrostatic protection capability; the second buffer division 222 is ion-implanted, so that it has a high resistivity, achieving high breakdown voltage and low leakage of the semiconductor device.

[0056] Figure 2 is a schematic diagram of the epitaxial structure of another semiconductor device provided by an embodiment of the present invention, see Figure 2Optionally, the semiconductor layer 2 further includes a blocking layer 23, which is located on the side of the buffer layer 22 away from the substrate 1, and the band gap width of the blocking layer 23 is greater than the band gap width of the buffer layer 22; along the direction from the source preset region 3 to the drain preset region 5, the blocking layer 23 includes a first blocking sub-section 231 and a second blocking sub-section 232 connected to each other, the vertical projection of the first blocking sub-section 231 on the substrate 1 overlaps with the vertical projection of the source preset region 3 on the substrate 1, and the vertical projection of the second blocking sub-section 232 on the substrate 1 overlaps with the vertical projections of the gate preset region 4 and the drain preset region 5 on the substrate 1; ions are injected into the blocking layer 23, and the ion injection concentration in the second blocking sub-section 232 is greater than the ion injection concentration in the first blocking sub-section 231, and the ion injection concentration in the second blocking sub-section 232 is less than the ion injection concentration in the second buffer sub-section 222.

[0057] like Figure 2 As shown, in this embodiment, ion implantation is also performed on the barrier layer 23 in different regions. Thus, when this epitaxial structure is applied to a semiconductor device, it can achieve high breakdown voltage and low leakage while improving the electrostatic protection capability of the semiconductor device. The specific reasons are described above and will not be repeated here. Furthermore, the provision of the barrier layer 23 in this embodiment can also ensure the mobility of the two-dimensional electron gas.

[0058] Specifically, the heterojunction structure in a semiconductor device usually includes a channel layer and a barrier layer. The barrier layer is located on the side of the channel layer away from the epitaxial structure. A two-dimensional electron gas (2DEG) is formed on the side of the channel layer close to the barrier layer. The channel layer provides a channel for the movement of the two-dimensional electron gas (2DEG). Usually, the channel layer also has leakage. Since ions cannot be injected into the channel layer, in order to reduce the leakage of the channel layer, it is usually necessary to reduce the thickness of the channel layer. If using Figure 1 In the semiconductor device fabricated from the epitaxial structure shown, reducing the thickness of the channel layer will cause the buffer layer 22 to be closer to the two-dimensional electron gas. Since the ion implantation concentration in the second buffer portion 222 is relatively high, the high concentration of ions will cause the electron mobility in the two-dimensional electron gas to decrease, thereby affecting the performance of the semiconductor device.

[0059] To avoid this problem, this embodiment provides another epitaxial structure. By adding a barrier layer 23 on the buffer layer 22, the barrier layer 23 can be used to isolate the barrier layer from the buffer layer. Furthermore, because the barrier layer 23 has a larger bandgap, compared to the buffer layer 22, during ion implantation, the barrier layer 23 (the second barrier subsection 232) only needs to be implanted with a lower concentration (dose) of ions to achieve a sufficiently high resistivity. This achieves the aforementioned beneficial effects while avoiding a reduction in electron mobility in the two-dimensional electron gas.

[0060] In addition, since the ions injected into the buffer layer 22 are usually in a free state, the barrier layer 23 is provided to isolate the two-dimensional electron gas and the buffer layer 22, thereby preventing the ions in the buffer layer 22 from entering the channel layer when a heterojunction structure is subsequently grown on the epitaxial structure 10.

[0061] Furthermore, in this embodiment, since the ion injection concentration in the second blocking section 232 is lower than the ion injection concentration in the second buffer section 222, the impact on the mobility of the two-dimensional electron gas is very small. Therefore, when preparing a semiconductor device using the epitaxial structure provided in the embodiment of the present invention, the thickness of the channel layer can be further reduced to reduce the leakage of the channel layer.

[0062] Further optionally, the material of the buffer layer 22 includes Al x Ga (1-x) N or In x Ga (1-x) N, where 0≤x≤0.5; the material of the barrier layer 23 includes Al x Ga (1-x) N, where 0.8≤x≤1; the ion implantation concentration C3 in the first blocking sub-section 231 satisfies C3=0; the resistivity ρ3 of the first blocking sub-section 231 satisfies 0.1Ω·cm≤ρ3≤100Ω·cm; the ion implantation concentration C4 in the second blocking sub-section 232 satisfies 1×10 15 cm -3 ≤C4≤5×10 16 cm -3 The resistivity ρ4 of the second blocking portion 232 satisfies 10 5 Ω·cm≤ρ4≤10 10 Ω·cm.

[0063] In this embodiment, by setting the Al composition in the barrier layer 23 to be higher than the Al composition in the buffer layer 22, the band gap width of the barrier layer 23 is made larger than the band gap width of the buffer layer 22, so that the buffer layer 22 only needs the above-mentioned lower concentration ion injection to obtain the above-mentioned sufficiently high resistivity. In this way, when this epitaxial structure is applied to semiconductor devices, the electron mobility can be guaranteed.

[0064] In addition, in this embodiment, the first blocking division 231 is not ion-implanted, so that the first blocking division 231 can maintain its original low resistivity. In this way, when this epitaxial structure is applied to a semiconductor device, the electrostatic protection capability of the semiconductor device can be better; the second blocking division 232 is ion-implanted, so that it has a high resistivity. In this way, when this epitaxial structure is applied to a semiconductor device, the semiconductor device can have a high breakdown voltage and low leakage.

[0065] Figure 3is a schematic diagram of the epitaxial structure of another semiconductor device provided by an embodiment of the present invention, see Figure 3 Optionally, the semiconductor layer 2 also includes a nucleation layer 21, which is located between the substrate 1 and the buffer layer 22; along the direction from the source preset area 3 to the drain preset area 5, the nucleation layer 21 includes a first nucleation section 211 and a second nucleation section 212 that are interconnected, the first nucleation section 211 is located between the first buffer section 221 and the substrate 1, and the second nucleation section 212 is located between the second buffer section 222 and the substrate 1; ions are injected into the nucleation layer 21, and the ion injection concentration in the second nucleation section 212 is greater than the ion injection concentration in the first nucleation section 211.

[0066] By providing the nucleation layer 21, the crystal lattices of the substrate 1 and the buffer layer 22 can be matched. Thus, when the epitaxial structure is applied to a semiconductor device, parameters such as the crystal quality, surface morphology, and electrical properties of the heterojunction structure above the epitaxial structure can be optimized. It should be noted that since the leakage current of the nucleation layer 21 is generally low, the nucleation layer 21 may or may not be ion implanted, and this is not limited in the present embodiment.

[0067] In this embodiment, by performing ion implantation on the nucleation layer 21 in different regions, the leakage of the nucleation layer 21 can be further reduced. In this way, when the epitaxial structure is applied to a semiconductor device, the semiconductor device can have a high breakdown voltage and the electrostatic protection capability of the semiconductor device can be improved. The specific reasons can be found in the above description and will not be repeated here. Further optionally, the material of the nucleation layer 21 includes Al x Ga (1-x) N, where 0.5≤x≤1; the ion implantation concentration C5 in the first nucleation subsection 211 satisfies C5=0; the resistivity ρ5 of the first nucleation subsection 211 satisfies 0.1Ω·cm≤ρ5≤100Ω·cm; the ion concentration C6 in the second nucleation subsection 212 satisfies 1×10 17 cm -3 ≤C6≤5×10 18 cm -3 The resistivity ρ6 of the second nucleation subsection 212 satisfies 10 5 Ω·cm≤ρ6≤10 10 Ω·cm.

[0068] In this embodiment, the first nucleation section 211 is not ion-injected, so that the first nucleation section 211 can maintain its original low resistivity and have better electrostatic protection capability; the second nucleation section 212 is ion-injected, so that it has a high resistivity, achieving high breakdown voltage and low leakage of the semiconductor device.

[0069] In summary, the above embodiments further describe the epitaxial structure. The following points need to be explained:

[0070] First, in other embodiments, the semiconductor layer may also include a nucleation layer, a buffer layer, and a barrier layer, and ion implantation may be performed on the nucleation layer, the buffer layer, and the barrier layer (as well as the substrate) in different regions, which is not limited in the embodiment of the present invention.

[0071] Second, in the above embodiments, when ion implantation is performed in different regions on two or more film layers in the semiconductor layer, the boundary lines of the film layers are consistent as an example, so that the ion implantation process is simpler and more efficient. In addition, for example, Figure 4 is a schematic structural diagram of an epitaxial structure of another semiconductor device provided by an embodiment of the present invention, Figure 4 Take the semiconductor layer including the nucleation layer, the buffer layer and the barrier layer stacked on one side of the substrate as an example, see Figure 4 Optionally, the boundary between the first nucleation sub-section 211 and the second nucleation sub-section 212, the boundary between the first buffer sub-section 221 and the second buffer sub-section 222, and the boundary between the first blocking sub-section 31 and the second blocking sub-section 232 may not be consistent, as long as the semiconductor layer on the side farthest from the substrate in the epitaxial structure is ensured, for example Figure 2 or the barrier layer in 4 and Figure 3 The buffer layer in the embodiment of the present invention can be formed as long as the boundary line of the ion implantation areas with different concentrations is closer to the gate preset area 4.

[0072] Optionally, the ions include at least one of boron ions, arsenic ions, helium ions, beryllium ions, magnesium ions, argon ions, aluminum ions, phosphorus ions, nitrogen ions, oxygen ions, carbon ions, and iron ions.

[0073] By injecting at least one of the above examples into the buffer layer 22 (as well as the barrier layer 23 , the nucleation layer 21 and the substrate 1 ), the resistivity of the corresponding film layer can be increased, thereby reducing the leakage of the semiconductor device.

[0074] Further optionally, the types of ions implanted into the barrier layer 23 , the buffer layer 22 and the nucleation layer 21 are the same. Such an arrangement can reduce the difficulty of preparation and improve production efficiency.

[0075] Based on the same inventive concept, an embodiment of the present invention further provides a method for preparing an epitaxial structure of a semiconductor device, which is used to prepare the epitaxial structure provided by any of the above embodiments. Figure 5 This is a flow chart of a method for preparing an epitaxial structure of a semiconductor device provided by an embodiment of the present invention. Figure 5 , the preparation method comprises the following steps:

[0076] S101, providing a substrate;

[0077] S102. Prepare a semiconductor layer on one side of the substrate; the semiconductor layer includes at least a buffer layer arranged on one side of the substrate; along the direction from the source preset region to the drain preset region, the buffer layer includes a first buffer section and a second buffer section connected to each other, the vertical projection of the first buffer section on the substrate overlaps with the vertical projection of the source preset region on the substrate, and the vertical projection of the second buffer section on the substrate overlaps with the vertical projections of the gate preset region and the drain preset region on the substrate; ions are injected into the buffer layer, and the ion injection concentration in the second buffer section is greater than the ion injection concentration in the first buffer section; the gate preset region is located between the source preset region and the drain preset region.

[0078] The preparation method provided by the embodiment of the present invention performs ion implantation on the buffer layer in different regions, and performs high-concentration ion implantation on the buffer layer between the gate preset region and the drain preset region (i.e., the second buffer region), thereby increasing the resistivity of the second buffer region. In this way, when the epitaxial structure is applied to the semiconductor device, the breakdown voltage of the semiconductor device can be increased and the leakage of the semiconductor device can be reduced. At the same time, by performing low-concentration ion implantation or no ion implantation on the buffer layer between the gate preset region and the source preset region (i.e., the first buffer region), the resistivity of the first buffer region can be maintained at a low level. In this way, when the epitaxial structure is applied to the semiconductor device, the electrostatic protection capability of the semiconductor device can be improved, so that the semiconductor device using the epitaxial structure has high breakdown voltage, low leakage and high electrostatic protection capability.

[0079] On this basis, the following is a further detailed description of the preparation method of the epitaxial structure in combination with the specific structure of the epitaxial structure. For parameters such as the materials of each film layer in the epitaxial structure and the ion implantation concentration, please refer to the above description and will not be repeated here.

[0080] like Figure 2 In the structure shown, the semiconductor layer 2 further includes a barrier layer 23, the band gap width of the barrier layer 23 is greater than the band gap width of the buffer layer 22; along the direction from the source preset region 3 to the drain preset region 5, the barrier layer 23 includes a first barrier sub-section 231 and a second barrier sub-section 232 connected to each other, the vertical projection of the first barrier sub-section 231 on the substrate 1 overlaps with the vertical projection of the source preset region 3 on the substrate 1, and the vertical projection of the second barrier sub-section 232 on the substrate 1 overlaps with the vertical projections of the gate preset region 4 and the drain preset region 5 on the substrate 1. At this time, you can refer to Figure 6 The epitaxial structure is prepared by the preparation method shown.

[0081] Figure 6 is a flow chart of another method for preparing an epitaxial structure of a semiconductor device provided by an embodiment of the present invention, see Figure 6 , the preparation method comprises the following steps:

[0082] S201: Provide a substrate.

[0083] S202 , sequentially preparing a buffer layer and a barrier layer on one side of the substrate.

[0084] S203. Ions are injected into the blocking layer and the buffer layer on the side of the blocking layer away from the substrate, the ion injection concentration in the second blocking section is greater than the ion injection concentration in the first blocking section, the ion injection concentration in the second buffer section is greater than the ion injection concentration in the first buffer section, and the ion injection concentration in the second blocking section is less than the ion injection concentration in the second buffer section.

[0085] It should be noted that this embodiment is illustrated by taking the example of completing ion implantation of the barrier layer and the buffer layer in the same process. In other embodiments, the buffer layer may be prepared first and ions may be implanted into the buffer layer, and then the barrier layer may be prepared and ions may be implanted into the barrier layer. Those skilled in the art may make their own arrangements.

[0086] The preparation method provided in this embodiment prepares a barrier layer on the side of the buffer layer away from the substrate, and ion implants are performed on different regions of the barrier layer. In this way, when the epitaxial structure is applied to a semiconductor device, the semiconductor device can have a high breakdown voltage, low leakage current, and high electrostatic protection capability while avoiding affecting the electron mobility in the two-dimensional electron gas.

[0087] like Figure 3 In the structure shown, the semiconductor layer 2 further includes a nucleation layer 21; along the direction from the source preset region 3 to the drain preset region 5, the nucleation layer 21 includes a first nucleation sub-section 211 and a second nucleation sub-section 212 connected to each other, the first nucleation sub-section 211 is located between the first buffer sub-section 221 and the substrate 1, and the second nucleation sub-section 212 is located between the second buffer sub-section 222 and the substrate 1. At this time, you can refer to Figure 7 The epitaxial structure is prepared by the preparation method shown.

[0088] Figure 7 is a flow chart of another method for preparing an epitaxial structure of a semiconductor device provided by an embodiment of the present invention, see Figure 7 , the preparation method comprises the following steps:

[0089] S301, providing a substrate;

[0090] S302, sequentially preparing a nucleation layer and a buffer layer on one side of the substrate;

[0091] S303. Ions are injected into the buffer layer and the nucleation layer on the side of the buffer layer away from the substrate, wherein the ion injection concentration in the second buffer portion is greater than the ion injection concentration in the first buffer portion, and the ion injection concentration in the second nucleation portion is greater than the ion injection concentration in the first nucleation portion.

[0092] It should be noted that the solution of this embodiment completes the ion implantation of the buffer layer and the nucleation layer in the same process. In other embodiments, the ion implantation of the buffer layer and the nucleation layer may also be completed separately, which is not limited in this embodiment of the present invention.

[0093] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device, Figure 8 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, Figure 9 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, see Figure 8 or Figure 9 The semiconductor device 100 includes the epitaxial structure 10 provided in the above embodiment; it also includes a heterojunction structure 24 located on a side of the epitaxial structure 10 away from the substrate 1, and a gate 41, a source 31 and a drain 51 located on a side of the heterojunction structure 24 away from the substrate 1, the gate 41 is arranged in a gate preset region, the source 31 is arranged in a source preset region, and the drain 51 is arranged in a drain preset region.

[0094] Among them, see Figure 8 The heterojunction structure 24 includes a channel layer 241 and a barrier layer 242 . The barrier layer 242 is located on a side of the channel layer 241 away from the epitaxial structure 10 . A two-dimensional electron gas 2DEG is formed on a side of the channel layer 241 close to the barrier layer 242 .

[0095] Optionally, the source electrode 31 and the drain electrode 51 form an ohmic contact with the heterojunction structure 24, and the gate electrode 41 forms a Schottky contact with the heterojunction structure 24. Optionally, the material of the source electrode 31 and the drain electrode 51 can be a combination of one or more metals such as Ni, Ti, Al, and Au, and the material of the gate electrode 41 can be a combination of one or more metals such as Ni, Pt, Pb, and Au.

[0096] It should be understood that the embodiments of the present invention improve the reliability of semiconductor devices from the perspective of epitaxial structure design of semiconductor devices. The semiconductor devices include but are not limited to: high-power gallium nitride high electron mobility transistors (HEMTs) operating in high voltage and high current environments, transistors with silicon-on-insulator (SOI) structures, gallium arsenide (GaAs)-based transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-semiconductor heterojunction field-effect transistors (MESFETs). Transistor, referred to as MISHFET) or other field effect transistors.

[0097] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. An epitaxial structure of a semiconductor device, characterized in that: include: substrate; a semiconductor layer located on one side of the substrate; the semiconductor layer at least includes a buffer layer provided on one side of the substrate; Along a direction from the source preset region to the drain preset region, the buffer layer includes a first buffer subsection and a second buffer subsection connected to each other, a vertical projection of the first buffer subsection on the substrate overlapping with a vertical projection of the source preset region on the substrate, and a vertical projection of the second buffer subsection on the substrate overlapping with a vertical projection of the gate preset region and a vertical projection of the drain preset region on the substrate; ions are implanted into the buffer layer, and the ion implantation concentration in the second buffer subsection is greater than the ion implantation concentration in the first buffer subsection; the gate preset region is located between the source preset region and the drain preset region; The semiconductor layer further includes a barrier layer, the barrier layer being located on a side of the buffer layer away from the substrate, and the band gap of the barrier layer being greater than the band gap of the buffer layer; Along the direction from the preset source region to the preset drain region, the blocking layer includes a first blocking sub-section and a second blocking sub-section connected to each other, a vertical projection of the first blocking sub-section on the substrate overlaps with a vertical projection of the preset source region on the substrate, and a vertical projection of the second blocking sub-section on the substrate overlaps with a vertical projection of the preset gate region and a vertical projection of the preset drain region on the substrate; The ions are implanted into the barrier layer, the ion implantation concentration in the second barrier sub-section is greater than the ion implantation concentration in the first barrier sub-section; and the ion implantation concentration in the second barrier sub-section is less than the ion implantation concentration in the second buffer sub-section; The ion implantation concentration C1 in the first buffer sub-section satisfies C1=0; the resistivity ρ1 of the first buffer sub-section satisfies 0.1Ω·cm≤ρ1≤100Ω·cm; The ion implantation concentration C2 in the second buffer section satisfies 1×10 17 cm -3 ≤C2≤5×10 18 cm -3 The resistivity of the second buffer section ρ2 satisfies 10 5 Ω·cm≤ρ2≤10 10 Ω·cm.

2. The epitaxial structure according to claim 1, wherein: The ion implantation concentration C3 in the first barrier sub-section satisfies C3=0; the resistivity ρ3 of the first barrier sub-section satisfies 0.1Ω·cm≤ρ3≤100Ω·cm; The ion implantation concentration C4 in the second blocking section satisfies 1×10 15 cm -3 ≤C4≤5×10 16 cm -3 The resistivity of the second blocking section ρ4 satisfies 10 5 Ω·cm≤ρ4≤10 10 Ω·cm.

3. The epitaxial structure according to claim 1, wherein: The semiconductor layer further includes a nucleation layer, wherein the nucleation layer is located between the substrate and the buffer layer; Along the direction from the predetermined source region to the predetermined drain region, the nucleation layer includes a first nucleation sub-section and a second nucleation sub-section connected to each other, the first nucleation sub-section is located between the first buffer sub-section and the substrate, and the second nucleation sub-section is located between the second buffer sub-section and the substrate; The ions are implanted into the nucleation layer, and the ion implantation concentration in the second nucleation subsection is greater than the ion implantation concentration in the first nucleation subsection.

4. The epitaxial structure according to claim 1, wherein: The ions include at least one of boron ions, arsenic ions, helium ions, beryllium ions, magnesium ions, argon ions, aluminum ions, phosphorus ions, nitrogen ions, oxygen ions, carbon ions, and iron ions.

5. A method for preparing an epitaxial structure of a semiconductor device, for preparing the epitaxial structure according to any one of claims 1 to 4, characterized in that: include: providing a substrate; A semiconductor layer is prepared on one side of the substrate; the semiconductor layer at least includes a buffer layer arranged on one side of the substrate in a direction pointing from the source preset region to the drain preset region, the buffer layer includes a first buffer section and a second buffer section connected to each other, the vertical projection of the first buffer section on the substrate overlaps with the vertical projection of the source preset region on the substrate, and the vertical projection of the second buffer section on the substrate overlaps with the vertical projections of the gate preset region and the drain preset region on the substrate; ions are injected into the buffer layer, and the ion injection concentration in the second buffer section is greater than the ion injection concentration in the first buffer section; the gate preset region is located between the source preset region and the drain preset region.

6. The preparation method according to claim 5, characterized in that The semiconductor layer further includes a barrier layer, wherein the band gap width of the barrier layer is greater than the band gap width of the buffer layer; along the direction from the source preset region to the drain preset region, the barrier layer includes a first barrier sub-section and a second barrier sub-section connected to each other, wherein a vertical projection of the first barrier sub-section on the substrate overlaps with a vertical projection of the source preset region on the substrate, and a vertical projection of the second barrier sub-section on the substrate overlaps with a vertical projection of the gate preset region and a vertical projection of the drain preset region on the substrate; The method comprises preparing a semiconductor layer on one side of the substrate, comprising: Sequentially preparing the buffer layer and the barrier layer on one side of the substrate; The ions are injected into the barrier layer and the buffer layer on a side of the barrier layer away from the substrate, the ion injection concentration in the second barrier section is greater than the ion injection concentration in the first barrier section, and the ion injection concentration in the second barrier section is less than the ion injection concentration in the second buffer section.

7. The preparation method according to claim 5, characterized in that The semiconductor layer further includes a nucleation layer; along a direction from the source predetermined region to the drain predetermined region, the nucleation layer includes a first nucleation sub-section and a second nucleation sub-section connected to each other, the first nucleation sub-section being located between the first buffer sub-section and the substrate, and the second nucleation sub-section being located between the second buffer sub-section and the substrate; The method comprises preparing a semiconductor layer on one side of the substrate, comprising: Sequentially preparing the nucleation layer and the buffer layer on one side of the substrate; The ions are implanted into the buffer layer and the nucleation layer at a side of the buffer layer away from the substrate, and the ion implantation concentration in the second nucleation portion is greater than the ion implantation concentration in the first nucleation portion.

8. A semiconductor device, characterized in that: comprising the epitaxial structure according to any one of claims 1 to 4; The semiconductor device also includes a heterojunction structure located on a side of the epitaxial structure away from the substrate, and a gate, a source and a drain located on a side of the heterojunction structure away from the substrate, the gate being arranged in the gate preset region, the source being arranged in the source preset region, and the drain being arranged in the drain preset region.

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