High voltage semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a high-voltage semiconductor device and a method for manufacturing the same, wherein the high-voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a portion of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate and includes a first portion and a second portion. The second portion is disposed on two horizontally opposite sides of the first portion, and the thickness of the first portion is greater than that of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a high-voltage semiconductor device and a manufacturing method thereof. Background Art

[0002] Among power devices with high-voltage handling capabilities, double-diffused MOS (DMOS) transistors continue to gain attention. Common DMOS transistors include vertical double-diffused MOS (VDMOS) and lateral double-diffused MOS (LDMOS) transistors. LDMOS transistors, due to their high operating bandwidth and efficiency, as well as their planar structure that allows for easy integration with other integrated circuits, are now widely used in high-voltage operating environments, such as CPU power supplies, power management systems, DC / AC converters, and high-power or high-frequency power amplifiers. The main feature of LDMOS transistors is that they utilize a large, low-doping lateral diffusion drift region to mitigate the high voltage between the source and drain terminals, thereby enabling LDMOS transistors to achieve a higher breakdown voltage. However, as the requirements for related products become increasingly stringent, how to improve the electrical performance, withstand voltage capability and / or reliability of high-voltage semiconductor devices through design adjustments in structure and / or manufacturing process remains a direction for continuous efforts by researchers in related fields. Summary of the Invention

[0003] The present invention provides a high-voltage semiconductor device and a method for manufacturing the same, which utilizes a gate oxide layer having portions of different thicknesses to improve the reliability of the high-voltage semiconductor device while simultaneously enhancing the electrical performance of the high-voltage semiconductor device with a relatively thick gate oxide layer.

[0004] One embodiment of the present invention provides a high-voltage semiconductor device comprising a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a portion of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate and includes a first portion and a second portion. The second portion is disposed on opposite sides of the first portion in a horizontal direction, and the first portion has a greater thickness than the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

[0005] One embodiment of the present invention provides a method for manufacturing a high-voltage semiconductor device, comprising the following steps: providing a semiconductor substrate; forming an isolation structure, wherein at least a portion of the isolation structure is formed in the semiconductor substrate and surrounds a channel region in the semiconductor substrate; forming a gate oxide layer on the semiconductor substrate, wherein the gate oxide layer includes a first portion and a second portion; the second portion is disposed on two opposite sides of the first portion in a horizontal direction, and the thickness of the first portion is greater than that of the second portion; and forming a gate structure on the gate oxide layer and the isolation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of a high-voltage semiconductor device according to a first embodiment of the present invention;

[0007] Figures 2 to 6 Schematic diagram of a method for manufacturing a high-voltage semiconductor device according to a first embodiment of the present invention, wherein

[0008] Figure 3 for Figure 2 Schematic diagram of the situation afterwards;

[0009] Figure 4 for Figure 3 Schematic diagram of the situation afterwards;

[0010] Figure 5 for Figure 4 Schematic diagram of the situation afterwards;

[0011] Figure 6 for Figure 5 Schematic diagram of the situation afterwards.

[0012] Figure 7 and Figure 8 Schematic diagram of a method for manufacturing a high-voltage semiconductor device according to a second embodiment of the present invention, wherein Figure 8 for Figure 7 Schematic diagram of the situation afterwards;

[0013] Figure 9 and Figure 10 Schematic diagram of a method for manufacturing a high-voltage semiconductor device according to a third embodiment of the present invention, wherein Figure 10 for Figure 9 Schematic diagram of the situation afterwards.

[0014] Description of main component symbols

[0015] 10 Semiconductor substrate

[0016] 10BS bottom surface

[0017] 10TS top surface

[0018] 12-well region

[0019] 14 Isolation Structure

[0020] 14BS bottom surface

[0021] 14TS top surface

[0022] 16 Drift Zone

[0023] 16BS bottom surface

[0024] 16TS top surface

[0025] 20 Gate oxide layer

[0026] 20A Part 1

[0027] 20B Part 2

[0028] 30 Gate structure

[0029] 32 spacer

[0030] 34 Source / drain region

[0031] 42 first patterned mask layer

[0032] 44 second patterned mask layer

[0033] 46 third patterned mask layer

[0034] 91 First doping process

[0035] 92 Second doping process

[0036] 93 Oxidation Production Process

[0037] 94 Third doping process

[0038] 101 High-voltage semiconductor devices

[0039] 102 High-voltage semiconductor devices

[0040] BS1 bottom surface

[0041] BS2 bottom surface

[0042] CH channel area

[0043] D1 First direction

[0044] D2 Second direction

[0045] D3 third direction

[0046] R1 first processed area

[0047] R2 Second processed area

[0048] S interface

[0049] TK1 thickness

[0050] TK1' thickness

[0051] TK2 thickness

[0052] TK2' thickness

[0053] TS1 top surface

[0054] TS2 top surface DETAILED DESCRIPTION

[0055] The following detailed description of the present invention discloses sufficient details to enable those skilled in the art to practice the present invention. The embodiments set forth below are to be considered illustrative rather than restrictive. It will be apparent to those skilled in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present invention.

[0056] Before further describing each embodiment, specific terms used throughout the document are explained below.

[0057] The terms “on,” “over,” and “over” should be interpreted in the broadest sense, so that “on” means not only “directly on” something, but also includes being on something with other intervening features or layers, and “over” or “over” means not only being “over” or “above” something, but also includes being “over” or “above” something with no other intervening features or layers (i.e., directly on something).

[0058] The ordinal numbers used in the specification and claims, such as "first" and "second", are used to modify claim elements. Unless otherwise specified, they do not imply or represent any previous ordinal number of the claimed element, nor do they represent the order of one claimed element and another claimed element, or the order in the manufacturing method. The use of these ordinal numbers is only used to clearly distinguish one claimed element with a certain name from another claimed element with the same name.

[0059] The term "etching" is generally used herein to describe a process for patterning a material so that at least a portion of the material remains after the etching is complete. When "etching" a material, at least a portion of the material may remain after the etching is complete. In contrast, when "removing" a material, substantially all of the material may be removed during the process. However, in some embodiments, "removing" may be considered a broad term to include etching.

[0060] The terms "forming" or "disposing" are used hereinafter to describe the act of applying a layer of material to a substrate. These terms are intended to describe any feasible layer formation technique, including but not limited to thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, etc.

[0061] See also Figure 1 . Figure 1 The diagram shows a schematic diagram of a high voltage semiconductor device according to a first embodiment of the present invention. Figure 1 As shown, the high-voltage semiconductor device 101 includes a semiconductor substrate 10, an isolation structure 14, a gate oxide layer 20, and a gate structure 30. The semiconductor substrate 10 includes a channel region CH, and at least a portion of the isolation structure 14 is disposed in the semiconductor substrate 10 and surrounds the channel region CH. The gate oxide layer 20 is disposed on the semiconductor substrate 10, and the gate oxide layer 20 includes a first portion 20A and a second portion 20B. The second portion 20B is disposed on the first portion 20A in a horizontal direction (e.g., Figure 1 The gate structure 30 is disposed on the gate oxide layer 20 and the isolation structure 14. The gate structure 30 is disposed on two opposite sides of the first portion 20A in the first direction D1 (shown in FIG), and the thickness TK1 of the first portion 20A is greater than the thickness TK2 of the second portion 20B. In the high-voltage semiconductor device 101, the relatively thick first portion 20A of the gate oxide layer 20 can be used to improve the reliability of the high-voltage semiconductor device 101, while the relatively thin second portions 20B located on two opposite sides of the first portion 20A in the first direction D1 can be used to improve the electrical performance of the high-voltage semiconductor device 101, but the present invention is not limited thereto.

[0062] To further illustrate, in some embodiments, the semiconductor substrate 10 may include a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator (SOI) substrate, or a substrate formed of other suitable semiconductor materials. The isolation structure 14 may include a single layer or multiple layers of insulating material such as an oxide insulating material (e.g., silicon oxide) or other suitable insulating material, and the isolation structure 14 may be considered as a shallow trench isolation (STI) structure, but is not limited thereto. In addition, in Figure 1The two portions marked 14 may be different portions of the isolation structure 14 and may be connected to or separated from each other. In other words, at least a portion of the isolation structure 14 may be disposed on two opposite sides of the gate oxide layer 20 in the first direction D1, but the present invention is not limited thereto. The gate oxide layer 20 may be sandwiched between different portions of the isolation structure 14 in the first direction D1. Therefore, the second portion 20B of the gate oxide layer 20 may be located between the first portion 20A of the gate oxide layer 20 and the isolation structure 14 in the first direction D1. One end of the second portion 20B of the gate oxide layer 20 in the first direction D1 may be directly connected to the first portion 20A, and the other end of the second portion 20B of the gate oxide layer 20 in the first direction D1 may be directly connected to the isolation structure 14, but the present invention is not limited thereto.

[0063] In some embodiments, a second direction D2 perpendicular to the first direction D1 can be considered as a thickness direction of the semiconductor substrate 10, and the semiconductor substrate 10 can have an upper surface 10TS and a bottom surface 10BS opposite to each other in the second direction D2, and the gate oxide layer 20 and the gate structure 30 can be disposed on one side of the upper surface 10TS, but the present invention is not limited thereto. A horizontal direction substantially perpendicular to the second direction D2 (e.g., Figure 1 The first direction D1 and the third direction D3 shown in the figure may be substantially parallel to the top surface 10TS and / or the bottom surface 10BS of the semiconductor substrate 10, but are not limited thereto. Furthermore, as described herein, the distance between a relatively higher position or / and component in the vertical direction (e.g., the second direction D2) and the bottom surface 10BS of the semiconductor substrate 10 in the second direction D2 is greater than the distance between a relatively lower position or / and component in the second direction D2 and the bottom surface 10BS of the semiconductor substrate 10 in the second direction D2. The lower portion or bottom of each component may be closer to the bottom surface 10BS of the semiconductor substrate 10 in the second direction D2 than the upper portion or top of the component. A component above a component may be considered to be relatively farther from the bottom surface 10BS of the semiconductor substrate 10 in the second direction D2, while a component below a component may be considered to be relatively closer to the bottom surface 10BS of the semiconductor substrate 10 in the second direction D2.

[0064] In some embodiments, the high-voltage semiconductor device 101 may further include two drift regions 16 disposed in the semiconductor substrate 10 and located on opposite sides of the channel region CH in the first direction D1. At least a portion of the isolation structure 14 may be disposed in the two drift regions 16, but the present invention is not limited thereto. Furthermore, the second portion 20B of the gate oxide layer 20 may be disposed on the two drift regions 16 in the second direction D2, while the first portion 20A of the gate oxide layer 20 may be disposed partially on the channel region CH and partially on the two drift regions 16 in the second direction D2, but the present invention is not limited thereto. In some embodiments, the length of the first portion 20A of the gate oxide layer 20 in the first direction D1 may be greater than the minimum length of the channel region CH in the first direction D1 and the shortest distance between the two drift regions 16 in the first direction D1. Therefore, opposite ends of the first portion 20A of the gate oxide layer 20 in the first direction D1 may be disposed on the two drift regions 16, but the present invention is not limited thereto. In some embodiments, the drift region 16 may include a doped region formed by performing a doping process (such as an implantation process) on the semiconductor substrate 10. The semiconductor substrate 10 may have a first conductivity type or include a region of the first conductivity type (such as Figure 1 The well region 12 shown in FIG. 1 is a semiconductor substrate 10, but is not limited thereto), and the drift region 16 may have a second conductivity type that is complementary to the first conductivity type. For example, in this embodiment, the first conductivity type may be p-type and the second conductivity type may be n-type, but is not limited thereto. In other words, the semiconductor substrate 10 may be a p-type semiconductor substrate or a semiconductor substrate having a p-type well (e.g., the well region 12), and the drift region 16 may be an n-type doped region, but is not limited thereto.

[0065] In some embodiments, gate oxide layer 20 may comprise silicon oxide or other suitable oxide dielectric materials. First portion 20A and second portion 20B of gate oxide layer 20 may have the same material composition and be directly connected, but this is not limiting. In some embodiments, first portion 20A and second portion 20B of gate oxide layer 20 may be formed using different oxide dielectric materials, depending on design requirements. Furthermore, thickness TK1 of first portion 20A of gate oxide layer 20 may be considered the length of first portion 20A in second direction D2, while thickness TK2 of second portion 20B of gate oxide layer 20 may be considered the length of second portion 20B in second direction D2. In some embodiments, the first portion 20A may have a relative upper surface TS1 and a bottom surface BS1 in the second direction D2, and the second portion 20B may have a relative upper surface TS2 and a bottom surface BS2 in the second direction D2. The bottom surface BS1 of the first portion 20A may be lower than the bottom surface BS2 of the second portion 20B in the second direction D2, and the upper surface TS1 of the first portion 20A may be higher than the upper surface TS2 of the second portion 20B in the second direction D2, but this is not limited to.

[0066] In some embodiments, the high-voltage semiconductor device 101 may further include a spacer 32 and two source / drain regions 34. The spacer 32 may be disposed on the sidewalls of the gate structure 30 and on the isolation structure 14 in the second direction D2. The two source / drain regions 34 may be disposed in the two drift regions 16, respectively, and located on opposite sides of the high-voltage semiconductor device 101. The spacer 32 may comprise a single layer or multiple layers of dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials. The source / drain regions 34 may comprise doped regions formed in the semiconductor substrate 10 using a doping process (e.g., an implantation process). In some embodiments, the conductivity type of the source / drain regions 34 may be the same as that of the drift region 16, but the doping concentration of the source / drain regions 34 may be higher than that of the drift region 16. For example, the source / drain regions 34 may be heavily n-type doped regions, but this is not limited thereto.

[0067] In addition, the gate structure 30 may include a gate dielectric layer (not shown) and a gate material layer (not shown) disposed on the gate dielectric layer. The gate dielectric layer may include a high-k dielectric material or other suitable dielectric material, and the gate material layer may include a non-metallic conductive material (such as doped polysilicon) or a metallic conductive material, such as a metal gate structure formed by stacking a work function layer and a low resistance layer, but is not limited thereto. The high-k dielectric material may include hafnium oxide (HfO X), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), or other suitable high-k materials. The work function layer may include titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium tri-aluminide (TiAl3), aluminum titanium nitride (TiAlN), or other suitable conductive work function materials, while the low-resistance layer may include, for example, tungsten, aluminum, copper, titanium aluminide, titanium, or other suitable low-resistance materials.

[0068] In some embodiments, the gate structure 30 may cover the first portion 20A and the second portion 20B of the gate oxide layer 20 in the second direction D2, and the gate structure 30 may cover a portion of the isolation structure 14 located on two opposite sides of the gate oxide layer 20 in the first direction D1 in the second direction D2. Therefore, the gate structure 30 may overlap with an interface S between the isolation structure 14 and the second portion 20B of the gate oxide layer 20 in the second direction D2. Furthermore, in the high-voltage semiconductor device 101, the bottom surface 14BS of the isolation structure 14 may be lower than the bottom surface BS1 of the first portion 20A and the bottom surface BS2 of the second portion 20B of the gate oxide layer 20 in the second direction D2, and the bottom surface 16BS of the drift region 16 may be lower than the bottom surface 14BS of the isolation structure 14 in the second direction D2. Therefore, the isolation structure 14 at least partially disposed in the drift region 16 can be used to adjust the current path in the drift region 16, thereby further improving the voltage withstand capability of the high-voltage semiconductor device 101. The high-voltage semiconductor device 101 having the drift region 16 and the isolation structure 14 can be regarded as a field drift metal oxide semiconductor (FDMOS) transistor, but is not limited thereto.

[0069] Generally speaking, a relatively thick gate oxide layer of a single thickness can improve the reliability of a high-voltage semiconductor device, but it can also negatively impact the device's electrical performance. However, in the present invention, the gate oxide layer 20 has a first portion 20A and a second portion 20B of different thicknesses. The relatively thick first portion 20A can improve the reliability of the high-voltage semiconductor device 101, for example, by improving negative-bias temperature instability (NBTI) of the high-voltage semiconductor device 101, but the invention is not limited thereto. Furthermore, the relatively thin second portion 20B, located above the drift region 16, can reduce the resistance at the end of the drift region 16, thereby improving the electrical performance of the high-voltage semiconductor device 101. For example, since the second portion 20B is thinner and the bottom surface BS2 of the second portion 20B is higher than the bottom surface BS1 of the first portion 20A in the second direction D2, an additional drift region 16 for accumulating drift current can be provided below the bottom surface BS2 of the second portion 20B (for example, the drift region 16 is located between the isolation structure 14 and the first portion 20A in the first direction D1 and below the second portion 20B in the second direction D2), thereby achieving the effect of improving the electrical performance of the high-voltage semiconductor device 101.

[0070] In some embodiments, top surface 14TS of isolation structure 14 may be substantially coplanar with top surface TS2 of second portion 20B of gate oxide layer 20, thereby reducing adverse effects caused by the height difference between isolation structure 14 and second portion 20B of gate oxide layer 20 (e.g., adverse effects on gate structure 30 and / or the fabrication process used to form gate structure 30), but the present invention is not limited thereto. In some embodiments, top surface TS2 of second portion 20B of gate oxide layer 20 may be slightly higher than top surface 14TS of isolation structure 14 or slightly lower than top surface 14TS of isolation structure 14 in second direction D2. In addition, the above-mentioned top surface TS1, top surface TS2, top surface 10TS and top surface 14TS may respectively be the topmost surfaces of the first portion 20A, the second portion 20B, the semiconductor substrate 10 and the isolation structure 14 in the second direction D2, and the above-mentioned bottom surface BS1, bottom surface BS2, bottom surface 10BS, bottom surface 14BS and bottom surface 16BS may respectively be the bottommost surfaces of the first portion 20A, the second portion 20B, the semiconductor substrate 10, the isolation structure 14 and the drift region 16 in the second direction D2, but are not limited to this.

[0071] See also Figures 1 to 6 . Figures 2 to 6The diagram shows a method for manufacturing a high-voltage semiconductor device according to a first embodiment of the present invention, wherein Figure 3 Draws Figure 2 Schematic diagram of the situation afterwards, Figure 4 Draws Figure 3 Schematic diagram of the situation afterwards, Figure 5 Draws Figure 4 Schematic diagram of the situation afterwards, Figure 6 Draws Figure 5 The following diagram shows the situation: Figure 1 can be considered as depicting Figure 6 Schematic diagram of the situation afterward. Figure 1 As shown, the method for manufacturing the high-voltage semiconductor device 101 of this embodiment may include the following steps. First, a semiconductor substrate 10 is provided. An isolation structure 14 is formed, and at least a portion of the isolation structure 14 is formed in the semiconductor substrate 10 and surrounds the channel region CH in the semiconductor substrate 10. A gate oxide layer 20 is formed on the semiconductor substrate 10, and the gate oxide layer 20 includes a first portion 20A and a second portion 20B. The second portion 20B is disposed on two opposite sides of the first portion 20A in a horizontal direction (e.g., a first direction D1), and the thickness TK1 of the first portion 20A is greater than the thickness TK2 of the second portion 20B. Then, a gate structure 30 is formed on the gate oxide layer 20 and the isolation structure 14.

[0072] To further illustrate, the manufacturing method of this embodiment may include but is not limited to the following steps. Figure 2 As shown, an isolation structure 14 may be formed, and at least a portion of the isolation structure 14 may be formed in the semiconductor substrate 10 to define a channel region CH in the semiconductor substrate 10. In some embodiments, the isolation structure 14 may be formed by forming a trench in the semiconductor substrate 10 and filling the trench with a single layer or multiple layers of insulating material. The top surface 14TS of the isolation structure 14 may be slightly higher than the top surface 10TS of the semiconductor substrate 10 in the second direction D2, but the present invention is not limited thereto. Furthermore, in some embodiments, before the isolation structure 14 is formed, a doping process may be performed on the semiconductor substrate 10 to form a well region 12 in the semiconductor substrate 10. The bottom surface of the well region 12 may be lower than the bottom surface 14BS of the isolation structure 14 in the second direction D2, but the present invention is not limited thereto.

[0073] Then, if Figure 3As shown, a first doping process 91 may be performed to form the two drift regions 16 described above in the semiconductor substrate 10. In some embodiments, a first patterned mask layer 42 may be formed on the semiconductor substrate 10 before the first doping process 91. The first patterned mask layer 42 may cover a portion of the channel region CH during the first doping process 91, so that the two drift regions 16 may be partially formed in the channel region CH. Therefore, after the first doping process 91, the two drift regions 16 may be located on opposite sides of the channel region CH in the first direction D1, and at least a portion of the isolation structure 14 may be located in the two drift regions 16. In some embodiments, the first patterned mask layer 42 may include a photopatternable material such as a photoresist, an organic dielectric material, an anti-reflective material, or other suitable mask material, and the first patterned mask layer 42 may be removed after the first doping process 91, but the present invention is not limited thereto.

[0074] like Figures 3 and 4 As shown, after the first doping process 91 and before the formation of the gate oxide layer, a second doping process 92 may be performed on the channel region CH to form a first processed region R1 in the semiconductor substrate 10. The first processed region R1 may include a plurality of first impurities and is formed above the channel region CH in the second direction D2. In some embodiments, before the second doping process 92, a second patterned mask layer 44 may be formed on the semiconductor substrate 10. The second patterned mask layer 44 may cover portions outside the channel region CH (e.g., the drift region 16, the top surface 16TS of the drift region 16, and the isolation structure 14) during the second doping process 92 to prevent the second doping process 92 from negatively impacting the isolation structure 14 and / or the drift region 16. The material composition of the second patterned mask layer 44 may be similar to that of the first patterned mask layer 42, and the second patterned mask layer 44 may be removed after the second doping process 92, but the present invention is not limited thereto.

[0075] In some embodiments, the dopant used in the second doping process 92 may include at least one of carbon, germanium, fluorine, and arsenic, and the first impurity in the first processed region R1 may therefore include at least one of carbon, germanium, fluorine, and arsenic, but is not limited thereto. In some embodiments, other suitable dopants may be used in the second doping process 92 or / and the first impurity in the first processed region R1 may include other suitable elements or / and compounds depending on design requirements to adjust the oxidation rate of the first processed region R1 in the subsequent oxidation process. In some embodiments, the implantation dose used in the second doping process 92 may be between 1E+15 ion / cm 2Up to 5E+15 ion / cm 2 The implantation energy may be between 20 KeV and 50 KeV, and the depth of the first processed region R1 in the second direction D2 may be between 200 angstroms and 500 angstroms, but the present invention is not limited thereto and the process conditions of the second doping process 92 may be adjusted according to design requirements (e.g., the thickness requirement of the gate oxide layer) so that the formed first processed region R1 may have the required depth and / or first impurity concentration.

[0076] Then, if Figures 5 and 6 As shown, an oxidation process 93 may be performed to form the gate oxide layer 20 described above. In some embodiments, before the oxidation process 93, a third patterned mask layer 46 may be formed on the semiconductor substrate 10. The third patterned mask layer 46 may cover a portion of the isolation structure 14 and a portion of the drift region 16 during the oxidation process 93, thereby exposing the first processed region R1 and the drift region 16 between the first processed region R1 and the isolation structure 14 to the oxidation process 93. The material composition of the third patterned mask layer 46 may be similar to that of the first patterned mask layer described above, and the third patterned mask layer 46 may be removed after the oxidation process 93, but the present invention is not limited thereto. In some embodiments, the oxidation process 93 may include a thermal oxidation process or other suitable oxidation method to oxidize the exposed semiconductor substrate 10 (e.g., the first processed region R1 and the drift region 16 between the first processed region R1 and the isolation structure 14) to form the gate oxide layer 20.

[0077] It is worth noting that the material selection of the first impurity in the first processed region R1 enables the oxidation rate of the first processed region R1 during the oxidation process 93 to be higher than the oxidation rate of the two drift regions 16 during the oxidation process 93, thereby forming a gate oxide layer 20 having first and second portions 20A, 20B, of different thicknesses. In some embodiments, the relatively thicker first portion 20A of the gate oxide layer 20 may be primarily formed by oxidation of the first processed region R1 during the oxidation process 93. Therefore, the first portion 20A may be formed initially from the first processed region R1 and partially extend into the drift region 16, while the relatively thinner second portion 20B of the gate oxide layer 20 may be primarily formed by oxidation of the exposed drift region 16 during the oxidation process 93, but the present invention is not limited thereto. The fabrication method of this embodiment allows the formation of gate oxide layers 20 having portions of different thicknesses while reducing and / or controlling the thermal budget of the fabrication process, positively impacting the overall fabrication process of high-voltage semiconductor devices. In addition, the method for forming the gate oxide layer 20 of this embodiment is not limited to the above-mentioned conditions, and other suitable methods may be used to form the gate oxide layer 20 with different thickness portions according to design requirements. Figure 6 and Figure 1 As shown, after the gate oxide layer 20 is formed, a gate structure 30, a spacer 32 and a source / drain region 34 may be formed, thereby forming a gate structure 30, a spacer 32 and a source / drain region 34. Figure 1 The high-voltage semiconductor device 101 is shown in FIG.

[0078] The following description will focus on different embodiments of the present invention. For simplicity, the following description will focus on the differences between the embodiments and will not repeat the similarities. In addition, the same elements in the various embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the various embodiments.

[0079] See also Figure 3 、 Figure 6 、 Figure 7 as well as Figure 8 . Figure 7 and Figure 8 The diagram shows a method for manufacturing a high-voltage semiconductor device according to a second embodiment of the present invention, wherein Figure 8 Draws Figure 7 Schematic diagram of the situation afterwards, Figure 7 can be considered as depicting Figure 3 The following diagram shows the situation: Figure 6 can be considered as depicting Figure 8 Schematic diagram of the situation afterward. Figure 3 and Figure 7As shown, in some embodiments, before forming the aforementioned gate oxide layer and after the first doping process 91, the semiconductor substrate 10 may be subjected to a third doping process 94 to form a second processed region R2 in the semiconductor substrate 10. The second processed region R2 may include a plurality of second impurities that are different from the first impurities in the aforementioned embodiments. In some embodiments, the aforementioned first patterned mask layer 42 may cover the channel region CH during the third doping process 94, thereby allowing the second processed region R2 to be formed above the two drift regions 16 through the third doping process 94. In other words, the first doping process 91 and the third doping process 94 may share the same patterned mask layer, thereby simplifying the manufacturing process, but the present invention is not limited thereto. In some embodiments, a different patterned mask layer than the first patterned mask layer 42 used in the first doping process 91 may be used in the third doping process 94, depending on design requirements, to further cover areas not required for subsequent gate oxide layer formation during the third doping process 94. In addition, the first patterned mask layer 42 and / or other patterned mask layers used in the third doping process 94 may be removed after the third doping process 94 .

[0080] In some embodiments, the dopant used in the third doping process 94 may include nitrogen or other substances that can be used to reduce the oxidation rate of the semiconductor substrate 10, and the second impurity in the second processed region R2 may therefore include nitrogen or other substances that can be used to reduce the oxidation rate of the semiconductor substrate 10, but is not limited to this. In some embodiments, other suitable dopants may be used in the third doping process 94 or / and the second impurity in the second processed region R1 may include other suitable elements or / and compounds according to design requirements to adjust the oxidation rate of the second processed region R2 in the subsequent oxidation process. In some embodiments, the implantation dose used in the third doping process 94 may be between 1E+15 ion / cm 2 Up to 5E+15 ion / cm 2 The injection energy may be between 2KeV and 8KeV, and the depth of the second processed region R2 in the second direction D2 may be less than or equal to 100 angstroms, but the present invention is not limited thereto and the process conditions of the third doping process 94 may be adjusted according to design requirements so that the second processed region R2 may have the desired depth and / or second impurity concentration.

[0081] Then, if Figure 8 and Figure 6As shown, an oxidation process 93 may be performed to form the aforementioned gate oxide layer 20. In some embodiments, the third patterned mask layer 46 may cover a portion of the isolation structure 14 and a portion of the drift region 16 during the oxidation process 93, thereby exposing the second processed region R2 and the channel region CH, which are sandwiched between different portions of the isolation structure 14 in the first direction D1, to the oxidation process 93. Furthermore, by selecting the material of the second impurity in the second processed region R2, the oxidation rate of the second processed region R2 during the oxidation process 93 may be lower than the oxidation rate of the channel region CH during the oxidation process 93, thereby forming the gate oxide layer 20 having the first portion 20A and the second portion 20B having different thicknesses. In some embodiments, a relatively thick first portion 20A of the gate oxide layer 20 may be primarily formed by oxidation of the channel region CH by the oxidation process 93. The first portion 20A may be formed starting from the channel region CH and partially extending into the drift region 16. A relatively thin second portion 20B of the gate oxide layer 20 may be primarily formed by oxidation of the exposed second processed region R2 by the oxidation process 93, but the present invention is not limited thereto. The fabrication method of this embodiment can also form gate oxide layers 20 having portions of varying thickness while reducing and / or controlling the thermal budget of the fabrication process, which positively impacts the overall fabrication process of high-voltage semiconductor devices.

[0082] See also Figure 9 and Figure 10 . Figure 9 and Figure 10 FIG. 1 is a schematic diagram of a method for manufacturing a high-voltage semiconductor device 102 according to a third embodiment of the present invention, wherein Figure 10 Draws Figure 9 Schematic diagram of the situation afterward. Figure 9 and Figure 10 As shown, in some embodiments, before performing the oxidation process 93 to form the gate oxide layer 20, a first processed region R1 and a second processed region R2 may be formed in the semiconductor substrate 10, and the depth of the second processed region R2 in the second direction D2 may be less than the depth of the first processed region R1 in the second direction D2, but the present invention is not limited thereto. In some embodiments, the first processed region R1 may be formed by the above-mentioned Figure 4 The second doping process 92 shown in FIG. 1 is formed, and the second processed region R2 can be formed by the above-mentioned Figure 7 The third doping process 94 is formed, and the third doping process 94 can be performed before the second doping process 92, so that the third doping process 94 can be combined with the above-mentioned Figure 3 The first doping process 91 shown in FIG. 4 shares the first patterned mask layer 42 , thereby achieving an effect of simplifying the manufacturing process, but the present invention is not limited thereto.

[0083] In addition, the oxidation rate of the first processed region R1 in the oxidation process 93 can be higher than the oxidation rate of the second processed region R2 in the oxidation process 93, thereby forming the gate oxide layer 20 having the first portion 20A and the second portion 20B with different thicknesses, and the thickness TK1' of the first portion 20A of the gate oxide layer 20 can be further increased (for example, it can be thicker than the first portion 20A in the first embodiment) or / and the thickness TK2' of the second portion 20B of the gate oxide layer 20 can be relatively reduced. Therefore, in the high-voltage semiconductor device 102 of this embodiment, the ratio of the thickness TK1' of the first portion 20A of the gate oxide layer 20 to the thickness TK2' of the second portion 20B can be higher than the above-mentioned ratio. Figure 1 The ratio of the thickness TK1 of the first portion 20A of the gate oxide layer 20 to the thickness TK2 of the second portion 20B is shown in FIG, but the present invention is not limited thereto.

[0084] In summary, in the high-voltage semiconductor device and its fabrication method of the present invention, the gate oxide layer can have portions with different thicknesses. The relatively thicker first portion of the gate oxide layer can be used to improve the reliability of the high-voltage semiconductor device, while the relatively thinner second portion of the gate oxide layer can be used to enhance the electrical performance of the high-voltage semiconductor device. Thus, both reliability and electrical performance can be improved. Furthermore, in the fabrication method of the present invention, a doping process can be utilized to adjust the oxidation rate of different regions on the semiconductor substrate, thereby forming a gate oxide layer with portions with different thicknesses during the oxidation process.

[0085] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A high-voltage semiconductor device, characterized in that: include: a semiconductor substrate including a channel region; an isolation structure, wherein at least a portion of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region; A gate oxide layer is disposed on the semiconductor substrate, wherein the gate oxide layer comprises: Part I; and a second portion disposed on two opposite sides of the first portion in a horizontal direction, wherein a thickness of the first portion is greater than a thickness of the second portion, and the second portion is located between the first portion and the isolation structure in the horizontal direction; and The gate structure is disposed on the gate oxide layer and the isolation structure. 2 . The high-voltage semiconductor device as claimed in claim 1 , wherein a bottom surface of the first portion is lower than a bottom surface of the second portion in a vertical direction orthogonal to the horizontal direction. 3 . The high-voltage semiconductor device as claimed in claim 1 , wherein an upper surface of the first portion is higher than an upper surface of the second portion in a vertical direction perpendicular to the horizontal direction. 4 . The high-voltage semiconductor device as claimed in claim 1 , wherein at least a portion of the isolation structure is disposed on two opposite sides of the gate oxide layer in the horizontal direction. 5 . The high voltage semiconductor device as claimed in claim 4 , wherein the second portion of the gate oxide layer is directly connected to the isolation structure. 6 . The high voltage semiconductor device of claim 5 , wherein the gate structure overlaps an interface between the isolation structure and the second portion of the gate oxide layer in a vertical direction orthogonal to the horizontal direction.

7. The high-voltage semiconductor device according to claim 1 , further comprising: Two drift regions are disposed in the semiconductor substrate and are respectively located at two opposite sides of the channel region in the horizontal direction, wherein at least a portion of the isolation structure is disposed in the two drift regions. 8 . The high voltage semiconductor device as claimed in claim 7 , wherein the second portion of the gate oxide layer is disposed on the two drift regions. 9 . The high voltage semiconductor device of claim 7 , wherein the first portion of the gate oxide layer is partially disposed on the channel region and partially disposed on the two drift regions.

10. A method for manufacturing a high-voltage semiconductor device, comprising: providing a semiconductor substrate; forming an isolation structure, wherein at least a portion of the isolation structure is formed in the semiconductor substrate and surrounds a channel region in the semiconductor substrate; forming a gate oxide layer on the semiconductor substrate, wherein the gate oxide layer comprises: Part I; and a second portion disposed on two opposite sides of the first portion in a horizontal direction, wherein a thickness of the first portion is greater than a thickness of the second portion, and the second portion is located between the first portion and the isolation structure in the horizontal direction; and A gate structure is formed on the gate oxide layer and the isolation structure.

11. The method for manufacturing a high-voltage semiconductor device according to claim 10 , further comprising: A first doping process is performed to form two drift regions in the semiconductor substrate, wherein the two drift regions are respectively located at two opposite sides of the channel region in the horizontal direction, and at least a portion of the isolation structure is located in the two drift regions.

12. The method for manufacturing a high-voltage semiconductor device according to claim 11, further comprising: Before forming the gate oxide layer and after the first doping process, a second doping process is performed on the channel region, wherein a first processed region including a plurality of first impurities is formed on the channel region through the second doping process. 13 . The method for manufacturing a high-voltage semiconductor device according to claim 12 , wherein the gate oxide layer is formed by an oxidation process, and an oxidation rate of the first processed region in the oxidation process is higher than an oxidation rate of the two drift regions in the oxidation process. 14 . The method for fabricating a high-voltage semiconductor device as claimed in claim 12 , wherein the first impurities comprise carbon, germanium, fluorine, or arsenic.

15. The method for manufacturing a high-voltage semiconductor device according to claim 11, further comprising: Before forming the gate oxide layer and after the first doping process, a third doping process is performed on the semiconductor substrate, wherein a second processed region including a plurality of second impurities is formed on the two drift regions through the third doping process. 16 . The method for manufacturing a high-voltage semiconductor device according to claim 15 , wherein the gate oxide layer is formed by an oxidation process, and an oxidation rate of the second processed region in the oxidation process is lower than an oxidation rate of the channel region in the oxidation process. 17 . The method for fabricating a high-voltage semiconductor device as claimed in claim 15 , wherein the second impurities comprise nitrogen. 18 . The method for manufacturing a high-voltage semiconductor device according to claim 15 , wherein a patterned mask layer is formed on the semiconductor substrate before the first doping process, and the patterned mask layer covers the channel region in the first doping process and the third doping process. 19 . The method for manufacturing a high-voltage semiconductor device according to claim 10 , wherein a bottom surface of the first portion is lower than a bottom surface of the second portion in a vertical direction perpendicular to the horizontal direction. 20 . The method for manufacturing a high-voltage semiconductor device according to claim 10 , wherein an upper surface of the first portion is higher than an upper surface of the second portion in a vertical direction perpendicular to the horizontal direction.

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