Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a substrate having a first fin and a second fin; a plurality of first gate structures located on the substrate, the first gate structures having a first sidewall structure on their sidewalls, the first sidewall structure having a second dimension; and a plurality of second gate structures located on the substrate, the second gate structures having a second sidewall structure on their sidewalls, the second sidewall structure having a fourth dimension, the fourth dimension being smaller than the second dimension. By increasing the second dimension of the first sidewall structure to cover the first fin, the size of the first source / drain opening formed is reduced. When the source / drain doping layer within the second source / drain opening is fully filled, the source / drain doping layer formed within the first source / drain opening can fill more space, thereby reducing the depression in the middle of the source / drain doping layer within the first source / drain opening, reducing the risk of the conductive layer penetrating the middle portion of the source / drain doping layer, and thereby improving the performance of the semiconductor structure ultimately formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As semiconductor device integration increases, the critical dimensions of transistors continue to shrink. This reduction in critical dimensions allows for more transistors to be placed on a chip, thereby improving device performance. However, as device area continues to shrink, problems arise. With the rapid reduction in transistor size, the gate dielectric thickness and operating voltage cannot be adjusted accordingly, making it more difficult to suppress short-channel effects, resulting in increased channel leakage current in transistors.

[0003] As MOS transistors shrink, the gate becomes shorter, shortening the current channel beneath the gate. When the MOS transistor channel shortens to a certain extent, the short channel effect occurs. Theoretically, the channel length is the distance from the source extension to the drain extension. However, the effective channel length varies due to the influence of the junction voids formed by the source and drain electrodes and the substrate. When the channel length is equal to or shorter than the depth of the junction voids, the junction voids significantly cut into the current channel, causing a decrease in the gate threshold voltage. This is the short channel effect.

[0004] To reduce the short channel effect of semiconductor devices, the prior art generally increases the first width of the gate structure along the fin extension direction. However, increasing the first width of the gate structure also creates other problems, resulting in reduced performance of the resulting semiconductor structure.

[0005] Therefore, the performance of the semiconductor structure formed in the prior art still needs to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0007] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a second region, the first region having a plurality of mutually separate first fins, the second region having a plurality of mutually separate second fins, the first fins and the second fins respectively extending along a first direction; a plurality of first gate structures located on the first region, the first gate structures spanning the first fins, and adjacent first gate structures having a first dimension along the first direction, the sidewalls of the first gate structures having a first spacer structure, the first spacer structure having a second dimension along the first direction; a plurality of second gate structures located on the second region, the second gate structures spanning the second fins, and adjacent first gate structures having a first dimension along the first direction. The second gate structures have a third size along the first direction, and the third size is smaller than the first size. The second gate structure has a second sidewall structure on the sidewall, and the second sidewall structure has a fourth size along the first direction, and the fourth size is smaller than the second size; first source and drain openings in the first fin on both sides of the first gate structure; second source and drain openings in the second fin on both sides of the second gate structure; source and drain doping layers in the first source and drain openings and the second source and drain openings, the top surface of the source and drain doping layer in the first source and drain openings is lower than the top surface of the first fin, and the top surface of the source and drain doping layer in the second source and drain openings is flush with the top surface of the second fin.

[0008] Optionally, it further includes: a conductive layer located on the source-drain doped layer.

[0009] Optionally, the material of the conductive layer includes metal, and the metal includes tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

[0010] Optionally, the first spacer structure includes: a first spacer located on a sidewall of the first gate structure, and a second spacer located on a sidewall of the first spacer.

[0011] Optionally, the second spacer structure includes: a third spacer located on a sidewall of the second gate structure.

[0012] Optionally, the first gate structure has a first width dimension along the first direction, the second gate structure has a second width dimension along the first direction, and the first width dimension is greater than the second width dimension.

[0013] Optionally, the material of the source / drain doping layer includes: SiP, SiCP, SiGe or SiGeB.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a first region and a second region, the first region having a plurality of mutually separate first fins, the second region having a plurality of mutually separate second fins, the first fins and the second fins respectively extending along a first direction; forming a plurality of first gate structures on the first region, the first gate structures spanning the first fins, and adjacent first gate structures having a first size along the first direction, the sidewalls of the first gate structures having a first sidewall structure, the first sidewall structure having a second size along the first direction; forming a plurality of second gate structures on the second region, the second gate structures spanning the second fins, and adjacent second gate structures having a first size. The second gate structure has a third size along the first direction, and the third size is smaller than the first size. A second sidewall structure is provided on the sidewall of the second gate structure, and the second sidewall structure has a fourth size along the first direction, and the fourth size is smaller than the second size. First source and drain openings are formed in the first fins on both sides of the first gate structure; second source and drain openings are formed in the second fins on both sides of the second gate structure; source and drain doping layers are simultaneously formed in the first source and drain openings and the second source and drain openings until the source and drain doping layers fill the second source and drain openings, and the top surface of the source and drain doping layer located in the first source and drain openings is lower than the top surface of the first fin, and the top surface of the source and drain doping layer located in the second source and drain openings is flush with the top surface of the second fin.

[0015] Optionally, after forming the source-drain doped layer, the method further includes: forming a conductive layer on the source-drain doped layer.

[0016] Optionally, the material of the conductive layer includes metal, and the metal includes tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

[0017] Optionally, the first spacer structure includes: a first spacer located on a sidewall of the first gate structure, and a second spacer located on a sidewall of the first spacer.

[0018] Optionally, the second spacer structure includes: a third spacer located on a sidewall of the second gate structure.

[0019] Optionally, before forming the first gate structure and the second gate structure, it also includes: forming a first dummy gate structure on the first region, the first dummy gate structure spanning the first fin; forming a second dummy gate structure on the second region, the second dummy gate structure spanning the second fin.

[0020] Optionally, the method for forming the first side wall includes: forming a first side wall material layer on the side walls and top surfaces of the first dummy gate structure and the second dummy gate structure, and on the substrate; etching back the first side wall material layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed to form an initial first side wall; removing the initial first side wall located on the side wall of the second dummy gate structure, and forming the first side wall on the side wall of the first dummy gate structure.

[0021] Optionally, the process for forming the first spacer material layer includes an atomic layer deposition process.

[0022] Optionally, the method for forming the second side wall and the third side wall includes: forming a second side wall material layer on the side walls of the first side wall and the second dummy gate structure, the top surfaces of the first dummy gate structure and the second dummy gate structure, and the substrate; etching back the second side wall material layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed, forming the second side wall on the side wall of the first side wall, and forming the third side wall on the side wall of the second dummy gate structure.

[0023] Optionally, the formation process of the second spacer material layer includes an atomic layer deposition process.

[0024] Optionally, the method for forming the first gate structure and the second gate structure includes: forming a dielectric layer on the substrate, the dielectric layer covering the side walls of the first dummy gate structure and the second dummy gate structure; removing the first dummy gate structure to form a first gate opening in the dielectric layer; removing the second dummy gate structure to form a second gate opening in the dielectric layer; forming the first gate structure in the first gate opening; and forming the second gate structure in the second gate opening.

[0025] Optionally, the first gate structure has a first width dimension along the first direction, the second gate structure has a second width dimension along the first direction, and the first width dimension is greater than the second width dimension.

[0026] Optionally, the method for forming the source-drain doped layer includes: using an epitaxial growth process to simultaneously form an epitaxial layer in the first source-drain opening and the second source-drain opening until the epitaxial layer fills the second source-drain opening; in-situ doping the epitaxial layer during the epitaxial growth process, and doping the source-drain ions into the epitaxial layer to form the source-drain doped layer.

[0027] Optionally, the material of the source / drain doping layer includes: SiP, SiCP, SiGe or SiGeB.

[0028] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0029] In the structure of the technical solution of the present invention, a first gate structure located on the first region has a first spacer structure on its sidewalls, the first spacer structure having a second dimension along the first direction; a second gate structure located on the second region has a second spacer structure on its sidewalls, the second spacer structure having a fourth dimension along the first direction, the fourth dimension being smaller than the second dimension. By increasing the second dimension of the first spacer structure along the first direction, the first fin is further covered, the exposed dimension of the first fin along the first direction is reduced, and the dimension of the first source / drain opening formed along the first direction is reduced. When the dimension of the first source / drain opening along the first direction is reduced, when the source / drain doping layer within the second source / drain opening is fully filled, the source / drain doping layer formed within the first source / drain opening can fill more space, thereby reducing the concavity of the source / drain doping layer in the middle of the first source / drain opening. This reduces the risk of a subsequently formed conductive layer penetrating the middle portion of the source / drain doping layer, improves the contact between the conductive layer and the source / drain doping layer within the first source / drain opening, and thereby improves the performance of the resulting semiconductor structure.

[0030] In the formation method of the technical solution of the present invention, a first gate structure is formed on the first region, with a first spacer structure on its sidewalls, the first spacer structure having a second dimension along the first direction; and a second gate structure is formed on the second region, with a second spacer structure on its sidewalls, the second spacer structure having a fourth dimension along the first direction, the fourth dimension being smaller than the second dimension. By increasing the second dimension of the first spacer structure along the first direction, the first fin is further covered, the exposed dimension of the first fin along the first direction is reduced, and the dimension of the first source / drain opening formed along the first direction is reduced. When the dimension of the first source / drain opening along the first direction is reduced, when the source / drain doping layer within the second source / drain opening is fully filled, the source / drain doping layer formed within the first source / drain opening can fill more space, reducing the concavity of the source / drain doping layer in the middle of the first source / drain opening. This reduces the risk of a subsequently formed conductive layer penetrating the middle portion of the source / drain doping layer, improves the contact between the conductive layer and the source / drain doping layer within the first source / drain opening, and thereby improves the performance of the resulting semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a structural diagram of a semiconductor structure;

[0032] Figures 2 to 13 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the performance of the semiconductor structure formed in the prior art still needs to be improved, which will be described in detail below with reference to the accompanying drawings.

[0034] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 has a plurality of mutually discrete fins 101, wherein the fins extend along a first direction X; forming an isolation layer 102 on the substrate 100, wherein the isolation layer 102 covers a portion of the sidewall surface of the fin 101, and the top surface of the isolation layer 102 is lower than the top surface of the fin 101; forming a dummy gate structure 103 on the substrate 100, wherein the dummy gate structure 103 spans the fin 101 and covers a portion of the sidewall and top surface of the fin 101; forming source and drain openings (not marked) in the fin 101 on both sides of the dummy gate structure 103; forming a source and drain doping layer 104 in the source and drain openings, wherein the source and drain doping layer 104 has source and drain ions; and forming a conductive layer 105 on the source and drain doping layer 104.

[0035] In this embodiment, the first width dimension d1 of the dummy gate structure 103 is increased in the first direction X, and the first width dimension d1 is greater than 50 nm, thereby increasing the length of the channel and reducing the influence of the channel effect.

[0036] However, when the first width d1 of the dummy gate structure 103 increases, the increased size of the fin 101 along the first direction X also increases, thereby increasing the second width d2 of the fin 101 exposed on both sides of the dummy gate structure 103. When the second width d2 of the exposed fin 101 increases, the size of the subsequently formed source and drain openings along the first direction X also increases. Because the source and drain doped layers 104 are formed by epitaxial growth on the fin 101 exposed on the surface of the source and drain openings, when the size of the source and drain openings along the first direction X is large, the volume of the source and drain doped layers 104 grown in the second direction Y is small. The second direction Y is perpendicular to the first direction X, resulting in a recess in the center of the source and drain doped layers 104.

[0037] When a depression appears in the middle of the source / drain doped layer 104, the source / drain doped layer 104 is easily etched through during the formation of the conductive layer 105, thereby causing the bottom surface of the conductive layer 105 finally formed to contact the fin 101, thereby increasing the contact resistance between the conductive layer 105 and the source / drain doped layer 104, and thereby reducing the performance of the finally formed semiconductor structure.

[0038] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein the first sidewall structure has a second dimension along the first direction; the second sidewall structure has a fourth dimension along the first direction, and the fourth dimension is smaller than the second dimension. By increasing the second dimension of the first sidewall structure along the first direction, the dimension of the first source / drain opening formed along the first direction is reduced. When the source / drain doping layer in the second source / drain opening is filled, the source / drain doping layer formed in the first source / drain opening can fill more space, reducing the depression in the middle of the source / drain doping layer in the first source / drain opening, thereby reducing the risk of the subsequently formed conductive layer penetrating the middle portion of the source / drain doping layer, thereby improving the contact between the conductive layer and the source / drain doping layer in the first source / drain opening, and thereby improving the performance of the semiconductor structure finally formed.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 2 to 13 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0041] Please refer to Figure 2 A substrate 200 is provided, wherein the substrate 200 includes a first region I and a second region II, wherein the first region I has a plurality of mutually separate first fins 201, and the second region II has a plurality of mutually separate second fins 202, and the first fins 201 and the second fins 202 extend along a first direction X respectively.

[0042] In this embodiment, the method for forming the substrate 200, the first fin 201 and the second fin 202 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, the patterned layer exposing a portion of the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate 200, the first fin 201 and the second fin 202; after forming the substrate 200, the first fin 201 and the second fin 202, removing the patterned layer.

[0043] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0044] In this embodiment, the material of the first fin 201 and the second fin 202 is silicon; in other embodiments, the material of the first fin and the second fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0045] Please refer to Figure 3 , an isolation layer 203 is formed on the substrate 200 , wherein the isolation layer 203 covers part of the sidewalls of the first fin 201 and the second fin 202 , and the top surface of the isolation layer 203 is lower than the top surface of the first fin 201 and the second fin 202 .

[0046] In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200, wherein the initial isolation layer covers the first fin 201 and the second fin 202; etching back the initial isolation layer to form the isolation layer 203, wherein the top surface of the initial isolation layer 203 is lower than the top surface of the first fin 201 and the second fin 202.

[0047] The isolation layer 203 is made of an insulating material, which includes silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 203 is made of silicon oxide.

[0048] After forming the isolation layer 203, the method further includes: forming a plurality of first gate structures on the first region I, wherein the first gate structures span the first fin 201, and adjacent first gate structures have a first size along the first direction X, and the sidewalls of the first gate structures have a first spacer structure, and the first spacer structure has a second size along the first direction X; forming a plurality of second gate structures on the second region II, wherein the second gate structures span the second fin 202, and adjacent second gate structures have a third size along the first direction X, and the third size is smaller than the first size, and the sidewalls of the second gate structures have a second spacer structure. The second sidewall structure has a fourth dimension along the first direction X, and the fourth dimension is smaller than the second dimension; first source-drain openings are formed in the first fins 201 on both sides of the first gate structure; second source-drain openings are formed in the second fins 201 on both sides of the second gate structure; source-drain doping layers are simultaneously formed in the first source-drain openings and the second source-drain openings until the source-drain doping layers fill the second source-drain openings, the top surface of the source-drain doping layer in the first source-drain opening is lower than the top surface of the first fin 201, and the top surface of the source-drain doping layer in the second source-drain opening is flush with the top surface of the second fin 202. For the specific process, please refer to Figures 4 to 12 .

[0049] Please refer to Figure 4 , a first dummy gate structure 204 is formed on the first region I, and the first dummy gate structure 204 spans the first fin 201; a second dummy gate structure 205 is formed on the second region II, and the second dummy gate structure 205 spans the second fin 202.

[0050] In this embodiment, the first dummy gate structure 204 includes: a first dummy gate dielectric layer, the first dummy gate dielectric layer covers a portion of the side walls and top surface of the first fin 201, and a first dummy gate layer (not labeled) located on the first dummy gate dielectric layer; the second dummy gate structure 205 includes: a second dummy gate dielectric layer, the second dummy gate dielectric layer covers a portion of the side walls and top surface of the second fin 202, and a second dummy gate layer (not labeled) located on the second dummy gate dielectric layer.

[0051] In this embodiment, the material of the first dummy gate dielectric layer and the second dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer and the second dummy gate dielectric layer may also be silicon oxynitride.

[0052] In this embodiment, the material of the first dummy gate layer and the second dummy gate layer is polysilicon.

[0053] In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously. The first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously through a global process, which can effectively improve production efficiency.

[0054] In this embodiment, a first dimension D1 is formed between adjacent first dummy gate structures 204 along the first direction X.

[0055] In this embodiment, a third dimension D3 is defined between adjacent second dummy gate structures 205 along the first direction X, and the third dimension D3 is smaller than the first dimension D1 .

[0056] Please refer to Figure 5 A first spacer material layer 206 is formed on the sidewalls and top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205 , and on the substrate 200 .

[0057] In this embodiment, the first spacer material layer 206 is formed by an atomic layer deposition process.

[0058] Please refer to Figure 6 , the first spacer material layer 206 is etched back until the top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205 are exposed, thereby forming an initial first spacer 207 .

[0059] In this embodiment, the process of etching back the first spacer material layer 206 is a dry etching process. In other embodiments, the process of etching back the initial first spacer material layer may also be a wet etching process.

[0060] Please refer to Figure 7 , the initial first spacer 207 located on the sidewall of the second dummy gate structure 205 is removed, and the first spacer 208 is formed on the sidewall of the first dummy gate structure 204 .

[0061] In this embodiment, the method for removing the initial first side wall 207 located on the side wall of the second pseudo gate structure 205 includes: forming a sacrificial layer (not shown) on the first region I, the sacrificial layer covering the first pseudo gate structure 204; after forming the sacrificial layer, removing the initial first side wall 207 located on the side wall of the second pseudo gate structure 205 to form the first side wall 208; after forming the first side wall 208, removing the sacrificial layer.

[0062] Please refer to Figure 8 After forming the first spacer 208 , a second spacer 209 is formed on the sidewall of the first spacer 208 , and a third spacer 210 is formed on the sidewall of the second dummy gate structure 205 .

[0063] In this embodiment, the second sidewall spacer 209 and the third sidewall spacer 210 are formed simultaneously.

[0064] In this embodiment, the method for forming the second sidewall 209 and the third sidewall 210 includes: forming a second sidewall material layer (not shown) on the sidewalls of the first sidewall 208 and the second dummy gate structure 205, the top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205, and the substrate 200; etching back the second sidewall material layer until the top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205 are exposed, forming the second sidewall 209 on the sidewall of the first sidewall 208, and forming the third sidewall 210 on the sidewall of the second dummy gate structure 205.

[0065] In this embodiment, the second spacer material layer is formed by an atomic layer deposition process.

[0066] In this embodiment, the first spacer structure includes: a first spacer 208 located on the sidewalls of the first gate structure, and a second spacer 209 located on the sidewalls of the first spacer 208. The first spacer structure has a second dimension D2 along the first direction X. The second spacer structure includes: a third spacer 210 located on the sidewalls of the second gate structure 205. The second spacer structure has a fourth dimension D4 along the first direction X, and the fourth dimension D4 is smaller than the second dimension D2. By increasing the second dimension D2 of the first spacer structure along the first direction X, the first fin 201 is further covered, the exposed dimension of the first fin 201 along the first direction X is reduced, and the dimension of the subsequently formed first source and drain opening along the first direction X is reduced. When the size of the first source-drain opening is reduced along the first direction X, when the source-drain doped layer in the second source-drain opening is filled, the source-drain doped layer formed in the first source-drain opening can fill more space, reducing the depression in the middle position of the source-drain doped layer in the first source-drain opening, thereby reducing the risk of the subsequently formed conductive layer penetrating the middle part of the source-drain doped layer, thereby improving the contact between the conductive layer and the source-drain doped layer in the first source-drain opening, thereby improving the performance of the semiconductor structure finally formed.

[0067] Please refer to Figure 9 After forming the first sidewall structure and the second sidewall structure, first source-drain openings 211 are formed in the first fin 201 on both sides of the first dummy gate structure 204; second source-drain openings 212 are formed in the second fin 205 on both sides of the second dummy gate structure 205.

[0068] In this embodiment, the method for forming the first source-drain opening 211 and the second source-drain opening 212 includes: etching the first fin 201 using the first dummy gate structure 204 and the first sidewall structure as a mask to form the first source-drain opening 211 in the first fin 201; etching the second fin 202 using the second dummy gate structure 205 and the second sidewall structure as a mask to form the second source-drain opening 212 in the second fin 202.

[0069] In this embodiment, the process of etching the first fin 201 and the second fin 202 is a wet etching process; in other embodiments, the process of etching the first fin and the second fin may also be a dry etching process.

[0070] Please refer to Figure 10 , a source-drain doped layer 213 is formed simultaneously in the first source-drain opening 211 and the second source-drain opening 212 until the source-drain doped layer 213 fills the second source-drain opening 212, and the top surface of the source-drain doped layer 213 located in the first source-drain opening 211 is lower than the top surface of the first fin 201, and the top surface of the source-drain doped layer 213 located in the second source-drain opening 212 is flush with the top surface of the second fin 202.

[0071] In this embodiment, the method for forming the source-drain doped layer 213 includes: using an epitaxial growth process to simultaneously form an epitaxial layer (not shown) in the first source-drain opening 211 and the second source-drain opening 212 until the epitaxial layer fills the second source-drain opening 212; in-situ doping the epitaxial layer during the epitaxial growth process, and doping the source-drain ions into the epitaxial layer to form the source-drain doped layer 213.

[0072] The material of the source / drain doping layer 213 includes: SiP, SiCP, SiGe or SiGeB. In this embodiment, the material of the source / drain doping layer 213 is SiP.

[0073] Please refer to Figure 11 After forming the source / drain doping layer 213 , a dielectric layer 214 is formed on the substrate 200 , and the dielectric layer covers the sidewalls of the first dummy gate structure 204 and the second dummy gate structure 205 .

[0074] In this embodiment, the material of the dielectric layer 214 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0075] Please refer to Figure 12 After forming the dielectric layer 214, the first dummy gate structure 204 is removed to form a first gate opening in the dielectric layer 214; the second dummy gate structure 205 is removed to form a second gate opening in the dielectric layer 214; the first gate structure 215 is formed in the first gate opening; and the second gate structure 216 is formed in the second gate opening.

[0076] In this embodiment, the first gate structure 215 includes: a first gate dielectric layer and a first gate layer (not labeled) located on the first gate dielectric layer; the second gate structure 216 includes: a second gate dielectric layer and a second gate layer (not labeled) located on the second gate dielectric layer.

[0077] In this embodiment, the material of the first gate dielectric layer and the second gate dielectric layer includes a high-K dielectric material.

[0078] The material of the first gate layer and the second gate layer includes metal, and the metal includes tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the first gate layer and the second gate layer is tungsten.

[0079] In this embodiment, the first gate structure 215 has a first width d1 along the first direction X, and the second gate structure 215 has a second width d2 along the first direction X. The first width d1 is greater than the second width d2.

[0080] In this embodiment, the first width dimension d1 is greater than 50 nm. By setting the first width dimension d1 of the first gate structure 215 to be greater than 50 nm, the length of the channel is increased, thereby reducing the influence of the channel effect.

[0081] Please refer to Figure 13 After forming the first gate structure 215 and the second gate structure 216 , a conductive layer 217 is formed on the source-drain doped layer 213 .

[0082] In this embodiment, the method for forming the conductive layer 217 includes: forming a conductive opening (not shown) in the dielectric layer 214 , wherein the conductive opening exposes the surface of the source / drain doped layer 213 ; and forming the conductive layer 217 in the conductive opening.

[0083] The conductive layer 217 is made of a metal including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the conductive layer 217 is made of copper.

[0084] Accordingly, a semiconductor structure is also provided in the embodiment of the present invention, please continue to refer to Figure 13 , comprising: a substrate 200, the substrate 200 comprising a first region I and a second region II, the first region I having a plurality of mutually separate first fins 201, the second region II having a plurality of mutually separate second fins 202, the first fins 201 and the second fins 202 respectively extending along a first direction X; a plurality of first gate structures 215 located on the first region I, the first gate structures 215 spanning the first fins 201, and adjacent first gate structures 215 having a first dimension D1 along the first direction X, the sidewalls of the first gate structures 215 having a first spacer structure, the first spacer structure having a second dimension D2 along the first direction X; a plurality of second gate structures 216 located on the second region II, the second gate structures 216 spanning the second fins 202, and adjacent second gate structures 216 having a first dimension D1 along the first direction X. The first direction X has a third dimension D3, and the third dimension D3 is smaller than the first dimension D1. The sidewall of the second gate structure 216 has a second sidewall structure, and the second sidewall structure has a fourth dimension D4 along the first direction X, and the fourth dimension D4 is smaller than the second dimension D2; first source and drain openings 211 within the first fin 201 on both sides of the first gate structure 215; second source and drain openings 212 within the second fin 202 on both sides of the second gate structure 216; source and drain doping layers 213 within the first source and drain openings 211 and the second source and drain openings 212, wherein the top surface of the source and drain doping layer 213 within the first source and drain openings 211 is lower than the top surface of the first fin 201, and the top surface of the source and drain doping layer 213 within the second source and drain openings 212 is flush with the top surface of the second fin 202.

[0085] In this embodiment, a first gate structure 215 is located on the first region I, and the sidewalls of the first gate structure 215 have a first spacer structure, and the first spacer structure has a second dimension D2 along the first direction X. A second gate structure 216 is located on the second region II, and the sidewalls of the second gate structure 216 have a second spacer structure, and the second spacer structure has a fourth dimension D4 along the first direction X, and the fourth dimension D4 is smaller than the second dimension D2. By increasing the second dimension D2 of the first spacer structure along the first direction X, the first fin 201 is further covered, and the exposed dimension of the first fin 201 along the first direction X is reduced, thereby reducing the dimension of the first source and drain opening 211 along the first direction X. When the size of the first source-drain opening 211 is reduced along the first direction X, when the source-drain doped layer 213 in the second source-drain opening 212 is filled, the source-drain doped layer 213 formed in the first source-drain opening 211 can fill more space, reducing the depression in the middle position of the source-drain doped layer in the first source-drain opening 211, thereby reducing the risk of the subsequently formed conductive layer 217 penetrating the middle part of the source-drain doped layer 213, thereby improving the contact between the conductive layer 217 and the source-drain doped layer 213 in the first source-drain opening 211, thereby improving the performance of the finally formed semiconductor structure.

[0086] In this embodiment, the layer further includes a conductive layer 217 located on the source-drain doped layer 213 .

[0087] In this embodiment, the conductive layer 217 is made of metal, such as tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel.

[0088] In this embodiment, the first spacer structure includes: a first spacer 208 located on a sidewall of the first gate structure 215 , and a second spacer 209 located on a sidewall of the first spacer 208 .

[0089] In this embodiment, the second spacer structure includes a third spacer 210 located on a sidewall of the second gate structure 216 .

[0090] In this embodiment, the first gate structure 215 has a first width d1 along the first direction X, and the second gate structure 216 has a second width d2 along the first direction X. The first width d1 is greater than the second width d2.

[0091] The material of the source / drain doping layer 213 includes: SiP, SiCP, SiGe or SiGeB. In this embodiment, the material of the source / drain doping layer 213 is SiP.

[0092] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate comprising a first region and a second region, wherein the first region has a plurality of mutually separate first fins, and the second region has a plurality of mutually separate second fins, wherein the first fins and the second fins extend along a first direction respectively; a plurality of first gate structures located on the first region, the first gate structures spanning the first fin, with a first dimension between adjacent first gate structures along the first direction, and first spacer structures on sidewalls of the first gate structures, with the first spacer structures having a second dimension along the first direction; a plurality of second gate structures located on the second region, the second gate structures spanning the second fin, and adjacent second gate structures having a third dimension along the first direction, the third dimension being smaller than the first dimension; and second spacers formed on sidewalls of the second gate structures, the second spacers having a fourth dimension along the first direction, the fourth dimension being smaller than the second dimension; first source and drain openings within the first fin located on both sides of the first gate structure; second source and drain openings within the second fin located on both sides of the second gate structure; The source-drain doped layer located in the first source-drain opening and the second source-drain opening has a top surface lower than the top surface of the first fin, and a top surface of the source-drain doped layer located in the second source-drain opening is flush with the top surface of the second fin.

2. The semiconductor structure according to claim 1, wherein Also includes: A conductive layer is located on the source-drain doped layer.

3. The semiconductor structure according to claim 2, wherein: The conductive layer is made of metal, including tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

4. The semiconductor structure according to claim 1, wherein: The first spacer structure includes: a first spacer located on a sidewall of the first gate structure, and a second spacer located on a sidewall of the first spacer.

5. The semiconductor structure according to claim 1, wherein The second spacer structure includes a third spacer located on a sidewall of the second gate structure.

6. The semiconductor structure according to claim 1, wherein The first gate structure has a first width dimension along the first direction, and the second gate structure has a second width dimension along the first direction, wherein the first width dimension is greater than the second width dimension.

7. The semiconductor structure according to claim 1, wherein: The material of the source / drain doping layer includes: SiP, SiCP, SiGe or SiGeB.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, the first region having a plurality of mutually separate first fins, the second region having a plurality of mutually separate second fins, the first fins and the second fins respectively extending along a first direction; forming a plurality of first gate structures on the first region, wherein the first gate structures span the first fin, and adjacent first gate structures have a first dimension along the first direction, and first spacer structures are formed on sidewalls of the first gate structures, and the first spacer structures have a second dimension along the first direction; forming a plurality of second gate structures on the second region, wherein the second gate structures span the second fin, and adjacent second gate structures have a third dimension along the first direction, wherein the third dimension is smaller than the first dimension; and second spacer structures are formed on sidewalls of the second gate structures, wherein the second spacer structures have a fourth dimension along the first direction, wherein the fourth dimension is smaller than the second dimension; forming first source and drain openings in the first fins on both sides of the first gate structure; forming second source and drain openings in the second fins on both sides of the second gate structure; A source-drain doped layer is formed simultaneously in the first source-drain opening and the second source-drain opening until the source-drain doped layer fills the second source-drain opening, wherein the top surface of the source-drain doped layer in the first source-drain opening is lower than the top surface of the first fin, and the top surface of the source-drain doped layer in the second source-drain opening is flush with the top surface of the second fin.

9. The method for forming a semiconductor structure according to claim 8, wherein: After forming the source-drain doped layer, the method further includes: forming a conductive layer on the source-drain doped layer.

10. The method for forming a semiconductor structure according to claim 9, wherein: The conductive layer is made of metal, including tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

11. The method for forming a semiconductor structure according to claim 8, wherein: The first spacer structure includes: a first spacer located on a sidewall of the first gate structure, and a second spacer located on a sidewall of the first spacer.

12. The method for forming a semiconductor structure according to claim 11, wherein: The second spacer structure includes a third spacer located on a sidewall of the second gate structure.

13. The method for forming a semiconductor structure according to claim 12, wherein: Before forming the first gate structure and the second gate structure, the method further includes: forming a first dummy gate structure on the first region, the first dummy gate structure spanning the first fin; and forming a second dummy gate structure on the second region, the second dummy gate structure spanning the second fin.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the first sidewall includes: forming a first sidewall material layer on the sidewalls and top surfaces of the first dummy gate structure and the second dummy gate structure, and on the substrate; etching back the first sidewall material layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed to form an initial first sidewall; removing the initial first sidewall located on the sidewall of the second dummy gate structure, and forming the first sidewall on the sidewall of the first dummy gate structure.

15. The method for forming a semiconductor structure according to claim 14, wherein: The formation process of the first spacer material layer includes an atomic layer deposition process.

16. The method for forming a semiconductor structure according to claim 14, wherein: The method for forming the second side wall and the third side wall includes: forming a second side wall material layer on the side walls of the first side wall and the second dummy gate structure, the top surfaces of the first dummy gate structure and the second dummy gate structure, and the substrate; etching back the second side wall material layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed, forming the second side wall on the side wall of the first side wall, and forming the third side wall on the side wall of the second dummy gate structure.

17. The method for forming a semiconductor structure according to claim 16, wherein: The second spacer material layer is formed by an atomic layer deposition process.

18. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the first gate structure and the second gate structure includes: forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the first dummy gate structure and the second dummy gate structure; removing the first dummy gate structure to form a first gate opening in the dielectric layer; removing the second dummy gate structure to form a second gate opening in the dielectric layer; forming the first gate structure in the first gate opening; and forming the second gate structure in the second gate opening.

19. The method for forming a semiconductor structure according to claim 8, wherein: The first gate structure has a first width dimension along the first direction, and the second gate structure has a second width dimension along the first direction, wherein the first width dimension is greater than the second width dimension.

20. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the source-drain doped layer includes: using an epitaxial growth process to simultaneously form an epitaxial layer in the first source-drain opening and the second source-drain opening until the epitaxial layer fills the second source-drain opening; in-situ doping the epitaxial layer during the epitaxial growth process, adding source and drain ions into the epitaxial layer to form the source-drain doped layer.

21. The method for forming a semiconductor structure according to claim 8, wherein: The material of the source / drain doping layer includes: SiP, SiCP, SiGe or SiGeB.

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