A reconfigurable single-stage resonant class E rectifier

Abstract

The present invention discloses a reconfigurable single-stage resonant E-type regulating rectifier. The reconfigurable E-type rectifier main power circuit adopts an E-type rectifier structure, which is connected to the load R through an active power tube and a passive structure. L The power conversion efficiency of the reconfigurable Class E rectifier is improved by providing a pulse-width modulated active power transistor gate control signal to the reconfigurable Class E rectifier main power circuit. This device achieves efficiency correction of the power structure and adjustment of the power rectifier output, integrating high-efficiency rectification and output voltage adjustment into a single-stage structure.

Description

Technical Field

[0001] The invention belongs to the technical field of power integrated circuit design, and in particular relates to a reconfigurable single-stage resonant type E-class regulating rectifier. Background Art

[0002] The design of the secondary energy receiving circuit in a wireless power transmission system is a key focus of the energy management circuitry closer to the battery. This circuit rectifies the energy received by the secondary coil to the battery load at the output end through the AC-to-DC conversion method of the primary power topology. As the receiving end and the circuit structure closest to the final battery load, the secondary receiving circuit in a wireless power transmission system typically requires a wide load variation range, a wide output voltage adjustment range, and high conversion efficiency. This significantly impacts the energy consumption of the wireless power transmission system that ultimately utilizes this secondary receiving circuit, as well as the voltage management performance of the battery end.

[0003] In wireless power transfer (WPT) systems, resonant power transfer (RWPT) is more popular than electromagnetic induction coupling due to its long transmission distance and low coupling location dependence. Existing RWPT output adjustment rectifier circuits often use a multi-stage structure. One approach uses a resistor divider to detect the voltage level. This voltage is then compared with a reference voltage from a low-dropout linear regulator (LDO). The rectifier is then configured as either a full-bridge rectifier (outputting a single-time multiplied DC output voltage, denoted as 1X) or a voltage doubler (outputting a double-time multiplied DC output voltage, denoted as 2X). The decision is based on which configuration best reduces the difference between the reference voltage input and output, thereby adjusting the output voltage. However, this requires an LDO regulator, which is a multi-stage structure. Another approach utilizes two flying capacitors in a charge pump-type configuration combined with a full-bridge rectifier. A feedback control loop periodically switches between 1X and 2X modes, adjusting the load output voltage amplitude by varying the capacitor conduction switching frequency or the duty cycle of the switching input signal. Although this structure avoids the use of LDOs, it still employs a multi-stage structure using switched capacitor circuits. The drawback of combining the rectification and regulation functions by connecting two stages of rectifier and voltage regulator or switched capacitor circuits in the above studies is also obvious: the multi-stage power structure leads to a multiplicative efficiency degradation, which is not worth the cost in terms of heat generation or energy utilization.

[0004] Therefore, single-stage integrated rectification and regulation functions are key design considerations for secondary resonant wireless power transmission to maximize energy transfer efficiency. A single-stage resonant regulation rectifier based on a Class D active rectification structure has been proposed. This also uses a pulse width modulation (PWM) control loop to periodically configure the output voltage to 1X, 1 / 2X, and 0X (idle) modes, achieving high-efficiency single-stage secondary energy transmission under output regulation. However, output regulation is achieved by configuring the main power topology to 1X and 1 / 2X modes, respectively, reconfiguring the rectification structure to Class D full-bridge and half-bridge rectification structures. During the rectification process, the four power transistors in the full-bridge and two power transistors in the half-bridge serve as current flow paths. During each half-cycle of the same cycle, only half of the power transistors are turned on. Therefore, current flows through the load during both half-cycles, completing the rectification. However, this mode rectifier structure always has two power tubes turned on throughout the entire cycle, resulting in two losses in the secondary due to the power tube on-resistance. The main loss in overall secondary power transmission efficiency comes from the power tube conduction loss. Therefore, minimizing the power tube conduction loss is the key to improving the power transmission efficiency of a single-stage rectifier. However, in this literature, higher transmission efficiency can only be achieved by increasing the on-chip power tube area in exchange for lower on-resistance. On the other hand, multiple power tubes require a corresponding number of gate drivers and control circuits in the control circuit, further increasing the complexity of the control circuit and the total power consumption, which is even more detrimental to improving the secondary power transmission efficiency. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a reconfigurable single-stage resonant Class E adjustment rectifier in response to the deficiencies in the above-mentioned prior art. In response to the conduction loss caused by multiple power tubes in the Class D single-stage resonant adjustment secondary solution with a control feedback loop, as well as the high design and power consumption cost of the control circuit and drive circuit, a new single-stage Class E adjustment rectifier is adopted, which has only a single power tube, and its passive structure is reconfigurable. The adjustment direction of the voltage modulation loop is determined according to the DC value of the load output voltage. When the output voltage changes due to changes in the load adjustment component at the battery end, the modulation direction is judged according to the instantaneous load DC voltage value obtained by sampling, and the output voltage is stabilized at the target voltage. At the same time, the single power tube is actively adjusted to ensure that the power tube meets the soft switching state, thereby achieving the design requirement of higher transmission efficiency relative to the traditional Class D single-stage resonant rectifier.

[0006] The present invention adopts the following technical solutions:

[0007] A reconfigurable single-stage resonant class E adjustment rectifier includes a reconfigurable class E rectifier main power circuit and an efficiency correction & load voltage modulator. The reconfigurable class E rectifier main power circuit adopts a class E rectifier structure and connects to the load R through an active power tube and a passive structure. LThe efficiency correction & load voltage modulator provides a reconstructed capacitor array switch control signal to the reconstructed Class-E rectifier main power circuit, realizing the passive structure configuration of the reconstructed Class-E rectifier main power circuit during the modulation process, and at the same time provides a pulse-width modulated active power tube gate control signal to realize the correction and improvement of the power conversion efficiency of the reconstructed Class-E rectifier main power circuit.

[0008] Specifically, the reconfigurable E-type rectifier main power circuit includes an active power tube SW, a reconfigurable parallel capacitor array C P , load capacitance C L and filter inductor L f , active power tube SW, reconfigurable parallel capacitor array and load capacitor C L The filter inductor L is connected in parallel at both ends of the input equivalent AC source. f In series with the reconfigurable parallel capacitor array and the load capacitor C L Between the drain end of the active power tube SW and the load R L The positive end of the efficiency correction & load voltage modulator is connected to the sampling input end of the efficiency correction & load voltage modulator respectively. The efficiency correction & load voltage modulator is based on the drain voltage v of the active power tube SW. sw and load R L The DC voltage V REC As a basis for judgment, a gate control signal Ctrl is generated to control the active power tube SW switch. Gate and reconfigurable capacitor array control signal Ctrl CP [5:0].

[0009] Furthermore, the parallel capacitor array C can be reconfigured P Includes six groups of MOS switches SW Ci , six groups of MOS switches SW Ci The source of the six MOS switches SW is connected to the ground level. Ci The drain and six capacitors C Pi The negative connection of six capacitors C Pi The positive terminal is connected to the drain of the active power tube SW; six groups of MOS switches SW Ci and the corresponding capacitance C Pi The six-bit switch-controlled capacitor array is connected in series and then connected in parallel with the fixed capacitor CPx at the input equivalent AC source AC end. The reconfigurable capacitor array control signal Ctrl is generated by the efficiency correction & load voltage modulator. CP [5:0] for six groups of MOS switches SW Ci The gate end is controlled to realize the capacitance control of the six-bit switch-controlled capacitor array.

[0010] Furthermore, the parallel capacitor array C can be reconfigured PThe capacitance is specifically:

[0011] C P =C Px +Σ2 i Ctrl CP [i]C P0

[0012] Among them, C P0 is the unit capacitance value, Ctrl CP [i] is represented by a digital code 0 or 1, i = 0, 1, 2, 3, 4, 5;

[0013] Reconfigurable parallel capacitor array C P Fixed capacitor C Px The satisfying relationship is as follows:

[0014] C Px >>C Drain,P

[0015] Among them, C Drain,P It is the source-drain parasitic capacitance of the active power tube.

[0016] Specifically, the circuit parameter characteristics of the Class E rectifier structure meet the following constraints:

[0017] Initial phase for:

[0018]

[0019] Filter inductor L f The current flowing is equal to the output load R L The current on the REC ,satisfy:

[0020]

[0021] Resonant operating frequency ω, total capacitance of reconfigurable capacitor array C P and the load resistor R L The product of ωC P R L satisfy:

[0022]

[0023] Load R L The DC voltage V REC satisfy:

[0024]

[0025] Among them, DT is the gate control signal duty cycle, I m Enter the peak value of the secondary sinusoidal AC current.

[0026] Specifically, the efficiency correction & load voltage modulator includes two circuit paths, a sampling clock generator and an asynchronous reset signal generator; the two circuit paths are respectively the reconfigurable capacitor array control signal Ctrl CP [5:0] Generates and drives the channel and gate control signal Ctrl Gate Pulse width modulation generation and driving path.

[0027] Furthermore, the capacitor array controls the signal generation and driving path to reconfigure the class E rectifier main power circuit output load R L The upper analog domain output rectified voltage V REC As the sampling input signal, the reconfigurable capacitor array control signal Ctrl CP [5:0] is output to the gate terminal of the MOS switch of the capacitor array of the reconfigurable Class E rectifier main power circuit;

[0028] The gate control signal pulse width modulation is generated and driven to reconfigure the active power tube SW drain voltage v of the E-class rectifier main power circuit. sw As the sampling input signal, the gate control signal Ctrl is finally generated Gate Output to the gate terminal of the active power tube SW to control its on and off;

[0029] The sampling clock generator is based on V REC The voltage generates the NRST reset signal, which is provided to the two circuit paths and the sampling clock generator as the reset control signal. When the NRST reset signal is low, the reconfigurable capacitor array control signal Ctrl CP The code value of [5:0] is cleared to zero, and the capacitance of the reconstructed parallel capacitor array is C Px At the same time, the gate control signal pulse width modulation generation and the vector modulation direction generation algorithm in the drive path output control code Duty<7:0> half of the maximum code value, so that the gate control signal Ctrl Gate The duty cycle is 50%, and the sampling clock generator generates the gate control signal Ctrl Gate As input, it generates the sampling clock CLK for the capacitor array control signal generation and drive path after frequency division and delay. REC The gate control signal pulse width modulation generates and drives the sampling clock CLK of the path ON .

[0030] Furthermore, the vector modulation direction generation algorithm is specifically as follows:

[0031] For [D HH , D H , D L , D LL ]-Ctrl CP[5:0] Vector modulation direction generation algorithm, at input [D HH , D H , D L , D LL ] is 1111, the output V REC In the large window [V RECHH , V RECLL ]; the window is above the sampling clock CLK REC When the edge comes, Ctrl CP The code value of [5:0] increases by the binary value ΔCtrl relative to the previous sampling clock cycle. CP =3'b100;

[0032] When inputting [D HH , D H , D L , D LL ] is 0000, the output V REC In the large window [V RECHH , V RECLL ], the window is under the sampling clock CLK REC When the edge comes, Ctrl CP [5:0] The code value decreases by ΔCtrl relative to the previous cycle CP =3'b100;

[0033] When inputting [D HH , D H , D L , D LL ] is 0111, the output V REC In the small window [V RECH , V RECL ] above, in the large window high level V RECHH Below, the window is at the sampling clock CLK REC When the edge comes, Ctrl CP The code value of [5:0] increases by ΔCtrl relative to the previous cycle CP =1'b1;

[0034] When inputting [D HH , D H , D L , D LL ] is 0001, the output V REC In the small window [V RECH , V RECL ], in the large window low level V RECLL Above, the window is at the sampling clock CLK REC When the edge comes, Ctrl CP The code value of [5:0] decreases by ΔCtrl relative to the previous cycle CP =1'b1;

[0035] When inputting [D HH , D H , D L , D LL ] is 0011, the output V REC In the small window [V RECH , V RECL ], the window is within the sampling clock CLK REC When the edge comes, Ctrl CP The code value of [5:0] remains unchanged relative to the previous sampling clock cycle. P The capacitance value remains unchanged. When the set signal NRST is at a low level, Ctrl CP The code value of [5:0] is set to 000000, C P The capacitance is set to a fixed capacitor C Px , after the circuit stabilizes V REC is the maximum output voltage;

[0036] For [D SWH , D SWL ]-Duty<7:0> vector modulation direction generation algorithm, only one step size ΔDuty=2'b100, according to the gate signal pulse width modulation generator and the boost sampling in the drive path to obtain the source and drain V SWO With window [V WH , V SWL ] determines the output code value Duty<7:0> adjustment direction:

[0037] When inputting [D SWH , D SWL ] is 11, the conduction edge moment v sw If the voltage is greater than 0, the Duty<7:0> code value is reduced by the step size ΔDuty, and the DAC output V Duty Decrease, PWM pulse width adjustment comparator output gate control signal Ctrl Gate The rising edge is delayed and the pulse duty cycle is reduced;

[0038] When inputting [D SWH , D SWL ] is 00, the conduction edge moment v sw The voltage is less than 0, the conduction edge is delayed, and the Duty<7:0> code value is increased by the step size ΔDuty. The DAC output V Duty Increase, PWM pulse width adjustment comparator output gate control signal Ctrl Gate The rising edge is advanced and the pulse duty cycle increases;

[0039] When inputting [D SWH , D SWL ] is 00, the conduction edge moment v swThe voltage is 0, meeting the ZVS condition, the active power tube SW is in the soft switching state, and high-efficiency adjustment is completed.

[0040] Furthermore, the specific signal transmission and circuit connection structure of the capacitor array control signal generation and drive path is as follows:

[0041] Reconfigurable Class E rectifier main power circuit output voltage V by sampling with resistor REC The voltage sampled by the resistor is compared with two sets of window voltages [V RECHH , V RECLL ] and [V RECH , V RECL ] to compare the output voltage V REC The analog domain voltage is converted into a digital domain code value [D HH , D LL ] and [D H , D L ]; Use the two sets of digital comparison outputs as the input of the vector modulation direction generation algorithm, and adjust the clock CLK in the vector modulation generation method REC When the edge comes, according to [D HH , D H , D L , D LL ] input code value, and the six-bit reconfigurable capacitor array control signal Ctrl is determined according to the vector modulation direction generation algorithm CP [5:0] The code value adjustment step size is increased or decreased with two different step sizes, and then the capacitor array control tube is turned on or off by driving the control capacitor array to realize the reconfigurable capacitor array control signal C P [5:0] Capacitance change.

[0042] Furthermore, the gate control signal pulse width modulation and the specific signal transmission and circuit connection structure of the driving path are as follows:

[0043] Gate control signal Ctrl Gate The conduction clock CLK generated by the sampling clock generator ON When the edge comes, v sw The instantaneous source-drain voltage V of this cycle obtained by boost sampling SWO , with the reference voltage window at ground voltage [V SWH V SWL ]Compare to get the comparison result code value [D SWH , D SWL ], according to [D SWH , D SWL ], the vector modulation direction generation algorithm uses a fixed step size adjustment algorithm to output the code value of Duty<7:0>, and the code value is decoded by the 8-bit DAC to obtain a voltage value V that changes according to the comparison result.Duty The corresponding level is compared with the ramp signal through the PWM comparator to obtain a square wave signal with a rising edge that changes successively. After driving, the gate control signal Ctrl with pulse width and rising edge modulated is obtained. Gate .

[0044] Compared with the prior art, the present invention has at least the following beneficial effects:

[0045] The present invention proposes a reconfigurable single-stage resonant Class E rectifier. This circuit, comprised of a reconfigurable Class E main power circuit and an efficiency correction and load voltage modulator, achieves AC-to-DC power conversion between the secondary AC input and the load in a single-stage structure, integrating both rectification and output load voltage regulation. Compared to a traditional three-stage structure consisting of a rectifier, a switched capacitor converter, and a linear regulator, this design offers a simpler structure and significantly reduces excess power loss caused by multi-stage cascading, resulting in higher AC-to-DC power conversion efficiency.

[0046] Furthermore, the reconfigurable capacitor array structure of the reconfigurable class E rectifier main power circuit is connected in parallel at both ends of the drain and source of the active power tube SW, and is also connected to the input AC current source and the second-order output filter network L f -C L The reconfigurable E-type rectifier main power circuit has only one active power tube SW. Compared with the D-type rectifier circuit with more than two power tubes, each power tube can be turned on for a period of time in one cycle, providing a path for both the forward and reverse flow of the input AC source current. The single active power tube SW of the reconfigurable E-type rectifier main power circuit can only provide a path when the AC source current flows in the reverse direction, while the reconfigurable capacitor array structure connected in parallel at both ends of SW can provide a path when the AC source current flows in the forward direction. When the AC source current is input in the forward direction, the reconfigurable capacitor array C P Charging, generating a periodic SW drain voltage v with a peak value sw , then through L f -C L Filter and get DC power supply V REC , the entire rectification process can be completed.

[0047] Furthermore, the parallel capacitor array C can be reconfigured P In the connection mode, let the six-position switch SW Ci The drain and the six-bit capacitor C Pi The purpose is to avoid the six-position switch SW Ci The source voltage is too large, which makes the gate drive control power rail design complicated, so the switch SW Ci The source is connected to the ground voltage, thus driving the six-bit switch SW CiThe power rail of the driving structure of the reconfigurable capacitor array control signal CtrlCP[5:0] can be normally set to a 5V power rail, while avoiding the breakdown problem caused by excessively high gate voltage.

[0048] Furthermore, the parallel capacitor array C can be reconfigured P The fixed capacitor C Px The relationship is satisfied due to the fixed capacitance C Px Determines the reconfigurable parallel capacitor array C P The minimum value determines the maximum voltage value of the output voltage adjustment. In order to avoid the influence of the source-drain parasitic capacitance of the active power tube SW on the maximum voltage value of the output voltage adjustment, we need to consider the size of its parasitic capacitance when selecting the active power tube SW so that it meets this limited relationship; the reconfigurable parallel capacitor array C P The capacitance value is set by the reconfigurable capacitor array control signal Ctrl CP [5:0] determines the reconfigurable capacitor array control signal Ctrl through the loop CP [5:0] code value, through the control of the six-bit switch SW Ci Switch to adaptively adjust C P The capacitance value is adjusted in binary mode to increase or decrease, and the minimum adjustment resolution is in unit capacitance value C. P0 Decide.

[0049] Furthermore, the circuit parameters of the reconfigurable high-efficiency single-stage resonant E-type rectifier are adjusted to the initial phase Current I REC ωC P R L and DC voltage V REC The purpose of setting the relationship is to make the E-class rectifier structure meet the zero voltage switching (Zero Voltage Switching, ZVS) of the active power tube SW at the moment of switching on and the zero voltage derivative switching (Zero Voltage Derivative Switching, ZVDS) of the active power tube SW at the moment of switching off, that is, the active power tube SW of the reconstructible E-class rectifier main power circuit can be in the form of soft switching, and its on / off switching loss can be minimized, so its power conversion efficiency can be maximized.

[0050] Furthermore, the efficiency correction & load voltage modulator sets two digital-analog hybrid paths to respectively complete the adaptive voltage adjustment and adaptive high-efficiency rectification functions of the reconstructed Class E rectifier main power circuit. Among them, the capacitor array control signal generation and drive path adaptively complete the load output voltage V RECThe voltage adjustment function is realized, and the gate control signal pulse width modulation generation and driving path are completed to improve the power conversion efficiency calibration of the reconstructible E-class rectifier main power circuit.

[0051] Furthermore, the gate control signal pulse width modulation and driving path are achieved by controlling the power tube gate control signal of the reconfigurable Class E main power topology, so that the synchronous power tube SW P At the on / off switching moment, it is in soft switching mode, that is, zero voltage switching (ZVS), where the voltage refers to the synchronous power tube SW P The source-drain voltage v sw , ZVS implementation requires SW P Gate control signal Ctrl Gate When the conduction edge of v sw =0, so that SW P The switching losses are minimized to achieve high power transmission efficiency.

[0052] Furthermore, the vector modulation direction generation algorithm is adopted, and the window comparison method is set to convert the target signal V REC and v sw After the adjustment is completed, adjust it to the target window. REC Adjusted [D HH , D H , D L , D LL ]-Ctrl CP [5:0] The vector modulation direction generation algorithm uses two windows to determine different adjustment steps with different windows. The ultimate goal is to adjust the output voltage to [D H , D L ] small window to achieve the final regulated voltage adjustment output. The purpose of setting two windows is to improve the load adjustment speed. After the load is switched, the voltage changes greatly. Adjusting with a large window and a large step size can effectively improve the load adjustment speed. sw Adjust the settings window [D SWH , D SWL ] is near the ground voltage. After the adjustment is completed, v sw Located in window [D SWH , D SWL ], it can be approximately regarded that the reconfigurable E-class main power structure is in the ZVS state, and the highest power conversion efficiency is approximately achieved.

[0053] Furthermore, the capacitor array controls the signal generation and driving path, and the mixed digital-analog signal transmission and circuit connection structure are designed to generate the output voltage V according to the sampling. REC The relationship between the target voltage and the adaptive feedback adjustment of the reconfigurable capacitor array C P Capacitance value to achieve the output voltage VREC voltage adjustment.

[0054] Furthermore, the gate control signal pulse width modulation and drive path, the set digital-analog hybrid signal transmission and circuit connection structure are designed to obtain the drain voltage v at the active power tube conduction moment according to the sampling sw The relationship between the size of the ground voltage GND is used to determine whether ZVS is achieved, and the adaptive feedback adjusts the active power tube gate control signal Ctrl Gate Pulse width (equivalent to the advance / delay adjustment gate control signal Ctrl Gate The conduction edge position) is used to realize the drain voltage v at the conduction moment. sw Adjust to meet ZVS conditions.

[0055] In summary, the present invention utilizes the proposed control adjustment loop consisting of efficiency correction and load voltage modulator in a single-stage power stage structure to achieve single-stage integration of high-efficiency rectification and output voltage adjustment functions, and proposes a vector modulation direction generation algorithm based on adaptive control, which is applied to the efficiency correction and load voltage modulation paths.

[0056] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 This is a schematic diagram of the structure of a reconfigurable high-efficiency single-stage resonant Class E regulating rectifier according to the present invention;

[0058] Figure 2 The reconfigurable class E rectifier main power circuit of the present invention and its equivalent diagram, including the specific circuit structure of the reconfigurable parallel capacitor array;

[0059] Figure 3 The parameters V of the reconstructed E-class rectifier main power circuit of the present invention are REC and C P Restriction relationship simulation diagram;

[0060] Figure 4 This is a specific circuit structure diagram of the efficiency correction & load voltage modulator of the present invention.

[0061] Figure 5 Schematic diagram of waveforms and output code values of the capacitor array control signal generation and drive path adaptive vector modulation direction algorithm of the present invention;

[0062] Figure 6 Schematic diagram of gate signal pulse width modulation and drive path adaptive vector modulation direction algorithm and DAC output waveform of the present invention;

[0063] Figure 7 is the light load R in the specific embodiment of the present invention L=5Ω Switch to heavy load R L =3Ω output load modulation at 5V DC output transient simulation diagram;

[0064] Figure 8 1 is a simulation result of the secondary AC-to-DC power conversion efficiency under different output load voltages and load resistances in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0065] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0066] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0067] It should also be understood that the terms used in the present specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0068] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0069] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments disclosed herein. These figures are not drawn to scale; for clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0070] The present invention provides a reconfigurable single-stage resonant Class E rectifier. A hybrid digital-analog control and adjustment circuit is designed for this new reconfigurable single-stage Class E rectifier. The voltage modulation circuit is designed using a hybrid digital-analog feedback loop. The output load voltage and power tube voltage are sampled separately as a basis for judgment. The digital result obtained through analog comparison serves as the judgment condition for controlling the direction of the controllable vector in the digital circuit. This hybrid digital-analog approach reduces the overall control loop power consumption and improves the algorithm's scalability, allowing it to be implemented off-chip in an FPGA. Furthermore, the single active power tube design of the Class E rectifier significantly reduces the losses in the drive section of the control system.

[0071] See also Figure 1 The present invention provides a reconfigurable single-stage resonant Class E adjustment rectifier, including a reconfigurable Class E rectifier main power circuit and an efficiency correction & load voltage modulator. The reconfigurable Class E rectifier main power circuit rectifies the AC input energy driven by the secondary current source to a DC output by combining an active power tube and a passive structure. This is the main power topology of the single-stage Class E resonant adjustment rectifier proposed by the present invention, and the power current flows through the main power topology; the efficiency correction & load voltage modulator provides the reconfigurable Class E rectifier main power circuit with a reconfigurable capacitor array switch control signal to realize the passive structure configuration of the reconfigurable Class E rectifier main power circuit during the modulation process, and also provides a pulse width modulated active power tube gate control signal to realize the correction and improvement of the power conversion efficiency of the reconfigurable Class E rectifier main power circuit.

[0072] See also Figure 2 , is a structural diagram of the main power circuit of the reconfigurable E-type rectifier proposed in the present invention. The reconfigurable E-type rectifier main power circuit includes an active power tube SW, a reconfigurable parallel capacitor array, and a load capacitor C L and filter inductor L f , active power tube SW, reconfigurable parallel capacitor array and load capacitor C L The filter inductor L is connected in parallel at both ends of the input equivalent AC source. f In series with the reconfigurable parallel capacitor array C P and load capacitance C L Between the drain of the active power tube SW (i.e. the positive electrode of the reconstructed parallel capacitor array) and the load resistor R L The positive end of the efficiency correction and load voltage modulator are connected to the sampling input end of the efficiency correction and load voltage modulator respectively. The efficiency correction and load voltage modulator are based on the active power tube SW drain voltage v sw and load R L The DC voltage V REC As a basis for judgment, a gate control signal Ctrl is generated to control the active power tube SW switch. Gate and reconfigurable capacitor array control signal Ctrl CP[5:0].

[0073] The reconfigurable parallel capacitor array C proposed in the present invention P The specific connection method is: six MOS switches SW Ci The source is connected to the ground level, and the drain is connected to six capacitors C Pi The negative plates are connected separately, and C Pi The positive plate is connected to the drain of the active power tube SW. Ci and capacitor C Pi The six-bit switch-controlled capacitor array obtained in series is then connected in parallel with the fixed capacitor CPx at the two ends of the input equivalent AC source AC (i.e. the source and drain ends of the active power tube SW). The capacitance value of the six-bit switch-controlled capacitor array is controlled by the reconfigurable capacitor array control signal Ctrl generated by the efficiency correction & load voltage modulator. CP [5:0] for six groups of MOS switches SW Ci The gate terminal is controlled.

[0074] See also Figure 2 Since the present invention is aimed at medium and high power wireless transmission systems such as wireless charging of electromagnetic loads, the proposed rectifier input accepts energy of watt-level AC energy. The power transmission efficiency of the primary transmitter of the entire wireless energy transmission system can be maximized when the secondary rectifier input adopts a series resonant secondary tank (SST) structure. Therefore, the reconstructed E-type main power circuit input resonant network proposed by the present invention consists of a secondary coil L sec , series resistance C S and the secondary coil parasitic resistance R S Composition, C S -L sec -R S The first is connected in series and then in parallel at the source and drain ends of the active power tube SW. The SST resonant input is equivalent to an approximately sinusoidal current source input with a peak current of 3A, which can generate a medium or high voltage of more than 25V at the drain end of the active power tube. S -L sec -R S The resonant frequency of the structure must meet the practical application requirements of wireless power products in the 6.78MHz or 13.56MHz Industrial Scientific Medical (ISM Band) frequency band. In addition, in order to make the AC input current source obtained after the power tube is disconnected more sinusoidal, it is necessary to properly arrange the series resonant C S -L sec -R SStructural quality factor Q. However, there is a compromise in the selection of quality factor Q. On the one hand, considering the good frequency selection characteristics of the secondary input resonance, a high quality factor is required. However, at the same time, the passive components of the rectifier circuit store as little energy as possible and consume all the energy on the load, which requires a low quality factor. In the E-class main power topology designed by the present invention, the quality factor should be slightly greater than 5, and 5≤Q≤10 is selected. The series resonant C S -L sec -R S The structure can be equivalent to a sinusoidal current input.

[0075] At the same time, considering that the main power loss of the rectifier comes from the loss of on-resistance when the power tube is turned on, the power tube SW adopts an actively controlled on-chip integrated silicon-based MOS switch with a source-drain withstand voltage of 32V. Compared with the asynchronously controlled Schottky diode as the power switch, which is passively turned on, there is no large on-voltage of the passive switch. Therefore, this type of MOS-type active power tube has smaller conduction loss and can effectively improve efficiency.

[0076] See also Figure 2 The specific voltage and current involved in the design of the main power circuit of the reconstructible E-type rectifier proposed by the present invention are: series resonant C S -L sec -R S Structural equivalent sinusoidal current input i in , the current isw of the active power tube SW, the reconfigurable capacitor array C P The current icp, the rectified output voltage V after the second-order filter network REC and the rectified output current I REC The specific circuit parameters involved are: active power tube SW gate control signal Ctrl Gate The duty cycle is DT, the equivalent sinusoidal input current i in The peak current input is I m and the initial phase is Load R L The DC voltage value V REC and the reconfigurable capacitor array capacitance C P The main power circuit of the reconfigurable Class E rectifier designed in the present invention satisfies soft switching, that is, it satisfies zero voltage switching (ZVS) at the moment of active power tube SW switching on and zero voltage derivative switching (ZVDS) at the moment of active power tube SW switching off. Its parameter restriction relationship satisfies:

[0077]

[0078]

[0079] See also Figure 2 In the circuit design of the specific reconfigurable parallel capacitor array, since the output load range and output voltage range have their limits, there is a minimum adjustment capacitance and its corresponding maximum adjustment voltage. The minimum adjustment capacitance should be much larger than the source-drain parasitic capacitance C of the synchronous power tube. Drain,P , so the fixed capacitor C of the reconfigurable parallel capacitor array is set Px , satisfying C Px >>C Drain,P In this invention, the fixed capacitance value is C Px =900pF and is implemented outside the chip. At the same time, due to the mapping between the output voltage and the capacitance of the reconstructed capacitor array, in an ideal case, the adjustment accuracy of the reconstructable parallel capacitor array is the resolution of the output voltage modulation. Therefore, the unit capacitance value C of the reconstructable parallel capacitor array is P0 will depend on the output voltage modulation resolution, at load R L =5Ω, the minimum unit voltage change during adjustment is ΔV REC =40mV, so the unit capacitance value in the present invention is C P0 =150pF. Similarly, the reconfigurable parallel capacitor array is also implemented outside the chip. The capacitance of each part of the reconfigurable parallel capacitor array is arranged according to the exponential power of 2, that is:

[0080] C P =C Px +Σ2 i Ctrl CP [i]C P0 ,i=0,1,2,3,4,5 (5)

[0082] Among them, C P0 is the unit capacitance value, Ctrl CP [i] is represented by a digital code 0 or 1.

[0083] See also Figure 3 The reconstructed E-class rectifier main power circuit parameters V obtained by simulation based on the parameter restriction relationship are shown as follows: REC and C P Change diagram, for the input series resonant network C S -L sec -R S , peak current I m and duty cycle DT, the load output voltage V REC Only the gate control signal duty cycle DT and the reconfigurable parallel capacitor value C PThe capacitance of the parallel capacitor and the output voltage are approximately inversely proportional. Based on this, the present invention adopts a new output load modulation method and uses Figure 4 The capacitor array control signal generation and driving path in the proposed efficiency correction & load voltage modulator are implemented.

[0084] See also Figure 4 The efficiency correction & load voltage modulator is implemented in a mixed digital-analog manner. The efficiency correction & load voltage modulator includes two circuit paths, a sampling clock generator and an asynchronous reset signal generator; the two circuit paths are respectively the reconfigurable capacitor array control signal Ctrl CP [5:0] Generates and drives the channel and gate control signal Ctrl Gate Pulse width modulation generation and driving path; wherein, the feedback control signal Ctrl is determined CP The digital vector modulation direction generation algorithm for the adjustment direction of [5:0] and Duty[7:0] is the key to feedback adjustment to achieve output voltage adjustment and efficiency correction;

[0085] The system circuit structure features are as follows: capacitor array control signal generation and drive path with reconfigurable Class E rectifier main power circuit output load R L The upper analog domain output rectified voltage V REC As the sampling input signal, the reconfigurable capacitor array control signal Ctrl CP [5:0] is output to the gate terminal of the MOS switch of the capacitor array of the reconfigurable E-class rectifier main power circuit. The gate control signal pulse width modulation is generated and the drive path is used to reconfigure the active power tube SW drain voltage v of the E-class rectifier main power circuit. sw As the sampling input signal, the gate control signal Ctrl is finally generated Gate The output is sent to the gate of the active power tube SW to control its on and off.

[0086] The asynchronous reset signal generator re-starts the circuit according to V REC The voltage generates the NRST reset signal, which is provided to the two circuit paths and the sampling clock generator as the reset control signal. When the NRST reset signal is low, the reconfigurable capacitor array control signal Ctrl CP The code value of [5:0] is cleared to zero, and the capacitance of the reconstructed parallel capacitor array is C Px At the same time, the gate control signal pulse width modulation generation and the vector modulation direction generation algorithm in the drive path output control code Duty<7:0> half of the maximum code value, so that the gate control signal Ctrl Gate The duty cycle is 50%. The sampling clock generator generates the gate control signal Ctrl Gate As input, it generates the sampling clock CLK for the capacitor array control signal generation and drive path after frequency division and delay.REC The gate control signal pulse width modulation generates and drives the sampling clock CLK of the path ON .

[0087] See also Figure 4 , the capacitor array control signal generation and drive path structure and signal connection of efficiency correction & load voltage modulator are as follows: the output voltage V of the reconfigurable E-class rectifier main power circuit is sampled by a resistor REC The voltage sampled by the resistor is compared with two sets of window voltages [V RECHH , V RECLL ] and [V RECH , V RECL ] to compare the output voltage V REC The analog domain voltage is converted into a digital domain code value [D HH , D LL ] and [D H , D L ]; Use the two sets of digital comparison outputs as the input of the vector modulation direction generation algorithm, and adjust the clock CLK in the vector modulation generation method REC When the edge comes, according to [D HH , D H , D L , D LL ] input code value, the vector modulation direction generation algorithm determines the six-bit reconfigurable capacitor array control signal Ctrl CP [5:0] The code value adjustment step size is increased or decreased with two different step sizes, and then the capacitor array control tube is turned on or off by driving the control capacitor array to realize the capacitor array C P <5:0>Capacitance change.

[0088] See also Figure 4 , the gate control signal pulse width modulation and drive path structure of the efficiency correction & load voltage modulator are connected to the signal: Gate The conduction clock CLK generated by the sampling clock generator ON When the edge comes, v sw The instantaneous source-drain voltage V of this cycle obtained by boost sampling SWO , with the reference voltage window near ground voltage [V SWH V SWL ]Compare to get the comparison result code value [D SWH , D SWL ], according to [D SWH , D SWL The vector modulation direction generation algorithm outputs the Duty<7:0> code value using a fixed step size adjustment algorithm. The code value is decoded by the 8-bit DAC to obtain a voltage value V that changes according to the comparison result.Duty The corresponding level is compared with the ramp signal through the PWM comparator to obtain a square wave signal with a rising edge that changes successively. After driving, the gate control signal Ctrl with pulse width and rising edge modulated is obtained. Gate .

[0089] See also Figure 5 ,Capacitor array control signal generation and drive path[D HH , D H , D L , D LL ]-Ctrl CP [5:0] The vector modulation direction generation algorithm is as follows: HH , D H , D L , D LL ] is 1111, which means the output is V REC In the large window [V RECHH , V RECLL ], the window is above the sampling clock CLK REC When the edge comes, Ctrl CP The code value of [5:0] increases by the binary value ΔCtrl relative to the previous sampling clock cycle. CP =3'b100, reconfigurable capacitor array C P The capacitance value increases with the larger capacitance value, and the output voltage V REC Adjust to reduce by a large margin; in [D HH , D H , D L , D LL ] is 0000, V REC In the large window [V RECHH , V RECLL ], under CLK REC When the edge comes, Ctrl CP [5:0] The code value decreases by ΔCtrl relative to the previous cycle CP =3'b100,C P The capacitance value decreases with the increase of the capacitance value, V REC Significantly increased; in [D HH , D H , D L , D LL ] is 0111, V REC In the small window [V RECH , V RECL ] above, but in the large window high level V RECHH Under CLK REC When the edge comes, Ctrl CP The code value of [5:0] increases by ΔCtrl relative to the previous cycle CP=1'b1,C P The capacitance value increases with a small capacitance value increment, V REC A slight decrease; in [D HH , D H , D L , D LL ] is 0001, V REC In the small window [V RECH , V RECL ] below, but in the large window low level V RECLL Above, on CLK REC When the edge comes, Ctrl CP The code value of [5:0] decreases by ΔCtrl relative to the previous cycle CP =1'b1,C P The capacitance value decreases with a small capacitance increment, V REC A small increase; when input [D HH , D H , D L , D LL ] is 0011, V REC In the small window [V RECH , V RECL ], the sampling clock CLK REC When the edge comes, Ctrl CP The code value of [5:0] remains unchanged relative to the previous sampling clock cycle. P The capacitance remains unchanged, V REC After a period of stabilization. When the set signal NRST is low, Ctrl CP The code value of [5:0] is set to 000000, C P The capacitance is set to a fixed capacitor C Px , at this time, after the circuit is stable, V REC is the maximum output voltage.

[0090] See also Figure 6 , gate control signal pulse width modulation and drive path [D SWH , D SWL ]-Duty<7:0> Vector modulation direction generation algorithm: The principle is the same as the vector modulation direction generation algorithm of the capacitor array control signal generation and the drive path, but there is only one step size ΔDuty=2'b100. The source and drain V are obtained based on the gate signal pulse width modulation generator and the boost sampling in the drive path. SWO With window [V WH , V SWL ] determines the output code value Duty<7:0> adjustment direction: [D SWH , D SWL ] is 11, representing the conduction edge moment v swThe voltage is greater than 0, the conduction edge is advanced, the pulse width is large, and the Duty<7:0> code value is reduced by the step size ΔDuty. The DAC output V Duty Decrease, PWM pulse width adjustment comparator output gate control signal Ctrl Gate The rising edge is delayed and the pulse width duty cycle is reduced. SWH , D SWL ] is 00, representing the conduction edge moment v sw The voltage is less than 0, the conduction edge is delayed, the pulse width is small, and the Duty<7:0> code value is increased by the step size ΔDuty. The DAC output V Duty Increase, PWM pulse width adjustment comparator output gate control signal Ctrl Gate The rising edge is advanced and the pulse width duty cycle increases. SWH , D SWL ] is 00, representing the conduction edge moment v sw The voltage is approximately 0, meeting the ZVS condition, and the active power tube SW is in a soft switching state. At this time, the power conversion efficiency is the highest, and high-efficiency adjustment is completed.

[0091] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0092] The present invention proposes a reconfigurable single-stage resonant Class E regulation rectifier. Utilizing the proposed control adjustment loop consisting of efficiency correction and load voltage modulator in a single-stage power stage structure, the invention achieves single-stage integration of high-efficiency rectification and output voltage regulation functions. Furthermore, an adaptive control-based vector modulation direction generation algorithm is proposed for application in the efficiency correction and load voltage modulation paths.

[0093] The reconfigurable single-stage resonant class E regulating rectifier designed in the present invention adopts 0.18μm standard CMOS process for circuit design and is verified by simulation.

[0094] See also Figure 7 ,,When the output voltage is regulated at 5V, the transient response time of switching from a light load of 5W to a heavy load of 8.4W is about 190 to 250μs.

[0095] See also Figure 8 The entire circuit operates at a resonant frequency of 6.78MHz and is compatible with a resonant frequency of 13.56MHz. The secondary equivalent input peak current is 3A, and the rectifier output DC level can be stabilized at three gears: 4.2V / 5V / 5.5V. The peak output power is 8.4W@5V and 10.03W@5.5V, and the peak AC-to-DC power conversion efficiency is 96.1%@6.57W&5V. In the output power range of 3.5 to 10.03W, the average power conversion efficiency is >90%.

[0096] Compared with the traditional D-type R 3 The resonant adjustment of the unipolar rectifier has smaller conduction loss, so the secondary average power conversion efficiency is effectively increased. At the same time, due to the configurability of the capacitor array, different load voltage outputs can be achieved under wide load resistance changes.

[0097] In summary, the present invention provides a reconfigurable single-stage resonant Class E adjustment rectifier, which adopts a mixed digital-analog feedback loop form to realize pulse width modulation of the gate signal and capacitance adjustment of the reconfigurable parallel capacitor array, thereby realizing efficiency calibration and output load voltage adjustment of the reconfigurable Class E main power structure. Compared with the traditional Class D multi-stage adjustment rectifier, the structure further reduces power consumption, simplifies the design, and the design of the digital algorithm is more conducive to later functional debugging; secondly, the capacitor array adopts an off-chip implementation method to make the array configuration have multiple possibilities, and high-efficiency rectification under different power load ranges can be achieved by reconfiguring the outside of the capacitor array.

[0098] The above content is only for explaining the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A reconfigurable single-stage resonant Class E rectifier, characterized in that: Including reconstructed E-class rectifier main power circuit and efficiency correction & load voltage modulator, the reconstructed E-class rectifier main power circuit adopts E-class rectifier structure, through active power tube and passive structure and load R L The connection rectifies the AC input energy driven by the secondary current source into DC and outputs it; the efficiency correction & load voltage modulator provides the reconstruction capacitor array switch control signal to the reconstructible Class E rectifier main power circuit, and also provides the pulse width modulated active power tube gate control signal; The reconfigurable class E rectifier main power circuit includes an active power tube SW and a reconfigurable parallel capacitor array C. P , load capacitance C L and filter inductor L f , active power tube SW, reconfigurable parallel capacitor array and load capacitor C L The filter inductor L is connected in parallel at both ends of the input equivalent AC source. f In series with the reconfigurable parallel capacitor array and the load capacitor C L Between the drain end of the active power tube SW and the load R L The positive end of the efficiency correction & load voltage modulator is connected to the sampling input end of the efficiency correction & load voltage modulator respectively. The efficiency correction & load voltage modulator is based on the drain voltage v of the active power tube SW. sw and load R L The DC voltage V REC As a basis for judgment, a gate control signal Ctrl is generated to control the active power tube SW switch. Gate and reconfigurable capacitor array control signal Ctrl CP [5:0]; The efficiency correction & load voltage modulator includes two circuit paths, a sampling clock generator and an asynchronous reset signal generator; the two circuit paths are respectively the reconfigurable capacitor array control signal Ctrl CP [5:0] Generates and drives the channel and gate control signal Ctrl Gate Pulse width modulation generation and drive path, capacitor array control signal generation and drive path to reconfigurable Class E rectifier main power circuit output load R L The upper analog domain output rectified voltage V REC As the sampling input signal, the reconfigurable capacitor array control signal Ctrl CP [5:0] is output to the gate terminal of the MOS switch of the capacitor array of the reconfigurable Class E rectifier main power circuit; The gate control signal pulse width modulation is generated and driven to reconfigure the active power tube SW drain voltage v of the E-class rectifier main power circuit. sw As the sampling input signal, the gate control signal Ctrl is finally generated Gate Output to the gate terminal of the active power tube SW to control its on and off; The sampling clock generator is based on V REC The voltage generates the NRST reset signal, which is provided to the two circuit paths and the sampling clock generator as the reset control signal. When the NRST reset signal is low, the reconfigurable capacitor array control signal Ctrl CP The code value of [5:0] is cleared to zero, and the capacitance of the reconstructed parallel capacitor array is C Px At the same time, the gate control signal pulse width modulation generation and the vector modulation direction generation algorithm in the drive path output control code Duty<7:0> half of the maximum code value, so that the gate control signal Ctrl Gate The duty cycle is 50%, and the sampling clock generator generates the gate control signal Ctrl Gate As input, it generates the sampling clock CLK for the capacitor array control signal generation and drive path after frequency division and delay. REC The gate control signal pulse width modulation generates and drives the sampling clock CLK of the path ON .

2. The reconfigurable single-stage resonant Class E regulating rectifier according to claim 1, characterized in that: Reconfigurable parallel capacitor array C P Includes six groups of MOS switches SW Ci , six groups of MOS switches SW Ci The source of the six MOS switches SW is connected to the ground level. Ci The drain and six capacitors C Pi The negative connection of six capacitors C Pi The positive terminal is connected to the drain of the active power tube SW; six groups of MOS switches SW Ci and the corresponding capacitance C Pi The six-bit switch-controlled capacitor array is connected in series and then connected in parallel with the fixed capacitor CPx at the input equivalent AC source AC end. The reconfigurable capacitor array control signal Ctrl is generated by the efficiency correction & load voltage modulator. CP [5:0] for six groups of MOS switches SW Ci The gate end is controlled to realize the capacitance control of the six-bit switch-controlled capacitor array.

3. The reconfigurable single-stage resonant Class E regulating rectifier according to claim 2, characterized in that: Reconfigurable parallel capacitor array C P The capacitance is specifically: C P =C Px +Σ2 i Ctrl CP [i]C P0 Among them, C P0 is the unit capacitance value, Ctrl CP [i] is represented by a digital code 0 or 1, i = 0, 1, 2, 3, 4, 5; Reconfigurable parallel capacitor array C P Fixed capacitor C Px The satisfying relationship is as follows: C Px >>C Drain,P Among them, C Drain,P It is the source-drain parasitic capacitance of the active power tube.

4. The reconfigurable single-stage resonant Class E regulating rectifier according to claim 1, characterized in that: The circuit parameter characteristics of the Class E rectifier structure meet the following constraints: The initial phase φ is: Filter inductor L f The current flowing is equal to the output load R L The current on the REC ,satisfy: Resonant operating frequency ω, total capacitance of reconfigurable capacitor array C P and the load resistor R L The product of ωC P R L satisfy: Load R L The DC voltage V REC satisfy: Where DT is the gate control signal duty cycle, I m Enter the peak value of the secondary sinusoidal AC current.

5. The reconfigurable single-stage resonant Class E regulating rectifier according to claim 1, characterized in that: The vector modulation direction generation algorithm is as follows: For [D HH , D H , D L , D LL ]-Ctrl CP [5:0] Vector modulation direction generation algorithm, at input [D HH , D H , D L , D LL ] is 1111, the output V REC In the large window [V RECHH , V RECLL ]; the window is above the sampling clock CLK REC When the edge comes, the capacitor array control signal Ctrl can be reconfigured CP The code value of [5:0] increases by the binary value ΔCtrl relative to the previous sampling clock cycle. CP =3'b100; When inputting [D HH , D H , D L , D LL ] is 0000, the output V REC In the large window [V RECHH , V RECLL ], the window is under the sampling clock CLK REC When the edge comes, the capacitor array control signal Ctrl can be reconfigured CP [5:0] The code value decreases by ΔCtrl relative to the previous cycle CP =3'b100; When inputting [D HH , D H , D L , D LL ] is 0111, the output V REC In the small window [V RECH , V RECL ] above, in the large window high level V RECHH Below, the window is at the sampling clock CLK REC When the edge comes, the capacitor array control signal Ctrl can be reconfigured CP The code value of [5:0] increases by ΔCtrl relative to the previous cycle CP =1'b1; When inputting [D HH , D H , D L , D LL ] is 0001, the output V REC In the small window [V RECH , V RECL ], in the large window low level V RECLL Above, the window is at the sampling clock CLK REC When the edge comes, the capacitor array control signal Ctrl can be reconfigured CP The code value of [5:0] decreases by ΔCtrl relative to the previous cycle CP =1'b1; When inputting [D HH , D H , D L , D LL ] is 0011, the output V REC In the small window [V RECH , V RECL ], the window is within the sampling clock CLK REC When the edge comes, the capacitor array control signal Ctrl can be reconfigured CP The code value of [5:0] remains unchanged relative to the previous sampling clock cycle. P The capacitance value remains unchanged. When the set signal NRST is at a low level, the capacitor array control signal Ctrl can be reconfigured. CP The code value of [5:0] is set to 000000, C P The capacitance is set to a fixed capacitor C Px , after the circuit stabilizes V REC is the maximum output voltage; For [D SWH , D SWL ]-Duty<7:0> vector modulation direction generation algorithm, only one step size ΔDuty=2'b100, according to the gate signal pulse width modulation generator and the boost sampling in the drive path to obtain the source and drain V SWO With window [V WH , V SWL ] determines the output code value Duty<7:0> adjustment direction: When inputting [D SWH , D SWL ] is 11, the conduction edge moment v sw If the voltage is greater than 0, the Duty<7:0> code value is reduced by the step size ΔDuty, and the DAC output V Duty Decrease, PWM pulse width adjustment comparator output gate control signal Ctrl Gate The rising edge is delayed and the pulse duty cycle is reduced; When inputting [D SWH , D SWL ] is 00, the conduction edge moment v sw The voltage is less than 0, the conduction edge is delayed, and the Duty<7:0> code value is increased by the step size ΔDuty. The DAC output V Duty Increase, PWM pulse width adjustment comparator output gate control signal Ctrl Gate The rising edge is advanced and the pulse width duty cycle increases; When inputting [D SWH , D SWL ] is 00, the conduction edge moment v sw The voltage is 0, meeting the ZVS condition, the active power tube SW is in the soft switching state, and high-efficiency adjustment is completed.

6. The reconfigurable single-stage resonant Class E regulating rectifier according to claim 1, characterized in that: The specific signal transmission and circuit connection structure of the capacitor array control signal generation and drive path is as follows: Reconfigurable Class E rectifier main power circuit output voltage V by sampling with resistor REC The voltage sampled by the resistor is compared with two sets of window voltages [V RECHH , V RECLL ] and [V RECH , V RECL ] to compare the output voltage V REC The analog domain voltage is converted into a digital domain code value [D HH , D LL ] and [D H , D L ]; Use the two sets of digital comparison outputs as the input of the vector modulation direction generation algorithm, and adjust the clock CLK in the vector modulation generation method REC When the edge comes, according to [D HH , D H , D L , D LL ] input code value, and the six-bit reconfigurable capacitor array control signal Ctrl is determined according to the vector modulation direction generation algorithm CP [5:0] The code value adjustment step size is increased or decreased with two different step sizes, and then the capacitor array control tube is turned on or off by driving the control capacitor array to realize the reconfigurable capacitor array control signal C P [5:0] Capacitance change.

7. The reconfigurable single-stage resonant Class E regulating rectifier according to claim 1, characterized in that: The specific signal transmission and circuit connection structure of the gate control signal pulse width modulation and drive path are as follows: Gate control signal Ctrl Gate The conduction clock CLK generated by the sampling clock generator ON When the edge comes, v sw The instantaneous source-drain voltage V of this cycle obtained by boost sampling SWO , with the reference voltage window at ground voltage [V SWH V SWL ]Compare to get the comparison result code value [D SWH , D SWL ], according to [D SWH , D SWL ], the vector modulation direction generation algorithm uses a fixed step size adjustment algorithm to output the code value of Duty<7:0>, and the code value is decoded by the 8-bit DAC to obtain a voltage value V that changes according to the comparison result. Duty The corresponding level is compared with the ramp signal through the PWM comparator to obtain a square wave signal with a rising edge that changes successively. After driving, the gate control signal Ctrl with pulse width and rising edge modulated is obtained. Gate .

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