Circuit structure for eliminating power-down noise of class-d audio power amplifier and circuit system thereof

Abstract

This invention relates to a circuit structure for eliminating the popping sound of a Class D audio amplifier during power loss. The circuit structure includes a voltage detection logic circuit module connected to both an operational amplifier input voltage logic selection circuit module and a pull-down current logic selection circuit module. The pull-down current logic selection circuit module is connected to a clamping voltage logic circuit module, which in turn is connected to an external Class D audio amplifier module. This invention also relates to a Class D audio amplifier circuit system for eliminating the popping sound during power loss. By employing the circuit structure and corresponding system of this invention, without altering the power-on and power-off sequence of existing amplifiers, and by detecting the high and low power supply voltage states, different DC voltages and corresponding pull-down currents are set at the amplifier input terminals. This solves the problem of the popping sound during power loss in mainstream amplifiers on the market when the minimum operating voltage is low, thus improving the user's auditory experience.

Description

Technical Field

[0001] This invention relates to the field of audio power amplifier technology, and more particularly to the field of audio processing technology for Class D power amplifiers, specifically to a circuit structure and circuit system for eliminating the popping sound when a Class D audio power amplifier loses power. Background Technology

[0002] For the circuit structure of existing Class D audio power amplifier modules, please refer to [link / reference]. Figure 1 As shown, it mainly consists of a preamplifier, a triangular wave generation circuit, a pulse width modulator, a shaping circuit, and a drive circuit. When an audio signal is input at the input INP terminal, the audio signal is amplified by two stages of differential operational amplifiers and compared with the triangular wave generated by the OSC oscillation module to obtain high-frequency PWM pulse signals with different pulse widths. After the pulse signal is shaped by the shaping circuit, a series of pulse signals are output to drive the power switching transistors to turn on in turn. Since the final output of the Class D power amplifier is a square wave signal, a low-pass filter is connected in front of the speaker to restore the audio signal in order to extract the audio signal.

[0003] The popping sound from an audio amplifier when it loses power is generally believed to be caused by a sudden voltage jump in the speaker or headphones, producing a popping sound that is audible to the human ear within the audio range. This sound is undesirable to users. Traditional methods for suppressing popping include adding a filter capacitor to the BYPASS bias voltage terminal to mitigate the voltage jump, but this method only reduces the popping sound to a certain extent and its effect is not particularly satisfactory. A second method involves adding popping suppression structures around the chip, such as adding appropriate resistors and capacitors at the chip's input terminals to reduce input voltage fluctuations. This method significantly increases design costs, and some customers are unwilling to change the external parameters of the circuit. A third method involves muting the I / O ports or shutting down the audio amplifier before turning off the chip's power supply when the amplifier loses power. However, this type of system cannot predict the audio system's power loss in advance, and therefore cannot eliminate the popping sound from the main chip manifesting at the audio amplifier's output when the system loses power. The fourth method is to set the low-voltage protection point of the circuit higher. Since the popping sound is generated when the power supply voltage drops to a certain value during the power outage, this method is only applicable to circuits where the low-voltage protection point is higher than the popping sound generation point. This method can also eliminate the popping sound, but its biggest drawback is that it limits the low-voltage application range of the circuit. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a simple and effective circuit structure and system for eliminating the popping sound of a Class D audio amplifier when it loses power.

[0005] To achieve the above objectives, the circuit structure for eliminating the popping sound of Class D audio amplifier power loss in this invention is as follows:

[0006] The circuit structure for eliminating the popping sound of a Class D audio amplifier during power loss includes a voltage detection logic circuit module, an operational amplifier input voltage logic selection circuit module, a pull-down current logic selection circuit module, and a clamping voltage logic circuit module. Its main features are as follows: the voltage detection logic circuit module includes a voltage detection logic unit and an inverter. The first input terminal of the voltage detection logic unit is connected to the power supply voltage terminal, the second input terminal is connected to the third reference voltage terminal, and the output terminal of the voltage detection logic unit is connected to the input terminal of the inverter. The output terminal of the inverter is connected to the operational amplifier input voltage logic selection circuit module. The output terminal of the operational amplifier input voltage logic selection circuit module is connected to the third input terminal of the clamping voltage logic circuit module. The input terminal of the pull-down current logic selection circuit module is connected to the pull-down current unit, and the output terminal of the pull-down current logic selection circuit module is connected to the fourth input terminal of the clamping voltage logic circuit module. The output terminal of the clamping voltage logic circuit module is connected to an external Class D audio amplifier module.

[0007] Preferably, the voltage detection logic circuit module is used to detect and compare the magnitude of the power supply voltage with that of the third reference voltage terminal;

[0008] The op-amp input voltage logic selection circuit module selects the output of the corresponding op-amp input voltage logic selection circuit unit as the op-amp input voltage of the circuit structure based on the detection and comparison results of the voltage detection logic circuit module.

[0009] The pull-down current logic selection circuit module selects the output of the corresponding pull-down current unit as the pull-down current of the circuit structure based on the detection result of the voltage detection logic circuit module.

[0010] The clamping voltage logic circuit module is used to ensure that the op-amp input midpoint of the circuit structure is stable at the op-amp input voltage.

[0011] Preferably, the operational amplifier input voltage logic selection circuit module includes a first operational amplifier input voltage logic selection circuit unit, a second operational amplifier input voltage logic selection circuit unit, a first transmission gate, and a second transmission gate. The first operational amplifier input voltage logic selection circuit unit includes a first operational amplifier input voltage logic selection output terminal for outputting the first operational amplifier input voltage. The first operational amplifier input voltage logic selection output terminal is disposed between a third resistor and a fourth resistor and is connected to the input terminal of the first transmission gate.

[0012] More preferably, the second operational amplifier input voltage logic selection circuit unit includes a second operational amplifier input voltage logic selection output terminal for outputting a stable voltage VREF2. The second operational amplifier input voltage logic selection output terminal is disposed between the first end of the fifth resistor and the positive terminal of the first diode and connected to the input terminal of the second transmission gate. The second end of the fifth resistor is connected to the first reference current source, and the negative terminal of the first diode is connected to the positive terminal of the second diode.

[0013] Preferably, the first transmission gate includes a fifth PMOS field-effect transistor and a fifth NMOS field-effect transistor, wherein the drain of the fifth PMOS field-effect transistor and the source of the fifth NMOS field-effect transistor are both connected to the input terminal of the first transmission gate.

[0014] Preferably, the second transmission gate includes a sixth PMOS field-effect transistor and a sixth NMOS field-effect transistor, with the drain of the sixth PMOS field-effect transistor and the source of the sixth NMOS field-effect transistor both connected to the input terminal of the second transmission gate; the output terminal of the first transmission gate is connected to the output terminal of the second transmission gate for outputting the operational amplifier input voltage.

[0015] Preferably, the pull-down current logic selection circuit module includes a pull-down current unit, a third transmission gate, and a fourth transmission gate. The pull-down current unit includes a first pull-down current unit and a second pull-down current unit. The first pull-down current unit includes a pull-down current subunit. The first input terminal of the pull-down current subunit is connected to the power supply voltage, the second input terminal of the pull-down current subunit is connected to the chip voltage, and the output terminal of the pull-down current subunit is used to output the first pull-down current.

[0016] Preferably, the second pull-down current unit includes a follower, an operational amplifier, a third NMOS field-effect transistor, and a current mirror element group. The positive input terminal of the follower is connected between the first resistor and the second resistor. The inverting input terminal and the output terminal of the follower are connected together to the positive terminal of the third diode. The negative terminal of the third diode is connected to the positive terminal of the fourth diode. The negative terminal of the fourth diode is connected between the second reference current source and the positive input terminal of the operational amplifier. The inverting input terminal of the operational amplifier is connected between the source of the third NMOS field-effect transistor and the feedback resistor. The output terminal of the operational amplifier is connected to the gate of the third NMOS field-effect transistor. The drain of the third NMOS field-effect transistor is connected to the current mirror element group. The input terminal of the third transmission gate is connected to the output terminal of the first pull-down current unit for outputting the first pull-down current Idown1. The input terminal of the fourth transmission gate is connected to the... The second pull-down current unit is connected to the output terminal of the second pull-down current Idown2. The third transmission gate includes a seventh PMOS field-effect transistor and a seventh NMOS field-effect transistor. The drain of the seventh PMOS field-effect transistor and the source of the seventh NMOS field-effect transistor are both connected to the input terminal of the third transmission gate, and the source of the seventh PMOS field-effect transistor and the drain of the seventh NMOS field-effect transistor are both connected to the output terminal of the third transmission gate. The fourth transmission gate includes an eighth PMOS field-effect transistor and an eighth NMOS field-effect transistor. The drain of the eighth PMOS field-effect transistor and the source of the eighth NMOS field-effect transistor are both connected to the input terminal of the fourth transmission gate, and the source of the eighth PMOS field-effect transistor and the drain of the eighth NMOS field-effect transistor are both connected to the output terminal of the fourth transmission gate. The output terminal of the third transmission gate is connected to the output terminal of the fourth transmission gate for outputting pull-down current.

[0017] Preferably, the current mirror element group includes a first PMOS field-effect transistor, a second PMOS field-effect transistor, a third PMOS field-effect transistor, and a fourth PMOS field-effect transistor. The drain of the first PMOS field-effect transistor is connected to the source of the second PMOS field-effect transistor, the drain of the second PMOS field-effect transistor is connected to the drain of the third PMOS field-effect transistor, the gate of the first PMOS field-effect transistor is connected to the gate of the third PMOS field-effect transistor, the gate of the second PMOS field-effect transistor is connected to the gate of the fourth PMOS field-effect transistor, the drain of the third PMOS field-effect transistor is connected to the source of the fourth PMOS field-effect transistor, and the sources of the first and third PMOS field-effect transistors are both connected to the power supply voltage.

[0018] Preferably, the first input terminal a5 of the clamping voltage logic circuit module is connected to the second terminal of the positive input terminal INP of the Class D audio power amplifier circuit module, the first input terminal a6 of the clamping voltage logic circuit module is connected to the second terminal of the negative input terminal INN of the Class D audio power amplifier circuit module, the third input terminal of the clamping voltage logic circuit module is connected to the output terminal of the operational amplifier input voltage logic selection circuit module, and the fourth input terminal of the clamping voltage logic circuit module is connected to the output terminal of the pull-down current logic selection circuit module.

[0019] The Class D audio power amplifier circuit system with the above-mentioned circuit structure for eliminating power-off popping noise is characterized in that the circuit system includes a Class D audio power amplifier module, which includes a first pre-differential amplifier, a second pre-differential amplifier, a triangular wave generation circuit unit, a first pulse width modulator, a second pulse width modulator, a shaping circuit unit, a first driving circuit, a second driving circuit, a low-pass filter, and a speaker.

[0020] In this configuration, the positive input terminal of the first preamplifier differential amplifier is connected to the second terminal of the first input terminal a5 of the clamping voltage logic circuit module; the inverting input terminal of the first preamplifier differential amplifier is connected to the second terminal of the second input terminal a6 of the clamping voltage logic circuit module; the inverting output terminal of the first preamplifier differential amplifier is connected to the positive input terminal of the second preamplifier differential amplifier; the positive output terminal of the first preamplifier differential amplifier is connected to the inverting input terminal of the second preamplifier differential amplifier; the inverting output terminal of the second preamplifier differential amplifier is connected to the positive input terminal of the first pulse width modulator; the positive output terminal of the second preamplifier differential amplifier is connected to the positive input terminal of the second pulse width modulator; and the inverting input terminal of the first pulse width modulator is connected to the second input terminal of the second pulse width modulator. The inverting inputs of both pulse width modulators are connected to the triangular wave generating circuit unit. The output of the first pulse width modulator is connected to the first input of the shaping circuit unit. The output of the second pulse width modulator is connected to the second input of the shaping circuit unit. The first output of the shaping circuit unit is connected to the input of the first driving circuit. The second output of the shaping circuit unit is connected to the input of the second driving circuit. The output of the first driving circuit is connected between the output of the Class D audio amplifier module (OUTPL) and the low-pass filter. The output of the second driving circuit is connected between the output of the Class D audio amplifier module (OUTNL) and the low-pass filter. The speaker is connected to the low-pass filter.

[0021] Furthermore, the first terminal of the positive input terminal INP of the Class D audio amplifier module is connected to the second terminal of the first DC blocking capacitor. The first terminal of the first DC blocking capacitor is connected to resistor Ra and resistor Rb in sequence to ground. The first terminal of the negative input terminal INN of the Class D audio amplifier module is connected to the first terminal of the second DC blocking capacitor. The second terminal of the second DC blocking capacitor is grounded.

[0022] The present invention employs a circuit structure and system for eliminating the popping sound of Class D audio amplifiers during power-down. By designing a fixed DC voltage at the amplifier input terminal and a new pull-down current logic selection circuit, without changing the existing power-on and power-off sequence of the amplifier, different DC voltages and corresponding pull-down currents are set at the amplifier input terminal based on the detection of high and low power supply voltages. This ensures that the feedback current and pull-down current remain constant and equal during power-down, solving the popping sound problem caused by sudden power failure when the minimum operating voltage of mainstream amplifiers on the market is as low as 3.5V. The method is simple, feasible, and widely applicable, suitable for mainstream Class D amplifier circuits on the market. For customers using amplifier circuits powered by a single lithium battery, it not only meets low-voltage requirements but also greatly improves the auditory experience. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of a Class D audio power amplifier module in the prior art.

[0024] Figure 2 This is a circuit structure diagram illustrating the overall implementation process of the circuit system for eliminating the popping sound when a Class D audio amplifier loses power, as described in this invention.

[0025] Figure 3 This is a schematic diagram of the structure of the first operational amplifier input voltage logic selection circuit unit and the second operational amplifier input voltage logic selection circuit unit of the present invention.

[0026] Figure 4 This is a schematic diagram of the operational amplifier input voltage logic selection circuit module of the present invention.

[0027] Figure 5 This is a schematic diagram of the pull-down current logic selection circuit module of the present invention.

[0028] Figure 6 This is a schematic diagram of the pull-down current unit of the present invention.

[0029] Figure 7 This is a schematic diagram of the clamping voltage logic circuit module of the present invention.

[0030] Figure 8 This is a schematic diagram of the structure of the Class D audio amplifier application of the present invention.

[0031] Figure 9A schematic diagram of the voltage difference component that generates the power-down popping sound in a Class D audio power amplifier circuit structure using existing technology.

[0032] Figure 10 This is a schematic diagram of the voltage difference component that generates the power-down popping sound using the Class D audio power amplifier circuit structure of the present invention. Detailed Implementation

[0033] To more clearly describe the technical content of the present invention, the following description is provided in conjunction with specific embodiments.

[0034] Before detailing embodiments of the invention, it should be noted that, hereinafter, relational terms such as "first" and "second" are used merely to distinguish one entity or action from another, and do not necessarily require or imply any actual such relationship or order between such entities or actions. The terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, thereby causing a process, method, article, or apparatus that comprises a list of elements to include not only those elements but also other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0035] Please see Figure 2 As shown, the circuit structure for eliminating the popping sound of a Class D audio amplifier during power loss includes a voltage detection logic circuit module, an operational amplifier input voltage logic selection circuit module, a pull-down current logic selection circuit module, and a clamping voltage logic circuit module. The voltage detection logic circuit module includes a voltage detection logic unit LOG1 and an inverter. The first input terminal of the voltage detection logic unit LOG1 is connected to the power supply voltage terminal VCC, the second input terminal of the voltage detection logic unit LOG1 is connected to the third reference voltage terminal VREF3, the output terminal of the voltage detection logic unit LOG1 is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the operational amplifier input voltage logic selection circuit module. The output terminal of the operational amplifier input voltage logic selection circuit module is connected to the third input terminal of the clamping voltage logic circuit module, which is a fixed voltage V0. The input terminal of the pull-down current logic selection circuit module is connected to a pull-down current unit, the output terminal of the pull-down current logic selection circuit module is connected to the fourth input terminal Idown of the clamping voltage logic circuit module, and the output terminal of the clamping voltage logic circuit module is connected to an external Class D audio amplifier module.

[0036] The voltage detection logic circuit module is used to detect and compare the power supply voltage VCC with the third reference voltage terminal VREF3.

[0037] The op-amp input voltage logic selection circuit module selects the output of the corresponding op-amp input voltage logic selection circuit unit as the op-amp input voltage of the circuit structure based on the detection and comparison results of the voltage detection logic circuit module.

[0038] The pull-down current logic selection circuit module selects the output of the corresponding pull-down current unit as the pull-down current of the circuit structure based on the detection result of the voltage detection logic circuit module.

[0039] The clamping voltage logic circuit module is used to ensure that the op-amp input midpoint of the circuit structure is stable at the op-amp input voltage.

[0040] Please see Figure 3 and Figure 4 As shown, in a preferred embodiment of the present invention, the operational amplifier input voltage logic selection circuit module includes a first operational amplifier input voltage logic selection circuit unit, a second operational amplifier input voltage logic selection circuit unit, a first transmission gate, and a second transmission gate. The first operational amplifier input voltage logic selection circuit unit includes a first operational amplifier input voltage logic selection output terminal for outputting the first operational amplifier input voltage VREF1. The first operational amplifier input voltage logic selection output terminal is disposed between the third resistor R3 and the fourth resistor R4 and connected to the input terminal of the first transmission gate. The second operational amplifier input voltage logic selection circuit unit includes a second operational amplifier input voltage logic selection output terminal for outputting a stable voltage VREF2. The second operational amplifier input voltage logic selection output terminal is disposed between the first end of the fifth resistor R5 and the positive terminal of the first diode D1 and connected to the input terminal of the first transmission gate. The input terminal of the second transmission gate is connected to the first transmission gate, the second terminal of the fifth resistor R5 is connected to the first reference current source I0, and the cathode of the first diode D1 is connected to the anode of the second diode D2. The first transmission gate includes a fifth PMOS field-effect transistor P5 and a fifth NMOS field-effect transistor N5, with the drain of the fifth PMOS field-effect transistor P5 and the source of the fifth NMOS field-effect transistor N5 both connected to the input terminal of the first transmission gate. The second transmission gate includes a sixth PMOS field-effect transistor P6 and a sixth NMOS field-effect transistor N6, with the drain of the sixth PMOS field-effect transistor P6 and the source of the sixth NMOS field-effect transistor N6 both connected to the input terminal of the second transmission gate. The output terminal of the first transmission gate is connected to the output terminal of the second transmission gate for outputting the operational amplifier input voltage.

[0041] Please see Figure 5 and Figure 6As shown, in a preferred embodiment of the present invention, the pull-down current logic selection circuit module includes a pull-down current unit, a third transmission gate, and a fourth transmission gate. The pull-down current unit includes a first pull-down current unit and a second pull-down current unit. The first pull-down current unit includes a pull-down current subunit (Pull-down Current). The first input terminal of the pull-down current subunit (Pull-down Current) is connected to the power supply voltage VCC, and the second input terminal is connected to the chip voltage VDD. The output terminal of Current is used to output the first pull-down current Idown1; the second pull-down current unit includes a follower FOLLOW1, an operational amplifier AMP, a third NMOS field-effect transistor N3, and a current mirror element group. The positive input terminal of the follower FOLLOW1 is connected between the first resistor R1 and the second resistor R2. The inverting input terminal and the output terminal of the follower FOLLOW1 are connected together to the positive terminal of the third diode D3. The negative terminal of the third diode D3 is connected to the positive terminal of the fourth diode D4. The negative terminal of the fourth diode D4 is connected between the second reference current source I1 and the positive input terminal of the operational amplifier AMP. The inverting input terminal of the operational amplifier AMP is connected between the source of the third NMOS field-effect transistor N3 and the feedback resistor Rf. The output terminal of the operational amplifier AMP is connected to the gate of the third NMOS field-effect transistor N3. The drain of the third NMOS field-effect transistor N3 is connected to the current mirror element group; the input terminal of the third transmission gate and the first pull-down current unit are used to output the first pull-down current Id. The output terminal of own1 is connected to the third transmission gate. The input terminal of the fourth transmission gate is connected to the output terminal of the second pull-down current unit for outputting the second pull-down current Idown2. The third transmission gate includes a seventh PMOS field-effect transistor P7 and a seventh NMOS field-effect transistor N7. The drain of the seventh PMOS field-effect transistor P7 and the source of the seventh NMOS field-effect transistor N7 are both connected to the input terminal of the third transmission gate. The source of the seventh PMOS field-effect transistor P7 and the drain of the seventh NMOS field-effect transistor N7 are both connected to the output terminal of the third transmission gate. The fourth transmission gate includes an eighth PMOS field-effect transistor P8 and an eighth NMOS field-effect transistor N8. The drain of the eighth PMOS field-effect transistor P8 and the source of the eighth NMOS field-effect transistor N8 are both connected to the input terminal of the fourth transmission gate. The source of the eighth PMOS field-effect transistor P8 and the drain of the eighth NMOS field-effect transistor N8 are both connected to the output terminal of the fourth transmission gate. The output terminal of the third transmission gate is connected to the output terminal of the fourth transmission gate for outputting the pull-down current.

[0042] In a preferred embodiment of the present invention, the current mirror element group includes a first PMOS field-effect transistor P1, a second PMOS field-effect transistor P2, a third PMOS field-effect transistor P3, and a fourth PMOS field-effect transistor P4. The drain of the first PMOS field-effect transistor P1 is connected to the source of the second PMOS field-effect transistor P2, the drain of the second PMOS field-effect transistor P2 is connected to the drain of the third NMOS field-effect transistor N3, the gate of the first PMOS field-effect transistor P1 is connected to the gate of the third PMOS field-effect transistor P3, the gate of the second PMOS field-effect transistor P2 is connected to the gate of the fourth PMOS field-effect transistor P4, the drain of the third PMOS field-effect transistor P3 is connected to the source of the fourth PMOS field-effect transistor P4, and the sources of the first PMOS field-effect transistor P1 and the third PMOS field-effect transistor P3 are both connected to the power supply voltage VCC.

[0043] Please see Figure 7 As shown, in a preferred embodiment of the present invention, the first input terminal a5 of the clamping voltage logic circuit module is connected to the second terminal of the positive input terminal INP of the Class D audio power amplifier circuit module; the first input terminal a6 of the clamping voltage logic circuit module is connected to the second terminal of the negative input terminal INN of the Class D audio power amplifier circuit module; the third input terminal of the clamping voltage logic circuit module is connected to the output terminal of the operational amplifier input voltage logic selection circuit module; and the fourth input terminal of the clamping voltage logic circuit module is connected to the output terminal of the pull-down current logic selection circuit module.

[0044] Please see Figure 2 and Figure 8As shown in the preferred embodiment of the present invention, this Class D audio amplifier circuit system for eliminating popping noise includes a Class D audio amplifier module comprising a first preamplifier AMP1, a second preamplifier AMP2, a triangular wave generation circuit unit OSC, a first pulse width modulator COMP1, a second pulse width modulator COMP2, a shaping circuit unit LOG, a first driver circuit Drive1, a second driver circuit Drive2, a low-pass filter Filter, and a speaker. The positive input terminal of the first preamplifier AMP1 is connected to the second terminal of the first input terminal a5 of the clamping voltage logic circuit module. The inverting input of the first preamplifier AMP1 is connected to the second input a6 of the clamping voltage logic circuit module. The inverting output of the first preamplifier AMP1 is connected to the non-inverting input of the second preamplifier AMP2. The non-inverting output of the first preamplifier AMP1 is connected to the inverting input of the second preamplifier AMP2. The inverting output of the second preamplifier AMP2 is connected to the non-inverting input of the first pulse width modulator COMP1. The non-inverting output of the second preamplifier AMP2 is connected to the non-inverting input of the second pulse width modulator COMP2. The inverting input terminals of the first pulse width modulator COMP1 and the second pulse width modulator COMP2 are both connected to the triangular wave generating circuit unit OSC. The output terminal of the first pulse width modulator COMP1 is connected to the first input terminal of the shaping circuit unit LOG. The output terminal of the second pulse width modulator COMP2 is connected to the second input terminal of the shaping circuit unit LOG. The first output terminal of the shaping circuit unit LOG is connected to the input terminal of the first driving circuit Drive1. The second output terminal of the shaping circuit unit LOG is connected to the input terminal of the second driving circuit Drive2. The output terminal of the first driving circuit Drive1... The output terminal is connected between the output terminal OUTPL of the Class D audio amplifier module and the low-pass filter. The output terminal of the second drive circuit Drive2 is connected between the output terminal OUTNL of the Class D audio amplifier module and the low-pass filter. The speaker is connected to the low-pass filter. The first terminal of the positive input terminal INP of the Class D audio amplifier module is connected to the second terminal of the first DC blocking capacitor C1. The first terminal of the first DC blocking capacitor C1 is connected to the ground via resistor Ra and resistor Rb. The first terminal of the negative input terminal INN of the Class D audio amplifier module is connected to the first terminal of the second DC blocking capacitor C2.The second terminal of the second DC blocking capacitor C2 is grounded.

[0045] In a preferred embodiment of the present invention, the Class D audio power amplifier uses a pulse width modulation (PWM) modulator, which compares an audio signal with a triangular wave to obtain a series of pulse signals of different widths. The midpoint potential of the triangular wave is set at 1 / 2 × VDD. If the midpoint of the output of the preamplifier is also set at 1 / 2 × VDD (VDD is the voltage generated internally by the chip, approximately 5V), when no audio signal is applied and the power amplifier circuit is in static operation, it outputs a square wave with a 50% duty cycle. Thus, the midpoint potential of the final output DC voltage is maintained at 1 / 2 × VCC. This DC voltage is output through OUTPL and OUUTNL, and fed back to the input terminals a5 and a6 through feedback resistors Rf1 and Rf2. Therefore, the feedback current is equal to (1 / 2 × VCC - 1 / 2 × VDD) / Rf.

[0046] The application diagram of the Class D audio amplifier of the present invention is shown below. Figure 8 As shown, in the power amplifier circuit, the INP and INN input terminals of the Class D audio power amplifier module are each coupled to the input pin through a DC blocking capacitor C1 and C2, respectively. The INN input terminal is connected to a capacitor C2 to ground, while the positive input terminal is used to apply the audio signal. The audio signal is connected to the input pin through the same DC blocking capacitor C1. When the power is suddenly cut off during the operation of the audio power amplifier, the DC potential 1 / 2 × VDD at the input terminal of the Class D audio power amplifier module is difficult to maintain at the ideal value because the internal feedback current is basically zero, making it difficult for the system to maintain a balanced state. Due to the difference in the external capacitors connected to the INP input and INN output terminals in actual applications (as shown in the dotted box in the figure), the voltage discharge rate at the op-amp input terminal is different, that is, a small voltage component appears at the input terminal. After being amplified by the system feedback gain, it is reflected at the output terminal, which is the so-called popping sound.

[0047] Therefore, when the operating voltage of the power amplifier circuit is low, such as VCC = 3.5V, it can be seen from the analysis that only when the pull-down current Idown of the power amplifier circuit equals the feedback current If, the input voltage of the Class D audio power amplifier module can be maintained at the ideal fixed voltage V0, where If = (1 / 2 × VCC - V0) / Rf.

[0048] In the existing technology, when the VCC power supply drops to almost equal to the VDD voltage, the feedback current of the system is almost zero. At this time, during the power-down process, the inconsistent discharge speed of the input capacitor will cause a slight fluctuation in the input voltage, which is equivalent to an AC signal appearing at the input. After gain adjustment, a popping sound is generated at the output.

[0049] Theoretically, a popping sound will only occur when the power supply voltage drops to 3V. Therefore, this technical solution sets the op-amp input voltage to 1.5V, which ensures that the pull-down current Idown is always equal to the feedback current If throughout the entire power-down process, thus avoiding disturbances in the input voltage and fully meeting the requirement of no popping sound when the power amplifier circuit is powered by a single lithium battery.

[0050] The working principle of the circuit structure for eliminating the popping sound of a Class D audio amplifier during power loss in this technical solution is as follows:

[0051] First, to detect the input voltage of the Class D audio amplifier module, a third reference voltage terminal VREF3 is set to 6V in the voltage detection logic circuit module. The externally input audio signal is input to the input port of the Class D audio amplifier module for voltage detection. If the detected power supply voltage of the audio signal is higher than 6V, the audio signal is input to the inverter through the voltage detection logic unit. At this time, the C port of the inverter outputs a high level, and the CN port outputs a low level. Then, the transmission gate 1 of the op-amp input voltage logic selection circuit module is turned on. That is, the fifth PMOS field-effect transistor P5 and the fifth NMOS field-effect transistor N5 are turned on, and the fixed voltage V0 selects VREF1. At the same time, the transmission gate 3 of the pull-down current logic selection circuit module is turned on, that is, the seventh PMOS field-effect transistor P7 and the seventh NMOS field-effect transistor N7 are turned on. The pull-down current logic selection circuit module selects the first operational amplifier input voltage logic selection circuit unit to output the first pull-down current Idown1 to the clamping voltage logic circuit module, so that the operational amplifier input voltage is stabilized at VREF1 (i.e., 1 / 2 × VDD); otherwise,

[0052] If the power supply voltage of the audio signal is detected to be lower than 6V, the C port of the inverter outputs a low level and the CN port outputs a high level. Then, the transmission gate 2 of the op-amp input voltage logic selection circuit module is turned on, that is, the sixth PMOS field-effect transistor P6 and the sixth NMOS field-effect transistor N6 are turned on, and the fixed voltage V0 voltage selection VREF2 is selected. At the same time, the transmission gate 4 of the pull-down current logic selection circuit module is turned on, that is, the eighth PMOS field-effect transistor P8 and the eighth NMOS field-effect transistor N8 are turned on. The pull-down current logic selection circuit module selects the second op-amp input voltage logic selection circuit unit to output the second pull-down current Idown2 to the clamping voltage logic circuit module, so that the op-amp input voltage is stabilized at the stable voltage VREF2.

[0053] The stable voltage VREF2 is formed by the first reference current source I0 flowing through the fifth resistor R5, which turns on the first diode D1 and the second diode D2 at the D1 terminal. It is approximately 1.5V.

[0054] In one specific embodiment of the present invention, when the power supply voltage is greater than 6V, an audio signal is input. After being detected by the voltage detection logic circuit module, the transmission gate 1 of the operational amplifier input voltage logic selection circuit module is turned on. Simultaneously, the pull-down current logic selection circuit module selects the first operational amplifier input voltage logic selection circuit unit to output the first pull-down current Idown1. The operational amplifier input voltage at the clamping voltage logic circuit module is VREF1 (i.e., 1 / 2 × VDD). At the same time, the pull-down current selection first operational amplifier input voltage logic selection circuit unit outputs the first pull-down current Idown1, i.e., Idown1 = (1 / 2 × VCC - VREF1) / Rf.

[0055] In another specific embodiment of the present invention, when the power supply voltage is less than 6V, an audio signal is input. After being detected by the voltage detection logic circuit module, the transmission gate 2 of the operational amplifier input voltage logic selection circuit module is turned on. Simultaneously, the pull-down current logic selection circuit module selects the second operational amplifier input voltage logic selection circuit unit to output the second pull-down current Idown2. The operational amplifier input voltage at the clamping voltage logic circuit module adopts a stable voltage VREF2 (i.e., 1.5V). At this time, the pull-down current selects the second operational amplifier input voltage logic selection circuit unit to output the second pull-down current Idown2.

[0056] The specific settings for the second pull-down current Idown2 are as follows:

[0057] In the second operational amplifier input voltage logic selection circuit unit, the first resistor R1 is set to equal the second resistor R2, the first reference current source I0 is equal to the second reference current source I1, and the signal outputs 1 / 2 × VCC voltage after passing through the follower FOLLOW1. The voltage drop generated by the second reference current source I1 across the third diode D3 and the fourth diode D4 is equal to the stable voltage VREF2 (where D1, D2, D3, and D4 have equal areas). Therefore, the voltage V1 at the non-inverting input terminal of the operational amplifier AMP is 1 / 2 × VCC - VREF2. The current generated by the V1 voltage across the feedback resistor Rf3 is converted into a pull-down current Idown2 after passing through the current mirror element group. Idown2 = (1 / 2 × VCC - VREF2) / Rf.

[0058] The clamping voltage logic circuit module described in this technical solution is used to ensure that the midpoint of the DC input voltage of the circuit system is stable at a fixed voltage V0, that is, to clamp the DC voltage at the input terminal. The prerequisite for the module to be effective is that the feedback current and the pull-down current must always exist and remain equal. If the feedback current is very small, the module will almost fail.

[0059] Please see Figure 9As shown, this is a schematic diagram of the power-down popping test results when the power supply voltage VCC is 12V in the prior art. It can be seen that when the Class D audio power amplifier circuit structure in the prior art is used, the power supply voltage VCC drops to about 4.7V, and the output produces a differential component.

[0060] Please see Figure 10 As shown, when the Class D audio power amplifier circuit structure of this technical solution is adopted, the power supply voltage VCC drops to about 3V before the differential component is generated.

[0061] It is understood that the same or similar parts in the above embodiments can be referred to each other, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0062] It should be noted that in the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means at least two.

[0063] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution device. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0064] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module.

[0065] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0066] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

[0067] This technical solution, without altering the existing circuit structure of the audio power amplifier, designs an additional set of pull-down current and clamping voltage to suit applications with power supply voltages below 6V. When the power supply voltage is above 6V, the original pull-down current and clamping voltage structure is still used. This ensures that when the chip suddenly loses power, the power amplifier's input DC voltage stabilizes at a fixed voltage V0, guaranteeing the continuous presence of feedback current. The feedback current, clamping voltage, and pull-down current maintain the stability of the input DC point, avoiding popping noises at the output caused by minor input voltage fluctuations, and eliminating the power-down popping noise problem that occurs when the circuit's low-voltage protection point is even lower.

[0068] The present invention employs a circuit structure and system for eliminating the popping sound of Class D audio amplifiers during power-down. By designing a fixed DC voltage at the amplifier input terminal and a new pull-down current logic selection circuit, without changing the existing power-on and power-off sequence of the amplifier, different DC voltages and corresponding pull-down currents are set at the amplifier input terminal based on the detection of high and low power supply voltages. This ensures that the feedback current and pull-down current remain constant and equal during power-down, solving the popping sound problem caused by sudden power failure when the minimum operating voltage of mainstream amplifiers on the market is as low as 3.5V. The method is simple, feasible, and widely applicable, suitable for mainstream Class D amplifier circuits on the market. For customers using amplifier circuits powered by a single lithium battery, it not only meets low-voltage requirements but also greatly improves the auditory experience.

[0069] In this specification, the invention has been described with reference to specific embodiments thereof. However, it will be apparent that various modifications and variations can be made without departing from the spirit and scope of the invention. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. A circuit structure for eliminating the popping sound of a Class D audio power amplifier during power loss, comprising a voltage detection logic circuit module, an operational amplifier input voltage logic selection circuit module, a pull-down current logic selection circuit module, and a clamping voltage logic circuit module, characterized in that, The voltage detection logic circuit module includes a voltage detection logic unit (LOG1) and an inverter. The first input terminal of the voltage detection logic unit (LOG1) is connected to the power supply voltage terminal VCC, the second input terminal of the voltage detection logic unit (LOG1) is connected to the third reference voltage terminal VREF3, the output terminal of the voltage detection logic unit (LOG1) is connected to the input terminal of the inverter, and the output terminal of the inverter is connected to the operational amplifier input voltage logic selection circuit module. The output terminal of the operational amplifier input voltage logic selection circuit module is connected to the third input terminal of the clamping voltage logic circuit module, which is a fixed voltage V0. The input terminal of the pull-down current logic selection circuit module is connected to the pull-down current unit, the output terminal of the pull-down current logic selection circuit module is connected to the fourth input terminal Idown of the clamping voltage logic circuit module, and the output terminal of the clamping voltage logic circuit module is connected to an external Class D audio power amplifier module. The voltage detection logic circuit module is used to detect and compare the power supply voltage VCC with the third reference voltage terminal VREF3. The op-amp input voltage logic selection circuit module selects the output of the corresponding op-amp input voltage logic selection circuit unit as the op-amp input voltage of the circuit structure based on the detection and comparison results of the voltage detection logic circuit module. The pull-down current logic selection circuit module selects the output of the corresponding pull-down current unit as the pull-down current of the circuit structure based on the detection result of the voltage detection logic circuit module. The clamping voltage logic circuit module is used to ensure that the input voltage of the Class D audio power amplifier module is stable at a fixed voltage.

2. The circuit structure for eliminating the popping sound of a Class D audio amplifier losing power, as described in claim 1, is characterized in that... The operational amplifier input voltage logic selection circuit module includes a first operational amplifier input voltage logic selection circuit unit, a second operational amplifier input voltage logic selection circuit unit, a first transmission gate, and a second transmission gate. The first operational amplifier input voltage logic selection circuit unit includes a first operational amplifier input voltage logic selection output terminal for outputting the first operational amplifier input voltage VREF1. This first operational amplifier input voltage logic selection output terminal is located between a third resistor (R3) and a fourth resistor (R4) and connected to the input terminal of the first transmission gate. The second operational amplifier input voltage logic selection circuit unit includes a second operational amplifier input voltage logic selection output terminal for outputting a stable voltage VREF2. This second operational amplifier input voltage logic selection output terminal is located between the first end of a fifth resistor (R5) and the anode of a first diode (D1) and connected to the input terminal of the second transmission gate. The second terminal of the fifth resistor (R5) is connected to the first reference current source (I0), and the cathode of the first diode (D1) is connected to the anode of the second diode (D2). The first transmission gate includes a fifth PMOS field-effect transistor (P5) and a fifth NMOS field-effect transistor (N5), with the drain of the fifth PMOS field-effect transistor (P5) and the source of the fifth NMOS field-effect transistor (N5) both connected to the input terminal of the first transmission gate. The second transmission gate includes a sixth PMOS field-effect transistor (P6) and a sixth NMOS field-effect transistor (N6), with the drain of the sixth PMOS field-effect transistor (P6) and the source of the sixth NMOS field-effect transistor (N6) both connected to the input terminal of the second transmission gate. The output terminals of the first and second transmission gates are connected to output the operational amplifier input voltage.

3. The circuit structure for eliminating the popping sound of a Class D audio amplifier losing power, as described in claim 1, is characterized in that... The pull-down current logic selection circuit module includes a pull-down current unit, a third transmission gate, and a fourth transmission gate. The pull-down current unit includes a first pull-down current unit and a second pull-down current unit. The first pull-down current unit includes a pull-down current subunit. The first input terminal of the pull-down current subunit is connected to the power supply voltage VCC, and the second input terminal is connected to the chip voltage VDD. The output terminal of the current source is used to output the first pull-down current Idown1; the second pull-down current unit includes a follower (FOLLOW1), an operational amplifier (AMP), a third NMOS field-effect transistor (N3), and a current mirror element group. The positive input terminal of the follower (FOLLOW1) is connected between the first resistor (R1) and the second resistor (R2). The inverting input terminal and the output terminal of the follower (FOLLOW1) are connected together to the positive terminal of the third diode (D3). The negative terminal of the third diode (D3) is connected to the positive terminal of the fourth diode (D4). The negative terminal of the fourth diode (D4) is connected between the second reference current source (I1) and the positive input terminal of the operational amplifier (AMP). The inverting input terminal of the operational amplifier (AMP) is connected between the source of the third NMOS field-effect transistor (N3) and the feedback resistor (Rf). The output terminal of the operational amplifier (AMP) is connected to the gate of the third NMOS field-effect transistor (N3). The drain of the third NMOS field-effect transistor (N3) is connected to the current mirror element group.The input terminal of the third transmission gate is connected to the output terminal of the first pull-down current unit for outputting the first pull-down current Idown1. The input terminal of the fourth transmission gate is connected to the output terminal of the second pull-down current unit for outputting the second pull-down current Idown2. The third transmission gate includes a seventh PMOS field-effect transistor (P7) and a seventh NMOS field-effect transistor (N7). The drain of the seventh PMOS field-effect transistor (P7) and the source of the seventh NMOS field-effect transistor (N7) are both connected to the input terminal of the third transmission gate. The source of the seventh PMOS field-effect transistor (P7) and the source of the seventh NMOS field-effect transistor (N7) are both connected to the input terminal of the third transmission gate. The drains of the field-effect transistors (N7) are all connected to the output of the third transmission gate. The fourth transmission gate includes an eighth PMOS field-effect transistor (P8) and an eighth NMOS field-effect transistor (N8). The drains of the eighth PMOS field-effect transistor (P8) and the sources of the eighth NMOS field-effect transistor (N8) are both connected to the input of the fourth transmission gate. The sources of the eighth PMOS field-effect transistor (P8) and the drains of the eighth NMOS field-effect transistor (N8) are both connected to the output of the fourth transmission gate. The output of the third transmission gate is connected to the output of the fourth transmission gate to output pull-down current.

4. The circuit structure for eliminating the popping sound of a Class D audio amplifier during power loss according to claim 3, characterized in that, The current mirror element group includes a first PMOS field-effect transistor (P1), a second PMOS field-effect transistor (P2), a third PMOS field-effect transistor (P3), and a fourth PMOS field-effect transistor (P4). The drain of the first PMOS field-effect transistor (P1) is connected to the source of the second PMOS field-effect transistor (P2), the drain of the second PMOS field-effect transistor (P2) is connected to the drain of the third NMOS field-effect transistor (N3), the gate of the first PMOS field-effect transistor (P1) is connected to the gate of the third PMOS field-effect transistor (P3), the gate of the second PMOS field-effect transistor (P2) is connected to the gate of the fourth PMOS field-effect transistor (P4), and the drain of the third PMOS field-effect transistor (P3) is connected to the source of the fourth PMOS field-effect transistor (P4). The sources of the first PMOS field-effect transistor (P1) and the third PMOS field-effect transistor (P3) are both connected to the power supply voltage VCC.

5. The circuit structure for eliminating the popping sound of a Class D audio amplifier losing power as described in claim 1, characterized in that, The first input terminal a5 of the clamping voltage logic circuit module is connected to the second terminal of the positive input terminal INP of the Class D audio power amplifier circuit module. The first input terminal a6 of the clamping voltage logic circuit module is connected to the second terminal of the negative input terminal INN of the Class D audio power amplifier circuit module. The third input terminal of the clamping voltage logic circuit module is connected to the output terminal of the operational amplifier input voltage logic selection circuit module. The fourth input terminal of the clamping voltage logic circuit module is connected to the output terminal of the pull-down current logic selection circuit module.

6. A Class D audio power amplifier circuit system having the circuit structure described in any one of claims 1 to 5 for eliminating popping noise, characterized in that, The circuit system further includes a Class D audio amplifier module, which includes a first preamplifier (AMP1), a second preamplifier (AMP2), a triangular wave generation circuit unit (OSC), a first pulse width modulator (COMP1), a second pulse width modulator (COMP2), a shaping circuit unit (LOG), a first driver circuit (Drive1), a second driver circuit (Drive2), a low-pass filter, and a speaker. The positive input terminal of the first preamplifier (AMP1) is connected to the second terminal of the first input terminal a5 of the clamping voltage logic circuit module. The inverting input terminal of P1 is connected to the second terminal of the second input terminal a6 of the clamping voltage logic circuit module. The inverting output terminal of the first preamplifier (AMP1) is connected to the non-inverting input terminal of the second preamplifier (AMP2). The non-inverting output terminal of the first preamplifier (AMP1) is connected to the inverting input terminal of the second preamplifier (AMP2). The inverting output terminal of the second preamplifier (AMP2) is connected to the non-inverting input terminal of the first pulse width modulator (COMP1). The non-inverting output terminal of the second preamplifier (AMP2) is connected to the non-inverting input terminal of the second pulse width modulator (COMP2). The inverting input terminals of the first pulse width modulator (COMP1) and the second pulse width modulator (COMP2) are both connected to the triangular wave generating circuit unit (OSC). The output terminal of the first pulse width modulator (COMP1) is connected to the first input terminal of the shaping circuit unit (LOG), and the output terminal of the second pulse width modulator (COMP2) is connected to the second input terminal of the shaping circuit unit (LOG). The first output terminal of the shaping circuit unit (LOG) is connected to the input terminal of the first driving circuit (Drive1), and the second output terminal of the shaping circuit unit (LOG) is connected to the input terminal of the second driving circuit (Drive2). The first drive circuit (Drive1) is connected between the output terminal OUTPL of the Class D audio amplifier module and the low-pass filter. The output terminal of the second drive circuit (Drive2) is connected between the output terminal OUTNL of the Class D audio amplifier module and the low-pass filter. The speaker is connected to the low-pass filter. The first terminal of the positive input terminal INP of the Class D audio amplifier module is connected to the second terminal of the first DC blocking capacitor (C1). The first terminal of the first DC blocking capacitor (C1) is connected in sequence to a resistor (Ra) and a resistor (Rb) to ground.The first terminal of the negative input INN of the Class D audio amplifier module is connected to the first terminal of the second DC blocking capacitor (C2), and the second terminal of the second DC blocking capacitor (C2) is grounded.

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