Data transmission method, apparatus, device, system, and storage medium

Abstract

This invention discloses a data transmission method, apparatus, device, system, and storage medium, comprising: receiving first data sent by a first data module at a first line rate and storing the first data in a first memory of the data transmission apparatus; when it is determined that the amount of data in the first memory meets a first preset condition, sending a first stop signal to the first data module so that the first data module stops sending the first data after receiving the first stop signal; when it is determined that the amount of data in the first memory is not empty, reading first data to be sent from the first memory and sending the first data to be sent to a second data module at a second line rate; when it is determined that the amount of data in the first memory is empty, stopping reading the first data to be sent from the first memory. This data transmission method avoids data transmission errors and achieves normal data transmission between a first data module and a second data module with mismatched interface line rates.

Description

Technical Field

[0001] The embodiments of the present invention relate to electronic technology, and more particularly to a data transmission method, apparatus, device, system, and storage medium. Background Technology

[0002] Electronic technology is advancing rapidly. Only by continuously adopting new technologies to improve product performance can we maintain the product's sustained competitiveness.

[0003] During product upgrades, due to considerations of cost, time, and controllability, new technologies are generally only applied to functions that significantly improve product performance or have special requirements. This can lead to interface incompatibility between upgraded and non-upgraded modules within a product or communication system.

[0004] Currently, normal data transmission cannot be achieved when the interfaces of the upgraded and non-upgraded modules are incompatible. Summary of the Invention

[0005] This invention provides a data transmission method, apparatus, device, system, and storage medium to solve the technical problem that normal data transmission cannot be achieved when the interfaces of upgraded and un-upgraded modules are incompatible.

[0006] In a first aspect, embodiments of the present invention provide a data transmission method, applied in a data transmission device, comprising:

[0007] The device receives first data sent by the first data module at a first line rate and stores the first data in the first memory of the data transmission device.

[0008] When it is determined that the amount of data in the first memory meets the first preset condition, a first stop signal is sent to the first data module so that the first data module stops sending the first data after receiving the first stop signal;

[0009] When it is determined that the amount of data in the first memory is not empty, the first data to be sent in the first memory is read and the first data to be sent to the second data module at the second line rate;

[0010] When it is determined that the amount of data in the first memory is empty, reading the first data to be sent from the first memory is stopped.

[0011] Secondly, embodiments of the present invention also provide a data transmission device, which includes: a first transceiver module, a second transceiver module, a data flow controller, and a first memory;

[0012] The first transceiver module, the second transceiver module, and the first memory are all connected to the data flow controller. The first transceiver module is used to connect to the first data module, and the second transceiver module is used to connect to the second data module.

[0013] The first transceiver module is used to receive first data sent by the first data module at a first line rate, and to send the first data to the data flow controller;

[0014] The data flow controller is used to store the first data in the first memory;

[0015] The data flow controller is further configured to send a first stop signal to the first data module through the first transceiver module when it is determined that the amount of data in the first memory meets the first preset condition, so that the first data module stops sending the first data after receiving the first stop signal;

[0016] The data flow controller is further configured to read the data to be sent from the first memory and send the data to be sent to the second transceiver module when it is determined that the amount of data in the first memory is not empty. The second transceiver module is configured to send the data to be sent to the second data module at a second linear rate.

[0017] The data flow controller is further configured to stop reading the first data to be sent from the first memory when it is determined that the amount of data in the first memory is empty.

[0018] Thirdly, embodiments of the present invention also provide a data transmission system, including: a first data module, a second data module, and a data transmission device as described in the second aspect;

[0019] The first data module is connected to the first transceiver module in the data transmission device, and the second data module is connected to the second transceiver module in the data transmission device.

[0020] Fourthly, embodiments of the present invention also provide an electronic device, including a memory, a processor, a computer program stored in the memory and executable on the processor, a programmable logic device, and a program stored in the memory and executable on the programmable logic device, wherein the processor or programmable logic device executes the program to implement the data transmission method as described in the first aspect.

[0021] Optionally, the programmable logic device may be a field-programmable gate array (FPGA).

[0022] Fifthly, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data transmission method as described in the first aspect.

[0023] The data transmission method, apparatus, device, system, and storage medium provided in this invention are applied in a data transmission apparatus, comprising: receiving first data sent by a first data module at a first line rate and storing the first data in a first memory of the data transmission apparatus; when it is determined that the amount of data in the first memory meets a first preset condition, sending a first stop signal to the first data module so that the first data module stops sending the first data after receiving the first stop signal; when it is determined that the amount of data in the first memory is not empty, reading the first data to be sent from the first memory and sending the first data to be sent to a second data module at a second line rate; when it is determined that the amount of data in the first memory is empty, stopping reading the first data to be sent from the first memory. This data transmission method can cache data in the first memory and control the data transmission between the first data module and the second data module based on the amount of data in the first memory. This avoids data overflow in the first memory and data transmission errors caused by the inability to read data from the first memory. It also avoids resource waste and data transmission errors caused by reading data from the first memory when the amount of data in the first memory is empty. It achieves line rate matching between the first data module and the second data module even when the interface line rate is mismatched, thereby enabling normal data transmission between the first data module and the second data module. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the structure of a current data transmission system;

[0025] Figure 2 This is a flowchart illustrating an embodiment of the data transmission method provided in this invention.

[0026] Figure 3 A schematic diagram illustrating the interaction process of the data transmission method provided in an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of the structure of a data transmission device provided in an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of another data transmission device provided in an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of the structure of another data transmission device provided in an embodiment of the present invention;

[0030] Figure 7A schematic diagram of a data transmission system provided in an embodiment of the present invention;

[0031] Figure 8 This is a schematic diagram of the structure of another data transmission system provided in an embodiment of the present invention;

[0032] Figure 9 This is a schematic diagram of a data frame format;

[0033] Figure 10 A schematic diagram of the format of the data frame after data padding;

[0034] Figure 11 This is a schematic diagram showing the connection between a submodule with a bit width of N and a submodule with a bit width of M.

[0035] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0036] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0037] Figure 1 This is a schematic diagram of the structure of a current data transmission system. (Example:) Figure 1As shown, the current data transmission system may include a first data module 11 and a second data module 12. Exemplarily, the first data module 11 may include a first terminal 111, a first codec 112, and a first transceiver 113 connected in sequence. The second data module 12 may include a second terminal 121, a second codec 122, and a second transceiver 123 connected in sequence. The first transceiver 113 is connected to the second transceiver 123. Before the upgrade, the line rate of both the first transceiver 113 and the second transceiver 123 is F1. The first data module 11 and the second data module 12 can achieve seamless interoperability. The following describes the data transmission process using the example of data transmission from the first data module 11 to the second data module 12: The first terminal 111 generates or acquires data and sends it to the first codec 112; the first codec 112 encodes the data sent by the first terminal 111 and sends the encoded data to the first transceiver 113; the first transceiver 113 converts the encoded data (e.g., photoelectric conversion, level conversion) to form first data and sends this first data to the second transceiver 123; after receiving the first data, the second transceiver 123 performs an inverse conversion on the first data and sends the inversely converted data to the second codec 122; the second codec 122 decodes the inversely converted data and sends the decoded data to the second terminal 121; the second terminal 121 receives the decoded data, completing one data transmission process. The process of data transmission from the second data module 12 to the first data module 11 is similar and will not be described again here.

[0038] However, if some modules in the data transmission system, for example, the second transceiver 123 is upgraded to the third transceiver 124, and the line rate of the third transceiver 124 is F2, then data transmission cannot be achieved between the first data module 11 and the second data module 12 because the line rate F1 of the first transceiver 113 does not match the line rate F2 of the third transceiver 124.

[0039] This invention provides a data transmission method, apparatus, device, system, and storage medium to enable normal data transmission between a first data module and a second data module.

[0040] Figure 2 This is a flowchart illustrating an embodiment of the data transmission method provided by the present invention. This embodiment is applicable to scenarios where the interfaces of upgraded and un-upgraded modules are incompatible, ensuring normal data transmission. This embodiment can be executed by a data transmission device, which can be implemented in software and / or hardware, and can be integrated into an electronic device. Figure 2 As shown, the data transmission method provided in this embodiment includes the following steps:

[0041] Step 201: Receive the first data sent by the first data module at a first line rate, and store the first data in the first memory of the data transmission device.

[0042] Specifically, in this embodiment, the line rate refers to the amount of data transmitted per line per unit time. For ease of description, in this embodiment, the line rate of the interface of the first data module is referred to as the first line rate, and the line rate of the interface of the second data module is referred to as the second line rate. Here, the interface refers to the interface through which the first data module and the second data module communicate; for example, the interface could be... Figure 1 The transceiver shown.

[0043] In this embodiment, the first data module and the second data module can be modules in two different devices, or they can be different modules in the same device. The device in this embodiment can be an electronic device that requires data transmission. For example, the device here can be a photolithography device.

[0044] Because the interface of the first data module and the interface of the second data module have different line rates, the first data module and the second data module cannot communicate directly.

[0045] In this embodiment, a data transmission device provided in this embodiment is provided between the first data module and the second data module. Taking the transmission of data from the first data module to the second data module as an example, the data transmission method provided in this embodiment will be described. For ease of description, the data sent by the first data module is referred to as the first data.

[0046] In step 201, the data transmission device receives the first data sent by the first data module at a first line rate. After receiving the first data, the first data is stored in the first memory of the data transmission device. This first memory can be a first-in-first-out (FIFO) memory.

[0047] Step 202: When it is determined that the amount of data in the first memory meets the first preset condition, a first stop signal is sent to the first data module so that the first data module stops sending the first data after receiving the first stop signal.

[0048] Specifically, the first preset condition here can be that the amount of data in the first memory is greater than or equal to the third data amount. The third data amount is a3*T, where T represents the capacity of the first memory, and a3≤1. For example, a3 can be 80%. This implementation can stop receiving first data from the first data module when the amount of data stored in the first memory is close to the capacity of the first memory. This avoids data overflow caused by inconsistent read and write rates in the first memory.

[0049] When the data transmission device determines that the amount of data in the first memory meets the first preset condition, it indicates that the first memory can no longer store data and needs to suspend receiving data from the first data module. Therefore, the data transmission device can send a first stop signal to the first data module.

[0050] After receiving the first stop signal, the first data module stops sending the first data.

[0051] In one implementation, after receiving the first stop signal, the first data module can send a first hold connection signal to the data transmission device in order to maintain the connection with the data transmission device. This first hold connection signal is used to maintain the connection with the first data module.

[0052] Correspondingly, the data transmission device can receive the first hold-on signal sent by the first data module.

[0053] The first hold signal can maintain the connection between the first data module and the data transmission device even after the first data module stops sending the first data, thereby improving the transmission efficiency when the first data transmission is resumed.

[0054] In another implementation, the bit widths of any two sub-modules within the first and second data modules may differ. Please refer to [link / reference needed]. Figure 1 For example, suppose the original bit width of the second codec 122 in the second data module is N bits, and it is upgraded to a third decoder 125 with a bit width of M bits. M is greater than N. The bit width of the third decoder 125 does not match that of the second terminal 121. In this embodiment, the preset N bits of the third decoder 125 can be connected to the N bits of the second terminal 121. The preset N bits here can be the highest N bits. Furthermore, valid data is transmitted on the preset N bits of the third decoder 125, and invalid data is transmitted on the remaining bits of the third decoder 125. The invalid data here can be data inserted by the first terminal 111 into the valid data.

[0055] For example, when the highest N bits of the third decoder 125 are connected to the second terminal 121, the first terminal inserts MN bits of invalid data after the N bits of valid data. Here, "bit" refers to a bit position. When the lowest N bits of the third decoder 125 are connected to the second terminal 121, the first terminal 111 inserts MN bits of invalid data before the N bits of valid data.

[0056] It is understandable that, based on the connection between the third decoder 125 and the second terminal 121, the first terminal 111 can determine the transmission timing of valid and invalid data.

[0057] Therefore, the first data transmitted by the first data module may include invalid data and valid data. After receiving the first stop signal, if the first data module is currently transmitting first data, it needs to send a first hold signal to the data transmission device after transmitting a set of first data. This set of first data includes: N bits of valid data and MN bits of invalid data. M and N are the bit widths of each sub-module in the first data module and the second data module, respectively.

[0058] In other words, the first hold signal is sent by the first data module after receiving the first stop signal and sending a set of first data. This implementation ensures that invalid and valid data can appear in groups, making it easier for the M-bit-width submodule to distinguish between valid and invalid data, and avoiding data corruption caused by the inability to distinguish between valid and invalid data.

[0059] It should be noted that the data transmission device does not store the first hold-on signal after receiving it.

[0060] Optionally, after the first data module receives the first stop signal and stops sending the first data, it can continue to send the first data to the data transmission device after waiting for a first preset time period.

[0061] Correspondingly, after sending the first stop signal, the data transmission device can return to the step of "receiving the first data sent by the first data module at a first line rate and storing the first data in the memory" after a first preset time period. This implementation method can achieve continuous data transmission and improve data transmission efficiency.

[0062] For example, the first preset time period is less than or equal to the time required for the first data module to transmit the first amount of data, and greater than or equal to the time required for the first data module to transmit the second amount of data. The first amount of data is a1*T, the second amount of data is a2*T, T represents the capacity of the first memory, and a2≤a1≤1. Optionally, a1 can be 70%, and a2 can be 10%. This implementation of setting the first preset time period can strike a balance between avoiding first memory overflow and improving data transmission efficiency.

[0063] Step 203: When it is determined that the amount of data in the first memory is not empty, read the first data to be sent from the first memory and send the first data to be sent to the second data module at the second line rate.

[0064] Specifically, there is no execution order between steps 202 and 203. These two steps can be executed sequentially or concurrently in any order.

[0065] In step 203, the data transmission device can determine whether the data in the first memory is empty at a preset frequency. If it is determined that the data in the first memory is not empty, the device reads the first data to be sent from the first memory. Here, the first data to be sent refers to the data that needs to be sent to the second data module. After reading the first data to be sent, the data transmission device sends the first data to be sent to the second data module at a second rate, thus realizing normal data transmission between the first and second data modules.

[0066] It is understandable that the first memory stores the first data. The first data to be sent read in step 203 also belongs to the first data.

[0067] Step 204: When it is determined that the amount of data in the first memory is empty, stop reading the first data to be sent from the first memory.

[0068] Specifically, the data transmission device stops reading the first data to be transmitted from the first memory when it determines that the first memory is empty. This is to avoid wasting resources and causing data transmission errors caused by continuing to read data from the first memory when the first memory is empty.

[0069] Furthermore, when it is determined that the data in the first memory is empty, the data transmission device can send a second hold-on signal to the second data module. This second hold-on signal is used to maintain the connection with the second data module. After receiving the second hold-on signal, the second data module discards it. The second data module then continues receiving data after receiving the first data again. This method of sending a second hold-on signal ensures that the connection between the data transmission device and the second data module is maintained even after the data transmission device stops sending data to the second data module, thus improving transmission efficiency when resuming data transmission.

[0070] Figure 3 This is a schematic diagram illustrating the interactive process of the data transmission method provided in an embodiment of the present invention. Figure 3 As shown, the data transmission method includes the following steps:

[0071] Step 301: The first data module sends the first data.

[0072] Step 302: The data transmission device receives the first data sent by the first data module at a first line rate and stores the first data in the first memory of the data transmission device.

[0073] Step 303: When it is determined that the amount of data in the first memory meets the first preset condition, a first stop signal is sent to the first data module.

[0074] Step 304: The first data module receives the first stop signal and stops sending the first data.

[0075] Step 305: The first data module sends a first keep-connection signal to the data transmission device.

[0076] Step 306: The data transmission device receives the first hold signal and discards it.

[0077] Step 307: The first data module resends the first data after the first preset time period.

[0078] Step 308: After the first preset time period, the data transmission device returns to step 302.

[0079] Step 309: When it is determined that the amount of data in the first memory is not empty, read the first data to be sent from the first memory.

[0080] Step 310: Send the first data to be sent to the second data module at the second line rate.

[0081] Step 311: The second data module receives the first data to be sent.

[0082] Step 312: When it is determined that the amount of data in the first memory is empty, a second keep-connect signal is sent to the second data module.

[0083] Step 313: The second data module receives the second hold-on signal and discards it.

[0084] There is no temporal relationship between steps 302, 303 and 309.

[0085] Furthermore, this embodiment can also enable the second data module to send data to the first data module. For ease of description, the data sent by the second data module will be referred to as the second data.

[0086] The data transmission device in this embodiment can also perform the following steps: receiving second data sent by the second data module at a second line rate, and storing the second data in the second memory of the data transmission device; when it is determined that the amount of data in the second memory meets a second preset condition, sending a second stop signal to the second data module so that the second data module stops sending the second data after receiving the second stop signal; when it is determined that the amount of data in the second memory is not empty, reading the second data to be sent from the second memory; and sending the second data to be sent to the first data module at a first line rate. This implementation method can realize bidirectional data transmission of the data transmission device.

[0087] The second memory here can also be a FIFO memory.

[0088] Optionally, after receiving the second stop signal from the data transmission device, the second data module may send a third hold-connection signal to the data transmission device. Correspondingly, after sending the second stop signal to the second data module, the data transmission device may also receive the third hold-connection signal sent by the second data module. The third hold-connection signal is used to maintain the connection between the data transmission device and the second data module.

[0089] Optionally, the third hold signal is sent by the second data module after receiving the second stop signal and after sending a set of second data. The set of second data includes N bits of valid data and MN bits of invalid data, where M and N are the bit widths of the sub-modules in the first and second data modules, respectively.

[0090] Optionally, when it is determined that the data in the second memory is empty, reading the second data to be transmitted from the second memory is stopped. Further, when it is determined that the data in the second memory is empty, a fourth hold-connection signal is sent to the first data module. The fourth hold-connection signal is used to maintain the connection between the data transmission device and the first data module.

[0091] Optionally, after the data transmission device sends a second stop signal to the second data module, it may also return to the step of "receiving the second data sent by the second data module at a second linear rate and storing the second data in the second memory" after a second preset time period.

[0092] More specifically, the second preset time period is less than or equal to the time required for the second data module to transmit the fourth data volume, and greater than or equal to the time required for the second data module to transmit the fifth data volume. The fourth data volume is a4*T', the fifth data volume is a5*T', T' represents the capacity of the second memory, and a5≤a4≤1.

[0093] Optionally, the second preset condition is that the amount of data in the second memory is greater than or equal to the sixth data amount. The sixth data amount is a6*T', where T' represents the capacity of the second memory, and a6≤1.

[0094] The data transmission method provided in this embodiment, applied in a data transmission device, includes: receiving first data sent by a first data module at a first line rate and storing the first data in a first memory of the data transmission device; when it is determined that the amount of data in the first memory meets a first preset condition, sending a first stop signal to the first data module so that the first data module stops sending the first data after receiving the first stop signal; when it is determined that the amount of data in the first memory is not empty, reading the first data to be sent from the first memory and sending the first data to be sent to a second data module at a second line rate; when it is determined that the amount of data in the first memory is empty, stopping reading the first data to be sent from the first memory. This data transmission method can cache data in the first memory and can control the data transmission between the first data module and the second data module based on the amount of data in the first memory. This avoids data overflow in the first memory and data transmission errors caused by the inability to read data from the first memory, as well as resource waste and data transmission errors caused by still reading data from the first memory when the amount of data in the first memory is empty. It achieves line rate matching between the first data module and the second data module even when the interface line rates are mismatched, thereby realizing normal data transmission between the first data module and the second data module.

[0095] Figure 4 This is a schematic diagram of a data transmission device provided in an embodiment of the present invention. The data transmission device provided in this embodiment can be used to perform... Figure 2 , Figure 3 The data transmission methods in the illustrated embodiments and various optional implementations. For example... Figure 4 As shown, the data transmission device provided in this embodiment includes: a first transceiver module 41, a second transceiver module 42, a data flow controller 43, and a first memory 44.

[0096] The first transceiver module 41, the second transceiver module 42, and the first memory 44 are all connected to the data flow controller 43. The first transceiver module 41 is used to connect to the first data module. The second transceiver module 42 is used to connect to the second data module.

[0097] The first transceiver module 41 is used to receive the first data sent by the first data module at a first line rate, and to send the first data to the data flow controller 43.

[0098] The data flow controller 43 is used to store the first data in the first memory 44.

[0099] The data flow controller 43 is also used to send a first stop signal to the first data module through the first transceiver module 41 when it is determined that the amount of data in the first memory 44 meets the first preset condition, so that the first data module stops sending the first data after receiving the first stop signal.

[0100] The data flow controller 43 is also used to read the first data to be sent from the first memory 44 when it is determined that the amount of data in the first memory 44 is not empty, and send the first data to be sent to the second transceiver module. The second transceiver module 42 is used to send the first data to be sent to the second data module at a second line rate.

[0101] The data flow controller 43 is also configured to stop reading the first data to be sent from the first memory 44 when it is determined that the amount of data in the first memory 44 is empty.

[0102] Optionally, the first transceiver module 41 can also receive a first hold-on signal sent by the first data module and send the first hold-on signal to the data flow controller 43. The first hold-on signal is used to maintain the connection between the data transmission device and the first data module. The first hold-on signal is sent by the first data module after receiving the first stop signal.

[0103] After receiving the first hold signal, the data flow controller 43 discards it and does not write it into the first memory 44.

[0104] Optionally, the first transceiver module 41 may also return to the step of "receiving the first data sent by the first transceiver module at a first line rate and sending the first data to the data flow controller" after a first preset time period.

[0105] For example, the first preset time period is less than or equal to the time required for the first data module to transmit the first amount of data, and greater than or equal to the time required for the first data module to transmit the second amount of data. The first amount of data is a1*T, the second amount of data is a2*T, T represents the capacity of the first memory 44, and a2≤a1≤1.

[0106] Furthermore, the data flow controller 43 is also configured to send a second hold-on signal to the second data module via the second transceiver module 42 when it determines that the amount of data in the first memory 44 is empty. The second hold-on signal is used to maintain the connection between the data transmission device and the second data module.

[0107] Optionally, the first preset condition is that the amount of data in the first memory 44 is greater than or equal to the third data amount. The third data amount is a3*T, where T represents the capacity of the first memory, and a3≤1.

[0108] It should be noted that the first memory 44 in this embodiment can output a signal indicating that the data volume is empty, a signal indicating that the data volume is not empty, and a signal indicating that the data volume meets a first preset condition. The data flow controller 43 can determine the state of the data volume in the first memory 44 based on the signals output by the first memory 44. For example, 1 can represent that the data volume in the first memory 44 is not empty, 0 can represent that the data volume in the first memory 44 is empty, and a full signal can represent that the data volume in the first memory 44 meets the first preset condition.

[0109] In the data transmission device provided in this embodiment, the first transceiver module can receive data from the first data module at a line rate matching the first data module, and the second transceiver module can send data to the second data module at a line rate matching the second data module. During this process, data can be cached in the first memory, and the data transmission between the first data module and the second data module can be controlled based on the amount of data in the first memory. This avoids data overflow in the first memory and data transmission errors caused by the inability to read data from the first memory. It also avoids resource waste and data transmission errors caused by reading data from the first memory when the amount of data in the first memory is empty. Line rate matching is achieved between the first data module and the second data module where the interface line rates are mismatched, thereby realizing normal data transmission between the first data module and the second data module.

[0110] Figure 5 This is a schematic diagram of another data transmission device provided in an embodiment of the present invention. Figure 4 Based on the illustrated embodiments and various optional solutions, other modules included in the data transmission device will be described in detail. For example... Figure 5 As shown, the data transmission device provided in this embodiment also includes a second memory 45. The second memory 45 is connected to the data flow controller 43.

[0111] The second transceiver module 42 is also used to receive the second data sent by the second data module at a second line rate, and to send the second data to the data flow controller 43.

[0112] The data flow controller 43 is also used to store the second data in the second memory 45.

[0113] The data flow controller 43 is also used to send a second stop signal to the second data module through the second transceiver module 42 when it is determined that the amount of data in the second memory 45 meets the second preset condition, so that the second data module stops sending the second data after receiving the second stop signal.

[0114] The data flow controller 43 is also configured to read the second data to be sent from the second memory 45 when it is determined that the amount of data in the second memory 45 is not empty, and send the second data to be sent to the first transceiver module 41. The first transceiver module 41 is also configured to send the second data to be sent to the first data module at a first line rate.

[0115] Optionally, after receiving the second stop signal sent by the second transceiver module 42, the second data module may send a third hold-connection signal to the data transmission device. Correspondingly, the second transceiver module 42 may also receive the third hold-connection signal sent by the second data module. The third hold-connection signal is used to maintain the connection between the data transmission device and the second data module.

[0116] Optionally, the third hold signal is sent by the second data module after receiving the second stop signal and after sending a set of second data. The set of second data includes N bits of valid data and MN bits of invalid data, where M and N are the bit widths of the sub-modules in the first and second data modules, respectively.

[0117] The data flow controller 43 is further configured to stop reading the second data to be transmitted from the second memory 45 when it is determined that the amount of data in the second memory 45 is empty. Further, the data flow controller 43 is also configured to send a fourth hold-on signal to the first data module when it is determined that the amount of data in the second memory 45 is empty. The fourth hold-on signal is used to maintain the connection between the data transmission device and the first data module.

[0118] Optionally, the second transceiver module 42 is further configured to, after sending a second stop signal to the second data module, return to the step of "receiving the second data sent by the second data module at a second line rate and sending the second data to the data flow controller" after a second preset time period.

[0119] More specifically, the second preset time period is less than or equal to the time required for the second data module to transmit the fourth data volume, and greater than or equal to the time required for the second data module to transmit the fifth data volume. The fourth data volume is a4*T', the fifth data volume is a5*T', T' represents the capacity of the second memory, and a5≤a4≤1.

[0120] Optionally, the second preset condition is that the amount of data in the second memory 45 is greater than or equal to the sixth data amount. The sixth data amount is a6*T', where T' represents the capacity of the second memory 45, and a6≤1.

[0121] It should be noted that the second memory 45 in this embodiment can output a signal indicating that the data volume is empty, a signal indicating that the data volume is not empty, and a signal indicating that the data volume meets a second preset condition. The data flow controller 43 can determine the state of the data volume in the second memory 45 based on the signals output by the second memory 45.

[0122] The data transmission device provided in this embodiment can realize bidirectional data transmission between the first data module and the second data module.

[0123] Figure 6 This is a schematic diagram of another data transmission device provided in an embodiment of the present invention. This embodiment... Figure 4 , Figure 5 Based on the illustrated embodiments and various optional implementation schemes, the first transceiver module, the second transceiver module, and the sub-modules included in the data flow controller are described in detail. For example... Figure 6 As shown, in the data transmission device provided in this embodiment, the first transceiver module 41 includes: a first receiving submodule 411 and a first sending submodule 412.

[0124] The data stream controller 43 includes: a first receiving data stream controller 431, a first transmitting data stream controller 432, a second receiving data stream controller 433, and a second transmitting data stream controller 434.

[0125] The second transceiver module 42 includes a second receiving submodule 421 and a second sending submodule 422.

[0126] The first receiving submodule 411, the first receiving data stream controller 431, the first memory 44, the first transmitting data stream controller 432, and the second transmitting submodule 422 are connected in sequence.

[0127] The second receiving submodule 421, the second receiving data stream controller 433, the second memory 45, the second transmitting data stream controller 434, and the first transmitting submodule 412 are connected in sequence.

[0128] The first receive data stream controller 431 is also connected to the second transmit data stream controller 434. The first transmit data stream controller 432 is also connected to the second receive data stream controller 433.

[0129] In the data transmission device provided in this embodiment, the first receiving submodule 411 is used to receive the first data sent by the first data module at a first line rate, and send the first data to the first receiving data stream controller 431.

[0130] The first receiving data stream controller 431 writes the first data into the first memory 44.

[0131] When the amount of data in the first memory 44 meets the first preset condition, the first memory 44 will output a signal that meets the first preset condition to the first receiving data stream controller 431 (assuming that the signal is represented by FULL1).

[0132] When the first receiving data stream controller 431 receives a signal from the first memory 44 that satisfies the first preset condition, it sends the signal that satisfies the first preset condition to the second transmitting data stream controller 434.

[0133] After receiving the signal indicating that the first preset condition is met, the second data stream controller 434 determines that the amount of data in the first memory 44 meets the first preset condition. The second data stream controller 434 then sends a first stop signal (let's assume this signal is represented by STOP1) to the first data module through the first transmission submodule 412, so that the first data module stops transmitting the first data after receiving the first stop signal.

[0134] Optionally, after receiving the first stop signal, the first data module may send a first hold-on signal (assuming this signal is represented by SYNC1) to the first receiving submodule 411. After receiving the first hold-on signal, the first receiving submodule 411 sends the first hold-on signal to the first receiving data stream controller 431.

[0135] After receiving the first keep-connect signal, the first receiving data stream controller 431 discards it and does not store it.

[0136] The first memory 44 can also output a signal to the first data stream controller 432 indicating whether the data volume is empty.

[0137] When the first data stream controller 432 receives a signal that the amount of data sent by the first memory 44 is not empty, the first data stream controller 432 reads the first data to be sent from the first memory 44 and sends the first data to be sent to the second data module through the second data stream submodule 422.

[0138] Optionally, when the first data stream controller 432 receives a signal that the amount of data sent by the first memory 44 is empty (assuming the signal is represented by EMPITY1), it stops reading the first data to be sent from the first memory 44.

[0139] The first transmit data stream controller 432 is also configured to send a second hold-on signal (assuming the signal is represented by SYNC2) to the second data module via the second transmit submodule 422 when it is determined that the amount of data in the first memory 44 is empty.

[0140] During the process of the second data module sending data to the first data module, the working process of each sub-module in the data transmission device is similar to the above process, and will not be repeated here.

[0141] In the data transmission device provided in this embodiment, the first transceiver module includes a first receiving submodule and a first sending submodule, and the data flow controller includes a first receiving data flow controller, a first sending data flow controller, a second receiving data flow controller, and a second sending data flow controller. The second transceiver module includes a second receiving submodule and a second sending submodule. The first receiving submodule, the first receiving data flow controller, the first memory, the first sending data flow controller, and the second sending submodule are sequentially connected, as are the second receiving submodule, the second receiving data flow controller, the second memory, the second sending data flow controller, and the first sending submodule. The first receiving data flow controller is also connected to the second sending data flow controller, and the first sending data flow controller is also connected to the second receiving data flow controller. By independently configuring the receiving and sending submodules in the transceiver module and the receiving and sending data flow controllers in the data flow controller, the transmission efficiency of the data transmission device can be improved.

[0142] Figure 7 This is a schematic diagram of a data transmission system provided in an embodiment of the present invention. Figure 7 As shown, the data transmission system provided in this embodiment includes: a first data module 71, a second data module 72, and a data transmission device 73.

[0143] The first data module 71 is connected to the first transceiver module 731 in the data transmission device 73. The second data module 72 is connected to the second transceiver module 732 in the data transmission device 73.

[0144] The working process and implementation principle of the data transmission device 73 in this embodiment are similar to those of the data transmission device in the above method embodiment and device embodiment. It has the corresponding functional modules and beneficial effects of the execution method, which will not be repeated here.

[0145] This data transmission system enables normal communication between a first data module and a second data module with mismatched line rates.

[0146] Figure 8 This is a schematic diagram of another data transmission system provided in an embodiment of the present invention. The data transmission system provided in this embodiment... Figure 7Based on the illustrated embodiment, the structures of the first data module and the second data module will be described in detail. In the data transmission system provided in this embodiment, the first data module and / or the second data module include a first submodule and a second submodule. The first submodule has a bit width of M bits, and the second submodule has a bit width of N bits. M is greater than N.

[0147] For ease of description, this embodiment uses an example where the second data module includes a first submodule and a second submodule, and the first submodule has a bit width of M bits, while the second submodule has a bit width of N bits. Figure 8 As shown, the second data module 72 includes a first submodule 721 and a second submodule 722. Of course, the second data module 72 may also include other submodules.

[0148] In this implementation, the bit width of each submodule of the first data module is N bits. In the second data module 72, the bit width of the first submodule 721 is larger than the bit width of the other submodules in the second data module 72. To achieve normal data transmission, a preset N bits of the bit width of the first submodule can be connected to the second submodule. This preset N bits can be the highest N bits. Of course, the preset N bits can also be any N bits. This embodiment is not limited to this.

[0149] Figure 11 This is a schematic diagram showing the connection between a submodule with a bit width of N and a submodule with a bit width of M. For example... Figure 11 As shown, the highest N bits of a submodule with a bit width of M are connected to a submodule with a bit width of N.

[0150] To facilitate normal data transmission and prevent data loss between the first and second data modules due to disconnected lines in the first submodule 721, based on the connection relationship between the first and second submodules, the data transmitted in this data transmission system includes valid data and invalid data. Valid data is transmitted on a preset N bit of the first submodule, and invalid data is transmitted on the remaining MN bits (excluding the preset N bits).

[0151] The invalid data here can be data inserted by the first data module into the valid data. Based on this implementation, in the second data module, after the first submodule receives the first data, the data transmitted on the line connected to the second submodule is valid data, while invalid data is placed on the unconnected lines, thereby realizing data transmission between modules with mismatched bit widths.

[0152] For example, when the highest N bits of the first submodule 721 are connected to the second submodule 722, the first data module inserts MN bits of invalid data after the N bits of valid data. Here, "bit" refers to a bit position. When the lowest N bits of the first submodule 721 are connected to the second submodule 722, the first data module inserts MN bits of invalid data before the N bits of valid data.

[0153] Understandably, based on the connection between the first submodule 721 and the second submodule 722, the first data module can determine the transmission timing of valid and invalid data.

[0154] Figure 9 This is a schematic diagram of a data frame format. For example... Figure 9 As shown, the serial data frame structure is as follows: The first data is the Start Of Frame (SOF), which is a special character according to a standard or user-defined convention, used to indicate the start of a frame of data transmission; followed by the data transmission, including some information of this data frame, such as the destination address, source address, data length, etc., represented by Data1, Data1, ..., Data(j); finally, the End Of Frame (EOF) is a special character according to a standard or user-defined convention, used to indicate the end of a frame of data transmission.

[0155] Figure 10 This is a schematic diagram of the data frame format after data padding. In a scenario where the highest N bits of the first submodule 721 are connected to the second submodule 722, the format of the padded data frame is as follows: Figure 10 As shown: After N bits of valid data VDATA, MN bits of invalid data ADATA are inserted. The N bits of valid data VDATA and the MN bits of invalid data ADATA constitute a set of data.

[0156] As shown above, after receiving the first stop signal, if a set of first data has not been sent, the first data module needs to stop sending data after sending the set of first data. This ensures that invalid data and valid data can appear in groups, making it easier for the sub-module with a bit width of M to distinguish between valid and invalid data, and avoiding data confusion caused by the inability to distinguish between valid and invalid data.

[0157] The data transmission system provided in this embodiment can not only realize normal communication between the first data module and the second data module with mismatched line rates, but also realize normal communication between modules with different bit widths.

[0158] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Figure 12 As shown, the electronic device includes a processor 120, a memory 126, and a computer program stored in the memory 126 and executable on the processor 120. The electronic device may have one or more processors 120. Figure 12 Taking a processor 120 as an example; the processor 120 and memory 126 in this electronic device can be connected via a bus or other means. Figure 12 Taking the example of a connection between China and Israel via a bus.

[0159] Optionally, the electronic device may further include a programmable logic device and a program stored in a memory and executable on the programmable logic device. For example, the programmable logic device may be an FPGA.

[0160] The memory 126, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as the program instructions and modules corresponding to the data transmission method in this embodiment of the invention. The processor 120 or programmable logic device executes the software programs, instructions, and modules stored in the memory 126 to perform various functional applications and data processing of the electronic device, thereby realizing the aforementioned data transmission method.

[0161] The memory 126 may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on terminal usage. Furthermore, the memory 126 may include high-speed random access memory and non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, the memory 126 may further include memory remotely located relative to the processor 120, which can be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0162] This invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform a data transmission method applied in a data transmission device. The method includes:

[0163] The device receives first data sent by the first data module at a first line rate and stores the first data in the first memory of the data transmission device;

[0164] When it is determined that the amount of data in the first memory meets the first preset condition, a first stop signal is sent to the first data module so that the first data module stops sending the first data after receiving the first stop signal;

[0165] When it is determined that the amount of data in the first memory is not empty, the first data to be sent in the first memory is read and the first data to be sent to the second data module at the second line rate;

[0166] When it is determined that the amount of data in the first memory is empty, reading the first data to be sent from the first memory is stopped.

[0167] Of course, the computer-executable instructions provided in the embodiments of the present invention are not limited to the above-described method operations, but can also perform related operations in the data transmission method provided in any embodiment of the present invention.

[0168] Based on the above description of the implementation methods, those skilled in the art can clearly understand that the present invention can be implemented using software and necessary general-purpose hardware, and of course, it can also be implemented using hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk, or optical disk, including several instructions to cause an electronic device to execute the methods of the various embodiments of the present invention.

[0169] It is worth noting that in the embodiments of the above data transmission device, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy distinction between each other and are not used to limit the scope of protection of the present invention.

[0170] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A data transmission method, suitable for the case that the interface line rate of a first data module and a second data module does not match, characterized in that, The application is applied to a data transmission device, comprising: receiving first data sent by a first data module at a first line rate and storing the first data in a first memory of the data transmission device; when determining that the amount of data in the first memory meets a first preset condition, sending a first stop signal to the first data module, so that the first data module stops sending first data after receiving the first stop signal; when determining that the amount of data in the first memory is not empty, reading first to-be-sent data in the first memory and sending the first to-be-sent data to a second data module at a second line rate; when determining that the amount of data in the first memory is empty, stopping reading the first to-be-sent data in the first memory; wherein the first data module and the second data module are modules in two different devices; after sending the first stop signal to the first data module, the method further comprises: receiving a first keep-alive signal sent by the first data module; wherein the first keep-alive signal is used to keep the connection between the first data module and the second data module, and the first keep-alive signal is sent by the first data module after receiving the first stop signal and after sending a group of first data; wherein the group of first data comprises N valid data and M-N invalid data, M and N are the bit widths of each sub-module in the first data module and the second data module, and M is greater than N.

2. The method of claim 1, wherein, the method further comprises: when determining that the amount of data in the first memory is empty, sending a second keep-alive signal to the second data module; wherein the second keep-alive signal is used to keep the connection between the second data module and the first data module.

3. The method according to claim 1 or 2, characterized in that, after sending the first stop signal to the first data module, the method further comprises: after a first preset time period, returning to execute the step of "receiving first data sent by a first data module at a first line rate and storing the first data in a memory".

4. The method of claim 3, wherein, The first preset time period is less than or equal to the time required for the first data module to transmit a first data amount and greater than or equal to the time required for the first data module to transmit a second data amount, the first data amount is T / 2, the second data amount is T / 4, and T represents the capacity of the first memory.

5. The method according to claim 1 or 2, characterized in that, The first preset condition is that the amount of data in the first memory is greater than or equal to a third data amount, and the third data amount is T / 4, and T represents the capacity of the first memory.

6. The method of claim 1 or 2, wherein, the method further comprises: receiving second data sent by a second data module at a second line rate and storing the second data in a second memory of the data transmission device; when determining that the amount of data in the second memory meets a second preset condition, sending a second stop signal to the second data module, so that the second data module stops sending second data after receiving the second stop signal; when determining that the amount of data in the second memory is not empty, reading second to-be-sent data in the second memory and sending the second to-be-sent data to the first data module at the first line rate; stop reading the second to-be-sent data in the second memory when it is determined that the amount of data in the second memory is empty.

7. A data transmission apparatus adapted for a mismatch of interface line rates between a first data module and a second data module for transmitting data therebetween, characterized by, The application comprises: a first transceiving module, a second transceiving module, a data flow controller, and a first memory; The first transceiving module, the second transceiving module, and the first memory are all connected to the data flow controller, the first transceiving module is used to connect a first data module, and the second transceiving module is used to connect a second data module; The first transceiving module is used to receive first data sent by the first data module at a first line rate and send the first data to the data flow controller; The data flow controller is used to store the first data in the first memory; The data flow controller is also used to send a first stop signal to the first data module through the first transceiving module when it is determined that the amount of data in the first memory meets a first preset condition, so that the first data module stops sending first data after receiving the first stop signal; The data flow controller is also used to read first to-be-sent data in the first memory and send the first to-be-sent data to the second transceiving module when it is determined that the amount of data in the first memory is not empty, and the second transceiving module is used to send the first to-be-sent data to the second data module at a second line rate; The data flow controller is also used to stop reading the first to-be-sent data in the first memory when it is determined that the amount of data in the first memory is empty. The first data module and the second data module are modules in two different devices; The first transceiving module is also used to: receive a first keep-connected signal sent by the first data module; the first keep-connected signal is used to keep the connection between the first transceiving module and the first data module, and the first keep-connected signal is sent by the first data module after receiving the first stop signal and after sending a group of first data; the group of first data includes N-bit valid data and M-N-bit invalid data, M and N are the bit widths of each sub-module in the first data module and the second data module, and M is greater than N.

8. The apparatus of claim 7, wherein, The device also comprises a second memory connected to the data flow controller; The second transceiving module is also used to receive second data sent by the second data module at a second line rate and send the second data to the data flow controller; The data flow controller is also used to store the second data in the second memory; The data flow controller is also used to send a second stop signal to the second data module through the second transceiving module when it is determined that the amount of data in the second memory meets a second preset condition, so that the second data module stops sending second data after receiving the second stop signal; The data flow controller is further configured to read second to-be-sent data in the second memory when determining that the amount of data in the second memory is not empty, and send the second to-be-sent data to the first transceiving module, and the first transceiving module is further configured to send the second to-be-sent data to the first data module at a first line rate. The data flow controller is further configured to stop reading the second to-be-sent data in the second memory when determining that the amount of data in the second memory is empty.

9. A data transmission system, characterized by The data transmission device comprises: a first data module, a second data module, and the data transmission device according to claim 7 or 8. The first data module is connected to a first transceiving module in the data transmission device, and the second data module is connected to a second transceiving module in the data transmission device.

10. The system of claim 9, wherein, The first data module and / or the second data module comprise a first sub-module and a second sub-module.

11. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the program to implement the data transmission method according to any one of claims 1-6.

12. A computer readable storage medium having stored thereon a computer program, characterized in that, The program is executed by the processor to implement the data transmission method according to any one of claims 1-6.

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