Verification method combining scoreboards and assertion checks

Abstract

The application discloses a verification method combining a score board and an assertion check, and comprises the following steps: declaring a uvm_event event in the score board, which is used for controlling an enabling switch variable of the assertion; instantiating the uvm_event event in a build_phase in a phase mechanism of UVM, and transmitting the uvm_event event into a configuration database of UVM; encapsulating all the assertions used for the check into a package file, and controlling the switch state of the assertion through a disable iff() keyword; creating an assertion configuration object derived from uvm_object in the package file; creating a verification platform, importing the package file in a top module of the verification platform, and using the encapsulated assertion check and the assertion configuration object in the verification environment of the verification platform; executing the check commands in the program control block according to the execution sequence, obtaining the results of the assertion check, and realizing further timing and protocol signal level checks on the problems tracked in the score board. The application can improve the verification efficiency and the verification quality.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and particularly relates to a verification method combining scoreboards and assertion checks. BACKGROUND

[0002] Generally, we will adopt two ways of assertion (systemVerilog assertion) and scoreboard to check the function of the (DUT) RTL design, so as to ensure that the function of the RTL design meets the description requirements of the design manual.

[0003] (1) Scoreboard verification method

[0004] As shown in Figure 1 , the scoreboard (scoreboard) is usually composed of two parts, namely the reference model (predictor) and the comparator (evaluator). Generally, in order to check the correctness of the DUT function, we need to write the reference model (predictor), and then send the same stimulus to the reference model and the DUT, and then calculate the results respectively, and send the calculation results to the comparator (evaluator) for comparison, and judge the correctness of the DUT function by comparing whether the calculation results are consistent. In the whole process, we will use the monitor to monitor the signals on the input and output interfaces (interfaces) of the DUT, and encapsulate them into transaction level data types, and then broadcast them to the scoreboard. The reference model in the scoreboard calculates the expected output result according to the received input interface transaction data, and then compares it with the received output interface transaction data in the comparator, so as to judge the correctness of the DUT function. The scoreboard is based on transaction level data checking, which is higher in abstraction level than the interface (interface) signal level. Higher abstraction level usually has higher simulation efficiency, faster speed, and is easier to model to check the function of the DUT.

[0005] However, this also brings a defect, that is, it is difficult to find errors caused by the timing protocol of the DUT, because the scoreboard is not based on the signal level data of the clock cycle to check, that is, it is difficult to find the root cause of the problem. Generally, when the comparison error is reported, the simulation time from the initial problem root cause has passed many clock cycles, so it is necessary to rely on the patience of the verification developer to observe the signal changes on the waveform to locate the specific problem, especially when there are many interface signals and the timing protocol is complex, the problem locating will become more difficult, which will consume a lot of time of the verification developer, and brings inconvenience to the problem tracking and debugging.

[0006] (2) Assertion verification mode

[0007] The assertion verification is divided into immediate assertion and concurrent assertion. The immediate assertion can be easily used in the verification component such as the class object, but the scene that can be checked is very limited, so we also need the concurrent assertion with more powerful function to do more detailed checking, such as the checking of the clock-based timing protocol. The assertion verification is a powerful supplement to the scoreboard checking, and can complete the signal level protocol checking based on the clock change, thereby helping the verification developer to quickly locate the root cause of the problem.

[0008] However, the more complex concurrent assertion cannot be used in the verification component such as the class object, but can only be used in the module or interface. In this case, the verification developer usually uses the concurrent assertion to do some signal level behavior checking in the interface, but cannot use the powerful concurrent assertion checking mode in the scoreboard, so as to make further checking according to the transaction level data obtained by the scoreboard and the problem tracked by the scoreboard during the simulation process.

[0009] As shown in FIG. 1, it is a verification platform using the two verification modes above. It can be seen that we instantiate the scoreboard in the verification environment (env) and use the assertion checking in the signal interface (interface), so as to do the signal level timing and protocol checking on the signal in the signal interface. Figure 2 Figure 2 Figure 2

[0010] In the existing scheme, the scoreboard (scoreboard) and the assertion (assertion) checking exist at the same time. Since the concurrent assertion is usually checked based on the clock change, the concurrent assertion will be checked at each clock cycle. However, there are a large number of situations that do not need to be checked by the assertion. Since the scoreboard does not report the existence of the comparison error at each clock cycle, the concurrent assertion checking at each clock cycle will reduce the simulation performance, prolong the simulation time, and thus reduce the work efficiency of the verification developer. Figure 2 Figure 2

[0011] ​​​​​The above defects are often caused by the fact that the two checking methods are independently operated, i.e., lack of association between each other. Therefore, a verification method is needed to closely combine the score board and the assertion checking, so as to utilize the respective advantages of the two verification methods while avoiding the influence of the defects, and finally improve the quality of verification and the work efficiency of the verification developers. SUMMARY

[0012] According to the embodiment of the present application, a verification method combining score board and assertion checking is provided, comprising the following steps:

[0013] An uvm_event event is declared in the score board, which is used to control the enable switch variable of the assertion;

[0014] The uvm_event event is instantiated in the build_phase in the phase mechanism of UVM, and is transmitted into the configuration database of UVM;

[0015] All the assertions used for checking are encapsulated into a package file, and the disable iff() keyword is used to control the on-off state of the assertion;

[0016] An assertion configuration object derived from uvm_object is created in the package file;

[0017] A verification platform is created, and the package file is imported into the top module of the verification platform, which is used to enable the verification environment of the verification platform to use the encapsulated assertion checking and assertion configuration object;

[0018] The checking commands are sequentially executed in the program control block of the top module of the verification platform according to the execution order, and the results of the assertion checking are obtained, so as to realize further timing and protocol signal level checking of the problems tracked in the score board.

[0019] Further, the assertion configuration object comprises: an enable switch variable for controlling the assertion, a simulation time variable, and other simulation process variables required in concurrent assertion.

[0020] Further, the enable switch variable, the simulation time variable, and the simulation process variable are set as global static variables by using the static keyword.

[0021] Further, the checking commands are sequentially executed in the program control block of the top module of the verification platform according to the execution order, and the results of the assertion checking comprise the following sub-steps:

[0022] The assertion configuration object is declared and instantiated;

[0023] The blocking wait verification platform executes to just enter the running phase of the consumption simulation time, and the wait_for_state method is called through the end_of_elaboration_phase handle, and the parameters UVM_PHASE_DONE and UVM_EQ are passed into the verification platform to wait for the end of the running of the end_of_elaboration_phase phase;

[0024] The uvm_event event in the scoreboard is obtained from the configuration database of UVM, and the wait_trigger method of the obtained uvm_event event is called to wait for the uvm_event event to be triggered;

[0025] When the uvm_event event is triggered, the data variable at the time of triggering of the uvm_event event in the scoreboard is obtained;

[0026] The data variable is assigned to the global static variable of the assertion configuration object in the package file;

[0027] The corresponding concurrent assertion in the package file is called for checking, the global static variable of the assertion configuration object is taken as an input parameter of the concurrent assertion checking and is transmitted, and the result of the assertion checking is obtained.

[0028] Further, the data variable includes an opened assertion control switch, simulation time and other simulation process parameter variables.

[0029] Further, the assignment of the data variable to the global static variable of the assertion configuration object in the package file includes the following sub-steps:

[0030] The obtained opened assertion control switch is assigned to the enable switch variable in the package file, so that the enable switch variable is in an enabled opened state;

[0031] The obtained simulation time is assigned to the simulation time variable in the package file, so that the simulation time variable is the simulation running time when the comparison problem of the scoreboard occurs.

[0032] Further, the assignment of the data variable to the global static variable of the assertion configuration object in the package file further includes the following sub-steps:

[0033] According to the project needs, other simulation process parameter variables are transmitted to the simulation process variables required to be used in other concurrent assertions.

[0034] The verification method combining the scoreboard and the assertion checking according to the embodiment of the application has the following beneficial effects:

[0035] (1) The embodiment of the present application innovatively uses uvm_event event synchronization, a configuration database of UVM and a comprehensive method of phase mechanism of UVM, realizes close cooperation between a score board and concurrent assertion checking, thereby helping verification developers to perform more comprehensive function checking and faster positioning of the root of a problem.

[0036] (2) The embodiment of the present application realizes parameter sharing in a simulation process between a score board and concurrent assertion checking, thereby innovatively realizing dynamic characteristics of concurrent assertion checking and avoiding defects that can only be used in static modules or interfaces.

[0037] (3) The embodiment of the present application avoids defects that a score board cannot check signal level problems and solves simulation performance problems caused by enabling and activating of concurrent assertion in the whole simulation process, innovatively combines the two to realize function checking from an abstract transaction level by a score board first and then checking from a more detailed signal level in terms of timing and protocol by concurrent assertion, finally realizes rapid positioning of the root of a DUT function problem, greatly improves the work efficiency of verification developers and greatly improves the quality of verification work.

[0038] It is to be understood that both the foregoing general description and the following detailed description are exemplary and intended to provide further explanation of the subject technology claimed. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 is a component structure diagram of a score board.

[0040] Figure 2 is a verification platform structure diagram of an existing scheme.

[0041] Figure 3 is a verification platform structure diagram of a verification method combining a score board and assertion checking according to the embodiment of the present application.

[0042] Figure 4 is a flow chart of the verification method combining a score board and assertion checking according to the embodiment of the present application.

[0043] Figure 5 is a first sub-step flow chart of the verification method combining a score board and assertion checking according to the embodiment of the present application.

[0044] Figure 6 is a second sub-step flow chart of the verification method combining a score board and assertion checking according to the embodiment of the present application.

[0045] Figure 7A third sub-step flowchart of the verification method combining scoreboards and assertion checks according to an embodiment of the present application. DETAILED DESCRIPTION

[0046] The preferred embodiments of the present application will be described in detail with reference to the drawings, and the present application will be further described.

[0047] First, the verification method combining scoreboards and assertion checks according to an embodiment of the present application will be described. Figures 3-7 The verification method combining scoreboards and assertion checks according to an embodiment of the present application is used for chip verification and has a wide range of application scenarios.

[0048] As shown in Figures 3-7 , the verification method combining scoreboards and assertion checks according to an embodiment of the present application has the following steps:

[0049] In S1, as shown in Figure 4 , declare a uvm_event event in the scoreboard to control the enable switch variable of the assertion.

[0050] In S2, as shown in Figure 4 , instantiate the uvm_event event in the build_phase of the phase mechanism of UVM and pass it into the configuration database of UVM. In this embodiment, the range space passed in is the entire verification platform. Then, in the process of comparing the reference model output result with the actual operation result of the DUT, if an error occurs, the trigger method is called to trigger the uvm_event event. At the same time, the system function $time is called to obtain the current simulation time, then the assertion control switch is opened, and the current simulation time and the enable opened assertion control switch are also passed into the UVM configuration database. Note that the range space passed in is still the entire verification platform. In addition, more simulation process variable parameters required in concurrent assertions can also be passed, so that the scoreboard and the assertion check are closely associated and cooperated to perform function checking and problem positioning.

[0051] In S3, as shown in Figure 4 , encapsulate all the assertions for checking into a package file, and control the switch state of the assertion through the disable iff() keyword. In this embodiment, disable iff() is a syntax function provided by SystemVerilog, which is used to control the enable switch of the statement, and SystemVerilog is a programming and development language for digital chip design and verification.

[0052] In S4, as shown in Figure 4As shown: Create an assertion configuration object derived from uvm_object in the package file. Further, in this embodiment, the assertion configuration object includes: enable / disable variables to control assertions, simulation time variables, and other simulation process variables needed in concurrent assertions. Enable / disable variables, simulation time variables, and simulation process variables must be set as global static variables using the static keyword.

[0053] In S5, such as Figure 4 As shown: Create a verification platform. Import the package file into the top-level module of the verification platform so that the verification environment of the verification platform can use the encapsulated assertion check and assertion configuration objects.

[0054] In S6, such as Figure 4 As shown: In the program control block of the top-level module of the verification platform, the check commands are executed sequentially according to the execution order to obtain the results of the assertion checks, thereby realizing further timing and protocol signal-level checks on the problems traced in the scoreboard. In this embodiment, the program control block `initial begin ... end` is a program block syntax provided by the SystemVerilog language, and this program block will only be executed once during the simulation run.

[0055] Furthermore, such as Figure 5 As shown: In this embodiment, the check commands are executed sequentially in the program control block of the top-level module of the verification platform to obtain the assertion check results, which includes the following sub-steps (i.e., the first sub-step):

[0056] In S61, such as Figure 5 As shown: Declare and instantiate the assertion configuration object.

[0057] In S62, such as Figure 5 As shown: The verification platform is blocked and waiting for the simulation time-consuming execution phase to begin. The `wait_for_state` method is called through the `end_of_elaboration_phase` handle, passing the parameters `UVM_PHASE_DONE` and `UVM_EQ` to the verification platform to wait for the `end_of_elaboration_phase` phase to finish. `UVM_EQ` refers to the logical operation action defined by UVM to represent equality; it is an enumeration type parameter. `UVM_PHASE_DONE` refers to the execution phase defined by UVM to represent the current phase, i.e., the state where the phase is about to end and close. Combining these two meanings, it means "blocking and waiting for the verification platform to enter the simulation time-consuming execution phase."

[0058] In S63, such as Figure 5As shown: retrieve the uvm_event event from the scoreboard in the UVM configuration database, and call the wait_trigger method of the retrieved uvm_event event to wait for the uvm_event event to be triggered.

[0059] In S64, such as Figure 5 As shown: When the uvm_event event is triggered, the data variables at the time of the uvm_event event triggering in the scoreboard are retrieved. Further, in this embodiment, the data variables include: the enabled assertion control switch, simulation time, and other simulation process parameter variables.

[0060] In S65, such as Figure 5 As shown: Assign the data variable to the global static variable of the assertion configuration object in the package file.

[0061] Furthermore, such as Figure 6 As shown, in this embodiment, assigning the data variable to the global static variable of the assertion configuration object in the package file includes the following sub-step (i.e., the second sub-step):

[0062] In S651, such as Figure 6 As shown: The acquired open assertion control switch is assigned to the enable switch variable in the package file, so that the enable switch variable is in the enabled state. This allows the assertion check to be turned on again when a comparison problem occurs on the scoreboard, thereby improving simulation performance.

[0063] In S652, such as Figure 6 As shown: The acquired simulation time is assigned to the simulation time variable in the package file, making the simulation time variable the simulation runtime when the scoreboard comparison problem occurs. This allows the simulation runtime variable to be used in concurrent assertions to control the simulation time window of the assertion check, thereby further narrowing the simulation time range and locating the root cause of the problem more quickly.

[0064] Furthermore, such as Figure 7 As shown, in this embodiment, assigning the data variable to the global static variable of the assertion configuration object in the package file further includes the following sub-step (i.e., the third sub-step):

[0065] In S653, such as Figure 7 As shown: According to project needs, other simulation process parameter variables can be passed to simulation process variables that need to be used in other concurrent assertions, thereby realizing the sharing of running parameters between the two.

[0066] In S66, such as Figure 5As shown, the corresponding concurrent assertion in the package file is called for checking, and the global static variable of the assertion configuration object is passed in as an input parameter of the concurrent assertion checking, and the result of the assertion checking is obtained.

[0067] The above, with reference to Figures 3-7 The verification method combining the score board and the assertion checking according to the embodiment of the application is described, and has the following beneficial effects:

[0068] (1) The embodiment innovatively uses the uvm_event event synchronization, the configuration database of UVM and the phase mechanism of UVM, realizes the close cooperation between the score board and the concurrent assertion checking, and thus helps the verification developers to perform more comprehensive function checking and faster positioning of the root cause of the problem.

[0069] (2) The embodiment realizes the parameter sharing in the simulation process between the score board and the concurrent assertion checking, and thus innovatively realizes the dynamic characteristics of the concurrent assertion checking and avoids the defects that can only be used in the static module or interface.

[0070] (3) The embodiment avoids the defects that the score board cannot check the signal level problem, solves the simulation performance problem caused by the concurrent assertion being enabled and activated in the whole simulation process, innovatively combines the two to realize the function checking from the abstract transaction level by the score board first, and then the timing and protocol checking from the more detailed signal level by the concurrent assertion, and finally realizes the fast positioning of the root cause of the DUT function problem, greatly improves the work efficiency of the verification developers, and at the same time greatly improves the quality of the verification work.

[0071] It should be noted that in the present specification, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, methods, articles or devices. Without more limitations, the elements defined by the statement "including" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0072] Although the content of the present application has been described in detail by the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present application. After reading the above content, various modifications and alternatives of the present application will be obvious to those skilled in the art. Therefore, the protection scope of the present application should be defined by the appended claims.

Claims

1. A verification method combining scoreboard and assertion check, characterized in that, The method comprises the following steps: Declaring a uvm_event event in a score board for controlling an enabling switch variable of an assertion; Instantiating the uvm_event event in a build_phase of a phase mechanism of UVM and inputting into a configuration database of UVM; Packaging all the assertions for checking into a package file and controlling the switch state of the assertions by a disable iff() keyword; Creating an assertion configuration object derived from uvm_object in the package file; Creating a verification platform, importing the package file in a top module of the verification platform for enabling the verification environment of the verification platform to use the packaged assertion checking and assertion configuration object; Executing the checking commands in the program control block of the top module of the verification platform in sequence according to the execution order, obtaining the results of the assertion checking, and thus realizing further timing and protocol signal level checking of the problems tracked in the score board; The assertion configuration object comprises an enabling switch variable of the assertion, a simulation time variable and other simulation process variables required in concurrent assertions; The enabling switch variable, the simulation time variable and the simulation process variable are set as global static variables by using a static keyword; The method comprises the following steps: Declaring and instantiating the assertion configuration object; Blocking and waiting for the verification platform to execute to the running phase just before consuming simulation time, calling a wait_for_state method through an end_of_elaboration_phase handle, and passing the parameters UVM_PHASE_DONE and UVM_EQ into the verification platform to wait for the running end of the end_of_elaboration_phase phase; Obtaining the uvm_event event in the score board from the configuration database of UVM, and calling a wait_trigger method of the obtained uvm_event event to wait for the uvm_event event to be triggered; After the uvm_event event is triggered, obtaining the data variable when the uvm_event event is triggered in the score board; Assigning the data variable to the global static variable of the assertion configuration object in the package file; Calling the corresponding concurrent assertion in the package file for checking, inputting the global static variable of the assertion configuration object as an input parameter of the concurrent assertion checking, and obtaining the results of the assertion checking.

2. The verification method combining scoreboard and assertion checking as described in claim 1, characterized in that, The data variable comprises an opened assertion control switch, simulation time and other simulation process parameter variables.

3. The verification method combining scoreboard and assertion checking as described in claim 2, characterized in that, The method comprises the following steps: Assigning the data variable to the global static variable of the assertion configuration object in the package file comprises the following steps: Assigning the acquired open assertion control switch to the enable switch variable in the package file, so that the enable switch variable is in an enable open state; Assigning the acquired simulation time to the simulation time variable in the package file, so that the simulation time variable is the simulation running time when the scoreboard appearance comparison problem occurs.

4. The method of claim 3, wherein the score board and assertion check are combined to verify that the system is functioning correctly.

5. The method of claim 4, wherein the score board and assertion check are combined to verify that the system is functioning correctly. The step of assigning the data variable to the global static variable of the assertion configuration object in the package file further includes the following sub-steps: According to the project needs, the other simulation process parameter variables are transmitted to the simulation process variables required to be used in the other concurrent assertions.

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