An integrated circuit package structure with a radio frequency chip and a method of manufacturing the same

Abstract

The application discloses a preparation method of an integrated circuit package structure containing a radio frequency chip, which comprises the following steps: providing a substrate, manufacturing a circuit structure on the substrate, and manufacturing a first area and a second area on the circuit structure; manufacturing a wall-type shielding wall around the first area and manufacturing a plurality of spaced conductive columns around the second area; providing at least one first chip and a plurality of second chips, wherein the first chip is a radio frequency chip, the first chip is attached to the first area, and the second chip is attached to the second area; plastic packaging the first chip, the second chip, the shielding wall and the conductive column to form a first plastic packaging layer; manufacturing a metal layer on the first plastic packaging layer, performing a patterning treatment on the metal layer, forming a shielding cover connected with the upper end of the shielding wall and covering the mounting groove and a third circuit layer connected with the upper end of the copper column, and the shielding wall and the shielding cover form a shielding cover; and providing a plurality of third chips, attaching the third chips to the third circuit layer and electrically leading out.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of advanced electronic packaging technology, and particularly relates to a preparation method of an integrated circuit packaging structure containing a radio frequency chip and an integrated circuit packaging structure containing a radio frequency chip prepared by the preparation method. BACKGROUND

[0002] In recent years, with the requirement of miniaturization of electronic products, packaging technology is constantly innovated, and intelligent module technology is rapidly developing. Due to the high distribution density of electronic components, the lines between electronic components are short, and the electronic components need to work at a very high working frequency, so the electromagnetic interference between the electronic components from the outside or inside of the electronic product is increasingly serious. In order to prevent mutual interference of electromagnetic waves, various anti-electromagnetic interference schemes have emerged.

[0003] There are mainly two kinds of traditional electromagnetic shielding structures: one is to add a metal cover on a wireless or radio frequency module alone, and the disadvantage is low integration and large size; the other is an existing electromagnetic shielding packaging module structure, and the main process is to groove, fill metal, and form an electromagnetic shielding layer on the surface of the encapsulation body by metal sputtering, spraying or other plating methods after encapsulation. The disadvantage of this method is that the epoxy resin filled with 70-75% metal material is used to fill the grooved part of the plastic encapsulation body during encapsulation, but the high content of metal is difficult to uniformly distribute in the epoxy resin, and is easy to deposit at the bottom of the encapsulation layer, forming a layered structure of metal aggregation area and epoxy resin area. SUMMARY

[0004] The purpose of the present application is to provide a preparation method of an integrated circuit packaging structure containing a radio frequency chip, which can simultaneously prepare a shielding cover integrated circuit packaging structure for shielding the electromagnetic effect of the radio frequency chip when preparing the circuit, simplify the process and structure, and reduce crosstalk and production cost.

[0005] To achieve this purpose, the present application adopts the following technical scheme:

[0006] On the one hand, a preparation method of an integrated circuit packaging structure containing a radio frequency chip is provided, comprising the following steps:

[0007] S10, a substrate with temporary bonding glue is provided, a circuit structure is made on the substrate, and the circuit structure has a first area and a second area;

[0008] The substrate can be an FR-4 substrate, and the size is not limited, and the shape is preferably square;

[0009] S20, a wall type shielding wall is made around the first area, and a plurality of shielding walls enclose an installation groove, and a plurality of spaced conductive columns are made around the second area;

[0010] The shielding wall and the conductive column are synchronously manufactured.

[0011] S30, providing at least one first chip and a plurality of second chips, the first chip being a radio frequency chip (RF), the first chip being attached to the first area and located in the mounting groove, and the second chip being attached to the second area;

[0012] S40, plastic packaging the first chip, the second chip, the shielding wall and the conductive column to form a first plastic packaging layer;

[0013] S50, manufacturing a metal layer on the first plastic packaging layer, and performing a patterning process on the metal layer to form a shielding cover connected to the upper end of the shielding wall and covering the mounting groove, and a third circuit layer connected to the upper end of the copper column, the shielding wall and the shielding cover forming a shielding cover;

[0014] S60, providing a plurality of third chips, and attaching the third chips to the third circuit layer and electrically leading out.

[0015] In the above preparation method, the first chip and the second chip are fixed above the circuit structure by reflow soldering to realize electrical connection, and the third chip is fixed above the third circuit layer by reflow soldering to realize electrical connection. The specific process parameters of reflow soldering are conventional technical means in the art, and will not be described in detail.

[0016] The present application aims at the problem of crosstalk and complex packaging method of radio frequency chips in integrated circuits, and the circuit and the shielding cover are manufactured together to simplify the process and structure, reduce crosstalk and cost.

[0017] Specifically, the present application first manufactures a circuit structure, then divides the packaging area according to the radio frequency chip and other chips (non-radio frequency chip) to be packaged, divides the circuit structure into a first area for packaging the radio frequency chip and a second area for packaging other chips, then simultaneously manufactures a shielding wall of metal material in the first area and a plurality of spaced conductive columns in the second area; after fixing the radio frequency chip and other chips, simultaneously manufacturing a shielding cover connected to the upper end of the shielding wall and a third circuit layer connected to the upper end of the conductive column on the first plastic packaging layer, so that the shielding wall and the shielding cover form a metal shielding cover, which wraps the radio frequency chip, effectively forms electromagnetic shielding, and reduces the crosstalk of the radio frequency chip signal to other chips.

[0018] Further, in one of the technical solutions of the present application, step S10 specifically comprises the following steps:

[0019] S10a, providing a substrate, and attaching a temporary bonding glue on the substrate;

[0020] S10b, making a first circuit layer on the temporary bonding glue;

[0021] The first circuit layer is the circuit structure.

[0022] The step S10b specifically comprises the following steps:

[0023] Making a first seed layer on the temporary bonding glue by vacuum sputtering;

[0024] Making a first metal layer on the first seed layer by electroplating;

[0025] Pasting a photosensitive film on the first metal layer;

[0026] Exposing and developing the photosensitive film to expose part of the first metal layer;

[0027] Etching the first metal layer exposed to the photosensitive film and the first seed layer directly below the first metal layer, and then removing the residual photosensitive film to obtain a first circuit layer, which is the circuit structure.

[0028] Further, in another technical solution of the present application, the step S10 specifically comprises the following steps:

[0029] S10a, providing a substrate, and pasting a temporary bonding glue on the substrate;

[0030] S10b, making a first circuit layer on the temporary bonding glue;

[0031] S10c, making a dielectric layer above the first circuit layer;

[0032] S10d, making a hole structure by hole processing the dielectric layer to expose part of the first circuit layer;

[0033] S10e, making a connecting column at the hole structure and a second circuit layer connected with the connecting column on the dielectric layer;

[0034] The circuit structure is formed by connecting the first circuit layer and the second circuit layer through the connecting column.

[0035] The step S10b specifically comprises the following steps:

[0036] Making a first seed layer on the temporary bonding glue by vacuum sputtering;

[0037] Making a first metal layer on the first seed layer by electroplating;

[0038] Pasting a photosensitive film on the first metal layer;

[0039] Exposing and developing the photosensitive film to expose part of the first metal layer;

[0040] Etching the first metal layer exposed to the photosensitive film and the first seed layer located directly below the first metal layer to remove the residual photosensitive film to obtain the first circuit layer.

[0041] The step S10e specifically comprises the following steps:

[0042] Exposing and developing the dielectric layer to form a hole structure exposing part of the first circuit layer;

[0043] Making a second seed layer on the inner wall of the hole structure and the dielectric layer by vacuum sputtering;

[0044] Filling the hole structure with metal by electroplating to form a connecting column, and making a second metal layer on the second seed layer by electroplating;

[0045] Pasting a photosensitive film on the second metal layer;

[0046] Exposing and developing the photosensitive film to expose part of the second metal layer;

[0047] Etching the second metal layer exposed to the photosensitive film and the second seed layer located directly below the second metal layer to remove the residual photosensitive film to obtain the second circuit layer.

[0048] Further, the step S20 specifically comprises the following steps:

[0049] S20a, making a first copper pad arranged in a ring around the first area and a plurality of second copper pads arranged at intervals in the second area;

[0050] S20b, making a wall type shielding wall on the first copper pad and surrounding a plurality of the shielding walls to form an installation slot, and making a conductive column on the second copper pad.

[0051] The preparation method of the first copper pad, the second copper pad and the conductive column is the same as the preparation method of the first circuit layer, and details are not repeated.

[0052] In the present application, the step S50 specifically comprises the following steps:

[0053] S50a, thinning the first plastic sealing layer to expose the upper end of the conductive column and the shielding wall;

[0054] S50b, making a third seed layer on the first plastic sealing layer by vacuum sputtering;

[0055] S50c, making a third metal layer on the third seed layer by electroplating;

[0056] S50d, sticking a photosensitive film on the third metal layer;

[0057] S50e, exposing and developing the photosensitive film to expose part of the third metal layer;

[0058] S50f, etching the third metal layer exposed to the photosensitive film and the third seed layer located directly below the third metal layer to remove the residual photosensitive film, thereby obtaining a shielding cover connected to the upper end of the shielding wall and covering the mounting groove, and a third circuit layer connected to the upper end of the conductive column, wherein the shielding wall and the shielding cover form a shielding cover.

[0059] Further, step S60 specifically comprises the following steps:

[0060] S60a, providing a plurality of third chips and sticking the third chips on the third circuit layer;

[0061] S60b, molding the third chips to form a second molding layer covering the shielding cover and the third chips;

[0062] S60c, disassembling and bonding to expose the first circuit layer;

[0063] S60d, manufacturing a solder resist layer on the first circuit layer and opening the solder resist layer to expose the pad area of the first circuit layer;

[0064] S60e, providing a plurality of metal bumps and welding the metal bumps to the pad area of the first circuit layer.

[0065] In the above technical solution, the metal layer includes but is not limited to a copper layer and a copper alloy layer.

[0066] On the other hand, the application provides an integrated circuit package structure containing a radio frequency chip prepared by the above method, comprising:

[0067] a first molding layer and a circuit structure located on one side of the first molding layer, wherein the circuit structure has a first area and a second area;

[0068] a shielding wall embedded in the first molding layer and located around the first area, and a plurality of conductive columns embedded in the first molding layer and distributed in the second area, wherein one end of the shielding wall is connected to the circuit structure, and one end of the conductive column is electrically connected to the circuit structure;

[0069] A shielding cover and a third circuit layer formed by patterning a metal layer are located on a side of the first plastic encapsulation layer away from the circuit structure, a periphery of the shielding cover is connected to an end of the shielding wall away from the circuit structure, and the shielding wall and the shielding cover form a shielding cover; the third circuit layer is connected to an end of the conductive column away from the circuit structure.

[0070] At least one first chip and a plurality of second chips encapsulated in the first plastic encapsulation layer, the first chip being a radio frequency chip, the first chip being located in the shielding cover and electrically connected to the circuit structure, and the second chip being located in the second region and electrically connected to the circuit structure.

[0071] A second plastic encapsulation layer and a plurality of third chips located on a side of the first plastic encapsulation layer away from the circuit structure, the third chip being encapsulated in the second plastic encapsulation layer and electrically connected to the third circuit layer.

[0072] The present application uses a first copper pad and a shielding wall as a periphery of a shielding metal cover, forms a shielding cover when forming a circuit layer, and combines the shielding cover and the metal cover to form a metal shielding cover, thereby electromagnetically shielding a radio frequency chip and reducing signal crosstalk of the radio frequency chip to other chips.

[0073] In the present application, the integrated circuit package structure containing a radio frequency chip further comprises a solder resist layer and a plurality of metal bumps, the solder resist layer being located on a side of the circuit structure away from the first plastic encapsulation layer and covering the circuit structure, and a pad area of the circuit structure being exposed to the solder resist layer, and a plurality of the metal bumps being welded to the pad area of the circuit structure. The metal bumps are used to lead out electrical signals.

[0074] In one of the schemes of the present application, the circuit structure is a single-layer structure, i.e., a first circuit layer.

[0075] Specifically, the first circuit layer is formed by patterning a first seed layer and a metal copper layer on the first seed layer.

[0076] In another technical scheme of the present application, the circuit structure is a double-layer structure. Specifically, the circuit structure comprises a first circuit layer and a second circuit layer, and a dielectric layer is arranged between the first circuit layer and the second circuit layer and extends into a patterned hole structure of the first circuit layer, a connecting column is embedded in the dielectric layer, one end of the connecting column is connected to the first circuit layer, and the other end of the connecting column is connected to the second circuit layer, the second circuit layer is embedded into the first plastic encapsulation layer and electrically connected to the first chip and the second chip, and a surface of the second circuit layer is flush with a surface of the first plastic encapsulation layer; the solder resist layer is located on a side of the first circuit layer away from the second circuit layer, and a plurality of the metal bumps are welded to a pad area of the first circuit layer.

[0077] The first circuit layer is formed by a first seed layer and a first metal layer on the first seed layer through a patterning process, and the second circuit layer is formed by a second seed layer and a second metal layer on the second seed layer through a patterning process.

[0078] Specifically, the first seed layer has first patterning holes, and the first metal layer has second patterning holes, the first patterning holes corresponding to the second patterning holes one by one.

[0079] Specifically, the second seed layer has third patterning holes, and the second metal layer has fourth patterning holes, the third patterning holes corresponding to the fourth patterning holes one by one.

[0080] Specifically, the third seed layer has fifth patterning holes, and the third metal layer has sixth patterning holes, the fifth patterning holes corresponding to the sixth patterning holes one by one.

[0081] The materials of the first seed layer and the second seed layer are conventional in the art, and will not be described in detail.

[0082] In the present application, the shielding wall is grounded through the circuit structure.

[0083] The present application has the following advantages: first, the circuit structure is prepared first, then the packaging area is divided according to the to-be-packaged radio frequency chip and other chips (non-radio frequency chips), the circuit structure is divided into a first area for packaging the radio frequency chip and a second area for packaging other chips, then a shielding wall made of metal is prepared in the first area and a plurality of spaced conductive columns are prepared in the second area; after the radio frequency chip and other chips are fixed, a shielding cover connected to the upper end of the shielding wall and a third circuit layer connected to the upper end of the conductive column are prepared on the first plastic packaging layer, so that the shielding wall and the shielding cover form a metal shielding cover, which wraps the radio frequency chip and effectively forms electromagnetic shielding, reducing the signal crosstalk of the radio frequency chip to other chips. BRIEF DESCRIPTION OF DRAWINGS

[0084] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0085] Figure 1 is a flow chart of the preparation method of the integrated circuit packaging structure containing a radio frequency chip according to the embodiment 1 of the present application.

[0086] Figure 2 is a sectional view of the temporary bonding glue attached to the substrate according to the embodiment 1 of the present application.

[0087] Figure 3 is a cross-sectional view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0088] Figure 4 is a cross-sectional view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0089] Figure 5 is a cross-sectional view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0090] Figure 6 is a cross-sectional view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0091] Figure 7 is a cross-sectional view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0092] Figure 8 is a cross-sectional view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0093] Figure 9 is a cross-sectional view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0094] Figure 10 is a cross-sectional view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0095] Figure 11 is a top view of Figure 6 .

[0096] Figure 12 is a top view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0097] Figure 13 is a cross-sectional view of the substrate with temporary bonding glue after the first circuit layer is prepared according to the embodiment 1 of the present application.

[0098] in the figure:

[0099] 1, substrate; 2, temporary bonding glue; 3, first circuit layer; 4, dielectric layer; 5, second circuit layer; 6, first copper pad; 7, second copper pad; 8, shielding wall; 9, conductive column; 10, first chip; 11, second chip; 12, first plastic sealing layer; 13, shielding cover; 14, third circuit layer; 15, third chip; 16, second plastic sealing layer; 17, solder resist layer; 18, metal bump. DETAILED DESCRIPTION

[0100] The technical solutions of the present application are further illustrated below in conjunction with the accompanying drawings and specific embodiments.

[0101] Wherein, the accompanying drawings are only used for exemplary illustration, and the representation is only a schematic diagram, not a physical diagram, and cannot be understood as a limitation on the present patent; in order to better illustrate the embodiments of the present application, some components in the drawings will be omitted, enlarged or reduced, and do not represent the actual product size; for those skilled in the art, it is understandable that some well-known structures in the drawings and their descriptions can be omitted.

[0102] The same or similar reference numerals in the drawings of the embodiments of the present application correspond to the same or similar components; in the description of the present application, it should be understood that if the terms "upper", "lower", "left", "right", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the terms describing the positional relationship in the drawings are only used for exemplary illustration, and cannot be understood as a limitation on the present patent, for those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0103] In the description of the present application, unless otherwise explicitly specified and limited, if the term "connection" and the like appear to indicate the connection relationship between components, the term should be broadly understood, for example, it can be a fixed connection, or a detachable connection, or an integral; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the internal communication of two components or the interaction relationship between two components. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0104] Embodiment one

[0105] The preparation method of the integrated circuit package structure containing a radio frequency chip in the present embodiment is as follows:

[0106] Step 1, providing a substrate 1 of FR-4 material, pasting a temporary bonding glue 2 on the substrate 1, for reference Figure 2 ;

[0107] Step 2, making a first seed layer on the temporary bonding glue 2 by vacuum sputtering;

[0108] Step 3, forming a first metal layer on the first seed layer by electroplating;

[0109] Step 4, pasting a photosensitive film on the first metal layer;

[0110] Step 5, exposing and developing the photosensitive film to make part of the first metal layer exposed;

[0111] Step 6, etching the first metal layer exposed to the photosensitive film and the first seed layer located directly below the first metal layer to remove the residual photosensitive film, to make the first circuit layer 3, as shown in Figure 3 ;

[0112] Step 7, making a dielectric layer 4 above the first circuit layer 3, as shown in Figure 4 ;

[0113] Step 8, making a hole structure that exposes part of the first circuit layer 3 by opening the dielectric layer 4;

[0114] Step 9, making a second seed layer on the inner wall of the hole structure and the dielectric layer 4 by vacuum sputtering;

[0115] Step 10, filling the hole structure with metal by electroplating to form a connecting column, and making a second metal layer on the second seed layer by electroplating;

[0116] Step 11, pasting a photosensitive film on the second metal layer;

[0117] Step 12, exposing and developing the photosensitive film to make part of the second metal layer exposed;

[0118] Step 13, etching the second metal layer exposed to the photosensitive film and the second seed layer located directly below the second metal layer to remove the residual photosensitive film, to make the second circuit layer 5; wherein the first circuit layer 3 and the second circuit layer 5 are connected through the connecting column to form a circuit structure, as shown in Figure 5 ;

[0119] Step 14, making a first copper pad 6 in the form of a ring around the first area A and a plurality of second copper pads 7 spaced apart in the second area; wherein the first copper pad 6 and the second copper pad 7 are made by the same processes of sputtering, electroplating, pasting film, exposure, development, and etching as the first circuit layer 3, and the specific process is not repeated here;

[0120] Step 15, making a wall-type shielding wall 8 on the first copper pad 6 and making a plurality of the shielding walls 8 surround an installation slot, and making a conductive column 9 on the second copper pad 7 (the preparation method is the same as the first circuit layer 3, and the specific process is not repeated here), as shown in Figure 6 ;

[0121] Step 16, provide a first chip 10 and three second chips 11, the first chip 10 is a radio frequency chip (RF), the first chip 10 is pasted to the first area and located in the mounting groove, the second chip 11 is pasted to the second area, reference Figure 11 ;

[0122] Step 17, the first chip 10, the second chip 11, the shielding wall 8 and the conductive column 9 are encapsulated by using epoxy encapsulating material, and a first encapsulating layer 12 is formed, reference Figure 7 ;

[0123] Step 18, the first encapsulating layer 12 is thinned, so that the upper end of the conductive column 9 and the shielding wall 8 is exposed;

[0124] Step 19, a third seed layer is made on the first encapsulating layer 12 by vacuum sputtering;

[0125] Step 20, a third metal layer is made on the third seed layer by electroplating;

[0126] Step 21, a photosensitive film is pasted on the third metal layer;

[0127] Step 22, the photosensitive film is exposed and developed, so that part of the third metal layer is exposed;

[0128] Step 23, the third metal layer exposed to the photosensitive film and the third seed layer located directly below the third metal layer are etched, and the residual photosensitive film is removed, so that a shielding cover 13 connected with the upper end of the shielding wall 8 and covering the mounting groove and a third circuit layer 14 connected with the upper end of the conductive column 9 are made, reference Figure 8 , the shielding wall 8 and the shielding cover 13 constitute a shielding cover;

[0129] Step 24, provide several third chips 15, the third chip 15 is pasted on the third circuit layer 14, reference Figure 12 ;

[0130] Step 25, the third chip 15 is encapsulated to form a second encapsulating layer 16 covering the shielding cover and the third chip 15, reference Figure 9 ;

[0131] Step 26, the first circuit layer 3 is exposed by dismounting and bonding;

[0132] Step 27, the first circuit layer 3 is brushed with solder resist ink, and a solder resist layer 17 is formed after curing, and the solder resist layer 17 is exposed and developed, so that the pad area of the first circuit layer 3 is exposed;

[0133] Step 28, providing a plurality of tin balls (metal bumps 18) which are soldered to the pad area of the first circuit layer 3, referring to Figure 10 .

[0134] In this embodiment, the metal bumps 18 are not limited to tin balls, and other metal materials commonly used in the art are also applicable. The shape of the metal bumps 18 is not limited to spherical, and square, ellipsoidal, and other shapes are also applicable.

[0135] The substrate 1 in this embodiment is not limited to FR-4 material, and can also be a glass substrate or other conventional chip packaging carrier board.

[0136] The integrated circuit packaging structure containing a radio frequency chip made by the method of this embodiment is shown in Figure 10 , which includes:

[0137] The first plastic packaging layer 12 and the circuit structure on one side of the first plastic packaging layer 12, the circuit structure having a first area and a second area;

[0138] The shielding wall 8 embedded in the first plastic packaging layer 12 and located around the first area, and a plurality of conductive columns 9 embedded in the first plastic packaging layer 12 and distributed in the second area, one end of the shielding wall 8 being connected to the circuit structure, and one end of the conductive column 9 being electrically connected to the circuit structure;

[0139] The shielding cover 13 and the third circuit layer 14 formed by patterning a metal layer, located on the side of the first plastic packaging layer 12 away from the circuit structure, the shielding cover 13 being connected to one end of the shielding wall 8 away from the circuit structure, the shielding wall 8 and the shielding cover 13 forming a shielding cover, and the third circuit layer 14 being connected to one end of the conductive column 9 away from the circuit structure;

[0140] At least one first chip 10 and a plurality of second chips 11 packaged in the first plastic packaging layer 12, the first chip 10 being a radio frequency chip, the first chip 10 being located in the shielding cover and electrically connected to the circuit structure, and the second chip 11 being located in the second area and electrically connected to the circuit structure;

[0141] The second plastic packaging layer 16 and a plurality of third chips 15 located on the side of the first plastic packaging layer 12 away from the circuit structure, the third chip 15 being packaged in the second plastic packaging layer 16 and electrically connected to the third circuit layer 14.

[0142] Specifically, the solder resist layer 17 is located on the side of the circuit structure away from the first plastic sealing layer 12 and covers the circuit structure, and the pad area of the circuit structure is exposed to the solder resist layer 17, and a plurality of metal bumps 18 are welded to the pad area of the circuit structure.

[0143] Specifically, the circuit structure includes a first circuit layer 3 and a second circuit layer 5, and a dielectric layer 4 extending into the patterned hole structure of the first circuit layer 3 is arranged between the first circuit layer 3 and the second circuit layer 5, a connecting column is embedded in the dielectric layer 4, one end of the connecting column is connected with the first circuit layer 3, and the other end is connected with the second circuit layer 5, the second circuit layer 5 is embedded into the first plastic sealing layer 12 and electrically connected with the first chip 10 and the second chip 11, and one surface of the second circuit layer 5 is flush with one surface of the first plastic sealing layer 12; the solder resist layer 17 is located on the side of the first circuit layer 3 away from the second circuit layer 5, and a plurality of metal bumps 18 are welded to the pad area of the first circuit layer 3.

[0144] Further, the first circuit layer 3 is composed of a first seed layer and a first metal layer which are patterned respectively. One surface of the first seed layer is flush with one surface of the dielectric layer 4, and the first metal layer is located on the other surface of the first seed layer and connected with one end of the connecting column.

[0145] Specifically, the first seed layer has a first patterned hole, the first metal layer has a second patterned hole, and the first patterned hole corresponds to the second patterned hole one by one.

[0146] Further, the second circuit layer 5 is composed of a second seed layer and a second metal layer which are patterned respectively. The second seed layer is located on the dielectric layer 4, and one surface of the second seed layer in contact with the dielectric layer 4 is flush with one surface of the first plastic sealing layer 12, and the second metal layer is located on the second seed layer and connected with the first chip 10 and the second chip 11 and the first copper pad 6 and the second copper pad 7.

[0147] Specifically, the second seed layer has a third patterned hole, the second metal layer has a fourth patterned hole, and the third patterned hole corresponds to the fourth patterned hole one by one.

[0148] Further, the third circuit layer 14 is composed of a third seed layer and a third metal layer which are patterned respectively.

[0149] Specifically, the third seed layer has a fifth patterned hole, the third metal layer has a sixth patterned hole, and the fifth patterned hole corresponds to the sixth patterned hole one by one.

[0150] In other specific embodiments, the third circuit layer 14 is a patterned third metal layer, i.e. without a third seed layer, and a stable electrical connection between the conductive pillars 9 can be achieved.

[0151] Embodiment two

[0152] This embodiment is basically the same as the above-mentioned embodiments, with the difference being the preparation method of the circuit structure.

[0153] The preparation method of the circuit structure of this embodiment is the preparation method of the first circuit layer, and compared with the above-mentioned embodiment 1, steps 7-13 are omitted, and details are not repeated.

[0154] Correspondingly, the prepared integrated circuit package structure containing a radio frequency chip is as shown in FIG. 6. Figure 13 The circuit structure is a single-layer structure, i.e. the first circuit layer 3, and compared with the integrated circuit package structure containing a radio frequency chip prepared in embodiment 1, the dielectric layer 4 and the second circuit layer 5 are omitted, and details are not repeated.

[0155] Of course, in other embodiments, three or more layers of circuit structures can also be prepared according to actual needs.

[0156] It should be noted that the above-mentioned specific embodiments are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art should understand that various modifications, equivalent replacements, changes, etc. can also be made to the present application. However, as long as these changes do not deviate from the spirit of the present application, they should be within the protection scope of the present application. In addition, some terms used in the present application specification and claims are not limited, but are only for the convenience of description.

Claims

1. A method for fabricating an integrated circuit packaging structure containing a radio frequency chip, characterized in that, Includes the following steps: S10. A substrate with temporary bonding adhesive is provided, and a circuit structure is fabricated on the substrate, the circuit structure having a first region and a second region. S20. A first copper pad arranged in a ring is made around the first area and a plurality of second copper pads are made at intervals in the second area; a wall-like shielding wall is made on the first copper pad and the shielding wall forms an installation groove, and a conductive post is made on the second copper pad. S30. Provide at least one first chip and several second chips, wherein the first chip is an radio frequency chip, the first chip is attached to the first area and located in the mounting slot, and the second chips are attached to the second area; S40. The first chip, the second chip, the shielding wall, and the conductive pillar are encapsulated to form a first encapsulation layer; S50. A metal layer is fabricated on the first molding layer, and the metal layer is patterned to form a shielding cover that is connected to the upper end of the shielding wall and covers the mounting groove, and a third circuit layer that is connected to the upper end of the conductive post. The shielding wall and the shielding cover constitute a shielding cover. S60. Provide a plurality of third chips, attach the third chips to the third circuit layer and electrically lead them out.

2. The method for fabricating an integrated circuit packaging structure containing an RF chip according to claim 1, characterized in that, Step S10 specifically includes the following steps: S10a. A substrate is provided, and temporary bonding adhesive is applied to the substrate; S10b, A first circuit layer is formed on the temporary bonding adhesive; The first line layer is the line structure.

3. The method for fabricating an integrated circuit packaging structure containing a radio frequency chip according to claim 1, characterized in that, Step S10 specifically includes the following steps: S10a. A substrate is provided, and temporary bonding adhesive is applied to the substrate; S10b, A first circuit layer is formed on the temporary bonding adhesive; S10c. Fabricate a dielectric layer above the first circuit layer; S10d: The dielectric layer is perforated to form a hole structure that exposes part of the first circuit layer. S10e, a connecting post is made at the hole structure and a second circuit layer connected to the connecting post is made on the dielectric layer; The circuit structure is formed by connecting the first circuit layer and the second circuit layer through connecting posts.

4. The method for fabricating an integrated circuit packaging structure containing a radio frequency chip according to claim 3, characterized in that, Step S50 specifically includes the following steps: S50a. The first molding layer is thinned to expose the upper ends of the conductive pillar and the shielding wall. S50b, Create a third seed layer on the first molding layer; S50c, A third metal layer is formed on the third seed layer; S50d, A photosensitive film is attached to the third metal layer; S50e, Expose and develop the photosensitive film to expose part of the third metal layer; S50f, the third metal layer exposed to the photosensitive film and the third seed layer located directly below the third metal layer are etched to remove the residual photosensitive film, thereby obtaining a shielding cover that is connected to the upper end of the shielding wall and covers the mounting groove, and a third circuit layer that is connected to the upper end of the conductive post. The shielding wall and the shielding cover constitute a shielding cover.

5. The method for fabricating an integrated circuit packaging structure containing an RF chip according to claim 4, characterized in that, Step S60 specifically includes the following steps: S60a. Provide a plurality of third chips and attach the third chips onto the third circuit layer; S60b, The third chip is encapsulated to form a second encapsulation layer covering the shield and the third chip; S60c, Debond the connection to expose the first circuit layer; S60d. A solder mask layer is fabricated on the first circuit layer, and the solder mask layer is made into an opening to expose the pad area of ​​the first circuit layer. S60e, Provide a plurality of metal bumps and solder the metal bumps to the pad area of ​​the first circuit layer.

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