Display panel and manufacturing method thereof, and display device

Abstract

The embodiment of the present application provides a display panel and a manufacturing method thereof, and a display device. The display panel includes a display area and a peripheral area surrounding the display area. The display panel includes a substrate, a thin film transistor layer, a first planarization layer, a wiring layer, a second planarization layer, and an anode metal layer stacked in sequence; the wiring layer is located in the display area, the first planarization layer and the second planarization layer extend from the display area to the peripheral area, and the anode metal layer includes an anode layer located in the display area and an alignment mark located in the peripheral area. By setting two planarization layers in the display panel and making an alignment mark on the surface of the second planarization layer, the unevenness of the alignment mark caused by the damage to the surface of the first planarization layer when making the alignment mark on the first planarization layer is avoided, which not only ensures the flatness of the alignment mark, but also reduces the risk of the alignment mark becoming black and difficult to identify.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Optical functional films (such as OCA optical adhesives, polarizers, etc.) are one of the important components of display panels. The efficiency and accuracy of film pasting affect the performance of the display panel and the production cost.

[0003] During the manufacturing process of the display panel, when attaching the optical functional film to the display panel, it is necessary to align the alignment marks set on the display panel. However, the display panel in the related art is prone to the problem that the alignment marks are black and difficult to identify, resulting in inaccurate alignment when attaching the optical functional film, which affects the performance of the display panel. Summary of the invention

[0004] In view of the shortcomings of the existing methods, the present application proposes a display panel and a manufacturing method thereof, and a display device to solve the problem that the alignment mark of the display panel in the related art is black and difficult to be identified.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including:

[0006] substrate;

[0007] A thin film transistor layer, comprising a plurality of thin film transistors, is disposed on one side of the substrate;

[0008] A first planarization layer is disposed on a side of the thin film transistor layer away from the substrate and located in the display area and the peripheral area;

[0009] A second planarization layer is disposed on a side of the first planarization layer away from the substrate and at least located in the peripheral area;

[0010] An anode layer is arranged on a side of the second planarization layer away from the substrate, comprising an anode located in the display area and an alignment mark located in the peripheral area, wherein the anode is electrically connected to the thin film transistor, and the orthographic projection of the alignment mark on the substrate is within the orthographic projection of the second planarization layer on the substrate.

[0011] Optionally, the first planarization layer is provided with through holes, at least part of the through holes are located in the peripheral area, and when the through holes are located in the peripheral area, the orthographic projection of the through holes on the substrate overlaps with the orthographic projection of the alignment mark on the substrate;

[0012] A portion of the second planarization layer fills the through hole.

[0013] Optionally, the through hole extends from the peripheral area to the display area, the second planarization layer is located in the display area and the peripheral area, and a portion of the second planarization layer fills the through hole.

[0014] Optionally, a protective layer is further included, wherein the protective layer is located between the first planarization layer and the thin film transistor layer, and the through hole penetrates the first planarization layer and exposes the protective layer.

[0015] Optionally, the through holes are arranged around the display area.

[0016] Optionally, it also includes a wiring layer, a light-emitting layer and a cathode layer;

[0017] The wiring layer is at least partially located in the display area, and part of the wiring layer is located on a side of the first planarization layer away from the substrate;

[0018] The light-emitting layer is located on a side of the anode layer away from the substrate, and the light-emitting layer is located in the display area;

[0019] The cathode layer is located at a side of the light emitting layer away from the substrate.

[0020] In a second aspect, an embodiment of the present application provides a display device, including the display panel in the embodiment of the present application.

[0021] In a third aspect, an embodiment of the present application provides a method for manufacturing a display panel, comprising:

[0022] Providing a substrate, the substrate comprising a display area and a peripheral area surrounding the display area;

[0023] forming a thin film transistor layer on one side of the substrate;

[0024] A first planarization layer is formed on a side of the thin film transistor layer away from the substrate, wherein the first planarization layer is located in the display area and the peripheral area;

[0025] Forming a second planarization layer on a side of the first planarization layer away from the substrate, wherein the second planarization layer is at least located in the peripheral area;

[0026] An anode and an alignment mark are made on a side of the second planarization layer away from the substrate through a composition process, the anode is located in the display area, the alignment mark is located in the peripheral area, and the orthographic projection of the alignment mark on the substrate is located within the orthographic projection of the second planarization layer on the substrate.

[0027] Optionally, after forming a first planarization layer on a side of the thin film transistor layer away from the substrate, the method further includes:

[0028] A through hole is opened on a side of the first planarization layer away from the substrate, and at least part of the through hole is located in the peripheral area. When the through hole is located in the peripheral area, the orthographic projection of the through hole on the substrate overlaps with the orthographic projection of the alignment mark on the substrate.

[0029] Optionally, after the through hole is opened on the side of the first planarization layer away from the substrate, the method further comprises:

[0030] Depositing a conductive layer on a side of the first planarization layer away from the substrate, wherein the conductive layer fills the through hole;

[0031] A portion of the conductive layer is removed by a patterning process to form a wiring layer at least partially located in the display area.

[0032] Optionally, before forming the first planarization layer on the side of the thin film transistor layer away from the substrate, the method further includes:

[0033] A protection layer is formed on a side of the thin film transistor layer away from the substrate, and the through hole penetrates through the first planarization layer and exposes the protection layer.

[0034] Optionally, after forming an anode and an alignment mark on a side of the second planarization layer away from the substrate by a patterning process, the method further includes:

[0035] Making a light-emitting layer on a side of the anode and the alignment mark away from the substrate;

[0036] A cathode layer is formed on a side of the light emitting layer away from the substrate.

[0037] The beneficial technical effects brought about by the technical solution provided by the embodiment of the present application include:

[0038] The display panel in the embodiment of the present application includes a display area and a peripheral area surrounding the display area, the display panel includes a substrate, a thin film transistor layer arranged on one side of the substrate, a first planarization layer arranged on a side of the thin film transistor layer away from the substrate, a second planarization layer arranged on a side of the first planarization layer away from the substrate, and an anode layer arranged on a side of the second planarization layer away from the substrate; the first planarization layer is located in the display area and the peripheral area, the second planarization layer is at least located in the peripheral area, and the anode layer includes an anode located in the display area and an alignment mark located in the peripheral area. By arranging two planarization layers in the display panel, since the alignment mark is located on the side of the second planarization layer away from the substrate, and the orthographic projection of the alignment mark on the substrate is located within the orthographic projection of the second planarization layer on the substrate, the alignment mark can be made on the surface of the second planarization layer, avoiding the unevenness of the alignment mark caused by the damage to the surface of the first planarization layer when making the alignment mark on the first planarization layer, ensuring the flatness of the alignment mark, and reducing the risk of the alignment mark becoming black and difficult to be identified.

[0039] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0041] Figure 1 It is a schematic diagram of a top view structure of a display panel in the related art;

[0042] Figure 2 A schematic diagram of the structure of different processes for making alignment marks in the peripheral area of ​​a display panel in the related art;

[0043] Figure 3 A schematic diagram of a top view of a display panel provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of the cross-sectional structure of a first display panel provided in an embodiment of the present application;

[0045] Figure 5 A schematic diagram of the cross-sectional structure of a second display panel provided in an embodiment of the present application;

[0046] Figure 6 A schematic cross-sectional structure diagram of a third display panel provided in an embodiment of the present application;

[0047] Figure 7 A schematic diagram of a cross-sectional structure of a fourth display panel provided in an embodiment of the present application;

[0048] Figure 8A schematic diagram of the manufacturing process of the display panel provided in the embodiment of the present application;

[0049] Figure 9a to Figure 9p A schematic diagram of the structures of different processes for manufacturing a display panel provided in an embodiment of the present application.

[0050] In the figure:

[0051] 10-display panel; 101-display area; 102-peripheral area;

[0052] 11-substrate; 12-thin film transistor layer; 13-planarization layer; 14-wiring layer; 141-first wiring layer; 142-second wiring layer; 16-anode layer; 161-anode; 162-alignment mark;

[0053] 120a-first gate insulating layer; 120b-second gate insulating layer; 121a-first gate layer; 121b-second gate layer; 122-active layer; 123-source and drain layer; 124a-first dielectric layer; 124b-second dielectric layer; 125-protective layer; 126a-first planarization layer; 126b-second planarization layer; 127-pixel defining layer; 20-through hole; 21-metal material; 22-light-emitting layer; 24-cathode layer. DETAILED DESCRIPTION

[0054] The present application is described in detail below, and examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. In addition, if the detailed description of the known technology is unnecessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0055] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0056] In order to improve the display effect of the display panel, it is usually necessary to attach optical functional film layers such as OCA optical glue and polarizer to the display panel during the production process of the display panel. In order to improve the efficiency of automatic film attachment, such as Figure 1 As shown, an alignment mark 162 is provided in the peripheral area 102 around the display panel. The alignment mark 162 is formed by a patterning process. Specifically, during the manufacturing process of the display panel, a metal layer with a high reflectivity is first deposited on the planarization layer, and then the metal layer is patterned so that the portion of the metal layer located in the peripheral area 102 constitutes the alignment mark, and the portion of the metal layer located in the display area 101 constitutes other functional film layers.

[0057] The inventor of the present application considers that, in the related art, combined with Figure 1 and Figure 2 As shown, before making the alignment mark 162, it is necessary to first make the wiring layer 14 on the planarization layer 13 through a patterning process. In the specific manufacturing process, it is necessary to first deposit a layer of metal material on the planarization layer 13, and then pattern the metal material, retaining its portion located in the display area 101 (as a metal wiring such as a data line), and etching away its portion located in the peripheral area 102. Since the etching process control is relatively rough when etching in the peripheral area 102, after the metal material in the peripheral area 102 is etched away, it is easy to cause damage to the surface of the planarization layer 13, making the surface of the planarization layer 13 uneven. When the alignment mark 162 is subsequently produced through a patterning process, the anode layer 16 deposited on the surface of the planarization layer 13 will also become uneven, and the surface of the alignment mark 162 formed after the anode layer 16 is patterned will also be uneven, resulting in a decrease in the reflectivity of the alignment mark 162, which is manifested macroscopically as the alignment mark 162 becoming black. When the optical film layer is attached, the alignment mark 162 will be difficult to identify, resulting in inaccurate alignment, which affects the performance of the display panel.

[0058] The display panel and its manufacturing method, and the display device provided in the present application are intended to solve the above technical problems in the prior art.

[0059] The display panel 10 and its manufacturing method and the display device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0060] The present application embodiment provides a display panel 10, such as Figure 3 and Figure 4 As shown, including:

[0061] substrate 11;

[0062] The thin film transistor layer 12 includes a plurality of thin film transistors and is disposed on one side of the substrate 11;

[0063] The first planarization layer 126 a is disposed on a side of the thin film transistor layer 12 away from the substrate 11 , and is located in the display area 101 and the peripheral area 102 ;

[0064] The second planarization layer 126 b is disposed on a side of the first planarization layer 126 a away from the substrate 11 , and is at least located in the peripheral area 102 ;

[0065] The anode layer 16 is arranged on the side of the second planarization layer 126b away from the substrate 11, and includes an anode 161 located in the display area 101 and an alignment mark 162 located in the peripheral area 102. The anode 161 is electrically connected to the thin film transistor, and the orthographic projection of the alignment mark 162 on the substrate 11 is located within the orthographic projection of the second planarization layer 126b on the substrate 11.

[0066] Specifically, Figure 4 As shown, the material of the substrate 11 includes polyimide, and the thin film transistor layer 12 is arranged on one side of the substrate 11. The thin film transistor layer 12 includes an active layer 122, a first gate insulating layer 120a, a first gate layer 121a, a second gate insulating layer 120b, a second gate layer 121b, a first dielectric layer 124a, a second dielectric layer 124b and a source-drain electrode layer 123 in sequence. The first gate layer 121a, the second gate layer 121b, the active layer 122 and the source-drain electrode layer 123 constitute a thin film transistor, which is located in the display area 101 and arranged in an array. The thin film transistor layer 12 serves as a driving circuit layer of the display panel. The source-drain electrode layer 123 is electrically connected to the active layer 122, and the first gate layer 121a, the second gate layer 121b and the active layer 122 are insulated from each other. The materials of the first dielectric layer 124a and the second dielectric layer 124b include materials with good insulation properties such as silicon oxide or silicon nitride to provide electrical insulation between the conductor region and metals inside the thin film transistor device and isolation protection from the surrounding environment.

[0067] like Figure 4 As shown, the anode layer 16 is arranged on the side of the second planarization layer 126b away from the substrate 11, including an anode 161 and an alignment mark 162 arranged in the same layer. The material of the anode layer 16 can be a metal or metal oxide material with good conductivity and reflectivity. During the manufacturing process of the display panel 10, a layer of metal is deposited on the second planarization layer 126b, and then the deposited metal is patterned to form the anode 161 located in the display area 101 and the alignment mark 162 located in the peripheral area 102. The anode 161 is electrically connected to the source and drain layer 123, and a pixel defining layer 127, a light-emitting layer 22 and a cathode layer 24 are arranged on the anode 161. In the display area 101, the anode 161, the light-emitting layer 22 and the cathode layer 24 constitute a light-emitting device.

[0068] Specifically, Figure 4As shown, the display panel in the embodiment of the present application includes a wiring layer 14 located in the display area 101, and the wiring layer 14 includes a first wiring layer 141 and a second wiring layer 142 that are stacked and insulated. The first wiring layer 141 is arranged in the same layer as the source and drain electrode layer 123 and is electrically connected. The first wiring layer 141 and the source and drain electrode layer 123 are arranged in the same layer, which means that during the manufacturing process of the display panel 10, the first wiring layer 141 and the source and drain electrode layer 123 are manufactured and formed by the same patterning process. The second wiring layer 142 is electrically connected to the first wiring layer 141, and the first wiring layer 141 and the second wiring layer 142 realize the transmission of data signals. The first planarization layer 126a is located on a side of the first routing layer 141 away from the substrate 11, the second routing layer 142 is located on a side of the first planarization layer 126a away from the substrate 11, the second planarization layer 126b is located on a side of the first planarization layer 126a away from the substrate 11 and covers the second routing layer 142, and the materials of the first planarization layer 126a and the second planarization layer 126b include organic materials.

[0069] In a specific implementation, in the process of making the second wiring layer 142, it is necessary to deposit metal on the first planarization layer 126a, and then pattern the metal, etch away the metal in the peripheral area 102, and retain part of the metal in the display area 101 as the second wiring layer 142. Since the etching process control of the display area 101 and the peripheral area 102 is different (the control of the etching in the peripheral area 102 is not as fine as that in the display area 101, that is, the control of the etching in the peripheral area 102 is rough), it is easy to damage the surface of the first planarization layer 126a in the peripheral area 102 during the etching process, making the surface of the first planarization layer 126a uneven, such as Figure 4 shown.

[0070] like Figure 2 As shown, if the alignment mark 162 is directly made on the first planarization layer 126a, the alignment mark 162 will also be uneven, resulting in a decrease in the reflectivity of the alignment mark 162. From a macroscopic point of view, the alignment mark 162 is black and difficult to be identified. In the embodiment of the present application, a second planarization layer 126b is provided on the first planarization layer 126a, such as Figure 4 As shown, an anode layer 16 (including an anode layer 161 and an alignment mark 162) is manufactured on the second planarization layer 126b, so that the alignment mark 162 can be manufactured on the second planarization layer 126b, and the orthographic projection of the alignment mark 162 on the substrate 11 is located within the orthographic projection of the second planarization layer 126b on the substrate 11, thereby ensuring the flatness of the alignment mark 162 and reducing the risk of the alignment mark 162 turning black and being difficult to identify.

[0071] Optional, such as Figure 5As shown, a through hole 20 is opened on the first planarization layer 126a, and at least a portion of the through hole 20 is located in the peripheral area 102, and when the through hole 20 is located in the peripheral area 102, the orthographic projection of the through hole 20 on the substrate 11 overlaps with the orthographic projection of the alignment mark 162 on the substrate 11, and a portion of the second planarization layer 126b fills the through hole 20.

[0072] Specifically, Figure 5 As shown, after the first planarization layer 126a is manufactured, a through hole 20 is opened on the first planarization layer 126a, and the through hole 20 penetrates the first planarization layer 126a and exposes the inorganic material film layer under the first planarization layer 126a. When the second wiring layer 142 is manufactured by the patterning process, the metal material in the peripheral area 102 is deposited in the through hole 20. Therefore, when the metal material in the peripheral area 102 is etched, the first planarization layer 126a will not be damaged when the metal material at the bottom of the through hole 20 is etched, which reduces the damaged area of ​​the first planarization layer 126a, that is, reduces the area of ​​the uneven area on the first planarization layer 126a, and then when the second planarization layer 126b is manufactured on the first planarization layer 126a, the surface of the second planarization layer 126b can be made flatter. This is conducive to improving the flatness of the alignment mark 162 and further reducing the risk of the alignment mark 162 turning black.

[0073] It should be noted that the specific position of the through hole 20 can be adjusted according to actual conditions. Figure 6 As shown, the through hole 20 extends from the peripheral area 102 to the display area 101, the second planarization layer 126b is located in the display area 101 and the peripheral area 102, and part of the second planarization layer 126b fills the through hole 20. Since the through hole 20 extends from the peripheral area 102 to the display area 101, the range of the through hole 20 in the peripheral area 102 is increased, thereby reducing the portion of the first planarization layer 126a that is damaged by etching. When the second planarization layer 126b is subsequently manufactured, the surface of the second planarization layer 126b can be made smoother, which is beneficial to improving the flatness of the alignment mark 162.

[0074] Optional, such as Figure 6As shown, the display panel 10 also includes a protective layer 125, and the protective layer 125 is located between the first planarization layer 126a and the thin film transistor layer 12, and the through hole 20 penetrates the first planarization layer 126a and exposes the protective layer 125. The material of the protective layer 125 includes an inorganic material, which is more resistant to etching than the first planarization layer 126a using an organic material. Therefore, when making the second wiring layer 142, etching the metal in the peripheral area 102 (deposited in the through hole 20) will not damage the surface of the protective layer 125, that is, the surface of the protective layer 125 is flat, so that the second planarization layer 126b made subsequently can also be flat. It should be noted that the depth of the through hole 20 can be determined according to actual conditions, combined with Figure 5 and Figure 6 As shown, the through hole 20 penetrates to the surface of the protective layer 125, that is, the surface of the protective layer 125 is not etched when the through hole is formed. By making the through hole 20 penetrate to the surface of the protective layer 125, it is possible to avoid the complexity of the process caused by the through hole 20 being formed too deep, which is conducive to reducing the manufacturing cost of the display panel 10. Figure 7 As shown, the through hole 20 continues to extend downward on the surface of the protection layer 125 , that is, the protection layer 125 is also etched when the through hole 20 is formed.

[0075] In the embodiments of the present application, Figure 3 and Figure 6 As shown, the through holes 20 are arranged around the display area 101, that is, the through holes 20 are arranged around the display area 101. As a result, the second planarization layer 126b can be relatively flat around the display area 101, and the flatness of the alignment mark 162 in the peripheral area 102 is improved to the greatest extent (the alignment mark 162 can be set at any position around the display area 101, so the alignment mark 162 set at any position can be flat), and the risk of the alignment mark 162 becoming black is reduced.

[0076] Optional, such as Figure 6As shown, in an embodiment of the present application, the display panel 10 also includes a wiring layer 14, a light-emitting layer 22 and a cathode layer 24. Part of the wiring layer 14 is located in the display area 101, and part of it is located in the peripheral area 102 (it should be noted that FIG. 9 only shows the wiring layer 14 located in the display area 101, and the actual wiring layer 14 extends from the peripheral area 102 to the display area 101). The wiring layer 14 includes a first wiring layer 141 and a second wiring layer 142 that are stacked and insulated. The first wiring layer 141 is arranged in the same layer as the source and drain layer 123 and is electrically connected. The first wiring layer 141 and the source and drain layer 123 are arranged in the same layer, which means that during the manufacturing process of the display panel 10, the first wiring layer 141 and the source and drain layer 123 are manufactured and formed by the same patterning process. The second wiring layer 142 is electrically connected to the first wiring layer 141, and the first wiring layer 141 and the second wiring layer 142 realize the transmission of data signals. The light-emitting layer 22 is located on the side of the anode 161 away from the substrate 11, and the light-emitting layer 22 is located in the display area 101. The cathode layer 24 is located on the side of the light-emitting layer 22 away from the substrate 11. The specific arrangement of the light-emitting layer 22 and the cathode layer 24 is similar to the prior art and will not be repeated here. In the display area 101, the light-emitting layer 22, the anode 161 and the cathode layer 24 constitute the light-emitting device of the display panel 10. It should be noted that the display surface in the embodiment of the present application can be a vehicle-mounted OLED display panel, etc., which can be determined according to actual conditions.

[0077] Based on the same inventive concept, the embodiment of the present application also provides a display device, which includes the display panel 10 provided in the embodiment of the present application. Since the display device includes the display panel 10 provided in the embodiment of the present application, the display device has the same beneficial effects as the display panel 10, which will not be described in detail here. The display device can be a tablet, a mobile phone, a television, etc., which can be determined according to actual conditions.

[0078] Based on the same inventive concept, the embodiment of the present application also provides a method for manufacturing a display panel 10, such as Figure 8 As shown, including:

[0079] S101, providing a substrate, the substrate comprising a display area and a peripheral area surrounding the display area;

[0080] S102, manufacturing a thin film transistor layer on one side of the substrate;

[0081] S103, forming a first planarization layer on a side of the thin film transistor layer away from the substrate, wherein the first planarization layer is located in the display area and the peripheral area;

[0082] S104, forming a second planarization layer on a side of the first planarization layer away from the substrate, wherein the second planarization layer is at least located in the peripheral area;

[0083] S105. Making an anode and an alignment mark on a side of the second planarization layer away from the substrate through a patterning process, wherein the anode is located in the display area, the alignment mark is located in the peripheral area, and the orthographic projection of the alignment mark on the substrate is located within the orthographic projection of the second planarization layer on the substrate.

[0084] In the manufacturing method provided in the embodiment of the present application, the display panel 10 includes a thin film transistor layer 12, a first planarization layer 126a, a second planarization layer 126b and an anode layer 16 which are sequentially stacked on a substrate 11; the anode layer 16 includes an anode 161 located in a display area 101 and an alignment mark 162 located in a peripheral area 102. By manufacturing two planarization layers in the display panel 10 and manufacturing the alignment mark 162 on the surface of the second planarization layer 126b, the unevenness of the alignment mark 162 caused by the damage to the surface of the first planarization layer 126a when manufacturing the alignment mark 162 on the first planarization layer 126a is avoided, that is, the flatness of the alignment mark 162 is guaranteed, and the risk of the alignment mark 162 becoming black and difficult to identify is reduced.

[0085] Optionally, in an embodiment of the present application, after the first planarization layer 126a is formed on a side of the thin film transistor layer 12 away from the substrate 11, the method further includes:

[0086] A through hole is opened on a side of the first planarization layer away from the substrate, and at least part of the through hole is located in the peripheral area. When the through hole is located in the peripheral area, the orthographic projection of the through hole on the substrate overlaps with the orthographic projection of the alignment mark on the substrate.

[0087] In an optional embodiment, after a through hole is opened on a side of the first planarization layer 126a away from the substrate 11, the method further includes:

[0088] Depositing a conductive layer on a side of the first planarization layer away from the substrate, wherein the conductive layer fills the through hole;

[0089] A portion of the conductive layer is removed through a patterning process to form a wiring layer at least partially located in the display area.

[0090] Specifically, Figure 5 and Figure 6As shown, after the first planarization layer 126a is manufactured, a through hole 20 is opened on the first planarization layer 126a, and the through hole 20 penetrates the first planarization layer 126a and extends to the inorganic material film layer under the first planarization layer 126a. When the second wiring layer 142 is manufactured by the patterning process, the metal material in the peripheral area 102 is deposited in the through hole 20. Therefore, when the metal material in the peripheral area 102 is etched, the first planarization layer 126a will not be damaged when the metal material at the bottom of the through hole 20 is etched, that is, the damaged area of ​​the first planarization layer 126a can be reduced, that is, the area of ​​the uneven area on the first planarization layer 126a is reduced, and then when the second planarization layer 126b is manufactured on the first planarization layer 126a, the surface of the second planarization layer 126b can be made flatter. This is conducive to improving the flatness of the alignment mark 162 and further reducing the risk of the alignment mark 162 turning black.

[0091] In an optional embodiment, before forming the first planarization layer on the side of the thin film transistor layer away from the substrate, the method further includes:

[0092] A protection layer is formed on a side of the thin film transistor layer away from the substrate, and a through hole penetrates through the first planarization layer to expose the protection layer.

[0093] Optionally, after forming an anode and an alignment mark on a side of the second planarization layer away from the substrate by a patterning process, the method further includes:

[0094] A light emitting layer is formed on the side of the anode and the alignment mark away from the substrate;

[0095] A cathode layer is formed on the side of the light emitting layer away from the substrate.

[0096] The following describes in detail a method for manufacturing the display panel 10 in an embodiment of the present application in conjunction with the accompanying drawings.

[0097] Specifically, the patterning process in the embodiments of the present application includes the coating, exposure, development, etching of photoresist and partial or all processes of removing the photoresist.

[0098] like Figure 9a As shown, first, a substrate 11 is provided. The material of the substrate 11 includes polyimide, which can be determined according to actual conditions.

[0099] like Figure 9b As shown, then, an active layer 122 is formed on one side of the substrate 11 through a patterning process.

[0100] like Fig.9c As shown, next, a first gate insulating layer 120 a is formed on a side of the active layer 122 away from the substrate 11 , and the first gate insulating layer 120 a covers the active layer 122 .

[0101] like Figure 9d As shown, next, a first gate layer 121 a is formed on a side of the first gate insulating layer 120 a away from the substrate 11 through a patterning process.

[0102] like Fig.9e As shown, next, a second gate insulating layer 120b is formed on a side of the first gate insulating layer 120a away from the substrate 11, and the second gate insulating layer 120b covers the first gate layer 121a.

[0103] like Figure 9f As shown, next, a second gate layer 121 b is formed on a side of the second gate insulating layer 120 b away from the substrate 11 through a patterning process, and the position of the second gate layer 121 b corresponds to the position of the first gate layer 121 a.

[0104] like Figure 9g As shown, next, a first dielectric layer 124a is formed on a side of the second gate insulating layer 120b away from the substrate 11, and the first dielectric layer 124a covers the second gate layer 121b.

[0105] like Figure 9h As shown, next, a second dielectric layer 124 b is formed on a side of the first dielectric layer 124 a away from the substrate 11 .

[0106] like Figure 9i As shown, next, a source-drain electrode layer 123 and a first wiring layer 141 are formed on a side of the second dielectric layer 124 b away from the substrate 11 through a patterning process, and the source-drain electrode layer 123 is electrically connected to the active layer 122 .

[0107] like Figure 9j As shown, next, a protection layer 125 is formed on a side of the second dielectric layer 124 b away from the substrate 11 .

[0108] like Figure 9k As shown, next, a first planarization layer 126 a is formed on a side of the protection layer 125 away from the substrate 11 .

[0109] like Figure 9l As shown, a through hole 20 is then opened on the first planarization layer 126a, and the through hole 20 penetrates the protective layer 125. The through hole 20 can be located in the peripheral area 102, or can extend from the peripheral area 102 to the display area 101, which can be adjusted according to actual conditions.

[0110] like Figure 9m As shown, next, a metal material 21 is deposited on a side of the first planarization layer 126 a away from the substrate 11 .

[0111] like Figure 9nAs shown, the metal layer is then patterned, and the portion of the metal layer located in the peripheral area 102 is etched, leaving the portion of the metal layer located in the display area 101 as the second wiring layer 142 .

[0112] like Figure 9o As shown, next, a second planarization layer 126 b is formed on the side of the first planarization layer 126 a away from the substrate 11 . After the second planarization layer 126 b fills the through hole 20 , a flat surface is formed on the side away from the substrate 11 .

[0113] like Figure 9p As shown, then, an anode 161 and an alignment mark 162 are formed on the side of the second planarization layer 126b away from the substrate 11 through a patterning process, and the anode 161 is electrically connected to the source-drain electrode layer 123. The anode 161 and the alignment mark 162 are arranged on the same layer, the anode 161 is located in the display area 101, and the alignment mark 162 is located in the peripheral area 102. It should be noted that, later, a pixel defining layer, a light emitting layer and a cathode layer ( Figure 9p ), etc., to complete the production of the display panel 10.

[0114] By applying the embodiments of the present application, at least the following beneficial effects can be achieved:

[0115] 1. The display panel 10 in the embodiment of the present application includes a display area 101 and a peripheral area 102 surrounding the display area 101. The display panel 10 includes a substrate 11, a thin film transistor layer 12, a first planarization layer 126a, a wiring layer 14, a second planarization layer 126b, and an anode metal layer 16 which are stacked in sequence; the wiring layer 14 is located in the display area 101, the first planarization layer 126a and the second planarization layer 126b extend from the display area 101 to the peripheral area 102, and the anode metal layer 16 includes an anode layer 161 located in the display area 101 and an alignment mark 162 located in the peripheral area 102. By providing two planarization layers in the display panel 10 and making the alignment mark 162 on the surface of the second planarization layer 126b, the unevenness of the alignment mark 162 caused by surface damage of the first planarization layer 126a when making the alignment mark 162 on the first planarization layer 126a is avoided, that is, the flatness of the alignment mark 162 is guaranteed, and the risk of the alignment mark 162 becoming black and difficult to identify is reduced.

[0116] 2. In the embodiment of the present application, by opening the through hole 20 on the first planarization layer 126a, when the second wiring layer 142 is manufactured by the patterning process, the metal material in the peripheral area 102 is deposited in the through hole 20, so when the metal material in the peripheral area 102 is etched, the damaged area of ​​the first planarization layer 126a is reduced, that is, the area of ​​the uneven area on the first planarization layer 126a is reduced, and then when the second planarization layer 126b is manufactured on the first planarization layer 126a, the surface of the second planarization layer 126b can be made flatter. This is conducive to improving the flatness of the alignment mark 162 and further reducing the risk of the alignment mark 162 turning black.

[0117] 3. In the embodiment of the present application, by making the through hole 20 penetrate the protective layer 125 located between the first planar layer and the thin film transistor layer 12, it is possible to avoid the process complexity caused by opening the through hole 20 too deep, which is beneficial to reducing the production cost of the display panel 10.

[0118] 4. In the embodiment of the present application, the through holes 20 are arranged around the display area 101, that is, the through holes 20 are arranged around the display area 101. In this way, the second planarization layer 126b can be relatively flat around the display area 101, and the flatness of the alignment mark 162 in the peripheral area 102 is improved to the greatest extent (the alignment mark 162 can be set at any position around the display area 101, so the alignment mark 162 set at any position can be flat), and the risk of the alignment mark 162 becoming black is reduced.

[0119] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0120] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0121] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0122] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A display panel, comprising a display area and a peripheral area surrounding the display area, characterized in that: include: substrate; A thin film transistor layer, comprising a plurality of thin film transistors, is disposed on one side of the substrate; A first planarization layer is disposed on a side of the thin film transistor layer away from the substrate and located in the display area and the peripheral area; A second planarization layer is disposed on a side of the first planarization layer away from the substrate and at least located in the peripheral area; an anode layer, arranged on a side of the second planarization layer away from the substrate, comprising an anode located in the display area and an alignment mark located in the peripheral area, the anode being electrically connected to the thin film transistor, and an orthographic projection of the alignment mark on the substrate being within an orthographic projection of the second planarization layer on the substrate; The first planarization layer is provided with through holes, at least part of which is located in the peripheral area, and when the through holes are located in the peripheral area, the orthographic projection of the through holes on the substrate overlaps with the orthographic projection of the alignment mark on the substrate; A portion of the second planarization layer fills the through hole.

2. The display panel according to claim 1, characterized in that: The through hole extends from the peripheral area to the display area, the second planarization layer is located in the display area and the peripheral area, and a portion of the second planarization layer fills the through hole.

3. The display panel according to claim 1, characterized in that: A protection layer is also included, wherein the protection layer is located between the first planarization layer and the thin film transistor layer, and the through hole penetrates the first planarization layer and exposes the protection layer.

4. The display panel according to claim 1 or 3, characterized in that: The through holes are arranged around the display area.

5. The display panel according to claim 1, characterized in that: It also includes a wiring layer, a light-emitting layer, and a cathode layer; The wiring layer is at least partially located in the display area, and part of the wiring layer is located on a side of the first planarization layer away from the substrate; The light-emitting layer is located on a side of the anode layer away from the substrate, and the light-emitting layer is located in the display area; The cathode layer is located at a side of the light emitting layer away from the substrate.

6. A display device, characterized in that: A display panel comprising any one of claims 1 to 5.

7. A method for manufacturing a display panel, characterized in that: include: Providing a substrate, the substrate comprising a display area and a peripheral area surrounding the display area; forming a thin film transistor layer on one side of the substrate; A first planarization layer is formed on a side of the thin film transistor layer away from the substrate, wherein the first planarization layer is located in the display area and the peripheral area; Forming a second planarization layer on a side of the first planarization layer away from the substrate, wherein the second planarization layer is at least located in the peripheral area; Making an anode and an alignment mark on a side of the second planarization layer away from the substrate by a patterning process, wherein the anode is located in the display area, the alignment mark is located in the peripheral area, and the orthographic projection of the alignment mark on the substrate is located within the orthographic projection of the second planarization layer on the substrate; After forming a first planarization layer on a side of the thin film transistor layer away from the substrate, the method further includes: A through hole is opened on a side of the first planarization layer away from the substrate, and at least part of the through hole is located in the peripheral area. When the through hole is located in the peripheral area, the orthographic projection of the through hole on the substrate overlaps with the orthographic projection of the alignment mark on the substrate.

8. The method according to claim 7, characterized in that: After the through hole is opened on the side of the first planarization layer away from the substrate, the method comprises: Depositing a conductive layer on a side of the first planarization layer away from the substrate, wherein the conductive layer fills the through hole; A portion of the conductive layer is removed by a patterning process to form a wiring layer at least partially located in the display area.

9. The manufacturing method according to claim 7, characterized in that: Before forming the first planarization layer on the side of the thin film transistor layer away from the substrate, the method further includes: A protection layer is formed on a side of the thin film transistor layer away from the substrate, and the through hole penetrates through the first planarization layer and exposes the protection layer.

10. The manufacturing method according to claim 7, characterized in that: After the anode and the alignment mark are formed on the side of the second planarization layer away from the substrate by the patterning process, the method further includes: Making a light-emitting layer on a side of the anode and the alignment mark away from the substrate; A cathode layer is formed on a side of the light emitting layer away from the substrate.

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