Memory element and method of manufacturing the same

Abstract

A memory element and a manufacturing method thereof, wherein the memory element comprises: a substrate, comprising a plurality of blocks, each block comprising a step region, a storage array region and a word line cutting region; a stacked structure located on the substrate in the storage array region, wherein the stacked structure comprises a plurality of first insulating layers and a plurality of conductor layers stacked alternately with each other; a first step structure located on the substrate in the step region, wherein the first step structure comprises a plurality of first insulating layers and a plurality of conductor layers stacked alternately with each other; and a first part of a second step structure located on the substrate in the word line cutting region, wherein the first part of the second step structure comprises a plurality of first insulating layers and a plurality of conductor layers stacked alternately with each other, and the two first parts of the two second step structures of two adjacent blocks are separated from each other.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit and storage technology, and relates to a memory element and a manufacturing method thereof. Background Art

[0002] Non-volatile memory elements (eg, flash memory) have become a type of memory element widely used in personal computers and other electronic devices because they have the advantage that stored data will not disappear even after power is turned off.

[0003] The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each storage unit in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory. Summary of the invention

[0004] The invention provides a memory element which can separate a plurality of word lines of two adjacent blocks from each other.

[0005] In one embodiment of the present invention, a memory element comprises: a substrate comprising a plurality of blocks, each block comprising a step region, a storage array region and a word line cutting region, wherein the storage array region is located between the step region and the word line cutting region; a stacked structure located on the substrate in the storage array region, wherein the stacked structure comprises a plurality of first insulating layers and a plurality of conductor layers stacked alternately with each other; a first step structure located on the substrate in the step region, wherein the first step structure comprises a plurality of first insulating layers and a plurality of conductor layers stacked alternately with each other; and a first portion of a second step structure located on the substrate in the word line cutting region, wherein the first portion of the second step structure comprises a plurality of first insulating layers and a plurality of conductor layers stacked alternately with each other, and two second step structures of two adjacent blocks are separated from each other.

[0006] In one embodiment of the present invention, a method for manufacturing a memory element includes: providing a substrate including a plurality of blocks, each block including a step region, a storage array region and a word line cutting region, wherein the storage array region is located between the step region and the word line cutting region; forming a stacked structure on the substrate in the step region, the storage array region and the word line cutting region, wherein the stacked structure includes a plurality of first insulating layers and a plurality of second insulating layers stacked alternately with each other; patterning the stacked structure in the step region to form a first step structure; patterning the stacked structure in the word line cutting region to form a first part of a second step structure so that two second step structures of two adjacent blocks are separated from each other; and performing a replacement process to replace the stacked structure in the storage array region, the first step structure in the step region and the first part of the second step structure in the word line cutting region with a plurality of conductor layers.

[0007] Based on the above, the embodiment of the present invention patterns the stacked structure between two adjacent blocks into a staircase structure and arranges a dielectric layer with an anti-staircase structure, so that a plurality of word lines in different blocks can be separated from each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 1 is a top view of a three-dimensional memory device according to an embodiment of the present invention.

[0009] Figures 2A to 2P It is a cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention.

[0010] Figure 3 It is shown Figure 1 Schematic diagram of the cross section along the tangent lines AA, BB, and CC.

[0011] Figure 4A , 5A , 6A, and 7A are top views of a three-dimensional memory device according to an embodiment of the present invention.

[0012] Figure 4B , 5B , 6B, 7B are Figure 4A , 5A , 6A, and 7A along the tangent line II.

[0013]

Explanation of symbols

[0014] 10: Base

[0015] 20: Component layer

[0016] 30, 40: Metal interconnect structure

[0017] 32, 42: Dielectric layer

[0018] 34, 44: Plug

[0019] 33: Metal interconnects

[0020] 36, 46: Wire

[0021] 90, 101: Laminated structure

[0022] 92, 102, 102 14 , 102 13 , 102 12 , 102 11 , 102 10 , 1029, 1028, 1027, 1026, 1025, 1024, 1023, 1022, 1021: insulation layer

[0023] 94: Conductor layer

[0024] 106, OP1, OP2, OP3, OP4, OP11, OP12, OP13, OP14, OP21, OP22, OP23, OP24, OP31, OP32, OP33, OP34, OP41, OP42, OP43, OP44: Open

[0025] 102T: Top insulation layer

[0026] 103: Dielectric layer

[0027] 1031, 1032, 1033: Island dielectric layer

[0028] 104, 104 14 , 104 13 , 104 12 , 104 11 , 104 10 , 1049, 1048, 1047, 1046, 1045, 1044, 1043, 1042, 1041: Sacrificial layer

[0029] 105: Stop layer

[0030] 107: Select source line to cut wall

[0031] 108: Charge storage structure

[0032] 110: Channel layer

[0033] 111: Groove

[0034] 112: Insulation column

[0035] 113: Insulated Wall

[0036] 114: Conductor plug

[0037] 115: Insulation top cover

[0038] 116, 119: Channel

[0039] 117: Gap wall

[0040] 118, 1181, 1182, 1183: Source line conductor wall

[0041] 121: Horizontal opening

[0042] 120: Source line

[0043] 122: Barrier layer

[0044] 124: Metal layer

[0045] 126: Gate layer

[0046] A1: Area 1

[0047] A2: Second Area

[0048] A3: The third area

[0049] A4: District 4

[0050] B, B1, B2, B3, B4: Block

[0051] C1, C2, C3, C5: Contact window

[0052] CP: Vertical Channel Column

[0053] D1, D2: Direction

[0054] PL1, PL2, PL3, PL4: Support structure

[0055] R1, R5: surrounding areas

[0056] R2: Step Area

[0057] R3: Storage array area

[0058] R4: word line cutting area

[0059] PR1, PR1', PR2, PR2': mask layer

[0060] SC1, SC2, SC3, SC4: Ladder structure

[0061] SC4a, SC4b, SC4c, SC4d, SC4e, SC4f: Sub-step structure

[0062] SC41, SC42, SC43: Guided ladder structure

[0063] T1: Phase 1

[0064] T2: Phase 2

[0065] T3: Stage 3

[0066] T4: Stage 4

[0067] TSC1, TSC2, TSC4, TSC1', TSC4': transitional ladder structure

[0068] W1, W2, W3, W4, W5: Width

[0069] II, II-II, AA, BB, CC: Tangent DETAILED DESCRIPTION

[0070] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0071] Figure 1 FIG. 1 is a top view of a three-dimensional memory device according to an embodiment of the present invention. Figures 2A to 2P It is a cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. Figures 2A to 2P It is along Figure 1 Schematic diagram of the cross section along tangent line II. Figure 1 Only some of the components are shown.

[0072] Please refer to Figure 1 and Figure 2A , a three-dimensional memory device 100 is formed on a substrate 10. Along a direction D2, the substrate 10 is divided into a plurality of blocks B arranged along the direction D2, such as blocks B1, B2, B3 and B4. Along the direction D1, each block B includes a peripheral region R1, a step region R2, a memory array region R3, a word line cutting region R4 and a peripheral region R5. Along the direction D2, each block B includes a first region A1, a second region A2, a third region A3 and a fourth region A4.

[0073] The three-dimensional memory device 100 includes a plurality of source line conductor walls 118 and a selective source line cut slit 107 extending along a direction D1. Some of the source line conductor walls 118 extend from the step region R2 to the word line cut region R4 between the fourth region A4 and the first region A1 of two adjacent blocks B. Other source line conductor walls 118 extend from the memory array region R3 to the word line cut region R4 between the second region A2 and the third region A3 of each block B. The selective source line cut slit 107 is located between the first region A1 and the second region A2 and between the third region A3 and the second region A4 of each block B.

[0074] In the embodiment of the present disclosure, the word line cutting region R4 and the peripheral region R5 of the three-dimensional memory device 100 have a step structure SC4. The step structure SC4 includes a portion P3 and a portion P3. The portion P3 and the portion P3 are respectively located in the word line cutting region R4 and the peripheral region R5, and are separated from each other by a dielectric layer 103. In this way, a plurality of word lines between two adjacent blocks B can be separated from each other.

[0075] The three-dimensional memory device 100 may refer to Figures 2A to 2P The present invention is formed by a manufacturing method, but the present invention is not limited to this.

[0076] Please refer to Figure 2A , a device layer 20 and a metal interconnect structure 30 are sequentially formed on a substrate 10. The substrate 10 may be a semiconductor substrate, such as a silicon substrate. The device layer 20 may include active devices or passive devices. Active devices are, for example, transistors, diodes, etc. Passive devices are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor device (CMOS).

[0077] The metal interconnect structure 30 may include a multi-layer dielectric layer 32 and a metal interconnect 33 formed in the multi-layer dielectric layer 32. The metal interconnect 33 includes a plurality of plugs 34 and a plurality of wires 36. The dielectric layer 32 separates adjacent wires 36. The wires 36 may be connected to each other through the plugs 34, and the wires 36 may be connected to the device layer 20 through the plugs 34.

[0078] Please refer to Figure 2A , a stacked structure 90 is formed on the metal interconnect structure 30. The stacked structure 90 includes a plurality of insulating layers 92 and a plurality of conductive layers 94 that are alternately stacked. In one embodiment, the insulating layer 92 is made of silicon oxide, and the conductive layer 94 is made of doped polysilicon.

[0079] Please refer to Figure 1 and Figure 2A The stacked structure 90 is patterned to form a groove 111, and a dielectric layer 95 (such as silicon oxide) is filled in the groove 111. A stacked structure 101 is formed on the stacked structure 90. The stacked structure 101 includes a plurality of insulating layers 102 and a plurality of sacrificial layers 104 stacked alternately. The insulating layer 102 includes a top insulating layer 102T, a top insulating layer 102T, and a bottom insulating layer 102T. 14 , 102 13 , 102 12 , 102 11 , 102 10 , 1029, 1028, 1027, 1026, 1025, 1024, 1023, 1022, 1021. The sacrificial layer 104 includes 104 14 , 104 13 , 104 12 , 104 11 , 104 10 , 1049, 1048, 1047, 1046, 1045, 1044, 1043, 1042, 1041. The insulating layer 102 and the sacrificial layer 104 may be referred to as the first insulating layer 102 and the second insulating layer 104, respectively. In one embodiment, the material of the insulating layer 102 includes silicon oxide, and the material of the sacrificial layer 104 includes silicon nitride. Afterwards, a stop layer 105 is formed on the stacked structure 101. The material of the stop layer 105 is different from that of the insulating layer 102 and the sacrificial layer 104, such as polysilicon. In one embodiment, the stacked structure 101 and the stop layer 105 are located on the peripheral region R1, the step region R2, the memory array region R3, the word line cutting region R4, and the peripheral region R5 of each block B.

[0080] Please refer to Figures 2B to 2K , the sacrificial layer 104 and the insulating layer 102 of the stacked structure 101 in the peripheral region R1, the step region R2, the word line cutting region R4 and the peripheral region R5 are patterned to form step structures SC1, SC2, SC3 and SC4, respectively. Figures 2B to 2K In some embodiments, the stair structures SC1, SC2, SC3 and SC4 are formed through a four-stage patterning process, but the present invention is not limited thereto. Figures 2B to 2D The patterning process of the first stage T1 is described. Figures 2E to 2I The patterning process of the second stage T2 is described. Figure 2J The patterning process of the third stage T3 is described. Figure 2K The patterning process in the fourth stage T4 is described.

[0081] Please refer to Figure 2B, the stop layer 105 is patterned to form openings OP1, OP2, OP3 and OP4. The opening OP1 exposes the top insulating layer 102T of the stacked structure 101 in the peripheral region R1 and the step region R2, the opening OP2 exposes the top insulating layer 102T of the stacked structure 101 in the step region R2, the opening OP3 exposes the top insulating layer 102T of the stacked structure 101 in the step region R2, and the opening OP4 exposes the top insulating layer 102T of the stacked structure 101 in the word line cutting region R4 and the peripheral region R5.

[0082] Please refer to Figure 2B , a patterning process of the first stage T1 is performed. A mask layer PR1 is formed on the stop layer 105 and the top insulating layer 102T. The mask layer PR1 is, for example, a patterned photoresist layer. The mask layer PR1 has openings OP11, OP12, OP13, and OP14, which are smaller than the openings OP1, OP2, OP3, and OP4, respectively. Next, an etching process is performed using the mask layer PR1 as a mask to pattern the stacked structure 101, thereby transferring the patterns of the openings OP11, OP12, OP13, and OP14 to the top insulating layer 102T and the sacrificial layer 104. 14 .

[0083] Please refer to Figure 2C The mask layer PR1 is trimmed to form a mask layer PR1'. The mask layer PR1' has openings OP21, OP22, OP23 and OP24, which are respectively larger than the openings OP11, OP12, OP13, OP14, and smaller than the openings OP1, OP2, OP3, OP4, respectively, exposing the top insulating layer 102T and the top insulating layer 102 14 The top surface of the top insulating layer 102T and the sacrificial layer 104 14 side wall.

[0084] Please refer to Figure 2D , with the mask layer PR1′ and the top insulating layer 102T having the openings OP11, OP12, OP13, OP14 and the sacrificial layer 104 14 The stacked structure 101 is patterned by using a mask to perform an etching process, so as to transfer the patterns of the openings OP21, OP22, OP23 and OP24 to the top insulating layer 102T and the sacrificial layer 104. 14 and transferring the pattern of the openings OP11, OP12, OP13, and OP14 to the insulating layer 102 14 and the sacrificial layer 104 13 .

[0085] Please refer to Figure 2E, remove the mask layer PR1', and then perform the patterning process of the second stage T2. A mask layer PR2 is formed on the stop layer 105 and the stacked structure 101. The mask layer PR2 is, for example, a patterned photoresist layer. The mask layer PR2 has openings OP31, OP32, OP33, and OP34. The openings OP31, OP32, and OP33 are smaller than the openings OP11, OP12, and OP13, respectively, and the size of the opening OP34 is equal to the opening OP14 and is aligned with the opening OP14.

[0086] Please refer to Figure 2F , using the mask layer PR2 as a mask, an etching process is performed to pattern the stacked structure 101, thereby transferring the patterns of the openings OP31, OP32, OP33 and OP34 to the insulating layer 102 13 and the sacrificial layer 104 12 .

[0087] Please refer to Figure 2G , the mask layer PR2 is trimmed to form a mask layer PR2'. The mask layer PR2' has openings OP41, OP42 and OP43, which are respectively larger than the openings OP31, OP32 and OP33, and respectively smaller than the openings OP11, OP12 and OP13. The opening OP41 is larger than the openings OP14 and OP34, and is equal to the opening OP24. The openings OP41, OP42 and OP43 expose the insulating layer 102. 13 , 102 12 The top surface and the insulating layer 102 13 With the sacrificial layer 104 12 The opening OP44 exposes the insulating layer 102 14 , 102 12 The top surface of the top insulating layer 102T and the insulating layer 102 14 , 102 13 and the sacrificial layer 104 14 , 104 13 , 104 12 side wall.

[0088] Please refer to Figure 2H , with the mask layer PR2', the insulating layer 102 having the openings OP31, OP32, OP33 13 and the sacrificial layer 104 12 and an insulating layer 102 having an opening OP14 14 and the sacrificial layer 104 13 The stacked structure 101 is patterned using a mask. The patterns of the openings OP41, OP42 and OP43 are transferred to the insulating layer 102. 13 With the sacrificial layer 104 12The pattern of the opening OP44 is transferred to the insulating layer 102 14 With the sacrificial layer 104 13 The patterns of the openings OP31 , OP32 , OP33 and OP14 are transferred to the insulating layer 102 12 With the sacrificial layer 104 11 .

[0089] Please refer to Fig.2I , and the mask layer PR2' is removed. Thus, the transition step structures TSC1, TSC2, the step structure SC3 and the transition step structure TSC4 are formed.

[0090] Please refer to Figure 1 and 2J , a patterning process of the third stage T3 is performed. A mask layer (not shown) is formed, and a selective etching process is performed on the transition step structures TSC1, TSC2, and TSC4 to form a transition step structure TSC1', a step structure SC2, and a transition step structure TSC4'. The mask layer is then removed.

[0091] Please refer to Figure 1 and 2K , and perform the patterning process of the fourth stage T4. A mask layer (not shown) is formed, and a selective etching process is performed on the transition step structures TSC1' and TSC4' to form step structures SC1 and SC4. The step structure SC1 is located in the peripheral region R1 and the step region R2. The step structures SC2 and SC3 are located in the step region R2. The step structure SC4 is located in the word line cutting region R4 and the peripheral region R5. The mask layer is then removed.

[0092] The side profiles of the step structures SC1, SC2, SC3, and SC4 are generally symmetrical structures. The step structures SC1 and SC4 extend toward the substrate 10 to expose the insulating layer 1021. Therefore, the depth H1 of the step structure SC1 is greater than the depth H2 of the step structure SC2. The depth H2 of the step structure SC2 is greater than the depth H3 of the step structure SC3. The depth H4 of the step structure SC4 is equal to the depth H1 of the step structure SC1. However, the number of steps of the step structure SC4 is less than the number of steps of the step structure SC1. For example, in Figure 2K , the number of steps of the step structure SC4 is 4, and the number of steps of the step structure SC1 is 6. The height of the first step of the step structure SC4 is the sum of the heights of the first and second steps of the step structure SC1. The height of the second step of the step structure SC4 is the sum of the heights of the third and fourth steps of the step structure SC1. The height of the third step of the step structure SC4 is equal to the height of the fifth step of the step structure SC1. The height of the fourth step of the step structure SC4 is equal to the height of the sixth step of the step structure SC1.

[0093] In addition, the stair structure SC1 includes portions P1 and P2; the stair structure SC4 includes portions P3 and P4. Portion P1 is located in the peripheral region R1; portion P2 is located in the stair region R2. Portion P1 and portion P2 are separated from each other. Portion P3 is located in the word line cutting region R4; portion P4 is located in the peripheral region R5. Portion P3 and portion P4 are separated from each other.

[0094] Please refer to Figure 1 and Figure 2K Furthermore, the portion P2 of the step structure SC1, the step structures SC2 and SC3, and the portion P3 of the step structure SC4 are located in the first area A1, the second area A2, the third area A3, and the fourth area A4 of the step region R2 of each block B. In the memory array region R3, the stop layer 105 and the stacked structures 101 and 90 are not patterned, and therefore, no step structure is formed.

[0095] Please refer to Figure 2L , a dielectric layer 103 is formed on the substrate 10 to cover the step structures SC1, SC2, SC3 and SC4. The dielectric layer 103 has an inverted step structure. The material of the dielectric layer 103 is, for example, silicon oxide. The method of forming the dielectric layer 103 is, for example, to form a dielectric material layer to fill and cover the step structures SC1, SC2, SC3 and SC4 and the stop layer 105. Then, a planarization process is performed using the stop layer 105 as a stop layer, such as a chemical mechanical polishing process, to remove the dielectric material layer above the stop layer 105.

[0096] Please refer to Figure 2M , remove the stop layer 105. An insulating cap layer 115 is formed on the stacked structure 101. In one embodiment, the material of the insulating cap layer 115 includes silicon oxide. Afterwards, a patterning process is performed to remove part of the insulating cap layer 115, part of the stacked structure 101, and part of the stacked structure 90 in the memory array region R3 to form one or more openings 106 passing through the insulating cap layer 115, the stacked structure 101, and the stacked structure 90. In one embodiment, the opening 106 may have a slightly inclined sidewall, such as Figure 2M As shown. In another embodiment, the opening 106 may have substantially vertical sidewalls (not shown). In one embodiment, the opening 106 is also referred to as a vertical channel (VC) hole. A vertical channel column CP is then formed in the opening 106. The vertical channel column CP may be formed by the following method.

[0097] Please refer to Figure 2M, a charge storage structure 108 is formed on the sidewall of the opening 106. The charge storage structure 108 is in contact with the insulating cap layer 115, the insulating layer 102, the sacrificial layer 104, the insulating layer 92 and the conductive layer 94. In one embodiment, the charge storage structure 108 is an oxide / nitride / oxide (ONO) composite layer. In one embodiment, the charge storage structure 108 is formed on the sidewall of the opening 106 in the form of a spacer, and the bottom surface of the opening 106 is exposed.

[0098] Then, please refer to Figure 2M , a channel layer 110 is formed on the charge storage structure 108. In one embodiment, the material of the channel layer 110 includes polysilicon. In one embodiment, the channel layer 110 covers the charge storage structure 108 on the sidewall of the opening 106, and also covers the channel layer 110 on the bottom surface of the opening 106. Next, an insulating column 112 is formed at the lower portion of the opening 106. In one embodiment, the material of the insulating column 112 includes silicon oxide. Thereafter, a conductor plug 114 is formed at the upper portion of the opening 106, and the conductor plug 114 is in contact with the channel layer 110. In one embodiment, the material of the conductor plug 114 includes polysilicon. The channel layer 110 and the conductor plug 114 may be collectively referred to as a vertical channel column CP. The charge storage structure 108 surrounds the vertical outer surface of the vertical channel column CP.

[0099] In some embodiments, when the opening 106, the charge storage structure 108, and the vertical channel column CP are formed, support structures PL1, PL2, PL3, and PL4 are also formed in the step region R2 and the word line cutting region R4 to prevent the portion P2 of the step structure SC1, the step structures SC2, SC3, and the portion P3 of the step structure SC4 from collapsing during the subsequent removal of the sacrificial layer 104. The support structures PL1, PL2, PL3, and PL4 may have the same structure as the structure formed by the charge storage structure 108 and the vertical channel column CP, but the present invention is not limited thereto. In other embodiments, the support structures PL1, PL2, PL3, and PL4 may be formed separately, and their structures may be different from the structure formed by the charge storage structure 108 and the vertical channel column CP. In this embodiment, in the subsequent process, the sacrificial layer 104 of the portion P1 of the step structure SC1, the portion P4 of the step structure SC4, and the second area A2 and the third area A3 of the step area R2 will not be removed. Therefore, there is no need to form a supporting structure in the portion P1 of the step structure SC1, the portion P4 of the step structure SC4, and the second area A2 and the third area A3 of the step area R2.

[0100] Please refer to Figure 1 and Figure 2N, a patterning process is performed to remove the insulating cap layer 115, a portion of the stacked structure 101, and a portion of the stacked structure 90 between two adjacent blocks B, such as between the fourth area A4 of the block B1 and the first area A1 of the block B2, to form a plurality of trenches 116 passing through the insulating cap layer 115 and the stacked structure 101 and through a portion of the stacked structure 90. In one embodiment, the trenches 116 may have substantially vertical sidewalls, such as Figure 2N In another embodiment, the trench 116 may have slightly inclined sidewalls (not shown). The trench 116 exposes the sidewalls of the insulating cap layer 115 , the sacrificial layer 104 , the insulating layer 102 , the insulating layer 92 and the conductive layer 94 .

[0101] Please refer to Figure 1 and Figure 2N , and then, a selective etching process is performed to make the etchant flow through the first area A1 and the fourth area A4 on both sides through the channel 116, and then flow through the second area A2 and the third area A3. Thus, the sacrificial layer 104 of the part P2 of the step structure SC1, the step structures SC2, SC3 and the part P3 of the step structure SC4 is removed to form a plurality of horizontal openings 121. The horizontal openings 121 expose the sidewalls of the part of the charge storage structure 108 and the insulating layer 102 in the storage array region R3, and expose the sidewalls of the part of the supporting structures PL1, PL2, PL3 and PL4. In this process, due to the arrangement of the supporting structures PL1, PL2, PL3 and PL4, the part P2 of the step structure SC1, the step structures SC2, SC3 and the part P3 of the step structure SC4 can be prevented from collapsing. The selective etching process can be an isotropic etching, such as a wet etching process. The etchant used in the wet etching process is, for example, hot phosphoric acid. The etchant flows into the step region R2, the memory array region R3, the first region A1 and the fourth region A4 of the word line cutting region R4 of each block B through the channel 116, and then extends to the second region A2 and the third region A3 of the memory array region R3 and the word line cutting region R4.

[0102] Please refer to Figure 1 and Figure 2N, the dielectric layer 103 separates the parts P1 and P2 of the step structure SC1 from each other, and separates the parts P3 and P4 of the step structure SC4 from each other. Therefore, the sacrificial layer 104 of the part P1 of the step structure SC1 and the part P4 of the step structure SC4 is blocked by the dielectric layer 103 and will not be removed, and thus is retained. In addition, in some embodiments, before the selective etching process is performed to remove the sacrificial layer 104, an insulating wall 113 is formed around the second area A2 and the third area A3 of the step region R2. Therefore, after the etchant flows through the first area A1 and the fourth area A4 on both sides through the channel 116, due to the blocking of the insulating wall 113, the etchant can no longer flow through the second area A2 and the third area A3 of the step region R2, so the sacrificial layer 104 of the second area A2 and the third area A3 of the step region R2 is not removed, but retained.

[0103] Please refer to Figure 2N Then, a conductor layer is formed in the channel 116 and the horizontal opening 121. The conductor layer includes, for example, a barrier layer 122 and a metal layer 124. In one embodiment, the material of the barrier layer 122 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the metal layer 124 includes tungsten (W). The conductor layer in the horizontal opening 121 serves as a gate layer 126.

[0104] Please refer to Figure 2N, the sacrificial layer 104 of the portion P2 of the step structure SC1, the step structures SC2 and SC3, and the portion P3 of the step structure SC4 is replaced by the gate layer 126. The sacrificial layer 104 of the portion P1 of the step structure SC1 and the portion P4 of the step structure SC4 is retained. The portions P1 and P2 of the step structure SC1 have symmetrical side profiles, but are stacked from different material layers. The portion P1 of the step structure SC1 is stacked from the insulating layer 102 and the sacrificial layer 104; the portion P2 of the step structure SC1 is stacked from the insulating layer 102 and the gate layer 126. The step structures SC2 and SC3 are respectively stacked from the insulating layer 102 and the gate layer 126, and have symmetrical structures respectively. The portions P3 and P4 of the step structure SC4 have symmetrical side profiles, but are stacked from different material layers. The portion P3 of the step structure SC4 is formed by stacking the insulating layer 102 and the gate layer 126; the portion P4 of the step structure SC4 is formed by stacking the insulating layer 102 and the sacrificial layer 104. In some embodiments, the portion P2 of the step structure SC1 in the step region R2 and the step structures SC2 and SC3 can be collectively referred to as the step structure SC. The portion P2 of the step structure SC1 and the step structures SC2 and SC3 can be respectively referred to as sub-step structures of the step structure SC. In the present embodiment, three sub-step structures (e.g., P2, SC2, and SC3) are used for illustration, however, the present invention is not limited thereto, and the step structure SC can include more or fewer sub-step structures.

[0105] Please refer to Figure 2N , then, a spacer 117 is formed on the sidewall of the trench 116. The spacer 117 includes a dielectric material different from the insulating layer 102, such as silicon nitride or a silicon oxide / silicon nitride / silicon oxide composite layer. Afterwards, the conductor layer 94 in the middle of the stacked structure 90 in the storage array region R3 is removed, and then the insulating layers 92 above and below the conductor layer 94 are removed to form a horizontal opening (not shown) in the stacked structure 90. Then, a conductor layer is filled in the trench 116 and the horizontal opening. The conductor layer in the horizontal opening and the conductor layers 94 above and below it together form a source line 120.

[0106] Please refer to Fig.2O A conductor layer is formed in the channel 116 to form a source line slit 118 for conducting current from the source line 120. The spacer 117 isolates the source line slit 118 from contacting the gate layer 126.

[0107] Please refer to Figure 1 and 2P, thereafter, contact windows C1 and C5 are formed in the peripheral regions R1 and R5 to be electrically connected to the conductor layer 36 of the metal interconnect structure 30. A plurality of contact windows C2 are formed in the first region A1 and the fourth region A4 of the step region R2 to be connected to the end of the gate layer 126. A plurality of contact windows (not shown) are formed in the second region A2 and the third region A3 of the step region R2 to be electrically connected to the conductor layer 36 of the metal interconnect structure 30. A plurality of contact windows C3 are formed in the memory array region R3 to be electrically connected to the conductor plug 114 of the vertical channel column CP. The contact windows C1, C2, C3 and C5 may be formed simultaneously or separately. In addition, the contact windows C1, C2, C3 and C5 may include one or more plugs, respectively. The plurality of plugs of the contact windows C1, C2, C3 and C5 may be formed simultaneously or separately. In one embodiment, each of the contact windows C1, C2, C3 and C5 may include a barrier layer and a conductor layer. The material of the barrier layer is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the conductor layer is, for example, tungsten (W).

[0108] In some embodiments, since portion P1 of step structure SC1 will not be electrically connected to contact window C1, portion P3 of step structure SC4 will not form a contact window, and portion P4 of step structure SC4 will not be electrically connected to contact window C5, portion P1 of step structure SC1 and step structure SC4 can also be called virtual step structures.

[0109] Please refer to Figure 1 and Figure 2P , forming a metal interconnect structure 40. The metal interconnect structure 40 may include a multi-layer dielectric layer 42 and a plurality of plugs 44 and a plurality of wires 46 formed in the multi-layer dielectric layer 42. The dielectric layer 42 separates adjacent wires 46. The wires 46 may be connected to each other through the plugs 44, and the wires 46 may be electrically connected to the contact windows C1, C2, C3 and C5. The wire 46 connected to the contact window C3 may serve as a bit line BL.

[0110] Thereafter, subsequent related processes are performed to complete the fabrication of the memory element.

[0111] Please refer to Figure 1 , Figure 2P and Figure 3 In some embodiments of the present invention, in each block B, the portion P3 of the step structure SC4 in the word line cutting region R4 and the portion P4 of the step structure SC4 in the peripheral region R5 are separated from each other and completely separated by the dielectric layer 103, such as Figure 2PAs shown. The portions P3 of the step structures SC4 of two adjacent blocks B (e.g., blocks B2 and B3) are also separated from each other and completely separated by the dielectric layer 103. Therefore, the gate layers (multiple word lines) 126 of the same level of the two adjacent blocks B (e.g., blocks B2 and B3) are separated from each other and separated by the dielectric layer 103, as shown. Figure 3 shown.

[0112] Please refer to Figure 1 , Figure 2K and Figure 2L In the above embodiment, the stair structure SC4 of each block B extends continuously from the first area A1 of the word line cutting area R4 to the fourth area A4. Therefore, the portion P3 of the stair structure SC4 and the portion P4 of the stair structure SC4 in the peripheral area R5 are separated from each other, and the channel 119 formed therebetween extends continuously from the block B1 to the block B4. Therefore, the dielectric layer 103 located between the word line cutting area R4 and the peripheral area R5 is also filled in the channel 119 and extends continuously from the block B1 to the block B4.

[0113] Please refer to Figure 4A and Figure 4B In other embodiments, the stair structure SC4 of the word line cutting region R4 and the peripheral region R5 does not extend continuously from the first region A1 to the fourth region A4, but includes a plurality of island stair structures SC41, SC42 and SC43. The island stair structures SC41, SC42 and SC43 are respectively formed at the ends of the source line conductor walls (source lineslit) 118 between two adjacent blocks B. That is, the island stair structure SC41 is formed in the fourth region A4 of the block B1 and the first region A1 of the block B2, the island stair structure SC42 is formed in the fourth region A4 of the block B2 and the first region A1 of the block B3, and the island stair structure SC43 is formed in the fourth region A4 of the block B3 and the first region A1 of the block B4. In some embodiments, the island stair structures SC41, SC42 and SC43 are formed through a patterning process of four stages (i.e., T1, T2, T3 and T4), but the present invention is not limited thereto.

[0114] Therefore, the dielectric layer 103 of each block B does not extend continuously from the first area A1 of the word line cutting area R4 to the fourth area A4, but includes island-shaped dielectric layers 1031, 1032, and 1033 separated from each other. The island-shaped dielectric layers 1031, 1032, and 1033 are respectively formed at the ends of the source line conductor walls (source line slits) 118 (i.e., 1181, 1182, and 1183) between two adjacent blocks B, as shown in FIG. Figure 4AThat is, the dielectric layer 103 is formed between two adjacent blocks B. For example, the island dielectric layer 1031 is formed in the fourth area A4 of the block B1 and the first area A1 of the block B2, the island dielectric layer 1032 is formed in the fourth area A4 of the block B2 and the first area A1 of the block B3, and the island dielectric layer 1033 is formed in the fourth area A4 of the block B3 and the first area A1 of the block B4.

[0115] Part P3 of the sub-step structures SC41, SC42 and SC43 on the side of the island dielectric layers 1031, 1032, 1033 close to the memory array region R3 is formed by stacking the insulating layer 102 and the gate layer 126. Part P4 of the sub-step structures SC41, SC42 and SC43 on the side of the island dielectric layers 1031, 1032, 1033 away from the memory array region R3 is formed by stacking the insulating layer 102 and the sacrificial layer 104. The other parts of the step structures SC41, SC42 and SC43 may be formed by stacking the insulating layer 102 and the gate layer 126, or by stacking the insulating layer 102 and the sacrificial layer 104, or a combination thereof.

[0116] Please refer to Figure 1 and Figure 4A In the above embodiments, the width W4 of the word line cutting region R4 is quite small, for example, smaller than the width W1 of the peripheral region R1, the width W2 of the step region R2 or the width W3 of the memory array region R3.

[0117] Please refer to Figure 5A and Figure 5BIn another embodiment, the width W4 of the word line cutting region R4 may be equal to the width W2 of the step region R2. The step structure SC4 in the word line cutting region R4 and the peripheral region R5 may include a plurality of sub-step structures SC4a, SC4b, and SC4c. The sub-step structure SC4a may have a similar width and side profile to the step structure SC3, the sub-step structure SC4b may have a similar width and side profile to the step structure SC2, and the sub-step structure SC4c may have a similar width and side profile to the step structure SC1. The sub-step structures SC4a and SC4b are formed by stacking the insulating layer 102 and the gate layer 126. The sub-step structure SC4c includes portions P3 and P4 separated from each other. The portion P3 of the sub-step structure SC4c is formed by stacking the insulating layer 102 and the gate layer 126; the portion P4 of the sub-step structure SC4c is formed by stacking the insulating layer 102 and the sacrificial layer 104. In some embodiments, the sub-step structure SC4a is formed through the patterning process of the first stage T1 and the second stage T2; the sub-step structure SC4b is formed through the patterning process of the first stage T1, the second stage T2 and the third stage T3; the sub-step structure SC4c is formed through the patterning process of the first stage T1, the second stage T2, the third stage T3 and the fourth stage T4, but the present invention is not limited to this.

[0118] The dielectric layer 103 between the portions P3 and P4 of the sub-staircase structure SC4c extends continuously from the block B1 to the block B4, so that the gate layers (word lines) 126 of adjacent blocks B are separated from each other. Figure 5A shown.

[0119] Please refer to Fig. 6A and 6B In another embodiment, the step structure SC4 in the word line cutting region R4 and the peripheral region R5 may have the same width and a similar side profile as the step structure SC1 in the peripheral region R1 and the step region R2. Similarly, the step structure SC4 includes portions P3 and P4 separated from each other. The portion P3 of the step structure SC4 is formed by stacking the insulating layer 102 and the gate layer 126; the portion P4 of the step structure SC4 is formed by stacking the insulating layer 102 and the sacrificial layer 104. In some embodiments, the step structure SC4 is formed by a patterning process of four stages (i.e., T1, T2, T3, and T4), but the present invention is not limited thereto.

[0120] The dielectric layer 103 between the portions P3 and P4 of the stepped structure SC4 extends continuously from the block B1 to the block B4, so that the gate layers (word lines) 126 of adjacent blocks B are separated from each other. Fig. 6A shown.

[0121] Please refer to Fig. 7A and Figure 7BIn another embodiment, the step structure SC4 in the word line cutting region R4 and the peripheral region R5 includes a plurality of sub-step structures SC4d, SC4e, and SC4f. The widths of the sub-step structures SC4d, SC4e, and SC4f are respectively smaller than the widths of the step structures SC3, SC2, and SC1. The sub-step structures SC4d and SC4e are respectively formed by stacking the insulating layer 102 and the gate layer 126. The sub-step structure SC4f includes portions P3 and P4 separated from each other. The portion P3 of the sub-step structure SC4f is formed by stacking the insulating layer 102 and the gate layer 126; the portion P4 of the step structure SC4f is formed by stacking the insulating layer 102 and the sacrificial layer 104. In some embodiments, the sub-step structure SC4d is formed through the patterning process of the first stage T1 and the second stage T2; the sub-step structure SC4e is formed through the patterning process of the first stage T1, the second stage T2 and the third stage T3; the sub-step structure SC4f is formed through the patterning process of the first stage T1, the second stage T2, the third stage T3 and the fourth stage T4, but the present invention is not limited to this.

[0122] The dielectric layer 103 between the portions P3 and P4 of the stepped structure SC4f extends continuously from the block B1 to the block B4, so that the gate layers (word lines) 126 of adjacent blocks B are separated from each other. Fig. 7A shown.

[0123] In this embodiment, the stacked structure between two adjacent blocks is patterned into two separated stepped structures, and a dielectric layer with an anti-staircase structure is disposed between them, so that multiple word lines of different blocks are separated from each other, and short circuits between multiple word lines of two blocks are avoided. Furthermore, since the stepped structure between two adjacent blocks can be formed simultaneously with the stepped structure of the stepped region, it can be integrated with the existing process without increasing the manufacturing cost and burden.

[0124] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory element, characterized in that: include: A substrate, comprising a plurality of blocks, each block comprising a step region, a memory array region and a word line cutting region, wherein the memory array region is located between the step region and the word line cutting region; A stacked structure located on the substrate in the storage array area, wherein the stacked structure includes a plurality of first insulating layers and a plurality of conductor layers alternately stacked with each other; A first stepped structure, located on the substrate in the stepped region, wherein the first stepped structure comprises a plurality of first insulating layers and a plurality of conductor layers alternately stacked with each other; as well as a first portion of a second stepped structure, located on the substrate in the word line cutting region, wherein the first portion of the second stepped structure comprises a plurality of first insulating layers and a plurality of conductive layers alternately stacked with each other, and two first portions of two second stepped structures of two adjacent blocks are separated from each other; Wherein, the substrate further comprises a peripheral region, and the word line cutting region is located between the memory array region and the peripheral region; and The second portion of the second stepped structure is located on the substrate in the peripheral region, wherein the second portion of the second stepped structure includes a plurality of first insulating layers and a plurality of second insulating layers alternately stacked with each other; The multiple conductor layers of the first stepped structure connect the multiple conductor layers of the stacked structure and the multiple conductor layers of the first part of the second stepped structure, and are separated from the multiple second insulating layers of the second part of the second stepped structure, and the first part of the second stepped structure is separated from the second part of the second stepped structure by a dielectric layer having an anti-step structure, and the dielectric layer having an anti-step structure extends continuously in the multiple blocks.

2. The memory device according to claim 1, characterized in that The second stepped structure has a plurality of sub-stepped structures located in the plurality of blocks.

3. The memory device according to claim 1, wherein: The second stepped structure includes a plurality of island-shaped stepped structures, and each island-shaped stepped structure is located between two adjacent blocks.

4. The memory device according to claim 1, wherein: The number of steps of the second stepped structure is smaller than the number of steps of the first stepped structure.

5. The memory device according to claim 1, wherein: Also includes: A plurality of first contact windows, respectively connected to the plurality of conductor layers of the first stepped structure; A plurality of first support pillars, penetrating the plurality of first insulating layers and the plurality of conductor layers of the first stepped structure; as well as A plurality of second support pillars penetrate the plurality of first insulating layers and the plurality of conductive layers of the first portion of the second stepped structure.

6. A method for manufacturing a memory element, characterized in that: include: Providing a substrate, including a plurality of blocks, each block including a step region, a memory array region and a word line cutting region, wherein the memory array region is located between the step region and the word line cutting region; forming a stacked structure on the substrate in the step region, the memory array region and the word line cutting region, wherein the stacked structure comprises a plurality of first insulating layers and a plurality of second insulating layers alternately stacked with each other; patterning the stacked structure in the stepped region to form a first stepped structure; Patterning the stacked structure in the word line cutting region to form a first portion of a second stepped structure, so that two first portions of two second stepped structures of two adjacent blocks are separated from each other; as well as Performing a replacement process to replace a plurality of second insulating layers of the stacked structure in the memory array area, the first stepped structure in the stepped area, and the first portion of the second stepped structure in the word line cutting area with a plurality of conductor layers; The substrate further includes a peripheral region, the word line cutting region is located between the memory array region and the peripheral region, and the stacked structure is also formed on the substrate in the peripheral region, and when patterning the stacked structure in the stepped region, the stacked structure in the peripheral region is further patterned to form a second portion of the second stepped structure, and the second portion of the second stepped structure is separated from the first portion of the second stepped structure; The method further includes forming a dielectric layer having an anti-step structure between the first portion of the second step structure and the second portion of the second step structure, so as to separate the first portions of the two second step structures of two adjacent blocks from each other.

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