Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are provided. A semiconductor device includes a capacitor disposed on a substrate, including a lower electrode, a dielectric layer, and an upper electrode; and a discharge structure spaced apart from the capacitor, connected to the upper electrode of the capacitor, and adapted to discharge a charge induced by a plasma process used to form the upper electrode of the capacitor to the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0000858, filed on January 5, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same, and more specifically, to semiconductor devices and methods of manufacturing the same including a discharge structure capable of discharging plasma-induced charges onto a substrate. Background Technology

[0004] Semiconductor device fabrication involves several steps in plasma processing. Plasma processing is primarily used during deposition or etching processes. However, plasma-induced charges from plasma processes can degrade the electrical performance of semiconductor devices, necessitating new and improved solutions. Summary of the Invention

[0005] Embodiments of the present invention relate to a semiconductor device and a method thereof capable of improving the performance of a semiconductor device by preventing plasma-induced damage (PID).

[0006] According to one embodiment of the present invention, a semiconductor device includes a capacitor disposed on a substrate and including a lower electrode, a dielectric layer and an upper electrode; and a discharge structure spaced apart from the capacitor, connected to the upper electrode of the capacitor, and adapted to discharge charge induced by a plasma process for forming the upper electrode of the capacitor to the substrate.

[0007] According to another embodiment of the present invention, a semiconductor device includes: a substrate including a first region and a second region; a capacitor disposed on the first region of the substrate and including a lower electrode, a dielectric layer and an upper electrode; and a discharge structure spaced apart from the capacitor, connected to the upper electrode of the capacitor and adapted to discharge charge induced by a plasma process for forming the upper electrode of the capacitor to the second region of the substrate.

[0008] According to another embodiment of the present invention, a method of manufacturing a semiconductor device includes: providing a substrate including a first region and a second region; forming a capacitor having a lower electrode, a dielectric layer and an upper electrode stacked on the first region of the substrate; and forming a discharge structure on the second region of the substrate, the discharge structure being spaced apart from the capacitor and connected to the upper electrode of the capacitor.

[0009] The embodiments of the present invention have the effect of improving the performance of semiconductor devices by preventing plasma-induced damage (PID). Attached Figure Description

[0010] Figure 1 This is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.

[0011] Figures 2A to 2K This illustrates the manufacture of an embodiment according to the present invention. Figure 1 A cross-sectional view of the method for the semiconductor device shown.

[0012] Figures 3A to 3D , Figures 4A to 4D , Figures 5A to 5D and Figures 6A to 6D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to another embodiment of the present invention. Detailed Implementation

[0013] The various embodiments described herein will be illustrated with reference to cross-sectional views, plan views, and block diagrams, which serve as ideal schematic diagrams of the invention. Therefore, the structures in the drawings may be modified due to manufacturing techniques and / or tolerances. Embodiments of the invention are not limited to the specific structures shown in the drawings, but include any variations in structure that may result from manufacturing processes. Accordingly, the regions and shapes shown in the drawings are intended to illustrate specific structures of regions of elements and are not intended to limit the scope of the invention.

[0014] Figure 1 This is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0015] Reference Figure 1 The substrate 101 may include a first region R1, a second region R2, and a third region R3. A capacitor may be disposed on the substrate 101 in the first region R1. The capacitor may include a lower electrode SN, a dielectric layer 116, and an upper electrode 119. The first region R1 and the capacitor may be electrically connected via a first contact plug 106 and a second contact plug 108. A discharge structure PS may be disposed on the substrate 101 in the second region R2. The discharge structure PS may include a first diode D1, a first discharge contact plug 106', a second discharge contact plug 108', a first electrode 114', and a second electrode 119'. A second diode D2, a peripheral gate PG, a first peripheral metal line 109, and a second peripheral metal line 125 may be disposed on the substrate 101 in the third region R3.

[0016] Substrate 101 may be a material suitable for semiconductor processing. Substrate 101 may include a semiconductor substrate. Substrate 101 may include a silicon-containing material. Substrate 101 may include, for example, silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, single-crystal silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof, or multilayers of two or more of them. Substrate 101 may also be made of other semiconductor materials such as germanium. Substrate 101 may be made of a group III / V semiconductor substrate, i.e., a compound semiconductor substrate, such as gallium arsenide (GaAs). Substrate 101 may include a silicon-on-insulator (SOI) substrate.

[0017] The first region R1 of substrate 101 may include a cell region in which devices such as gates, bit lines, and capacitors are formed. The second region R2 may include a discharge region in which plasma-induced charges are discharged onto the substrate. The third region R3 may include a peripheral region for controlling the operation of devices formed in the first region R1. In one embodiment, the second region R2 may include a dummy region located between the cell region and the peripheral region.

[0018] The first region R1, the second region R2, and the third region R3 can be divided by an isolation layer 102. Each of regions R1 to R3 may include an active region 103 defined by the isolation layer 102. The isolation layer 102 may be a region formed by a shallow trench isolation (STI) process. The isolation layer 102 may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0019] The gate structure BG can be disposed in the first region Rl. The gate structure BG can be a buried gate structure. According to... Figure 1 The gate structure BG can be located at a horizontal plane lower than the upper surface of the substrate 101. However, the present invention is not limited thereto. The present invention can be applied to any type of gate structure, such as recessed gates, finned gates, and planar gates.

[0020] The source / drain region 104 can be disposed in the substrate 101 between the gate structures BG and in the substrate 101 on both sides of the gate structure BG.

[0021] Bit line structure BL can be disposed on substrate 101 between gate structures BG. Bit line structure BL can be formed to directly contact source / drain regions 104 located between gate structures BG.

[0022] A first insulating layer 105 may be formed on a substrate 101. The first insulating layer 105 may be formed collectively on a first region R1, a second region R2, and a third region R3 of the substrate. The first insulating layer 105 may include an insulating material. The first insulating layer 105 may be a single layer or multiple layers. The first insulating layer 105 may include multiple layers of insulating material having the same etch selectivity. The first insulating layer 105 may include multiple layers of insulating material with different etch selectivity. The first insulating layer 105 may include, for example, nitrides, oxides, oxynitrides, or combinations thereof.

[0023] The first contact plug 106 and the second contact plug 108 may be configured to penetrate the first insulating layer 105 of the first region R1 to contact the substrate 101. The first contact plug 106 may be formed to contact the source / drain region 104. The upper surface of the second contact plug 108 and the upper surface of the first insulating layer 105 may be located on the same horizontal plane. The first contact plug 106 may include a semiconductor material. The second contact plug 108 may include a metal.

[0024] Various embodiments of the present invention illustrate a first contact plug 106 and a second contact plug 108 passing through a first insulating layer 105. However, the present invention is not limited thereto. The first insulating layer 105 may comprise multiple layers of insulating material adapted to form separate insulating layers for the first contact plug 106 and the second contact plug 108.

[0025] The linewidth of the second contact plug 108 can be adjusted to be wider than that of the first contact plug 106. In this embodiment, the upper surface of the first contact plug 106 is shown to be covered by the second contact plug 108, but this embodiment is not limited thereto. If necessary, the first contact plug 106 and the second contact plug 108 can partially overlap within the limits of being electrically connected.

[0026] One end of the first contact plug 106 can directly contact the source / drain region 104 of the substrate 101, and the other end of the first contact plug 106 can directly contact the second contact plug 108. One end of the second contact plug 108 can directly contact the other end of the first contact plug 106, and the other end of the second contact plug 108 can directly contact the lower electrode SN of the capacitor.

[0027] Etch stop pattern 110 may be formed on the first insulating layer 105. Etch stop pattern 110 may be formed collectively on the first insulating layer 105 over the first region R1, the second region R2, and the third region R3. Etch stop pattern 110 may be formed to protect the underlying layer including the first insulating layer 105 during subsequent processes such as upper layer etching processes. Etch stop pattern 110 may be formed of a material having an etch selectivity ratio relative to the sacrificial layer 111A. Etch stop pattern 110 may include nitrides, oxides, oxynitrides, or combinations thereof.

[0028] A capacitor can be disposed on the second contact plug 108 of the first region R1. The capacitor can be formed of a lower electrode SN, a dielectric layer 116, and an upper electrode 119. The lower electrode SN, dielectric layer 116, and upper electrode 119 can be stacked. The dielectric layer 116 can be disposed between the lower electrode SN and the upper electrode 119. The capacitor, particularly the lower electrode SN, can contact the first region R1 of the substrate 101 through the first and second contact plugs 106 and 108. The capacitor can be located at a horizontal plane higher than the upper surface of the first insulating layer 105.

[0029] The lower electrode SN may include a structure of a first lower electrode 114 and a second lower electrode 115. The lower electrode SN may be cylindrical. The lower electrode SN may include a cylindrical first lower electrode 114 and a cylindrical second lower electrode 115. The second lower electrode 115 may be formed inside the first lower electrode 114. The first lower electrode 114 and the second lower electrode 115 may be made of the same or different materials. The first lower electrode 114 and the second lower electrode 115 may have a metal-based material. A metal-based material can refer to a material containing metals. In another embodiment of the invention, the first lower electrode 114 may have a metal-based material, while the second lower electrode 115 may have a silicon-based material. A silicon-based material can refer to a silicon-containing material. For example, the first lower electrode 114 and the second lower electrode 115 may have titanium nitride (TiN). The first lower electrode 114 may have titanium nitride (TiN), while the second lower electrode 115 may have doped polycrystalline silicon. Doped polycrystalline silicon can refer to polycrystalline silicon doped with conductive impurities.

[0030] The dielectric layer 116 may comprise a single-layer structure, a multilayer structure, or a laminated structure. The dielectric layer 116 may have a doped structure or a hybrid structure. The dielectric layer 116 may comprise a high-k material. The dielectric layer 116 may have a higher dielectric constant than silicon oxide (SiO2). In one embodiment, silicon oxide may have a dielectric constant of about 3.9, and the dielectric layer 116 may comprise a material having a dielectric constant of 4 or greater. The high-k material may have a dielectric constant of about 20 or greater. High-k materials may include, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). In another embodiment of the invention, the dielectric layer 116 may be formed from multiple layers of high-k material. The dielectric layer 116 may comprise a zirconium-based oxide layer. The dielectric layer 116 may comprise a stacked structure of zirconium oxide (ZrO2). The stacked structure of zirconia may include ZA (ZrO2 / Al2O3) or ZAZ (ZrO2 / Al2O3 / ZrO2). ZA may be a stacked structure in which alumina is stacked on zirconia. ZAZ may be a stacked structure in which zirconia, alumina, and zirconia are stacked sequentially. Each of the ZrO2, ZA, and ZAZ structures may also be referred to as a "zirconia base layer (ZrO2 base layer)". In some embodiments, the dielectric layer 116 may be formed of a hafnium (Hf)-based oxide. For example, a stacked structure including hafnium (HfO2) may include an HA (HfO2 / Al2O3) structure in which alumina is stacked on hafnium oxide, or an HAH (HfO2 / Al2O3 / HfO2) structure in which hafnium oxide, alumina, and hafnium oxide are stacked sequentially. Each of the HfO2, HA, and HAH structures may also be referred to as a "hafnium (HfO2) base layer".

[0031] The alumina (Al2O3) in the ZA, ZAZ, HA, and HAH structures can have a higher band gap than zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of alumina (Al2O3) can be lower than that of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, dielectric layer 116 can comprise a stack of high-k materials and high-bandgap materials with band gaps higher than the high-k materials. In some embodiments, dielectric layer 116 can comprise silicon oxide (SiO2) as the high-bandgap material instead of alumina. Dielectric layer 116 comprising high-bandgap materials can suppress leakage current. The high-bandgap materials can be ultrathin. The high-bandgap materials can be thinner than the high-k materials.

[0032] In embodiments of the present invention, dielectric layer 116 may include a stacked structure in which high-k materials and high-bandgap materials are alternately stacked. For example, the stacked structure may include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2), HAHA (HfO2 / Al2O3 / HfO2 / Al2O3), or HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) structures. In the stacked structure, alumina (Al2O3) may be ultrathin. In other embodiments of the present invention, dielectric layer 116 may include a structure of a first high-k material doped with a second high-k material. For example, some embodiments may include zirconium oxide (TiO2-doped ZrO2) doped with titanium oxide (TiO2). Moreover, in other embodiments of the present invention, dielectric layer 116 may include a hybrid structure of different high-k materials. For example, some implementations may include TiZrAlO in which zirconium oxide, titanium oxide and aluminum oxide are mixed.

[0033] The upper electrode 119 may include silicon-containing materials, germanium-containing materials, metallic materials, or any combination thereof. The upper electrode 119 may include metals, metal nitrides, metal carbides, conductive metal oxides, or any combination thereof. The upper electrode 119 may include, for example, titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), titanium carbonitride (TiCN), tantalum carbonitride (TaCN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), iridium (Ir), ruthenium oxide (RuO2), iridium oxide (IrO2), or any combination thereof. The upper electrode 119 may include a silicon (Si) layer, a germanium (Ge) layer, a silicon-germanium (SiGe) layer, or any combination thereof. The upper electrode 119 may have a multilayer structure (Si / SiGe) formed by stacking silicon-germanium layers on a silicon layer. The upper electrode 119 may have a multilayer structure (Ge / SiGe) formed by stacking silicon-germanium layers on a germanium layer. The upper electrode 119 may include a stacked structure of silicon-containing materials and metallic materials. The upper electrode 119 can be formed by stacking silicon-germanium layers and metal nitrides. The upper electrode 119 can have a multilayer structure (TiN / SiGe / WN) formed by stacking silicon-germanium layers and tungsten nitride on titanium nitride.

[0034] The unit metal line 124 can be disposed above the capacitor in the first region Rl. The unit metal line 124 can be disposed at a horizontal plane higher than the upper surface of the capacitor. The second insulating layer 121 can be disposed between the unit metal line 124 and the capacitor.

[0035] The unit metal wire 124 can be connected to the capacitor via the unit metal wire contact 122. The unit metal wire contact 122 can pass through the second insulating layer 121. One end of the unit metal wire contact 122 can contact the upper electrode 119, and the other end of the unit metal wire contact 122 can contact the unit metal wire 124.

[0036] A discharge structure PS for discharging electrons induced by plasma processing can be disposed on a second region R2 of substrate 101. The discharge structure PS may include a first diode D1, a first discharge contact plug 106', a second discharge contact plug 108', a first electrode 114', and a second electrode 119' stacked vertically from the substrate.

[0037] The first diode Dl can be defined by a junction region 104' and a substrate 101. The junction region 104' and the source / drain region 104 in the first region Rl can be formed simultaneously.

[0038] The first discharge contact plug 106' and the second discharge contact plug 108' can be disposed on the second region R2 of the substrate 101, with the first discharge contact plug 106' contacting the junction region 104' of the first diode D1. The first discharge contact plug 106' and the second discharge contact plug 108' can be located at the same horizontal plane as the first contact plug 106 and the second contact plug 108 in the first region R1, respectively. The first discharge contact plug 106' and the second discharge contact plug 108' can be formed simultaneously with the first contact plug 106 and the second contact plug 108. The first discharge contact plug 106' and the second discharge contact plug 108' can be formed of the same material as the first and second contact plugs 106 and 108, respectively. The first discharge contact plug 106' can include a semiconductor material. The second discharge contact plug 108' can include a metal.

[0039] The first electrode 114' of the discharge structure PS can be located at the same horizontal plane as the first lower electrode 114 of the capacitor. The first electrode 114' and the first lower electrode 114 can be formed simultaneously. The first electrode 114' and the first lower electrode 114 can be made of the same material.

[0040] The second electrode 119' of the discharge structure PS can be located at the same horizontal plane as the upper electrode 119 of the capacitor. The second electrode 119' and the upper electrode 119 can be formed simultaneously. The second electrode 119' and the upper electrode 119 can be made of the same material. The second electrode 119' and the upper electrode 119 of the capacitor can be formed as a continuous single unit. In other words, the second electrode 119' can be electrically connected to the upper electrode 119 of the capacitor.

[0041] According to an embodiment of the present invention, the discharge structure PS can discharge plasma-induced charge to the substrate by contacting the upper electrode 119 of the capacitor and forming an electrical connection current path through the first diode D1 in the second region R2. In other words, embodiments of the present invention can prevent the performance of the dielectric layer 116 of the capacitor from being degraded by plasma-induced damage (PID) by discharging the charge induced from the plasma process forming the upper electrode 119, the unit metal line contact 122 and / or the unit metal line 124 to the substrate.

[0042] The third region R3 of substrate 101 may include a peripheral gate PG, a first peripheral metal line 109, and a second peripheral metal line 125. The first peripheral metal line 109 and the second peripheral metal line 125 may contact the third region R3 of substrate 101 via a first peripheral metal line contact 107 and a second peripheral metal line contact 123. A junction region 104 may be formed at the location where the first peripheral metal line contact 107 contacts the substrate 101 in region R3.

[0043] The third region R3 of substrate 101 may include a second diode D2. The second diode D2 may be electrically connected to a discharge structure PS in the second region R2. The second diode D2 may discharge charge induced from the plasma process into the third region R3 of substrate 101. The second diode D2 may contact the discharge structure PS via a third discharge contact plug 107'. The second discharge contact plug 108' may extend to contact the first discharge contact plug 106' in the second region R2 and the third discharge contact plug 107' in the third region R3.

[0044] Embodiments of the present invention illustrate a discharge structure PS including a cylindrical first electrode 114'. However, the invention is not limited thereto. In other embodiments, the first electrode 114' of the discharge structure PS can be formed in various structures based on the structure of the lower electrode SN of the capacitor in the first region R1. In other embodiments, the first electrode 114' of the discharge structure PS can be cylindrical. In other embodiments, the first electrode 114' of the discharge structure PS may also include a support member covering the outer wall of the first electrode 114'.

[0045] Figures 2A to 2K This illustrates the manufacture of an embodiment according to the present invention. Figure 1 A cross-sectional view of the method for the semiconductor device shown. Figures 2A to 2K As shown in and by Figure 1 The same reference numerals in the figures may indicate parts that have reference numerals. Figure 1 The components described in the attached drawings are marked with reference to the figures.

[0046] Reference Figure 2AA substrate 101 may be provided, comprising a first region R1, a second region R2, and a third region R3. The first region R1, the second region R2, and the third region R3 may be divided by an isolation layer 102. Each of regions R1 to R3 may include an active region 103 defined by the isolation layer 102.

[0047] Subsequently, a gate structure BG can be formed on the first region Rl of the substrate 101. According to Figure 1 The gate structure BG may have a buried gate structure located at a horizontal plane lower than the upper surface of the substrate 101. However, the present invention is not limited thereto.

[0048] Subsequently, source / drain regions 104 can be formed in the substrate 101 on both sides of each gate structure BG using an ion implantation process. Junction regions 104' and 104" can be formed in the second and third regions R2 and R3 of the substrate 101. Ion implantation for the source / drain regions 104 and junction regions 104' and 104" can be performed simultaneously, or they can be performed separately using an opening mask that opens the respective regions 104, 104', and 104"

[0049] Subsequently, a bit line structure BL can be formed on the gate structure BG. The bit line structure BL can be formed to contact the source / drain regions 104 located between the gate structures BG. The peripheral gate PG can be formed on the third region R3 of the substrate 101. The peripheral gate PG and the bit line structure BL can be formed simultaneously or at different times.

[0050] Subsequently, a first insulating layer 105 may be formed on the first to third regions R1, R2 and R3 of the substrate 101.

[0051] Subsequently, first and second contact plugs 106 and 108, first to third discharge contact plugs 106', 108' and 107', first peripheral metal wire contacts 107 and first peripheral metal wires 109 can be formed to pass through the first insulating layer 105 and contact corresponding regions R1 to R3 of the substrate 101.

[0052] The embodiments of the present invention are described using the example of a first insulating layer 105 that can be a single layer and where the contact plug can pass through the corresponding regions R1 to R3. However, the first insulating layer 105 may include multiple layers of insulating material.

[0053] For example, the first insulating layer 105 may be formed as a first layer including a first contact plug 106, a first discharge contact plug 106', a third discharge contact plug 107' and a first peripheral metal wire contact 107, and a second layer including a second contact plug 108, a second discharge contact plug 108' and a first peripheral metal wire 109.

[0054] First, a first layer can be formed on the substrate 101, and an opening can be formed through the first layer. The first contact plug 106, the first discharge contact plug 106', the third discharge contact plug 107', and the first peripheral metal line contact 107 can be formed by filling the opening with semiconductor material. Subsequently, a second layer can be formed on the first layer. An opening can be formed through the second layer, exposing the first contact plug 106, the first and third discharge contact plugs 106' and 107', and the first peripheral metal line contact 107. The second contact plug 108, the second discharge contact plug 108', and the first peripheral metal line 109 can be formed by filling the opening with metal.

[0055] The first contact plug 106, the first and third discharge contact plugs 106' and 107', and the first peripheral metal wire contact 107 can be located on the same horizontal plane. The second contact plug 108, the second discharge contact plug 108', and the first peripheral metal wire 109 can be located on the same horizontal plane.

[0056] Subsequently, an etch stop layer 110A may be formed on the first insulating layer 105. The etch stop layer 110A may include an insulating material. The etch stop layer 110A and the first insulating layer 105 may include materials with different etch selectivity ratios.

[0057] Subsequently, a sacrificial layer 111A can be formed on the etch stop layer 110A. The sacrificial layer 111A provides an opening for forming the lower electrode of the capacitor. The thickness of the sacrificial layer 111A can be adjusted to be at least the same as the height of the lower electrode of the capacitor. The sacrificial layer 111A may include an easily removable material. The sacrificial layer 111A may include a material having an etch selectivity ratio relative to the etch stop layer 110A. The sacrificial layer 111A can be formed by a deposition process such as chemical vapor deposition (CVD) and physical vapor deposition (PVD). The sacrificial layer 111A may include an insulating material. For example, the sacrificial layer 111A may include silicon oxide.

[0058] Reference Figure 2BA first mask pattern 112 can be formed on the sacrificial layer 111A. A sacrificial pattern 111 and an etch stop pattern 110 can be formed based on the first mask pattern 112. The sacrificial pattern 111 and the etch stop pattern 110 can define a lower electrode opening 113 in a first region R1 and a second region R2. By passing through the sacrificial pattern 111 and the etch stop pattern 110, the lower electrode opening 113 can expose a second contact plug 108 in the first region R1 and a second discharge contact plug 108' in the second region R2. The lower electrode opening 113 can have a high aspect ratio. The lower electrode opening 113 can have an aspect ratio of at least 1:1 or greater. For example, the lower electrode opening 113 can have an aspect ratio of 1:10 or greater. The aspect ratio used herein refers to the ratio of width to height.

[0059] Subsequently, the first mask pattern 112 can be removed. The first mask pattern, including the photosensitive material, can be removed by a stripping process.

[0060] Reference Figure 2C The first lower electrode material layer 114A and the second lower electrode material layer 115A can be formed sequentially along the lower electrode opening 113.

[0061] The first lower electrode material layer 114A and the second lower electrode material layer 115A may comprise polycrystalline silicon, metal, metal nitride, conductive metal oxide, metal silicide, noble metal, or combinations thereof. The first lower electrode material layer 114A and the second lower electrode material layer 115A may comprise, for example, at least one of the following: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W) or tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), or combinations thereof.

[0062] In embodiments of the present invention, the first lower electrode material layer 114A may include a metal. The first lower electrode material layer 114A may include a material with good step coverage. For example, the first lower electrode material layer 114A may include titanium nitride (TiN).

[0063] A second lower electrode material layer 115A may be formed on the first lower electrode material layer 114A to fill the lower electrode opening 113. The second lower electrode material layer 115A may include a semiconductor material. The second lower electrode material layer 115A may include a material having an etch selectivity ratio relative to the first lower electrode material layer 114A. The second lower electrode material layer 115A may include a material with good gap-filling properties. For example, the second lower electrode material layer 115A may include doped polysilicon.

[0064] In another embodiment of the present invention, both the first lower electrode material layer 114A and the second lower electrode material layer 115A may comprise titanium nitride (TiN). The first lower electrode material layer 114A and the second lower electrode material layer 115A may comprise titanium nitride (ALD-TiN) formed by atomic layer deposition (ALD). In another embodiment, the first lower electrode material layer 114A and the second lower electrode material layer 115A may comprise a stacked structure of titanium nitride (TiN) and tungsten (W). In another embodiment, the first lower electrode 114 and the second lower electrode 115 may have a single-layer structure with the same material.

[0065] Reference Figures 2D to 2E The lower electrode SN can have a columnar structure. The separation process of the lower electrode SN can be performed to form the lower electrode SN. The separation process of the lower electrode can include an etch-back process and / or a CMP process. The columnar lower electrode SN can be formed from a first lower electrode 114 of cylindrical structure and a second lower electrode 115 of columnar structure in contact with the first lower electrode 114. The separation process can be performed on the upper surface of the exposed sacrificial pattern 111. In other words, the upper surface of the lower electrode SN and the upper surface of the sacrificial pattern 111 can be at the same horizontal plane.

[0066] Subsequently, the sacrificial pattern 111 can be removed. The sacrificial pattern 111 can be removed by a dip-out process. The dip-out process can use one or more wet chemicals selected from HF, NH4F / NH4OH, H2O2, HCl, HNO3, and H2SO4.

[0067] Reference Figure 2FA dielectric material layer 116A can be formed along the entire surface region of the lower electrode SN. The dielectric material layer 116A can be formed using chemical vapor deposition (CVP) or atomic layer deposition (ALD) processes, exhibiting good step coverage. The dielectric material layer 116A may include an insulating material. The dielectric material layer 116A may include a high-k material with a dielectric constant higher than that of silicon oxide (SiO2). High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the invention, the dielectric material layer 116A may be a composite layer comprising two or more layers of the listed high-k materials. According to an embodiment of the invention, the dielectric layer 116A may be formed from a zirconium oxide-based material that sufficiently reduces the equivalent oxide layer thickness (EOT) and has good leakage current characteristics. For example, in this embodiment, dielectric layer 116A may include ZAZ (ZrO2 / Al2O3 / ZrO2). According to another embodiment of the invention, dielectric layer 116A may include HAH (HfO2 / Al2O3 / HfO2). According to yet another embodiment of the invention, dielectric layer 116A may include TZAZ (TiO2 / ZrO2 / Al2O3 / ZrO2), TZAZT (TiO2 / ZrO2 / Al2O3 / ZrO2 / TiO2), ZAZT (ZrO2 / Al2O3 / ZrO2 / TiO2), TZ (TiO2 / ZrO2), or ZAZAT (ZrO2 / Al2O3 / ZrO2 / Al2O3 / TiO2). In the dielectric layer stacks of TZAZ, TZAZT, ZAZT, TZ, and ZAZAT, TiO2 may be replaced with Ta2O5.

[0068] Reference Figure 2G A second mask pattern 117 may be formed on a substrate 101 containing a dielectric material layer 116A. The second mask pattern 117 may include a material that is easily removable. The second mask pattern 117 may include a material having an etch selectivity different from that of the dielectric material layer 116A or the lower electrode SN. The second mask pattern 117 may include openings that selectively expose the dielectric material layer 116A formed on the upper surface of the lower electrode SN.

[0069] Reference Figure 2H The dielectric material layer 116A in the second region R2 exposed by the second mask pattern 117 can be etched (refer to...). Figure 2G ) and the second lower electrode 115 (refer to) Figure 2GThe second lower electrode 115 in the second region R2 can be completely removed while the first lower electrode 114 can be retained alone. Therefore, an opening 118 can be formed between the first lower electrodes 114 in the second region R2. The etched dielectric material layer is indicated by reference numeral 116B.

[0070] Subsequently, the second mask pattern 117 can be removed. The second mask pattern 117, which is made of silicon oxide, can be removed by a wet dip-out process. In another embodiment of the invention, the second mask pattern 117, which is made of photoresist, can be removed by a stripping process.

[0071] Reference Figure 2I An upper electrode material layer 119A can be formed on a substrate 101 containing a dielectric material layer 116B. The upper electrode material layer 119A may include a metal-based material. For example, the upper electrode material layer 119A may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), or combinations thereof. The upper electrode material layer 119A can be formed by a low-pressure chemical vapor deposition (LPCVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, or an atomic layer deposition (ALD) process. According to an embodiment of the present invention, the upper electrode material layer 119A may include titanium nitride (ALD-TiN) formed by an ALD process.

[0072] According to another embodiment of the present invention, the upper electrode material layer 119A may have a multilayer structure. The upper electrode material layer 119A can be formed by sequentially stacking a first metal-containing material, silicon-germanium, and a second metal-containing material. The first and second metal-containing layers may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), or combinations thereof. For example, the first metal-containing material may include titanium nitride, and the second metal-containing material may include a WN / W layer in which tungsten nitride and tungsten are stacked. The silicon-germanium layer may be doped with boron.

[0073] According to an embodiment of the present invention, the upper electrode material layer 119A may include a gap-filling material or a low-resistance material. The gap-filling material may include silicon germanium (SiGe). The low-resistance material may include tungsten nitride (WN). The gap-filling material can fill the narrow gap between the lower electrodes SN without voids. The low-resistance material can reduce the resistance of the upper electrode material layer 119A.

[0074] Subsequently, a third mask pattern 120 can be formed on the upper electrode material layer 119A. The third mask pattern 120 can be patterned such that the third region R3 is open.

[0075] Reference Figure 2J Third mask pattern 120 (refer to) Figure 2I It can be used to etch the upper electrode material layer 119A and dielectric material layer 116B in the third region R3.

[0076] Therefore, the first region R1 may include a lower electrode SN, a dielectric layer 116, and an upper electrode 119 capacitor stacked therein. The second region R2 may include a discharge structure PS in which a first electrode 114' and a second electrode 119' are stacked. The first electrode 114' and the first lower electrode 114 may be formed simultaneously from the same material, with the same structure, and at the same horizontal plane. The second electrode 119' may contact the upper electrode 119 in the first region R1.

[0077] Reference Figure 2K A second insulating layer 121 may be formed on a substrate 101 including the upper electrode 119 of the capacitor. The second insulating layer 121 may include a single layer or a multilayer structure.

[0078] Subsequently, unit metal line contact 122 can be formed in the first region R1. Unit metal line contact 122 can contact the upper electrode 119 of the capacitor by passing through the second insulating layer 121. Second peripheral metal line contact 123 can be formed in the third region R3. Second peripheral metal line contact 123 can contact the first peripheral metal line 109 by passing through the second insulating layer 121 and the etch stop pattern 110.

[0079] Subsequently, unit metal wire 124 can be formed on the second insulating layer 121 in the first region R1. Unit metal wire 124 can contact unit metal wire contact 122. Second peripheral metal wire 125 can be formed on the second insulating layer 121 in the third region R3 and can contact second peripheral metal wire contact 123.

[0080] The unit metal wire 124 and the second peripheral metal wire 125 can be made of the same material and located on the same horizontal plane.

[0081] According to an embodiment of the present invention, the discharge structure PS can discharge plasma-induced charges to the substrate by contacting the upper electrode 119 of the capacitor and forming a current path electrically connected through the first diode D1 in the second region R2 and the second diode D2 in the third region R3. In other words, the discharge structure PS according to an embodiment of the present invention can prevent the performance of the dielectric layer from being degraded due to plasma-induced damage (PID) caused by the plasma etching process forming the upper electrode 119, the unit metal line contact 122, and the unit metal line 124.

[0082] According to an embodiment of the present invention, the discharge structure PS is formed to contact the upper electrode 119 of the capacitor in the first region Rl. However, the present invention is not limited thereto. In another embodiment of the present invention, the discharge structure PS may be formed to contact the upper electrode of the storage capacitor in the peripheral circuit region.

[0083] According to an embodiment of the present invention, a single discharge structure PS exists. In other embodiments, multiple discharge structures PS may be present. The multiple discharge structures PS can discharge to the substrate 101 through a first discharge contact plug 106', a second discharge contact plug 108', and a third discharge contact plug 107'.

[0084] According to an embodiment of the present invention, the discharge structure PS includes a cylindrical first electrode 114'. However, the present invention is not limited thereto. In other embodiments, the first electrode 114' of the discharge structure PS can be formed in various structures depending on the structure of the lower electrode SN of the capacitor in the first region R1. For example, the first electrode 114' of the discharge structure PS can be formed as a column. In another embodiment, the first electrode 114' of the discharge structure PS can be formed as a column structure. In another embodiment of the present invention, the first electrode 114' of the discharge structure PS may further include a support member covering the outer wall of the first electrode 114'.

[0085] Figures 3A to 3D This is a cross-sectional view illustrating another embodiment of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 3A to 3D It is shown in the reference Figures 2A to 2G A cross-sectional view of a method for manufacturing a semiconductor device according to another embodiment following the described manufacturing process. Figure 3A As shown in and by Figures 2A to 2G The same reference numerals in the figures may indicate parts that have reference numerals. Figures 2A to 2G The parts described in these figures are marked with reference to the figures. Figures 2A to 2G The same process described is used to form it.

[0086] Reference Figure 3AReference numeral 201 can represent the first lower electrode. Reference numeral 202 can represent the second lower electrode. Reference numeral 203A can represent the dielectric material layer. Reference numeral 204 can represent the second mask pattern.

[0087] The second mask pattern 204 may include a material that is easily removable. The second mask pattern 204 may include a material having a different etching selectivity than the dielectric material layer 203A and the lower electrode SN. The second mask pattern 204 may include openings that selectively expose the dielectric material layer 203A formed over the lower electrode SN in the second region R2.

[0088] Reference Figure 3B The dielectric material layer 203A in the second region R2 exposed by the second mask pattern 204 can be etched (see reference). Figure 3A ) and the second lower electrode 202 (refer to) Figure 3A The second lower electrode 202 of the second region R2 can be partially removed. The second lower electrode 202 can be recessed and is indicated as 202'. The trench 205 can be defined by the first lower electrode 201 and the second lower electrode 202' of the second region R2. The etched dielectric material layer is indicated by reference numeral 203B.

[0089] Subsequently, the second mask pattern 204 can be removed.

[0090] Reference Figure 3C An upper electrode material layer 206A can be formed on a substrate 101 containing a dielectric material layer 203B.

[0091] Subsequently, a third mask pattern 207 can be formed on the upper electrode material layer 206A. The third mask pattern 207 can be patterned such that the third region R3 is open.

[0092] Reference Figure 3D This can be achieved by using a third mask pattern 207 (see reference). Figure 3C Etch the upper electrode material layer 206A and dielectric material layer 203B in the third region R3.

[0093] Therefore, the first region R1 may include a capacitor in which a lower electrode SN, a dielectric layer 203, and an upper electrode 206 are stacked sequentially. The second region R2 may include a discharge structure PS in which a first electrode 201', a second electrode 202', and a third electrode 206' are stacked. The first electrode 201' and the second electrode 202' may be formed simultaneously from the same material with the same structure as the first lower electrode 201 and the second lower electrode 202. The third electrode 206' and the upper electrode 206 may be formed simultaneously from the same material at the same horizontal plane. The third electrode 206' may contact the upper electrode 206 in the first region R1.

[0094] Figures 4A to 4D This is a cross-sectional view illustrating another method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 4A to 4D It shows that it contains having with Figure 1 The capacitors shown are semiconductor devices with different structures. Figures 4A to 4D As shown in and by Figure 1 The same reference numerals in the figures may indicate parts that have reference numerals. Figure 1 The parts described in the attached drawings are labeled.

[0095] Reference Figure 4A Reference numeral 301 can represent a cylindrical lower electrode made of a single material. Reference numeral 302A can represent a dielectric material layer. Reference numeral 303 can represent a second mask pattern.

[0096] The second mask pattern 303 may include a material that is easily removable. The second mask pattern 303 may include a material having a different etching selectivity than the dielectric material layer 302A and the lower electrode 301. The second mask pattern 303 may include openings that selectively expose the dielectric material layer 302A formed over the lower electrode 301 in the second region R2.

[0097] Reference Figure 4B The dielectric material layer 302A in the second region R2 exposed by the second mask pattern 303 can be etched (refer to...). Figure 4A Therefore, the exposed top surface of the lower electrode 301 in the second region R2 can be defined as opening 304. The etched dielectric material layer is designated as 302B.

[0098] Subsequently, the second mask pattern 303 can be removed.

[0099] Reference Figure 4C An upper electrode material layer 305A can be formed on a substrate 101 containing a dielectric material layer 302B.

[0100] Subsequently, a third mask pattern 306 can be formed on the upper electrode material layer 305A. The third mask pattern 306 can be patterned so that the third region R3 is open.

[0101] Reference Figure 4D Third mask pattern 306 (refer to) Figure 4C ) can be used to etch the upper electrode material layer 305A in the third region R3 (refer to) Figure 4C ) and dielectric material layer 302B (refer to) Figure 4C ).

[0102] Therefore, the first region R1 may include a capacitor in which a lower electrode 301, a dielectric layer 302, and an upper electrode 305 are stacked. The second region R2 may include a discharge structure PS in which a first electrode 301' and a second electrode 305' are stacked. The first electrode 301' and the first lower electrode 301 may be formed simultaneously from the same material at the same horizontal plane. The second electrode 305' may contact the upper electrode 305 in the first region R1.

[0103] Figures 5A to 5D This is a cross-sectional view illustrating another method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 5A to 5D It shows that it contains having with Figure 1 The capacitors shown are semiconductor devices with different structures. Figures 5A to 5D As shown in and by Figure 1 The same reference numerals in the figures may indicate parts that have reference numerals. Figure 1 The parts described in the attached drawings are labeled.

[0104] Reference Figure 5A Reference numeral 401 can represent a cylindrical lower electrode. Reference numeral 402A can represent a dielectric material layer. Reference numeral 403 can represent a second mask pattern.

[0105] The second mask pattern 403 may include a material that is easily removable. The second mask pattern 403 may include a material having a different etching selectivity than the dielectric material layer 402A and the lower electrode 401. The second mask pattern 403 may include an opening 404 that selectively exposes the dielectric material layer 402A formed over the lower electrode 401 in the second region R2.

[0106] Reference Figure 5B The dielectric material layer 402A in the second region R2 exposed by the second mask pattern 403 can be etched (refer to...). Figure 5A Therefore, the exposed top surface of the lower electrode 401 in the second region R2 can be defined as an opening 404. The etched dielectric material layer is designated as 402B. According to an embodiment of the invention, dielectric material layer 402A (see reference) Figure 5A The exposed portion of the dielectric material layer 402A is completely removed. However, the invention is not limited thereto. Figure 5A The lower electrode 401 may be partially removed, thereby exposing one or more sidewalls of the lower electrode 401 or the bottom surface of the lower electrode 401. All or part of the lower electrode 401 may be exposed, such that the lower electrode 401 can form a current path by being electrically connected to the subsequent upper electrode.

[0107] Subsequently, the second mask pattern 403 can be removed.

[0108] Reference Figure 5CThe upper electrode material layer 405A can be formed on the substrate 101 containing the dielectric material layer 402B.

[0109] Subsequently, a third mask pattern 406 can be formed on the upper electrode material layer 405A. The third mask pattern 406 can be patterned such that the third region R3 is open.

[0110] Reference Figure 5D Third mask pattern 406 (refer to) Figure 5C ) can be used to etch the upper electrode material layer 405A in the third region R3 (refer to) Figure 5C ) and dielectric material layer 402B (refer to) Figure 5C ).

[0111] Therefore, the first region R1 may include a capacitor in which a lower electrode 401, a dielectric layer 402, and an upper electrode 405 are stacked. The second region R2 may include a discharge structure PS in which a first electrode 401' and a second electrode 405' are stacked. The first electrode 401' and the first lower electrode 401 may be formed simultaneously from the same material, with the same structure, and at the same horizontal plane. The second electrode 405' and the upper electrode 405 may be formed simultaneously from the same material at the same horizontal plane. The second electrode 405' may contact the upper electrode 405 in the first region R1.

[0112] Figures 6A to 6D This is a cross-sectional view illustrating another method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 6A to 6D It shows a reference Figure 1 The capacitor described also includes a semiconductor device with a support disposed on the upper part of the capacitor and adapted to prevent the capacitor from collapsing. Figures 6A to 6D As shown in and by Figure 1 The same reference numerals in the figures can refer to components that have these reference numerals.

[0113] Reference Figure 6A Reference numeral 501 can indicate a support member. Reference numeral 502 can indicate a first lower electrode. Reference numeral 503 can indicate a second lower electrode. Reference numeral 504A can indicate a dielectric material layer. Reference numeral 505 can indicate a second mask pattern.

[0114] when Figure 2A When the sacrificial layer 111A is formed, a support member 501 may be formed on or inside the sacrificial layer 111A. The support member 501 may be formed of silicon nitride or silicon carbonitride (SiCN). According to an embodiment of the present invention, the support member 501 is formed on the first lower electrode 502. However, the present invention is not limited thereto. For example, the support member 501 may be composed of a single level, a double level, a triple level, or multiple levels.

[0115] The second mask pattern 505 may include a material that is easily removable. The second mask pattern 505 may include a material having a different etching selectivity than the dielectric material layer 504A and the lower electrode SN. The second mask pattern 505 may include openings that selectively expose the dielectric material layer 504A formed over the lower electrode SN in the second region R2.

[0116] Reference Figure 6B The dielectric material layer 504A in the second region R2 exposed by the second mask pattern 505 can be etched (refer to...). Figure 6A ) and the second lower electrode 503 (refer to) Figure 6A The trench 506 may be defined by the first lower electrode 502 in the second region R2. The etched dielectric material layer is designated as 504B.

[0117] Subsequently, the second mask pattern 505 can be removed.

[0118] Reference Figure 6C An upper electrode material layer 506A can be formed on a substrate 101 containing a dielectric material layer 504B.

[0119] Subsequently, a third mask pattern 508 can be formed on the upper electrode material layer 507A. The third mask pattern 508 can be patterned so that the third region R3 is open.

[0120] Reference Figure 6D Third mask pattern 508 (refer to) Figure 6C ) can be used to etch the upper electrode material layer 507A in the third region R3 (refer to) Figure 6C ) and dielectric material layer 504B (refer to) Figure 6C ).

[0121] Therefore, the first region R1 may include a capacitor in which a lower electrode SN, a dielectric layer 504, and an upper electrode 507 are stacked. The second region R2 may include a discharge structure PS in which a first electrode 502' and a second electrode 507' are stacked. The first electrode 502' and the first lower electrode 502 may be formed simultaneously from the same material, with the same structure, and at the same horizontal plane. The second electrode 507' and the upper electrode 507 may be formed simultaneously from the same material at the same horizontal plane. The second electrode 507' may contact the upper electrode 507 in the first region R1.

[0122] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A capacitor is disposed on a substrate and includes a lower electrode, a dielectric layer, and an upper electrode. as well as A discharge structure, spaced apart from the capacitor, is connected to the upper electrode of the capacitor and is adapted to discharge charge induced by the plasma process used to form the upper electrode of the capacitor to the substrate. The discharge structure includes: Second electrode; The first electrode is connected to the second electrode; Discharge contact plug, connected to the first electrode; and A diode, connected to the discharge contact plug and formed in the substrate, The discharge contact plug further includes: The first discharge contact plug is connected to the diode; and The second discharge contact plug has its two ends connected to the first discharge contact plug and the first electrode, respectively.

2. The semiconductor device as claimed in claim 1, wherein, The second electrode is connected to the upper electrode.

3. The semiconductor device as described in claim 1, Also includes: A contact plug, the two ends of which are connected to the substrate and the capacitor, respectively. The discharge contact plug and the contact plug are located on the same horizontal plane.

4. The semiconductor device as claimed in claim 1, wherein, The first electrode and the lower electrode have the same structure and are located on the same horizontal plane.

5. The semiconductor device as claimed in claim 1, wherein, The first electrode, the second electrode, and the second discharge contact plug are all made of metal.

6. The semiconductor device of claim 1, wherein, The first discharge contact plug comprises a semiconductor material.

7. The semiconductor device of claim 1, further comprising a metal wire connected to the capacitor over the capacitor.

8. The semiconductor device of claim 1, wherein, The first electrode has a cylindrical or cylindrical shape.

9. The semiconductor device of claim 1, further comprising a support member covering the outer wall of the first electrode.

10. A semiconductor device, comprising: The substrate includes a first region and a second region; A capacitor is disposed on a first region of the substrate and includes a lower electrode, a dielectric layer and an upper electrode; as well as A discharge structure, spaced apart from the capacitor, is connected to the upper electrode of the capacitor and adapted to discharge charge induced by the plasma process used to form the upper electrode of the capacitor to a second region of the substrate. The discharge structure includes: Second electrode; The first electrode is connected to the second electrode; Discharge contact plug, connected to the first electrode; and A diode, connected to the discharge contact plug and formed in the second region of the substrate, and The discharge contact plug further includes: The first discharge contact plug is connected to the diode; and The second discharge contact plug has its two ends connected to the first discharge contact plug and the first electrode, respectively.

11. The semiconductor device of claim 10, wherein, The second electrode is connected to the upper electrode.

12. The semiconductor device of claim 10, Also includes A contact plug, the two ends of which are respectively connected to a first region of the substrate and the capacitor. in, The discharge contact plug and the contact plug are located on the same horizontal plane.

13. The semiconductor device as claimed in claim 10, in, The diode is referred to as the first diode; The substrate also includes a third region, and The discharge structure further includes: A third discharge contact plug, the two ends of which are respectively connected to the second discharge contact plug and the third region of the substrate; and A second diode is connected to the third discharge contact plug and formed in the third region of the substrate.

14. A method for manufacturing a semiconductor device, the method comprising: A substrate comprising a first region and a second region is provided; A capacitor is formed, wherein the lower electrode, dielectric layer and upper electrode of the capacitor are stacked on a first region of the substrate; as well as A discharge structure is formed on a second region of the substrate, the discharge structure being spaced apart from the capacitor and connected to the upper electrode of the capacitor. The discharge structure includes: Second electrode; The first electrode is connected to the second electrode; Discharge contact plug, connected to the first electrode; and A diode, connected to the discharge contact plug and formed in the second region of the substrate, and The discharge contact plug further includes: The first discharge contact plug is connected to the diode; and The second discharge contact plug has its two ends connected to the first discharge contact plug and the first electrode, respectively.

15. The method of claim 14, wherein, Forming the discharge structure includes: The diode is formed in a second region of the substrate; The first discharge contact plug is formed on the diode; A second discharge contact plug is formed on top of the first discharge contact plug; The first electrode is formed on the second discharge contact plug; and A second electrode is formed on top of the first electrode.

16. The method of claim 15, in, The formation of the first electrode and the formation of the lower electrode of the capacitor are carried out simultaneously.

17. The method of claim 15, in, The formation of the second electrode is carried out simultaneously with the formation of the upper electrode of the capacitor.

18. The method of claim 15, wherein, The discharge contact plug comprises a stacked structure of semiconductor material and metal.

19. The method of claim 15, wherein, Each of the first electrode and the second electrode comprises a metal.

20. The method of claim 14, further comprising: Unit metal wires connected to the capacitor are formed on the capacitor.

21. The method of claim 15, in, The diode is referred to as the first diode; The substrate further includes a third region, and The formation of the discharge structure further includes forming a second diode connected to the discharge contact plug in a third region of the substrate.

Images