Semiconductor devices and methods for forming SRAM memory cell structures

Abstract

The present disclosure relates to semiconductor devices and methods for forming SRAM memory cell structures. An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port disposed in a first doped region and a first read port disposed in a second doped region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices and methods for forming SRAM memory cell structures. Background Technology

[0002] Semiconductor memories are electronic data storage devices implemented on semiconductor-based integrated circuits, and they offer access times much faster than other types of data storage technologies. For example, static random access memory (SRAM) is commonly used in integrated circuits. Embedded SRAM is popular in high-speed communications, image processing, and system-on-a-chip (SoC) applications. Bits can be read from or written to SRAM cells in nanoseconds, while the access times of rotating storage devices (such as hard disks) are in the millisecond range. Summary of the Invention

[0003] According to one embodiment of the present disclosure, an apparatus for storage is provided, comprising: a plurality of storage cells, including at least a first storage cell and a second storage cell; a first write port disposed in a first doped region of the first storage cell; and a first read port disposed in a second doped region of the first storage cell, wherein the first read port is separated from the first write port by a second write port of the second storage cell.

[0004] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a first memory cell, including: a first memory unit including an n-type transistor formed in a first n+ (NP) region and a p-type transistor formed in a first p+ (PP) region between the first NP region and the second NP region; a plurality of first write access transistors formed in the first NP region or the first PP region; and a plurality of first read access transistors formed in the second NP region.

[0005] According to another embodiment of the present disclosure, a method for forming an SRAM memory cell structure is provided, comprising: forming a first write access transistor for a first memory cell in a first region; forming a first read access transistor for the first memory cell in a second region; and forming a second write transistor for a second memory cell in a third region between the first region and the second region, wherein the first memory cell and the second memory cell are memory cells located in adjacent rows in the same column. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A A perspective view of an exemplary FinFET device according to some embodiments of the present disclosure is shown.

[0008] Figure 1B A cross-sectional side view of a FinFET transistor in a CMOS configuration according to some embodiments of the present disclosure is shown.

[0009] Figure 1C A top view of a standard (STD) cell array according to some embodiments of the present disclosure is shown.

[0010] Figure 1D This is a circuit diagram of a portion of a storage circuit according to some embodiments of the present disclosure.

[0011] Figures 2-4 and Figures 5A-5C This is a layout diagram of a portion of a storage circuit according to some embodiments of the present disclosure.

[0012] Figure 5D A perspective view of an exemplary transistor in an SRAM cell according to some embodiments of the present disclosure is shown.

[0013] Figure 6 This is a circuit diagram of a portion of a storage circuit according to some embodiments of the present disclosure.

[0014] Figures 7-9 , Figure 10A and Figure 10B This is a layout diagram of a portion of a storage circuit according to some embodiments of the present disclosure.

[0015] Figure 11 This is a circuit diagram of a portion of a storage circuit according to some embodiments of the present disclosure.

[0016] Figures 12-15 This is a layout diagram of a portion of a storage circuit according to some embodiments of the present disclosure.

[0017] Figure 16 This is a circuit diagram of a portion of a storage circuit according to some embodiments of the present disclosure.

[0018] Figure 17 This is a block diagram of an integrated circuit design system for designing semiconductor devices according to some embodiments of the present disclosure.

[0019] Figure 18 This is a flowchart of a method for generating layout designs according to some embodiments of the present disclosure. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] The terms used in this specification generally have their ordinary meaning in the art and in the specific context in which each term is used. The use of examples in this specification, including examples of any terms discussed herein, is merely illustrative and in no way intended to limit the scope and meaning of this disclosure or any exemplary terminology. Similarly, this disclosure is not limited to the various embodiments given in this specification.

[0022] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0023] In addition, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "above," "upper") to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0024] In this document, the term "coupling" may also be referred to as "electrical coupling," and the term "connection" may be referred to as "electrical connection." "Coupling" and "connection" can also be used to describe the cooperation or interaction of two or more elements.

[0025] This disclosure relates to, but is not otherwise limited to, FinFET devices. FinFET devices can be, for example, complementary metal-oxide-semiconductor (CMOS) devices, including P-type metal-oxide-semiconductor (PMOS) FinFET devices and N-type metal-oxide-semiconductor (NMOS) FinFET devices. The following disclosure will continue to illustrate various embodiments of this disclosure by way of one or more FinFET examples. However, it should be understood that, unless specifically stated otherwise, this application should not be limited to a particular type of device.

[0026] The use of FinFET devices is becoming increasingly popular in the semiconductor industry. (Reference) Figure 1A This diagram illustrates a perspective view of an exemplary FinFET device 50 according to some embodiments of the present disclosure. The FinFET device 50 is a non-planar multi-gate transistor constructed on a substrate (e.g., a bulk substrate). Thin silicon-containing "fin" structures (hereinafter referred to as "fins") form the body of the FinFET device 50. The fins extend along... Figure 1A The fin extends in the X direction as shown. The fin has a fin width W measured along the Y direction, which is orthogonal to the X direction. fin The gate 60 of the FinFET device 50 surrounds the fin, for example, surrounding the top surface and the opposite sidewall surface of the fin. Therefore, a portion of the gate 60 lies above the fin in the Z direction, which is orthogonal to both the X and Y directions.

[0027] L G This indicates the length (or width, depending on perspective) of the gate 60 as measured in the X direction. The gate 60 may include a gate electrode assembly 60A and a gate dielectric assembly 60B. The gate dielectric 60B has a thickness t as measured in the Y direction. ox A portion of the gate 60 lies on a dielectric isolation structure such as shallow trench isolation (STI). The source 70 and drain 80 of the FinFET device 50 are formed in an extension of the fin located opposite the gate 60. A portion of the fin surrounded by the gate 60 serves as the channel of the FinFET device 50. The effective channel length of the FinFET device 50 is determined by the size of the fin.

[0028] Figure 1BA cross-sectional side view of a FinFET transistor in a CMOS configuration according to some embodiments of the present disclosure is shown. The CMOS FinFET includes a substrate, such as a silicon substrate. An N-type well and a P-type well are formed in the substrate. A dielectric isolation structure, such as a shallow trench isolation (STI), is formed over the N-type well and the P-type well. A P-type FinFET 90 is formed over the N-type well, and an N-type FinFET 91 is formed over the P-type well. The P-type FinFET 90 includes a fin 95 projecting upward from the STI, and the N-type FinFET 91 includes a fin 96 projecting upward from the STI. Fin 95 includes a channel region of the P-type FinFET 90, and fin 96 includes a channel region of the N-type FinFET 91. In some embodiments, fin 95 is composed of silicon germanium, and fin 96 is composed of silicon. A gate dielectric is formed over fins 95-96 and over the STI, and a gate electrode is formed over the gate dielectric. In some embodiments, the gate dielectric comprises a high-k dielectric material, and the gate electrode comprises a metal gate electrode, such as aluminum and / or other refractory metals. In some other embodiments, the gate dielectric may comprise SiON, and the gate electrode may comprise polysilicon. Gate contacts are formed on the gate electrode to provide electrical connection to the gate.

[0029] FinFET devices offer several advantages over traditional metal-oxide-semiconductor field-effect transistor (MOSFET) devices (also known as planar transistor devices). These advantages can include better chip area efficiency, improved carrier mobility, and manufacturing processes compatible with those used in planar devices. Therefore, it may be desirable to use FinFET devices in the design of integrated circuit (IC) chips for use in a portion or the entire IC chip.

[0030] Figure 1C Some embodiments of the present disclosure are shown having multiple Figure 1B The diagram shows a top view of a standard (STD) cell array 100c of FinFET devices (e.g., P-type FinFET 90 and N-type FinFET 91). The standard cell array 100c may include logic circuitry or logic devices, and is therefore also referred to as a logic cell array or logic circuit array. In various embodiments, the logic circuitry or devices may include components such as inverters, NAND gates, NOR gates, flip-flops, or combinations thereof.

[0031] In at least one example, the term "oxide-defined (OD) region" is the active region of a transistor, i.e., the region forming the source, drain, and channel below the gate of the transistor. In some examples, the oxide-defined region is between insulating regions. In some embodiments, the insulating region is a shallow trench isolation (STI), a field oxide (FOX) region, or other suitable electrically insulating structure. In some embodiments, the insulating region is referred to as a passive region or an isolation region. Figure 1C As shown, the standard cell array 100c includes N-type FinFET transistors in n-plus (NP) regions NP1, NP2, and NP3 associated with corresponding P-type wells, and P-type FinFET transistors in p-plus (PP) regions PP1 and PP2 associated with corresponding N-type wells. The standard cell array 100c also includes elongated fins, for example, fins in oxide-defined (OD) regions OD2, OD3, OD8, ​​and OD9, which are portions of the P-type FinFET transistors, and fins in OD regions OD1, OD4-7, and OD10, which are portions of the N-type FinFET transistors. The P-type FinFET fins are located above the N-type wells in the PP regions PP1 and PP2, while the N-type FinFET fins are located above the P-type wells in the NP regions NP1, NP2, and NP3. Figure 1C As shown, in order to meet the basic standard unit rules, each PP or NP area includes at least two OD areas. In addition, the two OD areas are sandwiched in the middle by adjacent power / ground ports (VDD or VSS) VDD1, VDD2, VSS1-VSS4.

[0032] As an example, the array 100c shown in this article includes cells arranged in rows and columns. Figure 1C Only an example of array 100c is shown, and other embodiments may have different numbers of cells and / or may be arranged differently.

[0033] like Figure 1C As shown, the fin lines in the OD regions OD1-OD10 are respectively in the X direction ( Figure 1A The fins extend through a corresponding column of cells in the X direction. Therefore, each fin can be considered "continuous." (See reference above.) Figure 1A The fins discussed each include a channel region and a source / drain region located adjacent to (e.g., on the opposite side of) the channel region. The FinFET transistors of the STD cell array 100c each include those formed on the reference above. Figure 1AThe description describes the corresponding gate electrode in a polysilicon region (e.g., polysilicon regions Poly1-Poly7) surrounding a corresponding fin. In some embodiments, the P-type FinFET (PMOSFET) fin is composed of silicon-germanium (SiGe) material (for enhancing strain effects), but the N-type FinFET (NMOSFET) fin is composed of a semiconductor material comprising non-germanium, such as silicon (Si). Thus, in some embodiments, the PMOSFET has a SiGe channel, and the NMOSFET has a Si channel. In some embodiments, the channel fin width of the NMOSFET is narrower than that of the PMOSFET. In some embodiments, the source / drain region of the NMOSFET comprises an epitaxial material selected from the group consisting of SiP, SiC, SiPC, SiAs, Si, or combinations thereof. It should be understood that the above materials or configurations are merely examples and are not intended to be limiting. Other possible materials or configurations are also within the scope of this disclosure. In some embodiments, the source / drain region of the PMOSFET has a wider width than the channel region. As described above, in some embodiments, the fins of the cell array 100c may be continuous and extend across two or more adjacent cells in the X direction.

[0034] Figure 1D This is a circuit diagram of a portion of a storage circuit 100 according to some embodiments. Figure 1D The storage circuit 100 can be based on Figure 1C Placement and connection in the layout design of the standard cell array 100c Figure 1A and / or Figure 1B The FinFET transistors shown are used for implementation. The storage circuit 100 includes multiple storage cells arranged in columns and one or more pairs of adjacent rows. A pair of adjacent rows refers to two rows of storage cells without any intermediate row of storage cells between them. For example, Figure 1D The storage circuit 100 is depicted including storage cells 110A and 110B belonging to column COL. Furthermore, storage cell 110A belongs to a first row ROW[0], and storage cell 110B belongs to a second row ROW[1]. In some embodiments, the storage circuit 100 includes two or more columns of storage cells. In some embodiments, the storage circuit 100 includes two or more rows of storage cells. Figure 1D Other storage units in rows ROW[0] and ROW[1] that correspond to columns other than column COL are not shown.

[0035] Memory cells 110A and 110B are two-port eight-transistor (2P-8T) SRAM cells. The two-port memory cell includes a write port (e.g., write port WPA or WPB) and a read port (e.g., read port 114A or 114B). The read port includes a read data line configured to carry data read from the memory cell through a read transfer gate. The read transfer gate is controlled by a read word line signal on a read word line. The write port includes a write data line configured to carry data to be written to the memory cell through one or more write transfer gates. The one or more write transfer gates are controlled by a write word line signal on a write word line.

[0036] For example, memory cell 110A, shown as a representative memory cell, includes a 6T portion 112A and a read port 114A. The 6T portion 112A includes two P-type transistors P0 and P1 forming the memory cell, two N-type transistors N0 and N1, and two additional N-type transistors N2 and N3 as part of a write port WPA. The read port 114A includes two additional N-type transistors N4 and N5. The write port WPA is further associated with a write word line WWL[0] and write bit lines WBL and WBLB. The read port 114A is further associated with a read word line RWL[0] and a read bit line RBL. Memory cell 110A also includes two power nodes VDD and VSS. Power node VDD is configured to have a first power supply voltage level corresponding to a logic high value. Power node VSS is configured to have a second power supply voltage level corresponding to a logic low value.

[0037] Transistors P0, P1, N0, and N1 form a cross-coupled inverter pair between power nodes VDD and VSS. Transistors P0 and N0 form the first inverter, while transistors P1 and N1 form the second inverter. The drains of transistors P0 and N0 are coupled together to form the data node MT. The drains of transistors P1 and N1 are coupled together to form the data node MB. The gates of transistors P0 and N0 are coupled together and then coupled to the drains of transistors P1 and N1. The gates of transistors P1 and N1 are coupled together and then coupled to the drains of transistors P0 and N0.

[0038] Transistor N2 is coupled to bit line WBL at access node AN1 and to data node MT. Transistor N3 is coupled to bit line WBLB at access node AN2 and to data node MB. Write word line WWL[0] is coupled to the gates of transistors N2 and N3. In some embodiments, bit lines WBL, WBLB, and RBL are also shared by other memory cells in column COL (e.g., memory cell 110B). Transistors N2 and N3 serve as transmission gates controlled by write word line WWL[0]. In some embodiments, write word line WWL[0] is also coupled to the gates of transistors corresponding to transistors N2 and N3 in other memory cells in row ROW[0].

[0039] In some embodiments, the storage circuit 100 includes multiple write data lines each coupled to an access node corresponding to an access node AN1 in a corresponding column of the storage cell column, and multiple write data lines each coupled to an access node corresponding to an access node AN2 in a corresponding column of the storage cell column.

[0040] The write word line WWL[0] is also called the write control line because the signal on the write word line WWL[0] controls transistors N2 and N3 to write the data on the write bit lines WBL and WBLB to the corresponding nodes MT and MB.

[0041] When memory cell 110A is accessed for a write operation, the data to be written to memory cell 110A is applied to write bit lines WBL and WBLB. Write word line WWL[0] is then activated, for example, set to a logic high value to turn on transistors N2 and N3. As a result, the data on write bit lines WBL and WBLB is transferred to and stored in the corresponding data nodes MT and MB.

[0042] Transistor N4 has a source coupled to power node VSS, a gate coupled to data node MB, and a drain coupled to transistor N5. Transistor N4 is configured to be turned off when its gate has a voltage level corresponding to a logic low value and turned on when its gate has a voltage level corresponding to a logic high value. Transistor N4 acts as a traction device, configured to selectively couple intermediate node IN1 to power node VSS in response to the voltage level at data node MB.

[0043] Transistor N5 is coupled to the read bit line RBL at access node AN3 and to the drain of transistor N4. The read word line RWL[0] is coupled to the gate of transistor N5. Transistor N5 serves as a read transmission gate controlled by the read word line RWL[0]. In some embodiments, the read word line RWL[0] is also coupled to the gate of the transistor corresponding to transistor N5 in another memory cell in row ROW[0].

[0044] When memory cell 110A is accessed for a read operation, the read bit line is precharged to a voltage level corresponding to a logic high value. Then, the read word line RWL[0] is activated, for example, set to a logic high value to turn on transistor N5, and the drain of transistor N4 and the read bit line RBL are electrically coupled together at intermediate node IN1. If data node MB has a voltage level corresponding to a logic low value, transistor N4 is turned off and the read bit line RBL remains at a logic high level. If data node MB has a voltage level corresponding to a logic high value, transistor N4 is turned on and pulls the read bit line RBL towards the voltage level at power node VSS. Therefore, transistor N5 (working in conjunction with transistor N4) is configured to selectively change the voltage level at access node AN3 according to the voltage level at data node MB if transistor N5 is turned on.

[0045] For example, memory cell 110B, shown as a representative memory cell, also includes a 6T portion 112B and a read port 114B. The 6T portion 112B includes two P-type transistors P10 and P11 forming the memory cell, two N-type transistors N10 and N11, and two additional N-type transistors N12 and N13 as part of the write port WPB. The read port 114B includes two additional N-type transistors N14 and N15. The write port WPB is further associated with the write word line WWL[1] and the write bit lines WBL and WBLB. The read port 114B is further associated with the read word line RWL[1] and the read bit line RBL. Memory cell 110B also includes two power nodes VDD and VSS. Power node VDD is configured to have a first power supply voltage level corresponding to a logic high value. Power node VSS is configured to have a second power supply voltage level corresponding to a logic low value. The transistors in memory cell 110B have a similar configuration to those in memory cell 110A, therefore their detailed description is omitted.

[0046] Figure 2 This is a layout diagram 200 of a portion of a memory circuit according to some embodiments, illustrating the lower layers of the layout (e.g., oxide definition regions, gate layers, and interconnect layers). Figure 2 The storage units in the middle are based on Figure 1D The storage units 110A and 110B are included and can be used to illustrate... Figure 1D The layout design of other storage cells in the storage circuit 100.

[0047] Layout 200 includes a p-plus (PP) region PP1 associated with N-well region 202, and NP (NP) regions NP1 and NP2 associated with two P-substrate or P-well regions (hereinafter referred to as "P-well regions") 204 and 206, respectively. Layout 200 also includes an oxide definition (OD) region 211 indicating an N-type implanted region buried in P-well region 204, OD regions 213 and 215 indicating a P-type implanted region buried in N-well region 202, and oxide definition (OD) regions 217 and 219 indicating an N-type implanted region buried in P-well region 206. In some embodiments, OD regions 211-219 refer to active regions.

[0048] Layout 200 also includes polysilicon regions 221, 223, 225, 227, 231, 233, 235, 237, 241, 243, and 245, and interconnect regions 251, 253, 255, 257, 259, 261, 263, 265, 267, 269, and 271, 273, 275, 277, and 279. In some embodiments, interconnect regions 251-279 correspond to the conductive structure of a common layer. Those skilled in the art will understand that one or more of the layout patterns described herein can be used to fabricate a set of masks, which can then be used to manufacture memory cells in an integrated circuit. Layout 200 serves as the basis for modifications to form other layout structures such as those described herein.

[0049] and Figure 1D The NMOS transistors N0, N1, N2 and N3 of the memory cell 110A are defined in a first N-type injection region (e.g., region NP1) including the OD region 211.

[0050] In this embodiment, interconnect structure 253, polysilicon region 223, OD region 211, and interconnect structure 255 define NMOS transistor N0 (e.g., Figure 1D (As shown). Polysilicon region 223 corresponds to the gate of NMOS transistor N0, interconnect structure 255 corresponds to the node connected to the power node VSS, and interconnect structure 253 corresponds to the data node MT in corresponding cell 110A. The gates of NMOS transistor N0 and PMOS transistor P0 are directly connected through polysilicon region 223. Interconnect structure 255, polysilicon region 225, OD region 211, and interconnect structure 257 define NMOS transistor N1 (as shown). Figure 1D (As shown). Polysilicon region 225 corresponds to the gate of NMOS transistor N1, and interconnect structure 257 corresponds to data node MB in corresponding cell 110A. The gates of NMOS transistor N1 and PMOS transistor P1 are directly connected through polysilicon region 225.

[0051] Interconnect structure 251, polysilicon region 221, OD region 211, and interconnect structure 253 define NMOS transistor N2 (e.g., Figure 1D (As shown). Polysilicon region 221 corresponds to the gate of NMOS transistor N2, and interconnect structure 251 corresponds to the node connected to the write bit line WBL. Interconnect structure 257, polysilicon region 227, OD region 211, and interconnect structure 259 define NMOS transistor N3 (as shown). Figure 1D (As shown). Polysilicon region 227 corresponds to the gate of NMOS transistor N3, and interconnect structure 259 corresponds to the node connected to the write bit line WBLB.

[0052] and Figure 1D The PMOS transistors P0, P1, P10 and P11 of memory cells 110A and 110B are defined in a P-type injection region (e.g., region PP1) including OD regions 213 and 215.

[0053] In this embodiment, interconnect structure 253, polysilicon region 223, OD region 213, and interconnect structure 265 define PMOS transistor P0 (e.g., Figure 1D (As shown). Polysilicon region 223 corresponds to the gate of PMOS transistor P0, and interconnect structure 265 corresponds to the node connected to the power supply node VDD. Interconnect structure 257, polysilicon region 225, OD region 213, and interconnect structure 265 define PMOS transistor P1 (as shown). Figure 1D (As shown). Polysilicon region 225 corresponds to the gate of PMOS transistor P1.

[0054] Interconnect structure 263, polysilicon region 233, OD region 215, and interconnect structure 265 define PMOS transistor P10 (e.g., Figure 1D (As shown). Polysilicon region 233 corresponds to the gate of PMOS transistor P10, and interconnect structure 263 corresponds to data node MT2 in corresponding cell 110B. Interconnect structure 267, polysilicon region 235, OD region 215, and interconnect structure 265 define PMOS transistor P11 (as shown). Figure 1D (As shown). The polysilicon region 235 corresponds to the gate of the PMOS transistor P11, and the interconnect structure 267 corresponds to the data node MB2 in the corresponding cell 110B.

[0055] and Figure 1D The NMOS transistors N10, N11, N12 and N13 of the memory cell 110B are defined in a second N-type injection region (e.g., region NP2) including OD regions 217 and 219.

[0056] In this embodiment, interconnect structure 263, polysilicon region 233, OD region 217, and interconnect structure 275 define NMOS transistor N10 (e.g., Figure 1D (As shown). Polysilicon region 233 corresponds to the gate of NMOS transistor N10. (As shown) Figure 2 As shown, the gates of NMOS transistors N10 and N14 and PMOS transistor P10 are directly connected through polysilicon region 233. Interconnect structure 275 corresponds to the node connected to power node VSS.

[0057] Interconnect structure 275, polysilicon region 235, OD region 217, and interconnect structure 267 define NMOS transistor N11 (e.g., Figure 1D (As shown). Polysilicon region 235 corresponds to the gate of NMOS transistor N11. (As shown) Figure 2 As shown, the gates of NMOS transistor N11 and PMOS transistor P11 are directly connected through polysilicon region 235.

[0058] Interconnect structure 261, polysilicon region 231, OD region 217, and interconnect structure 263 define NMOS transistor N12 (e.g., Figure 1D (As shown). The polysilicon region 231 corresponds to the gate of the NMOS transistor N12, and the interconnect structure 261 corresponds to the node connected to the write bit line WBL.

[0059] Interconnect structure 267, polysilicon region 237, OD region 217, and interconnect structure 269 define NMOS transistor N13 (e.g., Figure 1D (As shown). Polysilicon region 237 corresponds to the gate of NMOS transistor N13, and interconnect structure 269 corresponds to the node connected to the write bit line WBLB.

[0060] In addition, with Figure 1D The NMOS transistors N4, N5, N14 and N15 in the read ports of memory cells 110A and 110B are also defined in a second N-type injection region (e.g., region NP2) including OD regions 217 and 219.

[0061] Interconnect structure 275, polysilicon region 243, OD region 219, and interconnect structure 277 define NMOS transistor N4 (e.g., Figure 1D (As shown). Polysilicon region 243 corresponds to the gate of NMOS transistor N4. Interconnect structure 277, polysilicon region 245, OD region 219, and interconnect structure 279 define NMOS transistor N5 (as shown). Figure 1D(As shown). Polysilicon region 245 corresponds to the gate of NMOS transistor N5, and interconnect structure 279 corresponds to the node connected to the read bit line RBL. NMOS transistors N4 and N5 are connected through interconnect structure 277.

[0062] Interconnect structure 273, polysilicon region 233, OD region 219, and interconnect structure 275 define NMOS transistor N14 (e.g. Figure 1D (As shown). Polysilicon region 233 corresponds to the gate of NMOS transistor N14. Interconnect structure 271, polysilicon region 241, OD region 219, and interconnect structure 273 define NMOS transistor N15 (as shown). Figure 1D (As shown). Polysilicon region 241 corresponds to the gate of NMOS transistor N15. Interconnect structure 271 corresponds to the node connected to the read bit line RBL. NMOS transistors N14 and N15 are connected via interconnect structure 273.

[0063] Figure 3 This is a layout diagram 300 of a portion of a storage circuit according to some embodiments, illustrating the lower and middle layers of the layout (e.g., contacts and a first metal layer M0). Figure 3 The storage units in the middle are based on Figure 1D The storage units 110A and 110B in the middle, and based on Figure 2 The lower layer is shown in the layout diagram 200.

[0064] like Figure 3 As shown, the first metal layer M0 may include power rails 312, 314 and 316, and metal line features 322-354.

[0065] The first power rail 312 is located within the first N-type transistor region NP1 and is configured to couple the SRAM cell to a first DC power supply, such as power node VSS. The second power rail 314 is located within the P-type transistor region PP1 and is parallel to the first power rail 312. Furthermore, according to... Figure 3 In the top view shown, the second power rail 314 is sandwiched between OD regions 213 and 215 in the P-type transistor region PP1. For example, the second power rail 314 is configured to couple an SRAM cell to a second DC power supply, such as power node VDD. The third power rail 316 is located within the second N-type transistor region NP2 and is parallel to the first power rail 312 and the second power rail 314. The third power rail 316 is also configured to couple an SRAM cell to a first DC power supply, such as power node VSS. Furthermore, according to... Figure 3 The top view shown shows that the third power rail 316 is sandwiched between the OD regions 217 and 219 in the second N-type transistor region NP2.

[0066] like Figure 3 As shown, contacts extend downwards from power rail 312 to interconnect structure 255 in the local interconnect layer to couple the respective source / drain regions of transistors N0 and N1 to power node VSS. Contacts extend downwards from power rail 314 to interconnect structure 265 in the local interconnect layer to couple the respective source / drain regions of transistors P0, P1, P10, and P11 to power node VDD. Contacts extend downwards from power rail 316 to interconnect structure 275 in the local interconnect layer to couple the respective source / drain regions of transistors N4, N14, N10, and N11 to power node VSS.

[0067] Metal line feature 322 corresponds to a node connected to the write word line WWL[0] of memory cell 110A. Contacts extend downward from metal line feature 322 to couple the gate regions of transistors N2 and N3 together.

[0068] Metal line features 324 and 326 correspond to nodes that are connected to write bit lines WBL and WBLB, respectively. Contacts extend downward from metal line features 324 and 326 to couple the corresponding source / drain regions of transistors N2 and N3 to metal line features 324 and 326, respectively.

[0069] Metal line feature 328 corresponds to data node MB. Contacts extend downward from metal line feature 328 to couple the gate region of transistor P0 and the interconnect structure 257 (the corresponding source / drain regions of transistor P1) together.

[0070] Metal line feature 332 corresponds to data node MT. Contacts extend downward from metal line feature 332 to couple the gate region of transistor P1 and interconnect structure 253 (the corresponding source / drain regions of transistor P0) together.

[0071] Metal line feature 334 corresponds to data node MT2. Contacts extend downward from metal line feature 334 to couple the gate region of transistor P11 and the interconnect structure 263 (the corresponding source / drain regions of transistor P10) together.

[0072] Metal line feature 336 corresponds to data node MB2. Contacts extend downward from metal line feature 336 to couple the gate region of transistor P10 and the interconnect structure 267 (the corresponding source / drain regions of transistor P11) together.

[0073] Metal line features 338 and 342 correspond to nodes that are connected to write bit lines WBL and WBLB, respectively. Contacts extend downward from metal line features 338 and 342 to couple the corresponding source / drain regions of transistors N12 and N13 to metal line features 338 and 342, respectively.

[0074] Metal line feature 344 corresponds to a node connected to the write word line WWL[1] of memory cell 110B. Contacts extend downward from metal line feature 344 to couple the gate regions of transistors N12 and N13 together.

[0075] Metal line feature 346 corresponds to a node connected to data node MB. Contacts extend downward from metal line feature 346 to couple the gate region of transistor N4 to metal line feature 346.

[0076] Metal line feature 348 corresponds to read bit line RBL. Contacts extend downward from metal line feature 348 to couple the corresponding source / drain regions of transistors N5 and N15 together.

[0077] Metal line features 352 and 354 correspond to nodes that are connected to the read word lines RWL[1] and RWL[0] of memory cells 110B and 110A, respectively. Contacts extend downward from metal line features 352 and 354 to couple the gate regions of transistors N15 and N5 to metal line features 352 and 354, respectively.

[0078] Figure 4 This is a layout diagram 400 of a portion of a memory circuit according to some embodiments, illustrating the middle and upper layers of the layout (e.g., a second metal layer M1, and a via layer VIA0 between metal layers M0 and M1). Figure 4 The storage units in the middle are based on Figure 1D The storage units 110A and 110B in the middle, and based on Figure 2 and Figure 3 The layout diagrams 200 and 300 show the layers.

[0079] like Figure 4 As shown, the second metal layer M1 may include metal line features 412-426 that are perpendicular to the metal line features in the first metal layer M0.

[0080] Metal line feature 412 corresponds to the write bit line WBL and is connected to metal line features 324 and 338 in the first metal layer M0 through corresponding via structures.

[0081] Metal line feature 414 corresponds to the write word line WWL[1] and is connected to metal line feature 344 in the first metal layer M0 through a corresponding via structure.

[0082] The metal line feature 416 corresponding to the read word line RWL[1] is connected to the metal line feature 352 in the first metal layer M0 through a corresponding via structure.

[0083] The metal line feature 418 corresponding to the data node MB is connected to the metal line features 328 and 346 in the first metal layer M0 through the corresponding via structure.

[0084] The metal line feature 422 corresponding to the read word line RWL[0] is connected to the metal line feature 354 in the first metal layer M0 through a corresponding via structure.

[0085] The metal line feature 424 corresponding to the write word line WWL[0] is connected to the metal line feature 322 in the first metal layer M0 through a corresponding via structure.

[0086] The metal line feature 426 corresponding to the write bit line WBLB is connected to the metal line features 326 and 342 in the first metal layer M0 through a corresponding via structure.

[0087] Figure 5A This is a layout diagram 500a of a portion of a storage circuit according to some embodiments, illustrating the... Figures 2-4 The layout shown Figure 1D The arrangement of transistors N0-N3, P0, and P1 in the 6T section 112A of the memory cell 110A and transistors N4 and N5 in the read port 114A. For example... Figure 5A As shown, transistors N2 and N3 in the write port of section 6T 112A are formed in a first doped region (e.g., NP region NP1). Transistors N4 and N5 in the read port 114A are formed in a second doped region (e.g., NP region NP2). The first and second doped regions are separated by a third doped region (e.g., p+ region PP1).

[0088] Furthermore, the 6T portion 112A overlaps with the doped regions NP1 and PP1. In the 6T portion 112A, the n-type transistors N0 and N1 within the storage unit 510A of the storage cell 110A are formed in the NP region NP1, and the p-type transistors P0 and P1 of the storage unit 510A are formed in the p-add region PP1.

[0089] Figure 5B This is a layout diagram 500b of a portion of a storage circuit according to some embodiments, illustrating the... Figures 2-4 The layout shown Figure 1D The arrangement of transistors within memory cells 110A and 110B. For example... Figure 5BAs shown, read port 114A is separated from write port and 6T portion 112B of memory cell 110B via 6T portion 112B (including write port), where memory cell 110B is located in the same row and column as memory cell 110A. In other words, the first read port (e.g., read port 114A) associated with memory cell 110A is separated from the first write port (e.g., transistors N2 and N3) of 6T portion 112A via a second write port (e.g., transistors N12 and N13) in 6T portion 112B of memory cell 110B.

[0090] The 6T portion 112B overlaps with doped regions NP2 and PP1. In the 6T portion 112B, n-type transistors N10 and N11 of storage unit 510B are formed in NP region NP2, and p-type transistors P10 and P11 of storage unit 510B are formed in p-type region PP1. As shown in Figure 5B, transistors N12 and N13 are formed in the write port of the 6T portion 112B and in the second doped region (e.g., NP region NP2). Transistors N14 and N15, forming the read port 114B, are also formed in the second doped region (e.g., NP region NP2).

[0091] As described above, the read access transistors N5 and N15 in different memory cells are connected by one or more conductive features (e.g., metal line feature 348) formed in the conductive metal layer M0 on transistors N5 and N15.

[0092] Write access transistors N2 and N12 in different memory cells are connected via one or more conductive features (e.g., metal line features 324, 338, 412) formed in one or more conductive metal layers M0 and M1 on top of write access transistors N2 and N12. Write access transistors N3 and N13 in different memory cells are also connected via one or more conductive features (e.g., metal line features 326, 342, 426) formed in one or more conductive metal layers M0 and M1 on top of write access transistors N3 and N13.

[0093] Figure 5C This is a layout diagram 500c of a portion of a storage circuit according to some embodiments, illustrating the... Figures 2-4 The layout shown depicts the arrangement of the 6T portion of the memory cells corresponding to the two rows ROW[0], ROW[1] and the two columns COL[0], COL[1], and the read ports. For example... Figure 5C As shown, in some embodiments, the read ports of memory cells in adjacent columns can be arranged in the same doped region in this layout.

[0094] For example, in addition to the 6T portions 112A, 112B and read ports 114A, 114B of storage cells 110A and 110B corresponding to rows ROW[0] and ROW[1] in column COL[0], layout diagram 500c also includes 6T portions 112C, 112D and read ports 114C, 114D. 6T portions 112C and read ports 114C are part of the storage cells corresponding to rows ROW[0] and columns COL[1]. 6T portions 112D and read ports 114D are part of the storage cells corresponding to rows ROW[1] and columns COL[1]. 6T portions 112C overlap with PP region PP2 and NP region NP3, and 6T portions 112D overlap with NP region NP2 and PP region PP2. The read ports 114A, 114B, 114C and 114D of the four storage cells are formed in the same NP region NP2 in this layout.

[0095] like Figures 5A-5C As shown, by correctly placing the transistors of the 8T2P SRAM cell and separating the read and write ports of the memory cell, the standard cell rules for wiring track allocation can be met. Therefore, SRAM cells can be implemented using a standard cell-based design. In some embodiments, when the array size is small, a smaller circuit area for the SRAM cell can be achieved by using a standard cell-based design.

[0096] Figure 5D A perspective view of an exemplary transistor (e.g., transistor N2) in an SRAM cell according to some embodiments is shown. Transistor N2 includes a pair of semiconductor fins 511a, 511b in an OD region 211, the pair of fins extending parallel to each other over a semiconductor substrate 520. The fins 511a, 511b extend upward from the semiconductor substrate 520 through openings in an isolation region 522 (e.g., silicon dioxide or a low-k dielectric layer (e.g., a buried oxide (BOX) layer)). A conductive gate electrode (e.g., 221) spans both semiconductor fins 511a, 511b, and a gate dielectric 524 (e.g., SiO2 or a high-k dielectric) separates the gate electrode from the semiconductor fins 511a, 511b. A contact 526 couples the gate electrode (e.g., 221) to a metal line feature 322 in a first metal layer M0. Local interconnects (e.g., interconnect region 251) short-circuit the first set of source / drain regions in fins 511a, 511b located on the gate electrode side; and the second interconnect ( Figure 5D(Not shown) The second set of source / drain regions in fins 511a and 511b located on the other side of the gate electrode are short-circuited to each other, so that fins 511a and 511b function as a single finFET instead of two finFETs. Contact 528 connects metal line feature 324 in the first metal layer M0 to a local interconnect layer (e.g., interconnect region 251). In some embodiments, one or more vias (see...) Figure 4 ;but Figure 5D (Not shown) Connect the metal line features 322 and 324 in the first metal layer M0 to the corresponding metal line features 424 and 412 in the second metal layer M1.

[0097] Figure 6 This is a circuit diagram of a portion of a storage circuit 600 according to some other embodiments. Figure 1D Compared to storage circuit 100, the access transistors for the write ports in storage circuit 600 are PMOS transistors (e.g., transistors P2, P3, P12, and P13), instead of the previously used ones. Figure 1D The NMOS transistors (e.g., transistors N2, N3, N12, and N13) shown in the storage circuit 100 are specifically similar to those in the memory circuit. Figure 1D The storage circuit 600 also includes storage cells arranged in columns and one or more pairs of adjacent rows. Figure 6 In the illustrated embodiment, memory cell 610A, shown as a representative memory cell, includes a 6T portion 612A and a read port 614A. The 6T portion 612A includes two P-type transistors P0 and P1 and two N-type transistors N0 and N1 forming the memory cell, and two additional P-type transistors P2 and P3 as part of the write port. The read port 614A includes two additional N-type transistors N4 and N5. Similarly, memory cell 610B, shown as another representative memory cell, includes a 6T portion 612B and a read port 614B. The 6T portion 612B includes two P-type transistors P10 and P11 and two N-type transistors N10 and N11 forming the memory cell, and two additional P-type transistors P12 and P13 as part of the write port. The read port 614B of memory cell 610B includes two additional N-type transistors N14 and N15.

[0098] and Figure 1D Compared to the memory circuit 100, N-type transistors N2 and N3 are replaced by P-type transistors P2 and P3. Furthermore, N-type transistors N12 and N13 are further replaced by P-type transistors P12 and P13. In other words, the access transistors at the write port are PMOS transistors, instead of the previously used ones. Figure 1D The NMOS transistors shown are (e.g., transistors N2, N3, N12, and N13).

[0099] Figure 7 This is a layout diagram 700 of a portion of a memory circuit according to some embodiments, illustrating the lower layers of the layout (e.g., oxide definition regions, gate layers, and interconnect layers). Figure 7 The storage units in the middle are based on Figure 6 The storage units 610A and 610B in the diagram are also available for use in the illustration. Figure 6 The layout design of other memory cells in the memory circuit 600. Figure 7 In and Figure 2 - Components that are identical or similar to those shown in Figure 5 are given the same reference numerals, and their detailed descriptions are omitted.

[0100] and Figure 6 The NMOS transistors N0 and N1 of the memory cell 610A are defined in a first N-type injection region (e.g., region NP1) including the OD region 211. Figure 6 The transistors corresponding to NMOS transistors N10 and N11 in memory cell 610B are defined in a second N-type injection region (e.g., region NP2) including OD regions 217 and 219. Additionally, with Figure 6 The NMOS transistors N4, N5, N14, and N15 in the read ports of memory cells 610A and 610B are also defined in a second N-type injection region (e.g., region NP2) including OD regions 217 and 219. The configuration of NMOS transistors N0, N1, N10, N11, N4, N5, N14, and N15 in memory cells 610A and 610B is similar to... Figure 1D The storage units 110A and 110B have similar configurations, so their detailed descriptions are omitted.

[0101] and Figure 6 The PMOS transistors P0, P1, P2, P3, P10, P11, P12, and P13 of memory cells 610A and 610B are defined in a P-type injection region (e.g., region PP1) including OD regions 213 and 215. The configuration of PMOS transistors P0, P1, P10, and P11 of memory cells 610A and 610B is similar to... Figure 1D The storage units 110A and 110B have similar configurations, so their detailed descriptions are omitted.

[0102] Layout 700 also includes polysilicon regions 721-727 and interconnect structures 731, 733. Interconnect structure 731, polysilicon region 721, OD region 213, and interconnect structure 253 define PMOS transistor P2 (e.g., Figure 6(As shown). Polysilicon region 721 corresponds to the gate of PMOS transistor P2, and interconnect structure 731 corresponds to the node connected to the write bit line WBL and connects PMOS transistors P2 and PMOS transistor P12. Interconnect structure 253 connects PMOS transistors P0 and PMOS transistor P2.

[0103] Interconnect structure 257, polysilicon region 723, OD region 213, and interconnect structure 733 define PMOS transistor P3 (e.g., Figure 6 (As shown). Polysilicon region 723 corresponds to the gate of PMOS transistor P3, and interconnect structure 733 corresponds to the node connected to the write bit line WBLB and connects PMOS transistor P3 and PMOS transistor P13. Interconnect structure 257 connects PMOS transistor P1 and PMOS transistor P3.

[0104] Interconnect structure 731, polysilicon region 725, OD region 215, and interconnect structure 263 define PMOS transistor P12 (e.g., Figure 6 (As shown). Polysilicon region 725 corresponds to the gate of PMOS transistor P12. Interconnect structure 263 connects PMOS transistor P10 and PMOS transistor P12.

[0105] Interconnect structure 267, polysilicon region 727, OD region 215, and interconnect structure 733 define PMOS transistor P13 (e.g., Figure 6 (As shown). Polysilicon region 727 corresponds to the gate of PMOS transistor P13. Interconnect structure 267 connects PMOS transistor P11 and PMOS transistor P13.

[0106] Figure 8 This is a layout diagram 800 of a portion of a storage circuit according to some embodiments, illustrating the lower and middle layers of the layout (e.g., contacts and a first metal layer M0). Figure 8 The storage units in the middle are based on Figure 6 The storage units 610A and 610B in the middle, and based on Figure 7 The lower layer is shown in the layout diagram 700. Figure 8 In and Figure 2 - Components that are identical or similar to those shown in Figure 5 are given the same reference numerals, and their detailed descriptions are omitted.

[0107] like Figure 8 As shown, the first metal layer M0 may include power rails 312, 314, and 316, and metal line features 322-354. The configuration of power rails 312, 314, and 316 and their contacts corresponding to the power nodes VSS and VDD of memory cells 610A and 610B is similar to... Figure 3The configuration shown in layout diagram 300 is omitted in detail hereafter. The configuration of the metal line features 346-354 and their contacts corresponding to the read ports of memory cells 610A and 610B is similar to... Figure 3 The layout shown in Figure 300 is omitted in its detailed description.

[0108] and Figure 3 Compared to the layout diagram 300, in Figure 8 In one embodiment, the arrangement of the metal line features 812-828 in the first metal layer M0 is modified to use PMOS transistors as access transistors (e.g., transistors P2, P3, P12, and P13) as read ports to implement memory cells 610A and 610B.

[0109] Metal line feature 812 corresponds to data node MT. Contacts extend downward from metal line feature 812 to couple the gate region of transistor P1 and interconnect structure 253 (the corresponding source / drain regions of transistor P0) together.

[0110] Metal line feature 814 corresponds to data node MB. Contacts extend downward from metal line feature 814 to couple the gate region of transistor P0 and the interconnect structure 257 (the corresponding source / drain regions of transistor P1) together.

[0111] Metal line feature 816 corresponds to a node connected to the write bit line WBLB. Contacts extend downward from metal line feature 816 to couple interconnect regions 733 (the respective source / drain regions of transistors P3 and P13) to metal line feature 816.

[0112] Metal line feature 818 corresponds to a node connected to the write word line WWL[0] of memory cell 110A. Contacts extend downward from metal line feature 818 to couple the gate regions of transistors P2 and P3 together.

[0113] Metal line feature 822 corresponds to a node connected to the write word line WWL[1] of memory cell 110B. Contacts extend downward from metal line feature 822 to couple the gate regions of transistors P12 and P13 together.

[0114] Metal line feature 824 corresponds to a node connected to the write bit line WBL. Contacts extend downward from metal line feature 824 to couple interconnect regions 731 (the respective source / drain regions of transistors P2 and P12) to metal line feature 824.

[0115] Metal line feature 826 corresponds to data node MB2. Contacts extend downward from metal line feature 826 to couple the gate region of transistor P10 and interconnect structure 267 (the corresponding source / drain regions of transistor P11) together.

[0116] Metal line feature 828 corresponds to data node MT2. Contacts extend downward from metal line feature 828 to couple the gate region of transistor P11 and interconnect structure 263 (the corresponding source / drain regions of transistor P10) together.

[0117] Figure 9 This is a layout diagram 900 of a portion of a memory circuit according to some embodiments, illustrating the middle and upper layers of the layout (e.g., a second metal layer M1, and a via layer VIA0 between metal layers M0 and M1). Figure 9 The storage units in the middle are based on Figure 6 The storage units 610A and 610B in the middle, and based on Figure 7 and Figure 8 The layers shown in the layout diagrams 700 and 800. Figure 9 In and Figure 2 - Components that are identical or similar to those shown in Figure 5 are given the same reference numerals, and their detailed descriptions are omitted.

[0118] like Figure 9 As shown, the second metal layer M1 may include metal line features 912-926 that are perpendicular to the metal line features in the first metal layer M0.

[0119] Metal line feature 912 corresponds to the write bit line WBL. Metal line feature 824 in the first metal layer M0 is connected to metal line feature 912 through a corresponding via structure.

[0120] Metal line feature 914 corresponds to the write word line WWL[1]. Metal line feature 822 in the first metal layer M0 is connected to metal line feature 914 through a corresponding via structure.

[0121] Metal line feature 916 corresponds to read word line RWL[1]. The configuration of metal line feature 916 is similar to Figure 4 The metal line feature 416 in the text is omitted in its detailed description.

[0122] Metal line feature 918 corresponds to data node MB. Metal line features 814 and 346 in the first metal layer M0 are connected to metal line feature 918 through corresponding via structures.

[0123] Metal line feature 922 corresponds to the read word line RWL[0]. The configuration of metal line feature 922 is similar to Figure 4The metal line feature 422 in the text is omitted in its detailed description.

[0124] Metal line feature 924 corresponds to the write word line WWL[0]. Metal line feature 818 in the first metal layer M0 is connected to metal line feature 924 through a corresponding via structure.

[0125] Metal line feature 926 corresponds to the write bit line WBLB. Metal line feature 816 in the first metal layer M0 is connected to metal line feature 926 through a corresponding via structure.

[0126] Figure 10A This is a layout diagram 1000a of a portion of a storage circuit according to some embodiments, illustrating the... Figures 7-9 The layout shown Figure 6 The arrangement of transistors N0, N1, and P0-P3 in the 6T section 612A of the memory cell 610A and transistors N4 and N5 in the read port 614A. For example... Figure 10A As shown, transistors P2 and P3, forming the write ports in the 6T portion 612A, are formed in the PP region PP1. The read port 614A is arranged in the NP region NP2. Transistors P2 and P3, as well as transistors N4 and N5, within the read port 614A are spaced apart. Furthermore, the 6T portion 612A overlaps with the doped regions NP1 and PP1. Similar to... Figure 5A In the 6T section 112A, n-type transistors N0 and N1 are formed in the NP region NP1, and p-type transistors P0 and P1 are formed in the PP region PP1.

[0127] Figure 10B This is a layout diagram 1000b of a portion of a storage circuit according to some embodiments, illustrating the... Figures 7-9 The layout shown Figure 6 The arrangement of transistors within memory cells 610A and 610B. For example... Figure 10B As shown, the read port 614A is separated from the write port and the 6T portion 612B (including the write port) of the storage cell 610B. The storage cell 610B is a storage cell located in the same row and column as the storage cell 610A.

[0128] The 6T portion 612B overlaps with doped regions NP2 and PP1. In the 6T portion 612B, n-type transistors N10 and N11 are formed in the NP region NP2, and p-type transistors P10 and P11 are formed in the PP region PP1. For example... Figure 10BAs shown, transistors P12 and P13, forming the write port in section 612B (6T), are formed in region PP1 (PP). Transistors N14 and N15, forming the read port in section 614B, are formed in region NP2 (NP). Similar to... Figure 5B In one embodiment, in layout diagram 1000b, a first read port (e.g., read port 614A) associated with memory cell 610A is separated from the first write port (e.g., transistors P2 and P3) in 6T portion 612B of memory cell 610B by a second write port (e.g., transistors P12 and P13) in 6T portion 612B.

[0129] Figure 11 This is a circuit diagram of a portion of a storage circuit 1100 according to some other embodiments. Similar to... Figure 1D The storage circuit 1100 also includes storage cells arranged in columns and one or more pairs of adjacent rows. For example, the storage circuit 1100 includes storage cells 1110A and 1110B belonging to column COL. In addition, storage cell 1110A belongs to the first row ROW[0] and storage cell 1110B belongs to the second row ROW[1].

[0130] and Figure 1D Compared to the 2P-8T SRAM cells shown (e.g., memory cells 110A and 110B), memory cells 1110A and 1110B are three-port ten-transistor (3P-10T) SRAM cells. The three-port memory cell includes a 6T portion (e.g., 1112A and 1112B) having a write port and two read ports (e.g., 1114A and 1116A, 1114B and 1116B), and can be used for either three-port or two-port operation. In three-port operation, the two read ports 1114A and 1116A of memory cell 1110A are independent. For example, as... Figure 11 As shown, the first read port 1114A of memory cell 1110A is coupled to the first read word line RWL[0], and the second read port 1116A of memory cell 1110A is coupled to the second read word line RWL2[0]. Read port operation of read ports 1114A and 1116A can include single-ended reading while maintaining the cell's value. In two-port operation, read ports 1114A and 1116A are connected, for example, via a single read word line (not shown). Two-port read port operation can include a voltage differential sense amplifier scheme.

[0131] exist Figure 11In the illustrated embodiment, memory cell 1110A, shown as a representative memory cell, includes two P-type transistors P0 and P1 and two N-type transistors N0 and N1 forming the memory cell; two additional N-type transistors N2 and N3 as part of the write port of memory cell 1110A; two additional N-type transistors N4 and N5 as part of the first read port of memory cell 1110A; and two additional N-type transistors N6 and N7 as part of the second read port of memory cell 1110A. Similarly, memory cell 1110B, shown as another representative memory cell, includes two P-type transistors P10 and P11 and two N-type transistors N10 and N11 forming the memory cell; two additional N-type transistors N12 and N13 as part of the write port of memory cell 1110B; two additional N-type transistors N14 and N15 as part of the first read port of memory cell 1110B; and two additional N-type transistors N16 and N17 as part of the second read port of memory cell 1110B.

[0132] and Figure 1D Compared to the storage circuit 100, the storage cells 1110A and 1110B each further include a second read port having two N-type transistors (e.g., transistors N6 and N7 forming the read port 116A of the storage cell 1110A, and transistors N16 and N17 forming the read port 116B of the storage cell 1110B).

[0133] For example, transistor N6 has a source coupled to power node VSS, a gate coupled to data node MT, and a drain coupled to transistor N7. Transistor N6 is configured to be turned off when its gate has a voltage level corresponding to a logic low value and turned on when its gate has a voltage level corresponding to a logic high value. Transistor N6 also functions as a traction device, configured to selectively couple intermediate node IN2 to power node VSS in response to a voltage level at data node MT.

[0134] Transistor N7 is coupled to the read bit line RBL2 at access node AN4 and to the drain of transistor N6. The read word line RWL2[0] is coupled to the gate of transistor N7. Transistor N7 serves as the read transmission gate controlled by the read word line RWL2[0].

[0135] Memory cell 1110B has a similar configuration to memory cell 1110A. For example, transistor N16 has a source coupled to power node VSS, a gate coupled to data node MT2, and a drain coupled to transistor N17. Transistor N16 is configured to be turned off when its gate has a voltage level corresponding to a logic low value and turned on when its gate has a voltage level corresponding to a logic high value. Transistor N16 also functions as a traction device, configured to selectively couple an intermediate node to power node VSS in response to a voltage level at data node MT2.

[0136] Transistor N17 is coupled to the read bit line RBL2 at the corresponding access node and to the drain of transistor N16. The read word line RWL2[0] is coupled to the gate of transistor N17. Transistor N17 serves as the read transmission gate controlled by the read word line RWL2[1].

[0137] for Figure 11 The storage cells 1110A and 1110B have separate control lines (RWL[0], RWL[1], RWL2[0], RWL2[1]) for each read port 114A, 114B and 116A, 116B. Read operations can be performed independently or simultaneously. Using two read ports provides additional flexibility and allows two outputs to be read from the cell simultaneously.

[0138] Figure 12 This is a layout diagram 1200 of a portion of a memory circuit according to some embodiments, illustrating the lower layers of the layout (e.g., oxide definition regions, gate layers, and interconnect layers). Figure 12 The storage units in the middle are based on Figure 11 The storage units 1110A and 1110B are included and can be used to illustrate... Figure 11 The layout design of other memory cells in the memory circuit 1100. Figure 12 In and Figure 2 - Components that are identical or similar to those shown in Figure 5 are given the same reference numerals, and their detailed descriptions are omitted.

[0139] and Figure 2 Compared to layout diagram 200, layout diagram 1200 further includes oxide-defined (OD) regions 1211 (which indicate N-type implanted regions buried in P-well regions 204), polysilicon regions 1221, 1223, and 1227, and interconnect regions 1231, 1233, 1237, and 1239. In some embodiments, interconnect regions 251-279 and 1231-1239 correspond to the conductive structure of a common layer. Those skilled in the art will understand that one or more layout patterns described herein can be used to prepare a set of masks, which can then be used to fabricate memory cells in integrated circuits.

[0140] like Figure 12 As shown, NMOS transistors N0, N1, N2, and N3 defined in the first N-type injection region (e.g., region NP1) and Figure 2 Those similar to those in the text are omitted in their detailed description.

[0141] In addition, with Figure 11 The NMOS transistors N6, N7, N16 and N17 in the second read ports RP2a and RP2b of memory cells 1110A and 1110B are also defined in the first N-type injection region (e.g., region NP1).

[0142] Interconnect structure 255, polysilicon region 225, OD region 1211, and interconnect structure 1237 define NMOS transistor N6 (e.g., Figure 11 (As shown). The polysilicon region 225 also corresponds to the gate of NMOS transistor N6 and connects to the gates of transistors N1, N6 and P1.

[0143] Interconnect structure 1237, polysilicon region 1227, OD region 1211, and interconnect structure 1239 define NMOS transistor N7 (e.g. Figure 11 (As shown). Polysilicon region 1227 corresponds to the gate of NMOS transistor N7, and interconnect structure 1239 corresponds to the node connected to read bit line RBL2. NMOS transistors N6 and N7 are connected through interconnect structure 1237.

[0144] Interconnect structure 1233, polysilicon region 1223, OD region 1211, and interconnect structure 255 define NMOS transistor N16 (e.g., Figure 11 (As shown). Polysilicon region 1223 corresponds to the gate of NMOS transistor N16.

[0145] Interconnect structure 1231, polysilicon region 1221, OD region 1211, and interconnect structure 1233 define NMOS transistor N17 (e.g., Figure 11 (As shown). Polysilicon region 1221 corresponds to the gate of NMOS transistor N17. Interconnect structure 1231 corresponds to the node connected to read bit line RBL2. NMOS transistors N16 and N17 are connected through interconnect structure 1233.

[0146] PMOS transistors P0, P1, P10, and P11 defined in the P-type injection region (e.g., region PP1) and Figure 2Those similar to those in the text are therefore omitted in detail. The NMOS transistors N10, N11, N12, N13 and NMOS transistors N4, N5, N14 and N15 (in the first read ports of memory cells 1110A, 1110B) defined in the second N-type injection region (e.g., region NP2) are similar to those in the text. Figure 2 Those similar to those in the text are omitted in their detailed description.

[0147] Figure 13 This is a layout diagram 1300 of a portion of a storage circuit according to some embodiments, illustrating the lower and middle layers of the layout (e.g., contacts and a first metal layer M0). Figure 13 The storage units in the middle are based on Figure 11 The storage cells 1110A and 1110B in the memory, and based on Figure 12 The lower layer is shown in the layout diagram 1200.

[0148] like Figure 13 As shown, power rails 312, 314, and 316, as well as metal wire features 322-354, are similar to Figure 3 Those mentioned above, therefore their detailed descriptions have been omitted.

[0149] In addition, the first metal layer M0 also includes metal line features 1312, 1314, 1316, and 1318. Metal line features 1312 and 1314 correspond to nodes that are connected to the read word lines RWL2[1] and RWL2[0] of memory cells 110B and 110A, respectively. Contacts extend downward from metal line features 1312 and 1314 to couple the gate regions of transistors N17 and N7 to metal line features 1312 and 1314, respectively.

[0150] Metal line feature 1316 corresponds to read bit line RBL2. Contacts extend downward from metal line feature 1316 to couple the corresponding source / drain regions of transistors N7 and N17 together.

[0151] Metal line feature 1318 corresponds to the node connected to data node MT2. Contacts extend downward from metal line feature 1318 to couple the gate region of transistor N16 to metal line feature 1318.

[0152] Figure 14 This is a layout diagram 1400 of a portion of a memory circuit according to some embodiments, illustrating the middle and upper layers of the layout (e.g., a second metal layer M1, and a via layer VIA0 between metal layers M0 and M1). Figure 14 The storage units in the middle are based on Figure 11 The storage cells 1110A and 1110B in the memory, and based on Figure 12 and Figure 13The layers shown in the layout diagrams 1200 and 1300.

[0153] like Figure 14 As shown, the metal line features 412, 414, 418, 424, and 426 in the second metal layer M1 are similar to Figure 4 Those mentioned above are omitted in detail. The second metal layer M1 also includes metal line features 1412, 1414, 1416, 1418 and 1422 that are perpendicular to the metal line features in the first metal layer M0.

[0154] The metal line feature 1412 corresponding to the read word line RWL2[1] is connected to the metal line feature 1312 in the first metal layer M0 through a corresponding via structure.

[0155] Metal line feature 1414 corresponding to data node MT2 is connected to metal line features 1318 and 334 in the first metal layer M0 through corresponding via structures.

[0156] The metal line feature 1416 corresponding to the read word line RWL[1] is connected to the metal line feature 352 in the first metal layer M0 through a corresponding via structure.

[0157] The metal line feature 1418 corresponding to the read word line RWL2[0] is connected to the metal line feature 1314 in the first metal layer M0 through a corresponding via structure.

[0158] The metal line feature 1422 corresponding to the read word line RWL[0] is connected to the metal line feature 354 in the first metal layer M0 through a corresponding via structure.

[0159] Figure 15 This is a layout diagram 1500 of a portion of a storage circuit according to some embodiments, illustrating the... Figures 12-14 The layout shown Figure 11 The arrangement of transistors within memory cells 1110A and 1110B.

[0160] like Figure 15 As shown, the 6T portions 1112A and 1112B of storage cells 1110A and 1110B and the read ports 1114A and 1114B are connected to... Figure 5B The 6T sections 112A and 112B and read ports 114A and 114B are similar, therefore their detailed descriptions are omitted. (Similar to...) Figure 5B Compared to layout diagram 500b, layout diagram 1500 also includes second read ports 1116A and 1116B for storage units 1110A and 1110B.

[0161] like Figure 15As shown, transistors N6 and N7 in read port 1116A and transistors N16 and N17 in read port 1116B are formed in the NP region NP1. In other words, the n-type transistors N6 and N7 forming read port 1116A and the n-type transistors N0, N1, N2, and N3 in the 6T portion 1112A are formed in the same doped region NP1. The n-type transistors N16 and N17 forming read port 1116B are separated from the 6T portion 1112B of memory cell 1110A by the 6T portion 1112A (including the write port). Memory cell 1110A is a memory cell located in the same row and column as memory cell 1110B.

[0162] Figure 16 This is a circuit diagram of a portion of a storage circuit 1600 according to some embodiments. For example... Figure 16 As shown, transistors N0-N5, N10-N15, P0, P1, P10, and P11 can also be used to implement 16T ternary content-addressable memory (TCAM) storage cells. In storage circuit 1600, transistors N4 and N14 serve as data gate transistors, and transistors N5 and N15 serve as search gate transistors. Figure 16 As shown, the gates of transistors N4 and N14 are connected to data nodes MB and MB2, respectively. In some embodiments, transistors N5 and N15 are connected together to the matching line ML. The gate of transistor N5 is connected to the search line SL, and the gate of transistor N15 is connected to the complementary search line SLB.

[0163] As shown above, by modifying the connections within the metal layer and vias, the above... Figure 1D - The layout design for the 8T2P memory cell discussed in Figure 5 can also be applied to the TCAM cell. In other words, transistors N0, N1, N2, and N3 in the first SRAM cell of the TCAM memory cell are arranged in the first NP region, while transistors N4, N5, N14, and N15 forming the comparator circuit of the TCAM memory cell are arranged in a second NP region separate from the first NP region. In some embodiments, transistors N10, N11, N12, and N13 in the second SRAM cell of the TCAM memory cell are also arranged in the second NP region. Transistors P0, P1, P10, and P11 are arranged in the first PP region between the first and second NP regions.

[0164] Figure 17 This is a block diagram of an integrated circuit design system 1700 for designing semiconductor devices according to some embodiments of the present disclosure. In some embodiments, system 1700 is implemented according to one or more embodiments. Figure 18The method 1800 describes a general-purpose computing device. The control system 1700 includes a hardware processor 1702 and a non-transitory computer-readable storage medium 1704 encoded (i.e., stored) with computer program code 1706, i.e., a set of executable instructions. The computer-readable storage medium 1704 also encodes instructions 1707 for interfacing with manufacturing machines used to manufacture semiconductor devices. The processor 1702 is electrically coupled to the computer-readable storage medium 1704 via a bus 1708. The processor 1702 is also electrically coupled to an I / O interface 1710 via a bus 1708. A network interface 1712 is also electrically connected to the processor 1702 via a bus 1708. The network interface 1712 is connected to a network 1714, enabling the processor 1702 and the computer-readable storage medium 1704 to be connected to external components via the network 1714. Processor 1702 is configured to execute computer program code 1706 encoded in computer-readable storage medium 1704 so that system 1700 can be used to perform part or all of the operations as described in method 1800.

[0165] In one or more embodiments, processor 1702 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0166] In one or more embodiments, the computer-readable storage medium 1704 is an electrical, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1704 includes semiconductor memory or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1704 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0167] In one or more embodiments, storage medium 1704 stores computer program code 1706 configured to cause system 1700 to perform method 1800. In one or more embodiments, storage medium 1704 also stores information required to perform method 1800, as well as information generated during the execution of method 1800, such as OD region layout 1716, polysilicon structure layout 1718, first interconnect (IC) region layout 1720, second IC region layout 1722, layout editor 1724, first metal structure layout 1726, second metal structure layout 1728, first wire layout 1730, second wire layout 1732, and / or a set of executable instructions for performing the operation of method 1800.

[0168] In one or more embodiments, storage medium 1704 stores instructions 1707 for interfacing with an external machine. Instructions 1707 enable processor 1702 to generate instructions that can be read by an external machine to efficiently implement method 1800 during a design process. In some embodiments, the design process is a semiconductor device comprising one or more circuit elements.

[0169] The control system 1700 includes an I / O interface 1710. The I / O interface 1710 is coupled to external circuitry. In one or more embodiments, the I / O interface 1710 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to the processor 1702.

[0170] The control system 1700 also includes a network interface 1712 coupled to the processor 1702. The network interface 1712 allows the system 1700 to communicate with a network 1714, to which one or more other computer systems are connected. The network interface 1712 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, WCDMA, etc.; or a wired network interface, such as ETHERNET, USB, or IEEE-1394. In one or more embodiments, the method 1800 is implemented in two or more systems 1700, and information such as the following is exchanged between the different systems 1700 via the network 1714: OD region layout 1716, polysilicon structure layout 1718, first interconnect (IC) region layout 1720, second IC region layout 1722, layout editor 1724, first metal structure layout 1726, second metal structure layout 1728, first wire layout 1730, and second wire layout 1732.

[0171] The control system 1700 is configured to receive UI-related information via I / O interface 1710. This information is transmitted to processor 1702 via bus 1708 to generate an OD (Original Design Environment) layout. This information is then stored as an OD layout 1716 in computer-readable medium 1704. The control system 1700 is also configured to receive polysilicon structure layout-related information via I / O interface 1710. This information is stored as a polysilicon structure layout 1718 in computer-readable medium 1704. Finally, the control system 1700 is configured to receive first IC (Integrated Circuit) region layout-related information via I / O interface 1710.

[0172] The information is stored in the computer-readable medium 1704 as a first IC region layout 1720. The control system 1700 is configured to receive information related to a second IC region layout via I / O interface 1710. This information is stored in the computer-readable medium 1704 as a second IC region layout 1722. The control system 1700 is configured to receive information related to a layout editor via I / O interface 1710. This information is stored in the computer-readable medium 1704 as a layout editor 1724. The control system 1700 is configured to receive information related to a first metal structure layout via I / O interface 1710. This information is stored in the computer-readable medium 1704 as a first metal structure layout 1726. The control system 1700 is configured to receive information related to a second metal structure layout via I / O interface 1710. This information is stored in the computer-readable medium 1704 as a second metal structure layout 1728. The control system 1700 is configured to receive information related to a first wire layout via I / O interface 1710. This information is stored in a computer-readable medium 1704 as a first wire layout 1730. The control system 1700 is configured to receive information related to a second wire layout via an I / O interface 1710. This information is stored in the computer-readable medium 1704 as a second wire layout 1732.

[0173] Figure 18 This is a flowchart of a method 1800 for generating a layout design according to some embodiments of this disclosure. It should be understood that... Figure 18 Additional operations, as well as some other processes, are performed before, during, and / or after the method 1800 shown, and may only be briefly described herein. In some embodiments, method 1800 is performed by operating a hardware computer (e.g., Figure 17 It is executed by the computer system 1700 in the middle.

[0174] In operation 1810, a layout pattern for the memory cells is generated, for example... Figures 2-4 , Figures 7-9 and Figures 12-14 The layout pattern depicted in the figure. The generated layout pattern includes one or more layout patterns for forming an SRAM memory cell structure. In some embodiments, the one or more layout patterns for forming the SRAM memory cell structure overlap with at least one of the corresponding active layout pattern and the corresponding isolation region of the memory cell, but not necessarily with both.

[0175] For example, in operation 1812, an active region layout pattern is generated associated with the active region forming the memory cell. An isolation region is located at least outside the active region layout pattern. In operation 1814, a polysilicon layout pattern is generated associated with the polysilicon structure forming the memory cell. The polysilicon layout pattern is configured to overlap with the active region layout pattern. In operation 1816, a first interconnect layout pattern is generated associated with a first interconnect structure forming the memory cell. In some embodiments, the first interconnect layout pattern is configured to overlap with the active region layout pattern. In some embodiments, in operation 1818, a second interconnect layout pattern is generated associated with a second interconnect structure forming the memory cell. The second interconnect layout pattern is configured to overlap with the isolation region. In operation 1820, a first metal layout pattern is generated associated with a first metal structure forming the memory cell. The first metal layout pattern is configured to overlap at least with the first polysilicon structure and the first interconnect structure. In operation 1822, a second metal layout pattern is generated associated with a second metal structure forming the memory cell. The second metal layout pattern is configured to overlap at least with the first metal structure.

[0176] Through the above operations, methods for forming SRAM memory cell structures can be executed accordingly based on standard cell rules to provide memory cells arranged in rows and columns (e.g., Figure 1D , Figure 6 , Figure 11 or Figure 16 The storage unit shown is an SRAM or TCAM memory.

[0177] and Figures 1D-5D Consistent with the embodiments described above, in some embodiments, the method may include forming first write access transistors N2 and N3 for a first memory cell 100A in OD region 211, forming first read access transistors N4 and N5 for the first memory cell 100A in OD region 219, and forming second write transistors N12 and N13 for a second memory cell 100B in OD region 217 between OD regions 211 and 219. In some embodiments, the method further includes forming second read access transistors N14 and N15 for the second memory cell 100B in OD region 219. In some embodiments, transistors N4, N5, and N10-N15 are formed in the same n-plus (NP) region NP2 overlapping with OD regions 217 and 219, while transistors N0-N3 are formed in another n-plus (NP) region NP1.

[0178] and Figures 6-10BConsistent with the embodiments, in some embodiments, the first write access transistors P2 and P3 for memory cell 600A are formed within OD region 213. The second write access transistors P12 and P13 for memory cell 600B are formed within OD region 215. PP region PP1 overlaps with OD regions 213 and 215.

[0179] and Figures 11-15 Consistent with the embodiments, in some embodiments, each of the memory cells 1110A and 1110B includes two read ports, and the method further includes forming third read access transistors N6 and N7 for the first memory cell 1110A within the OD region 1211, and forming fourth read access transistors N16 and N17 for the second memory cell 1110B within the OD region 1211. In some embodiments, transistors N6, N7, N16, and N17 are formed in an NP region NP1 that overlaps with the OD regions 211 and 1211.

[0180] The above description includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be added, replaced, rearranged, and / or eliminated as appropriate without departing from the spirit and scope of this disclosure.

[0181] By appropriately arranging read and write access transistors, and separating them into different regions for certain memory cells, standard cell rules can be met when designing layouts for various SRAM or TCAM memories. Accordingly, circuit area reduction can be achieved based on standard cell-based designs and appropriate routing track allocation.

[0182] In some embodiments, an apparatus including a memory cell is disclosed. A first memory cell within the memory cell includes a first write port disposed in a first doped region and a first read port disposed in a second doped region. The first read port is separated from the first write port by a second write port of a second memory cell within the memory cell.

[0183] In some embodiments, a semiconductor device including a first memory cell is also disclosed. The first memory cell includes a first memory unit comprising an n-type transistor formed in a first n+ (NP) region and a p-type transistor formed in a first p+ (PP) region between the first NP region and the second NP region, a first write access transistor formed in the first NP region or the first PP region, and a first read access transistor formed in the second NP region.

[0184] In some embodiments, a method for forming an SRAM memory cell structure is also disclosed. The method includes forming a first write access transistor for a first memory cell in a first region; forming a first read access transistor for a first memory cell in a second region; and forming a second write transistor for a second memory cell in a third region between the first and second regions, wherein the first and second memory cells are memory cells located in adjacent rows of the same column.

[0185] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0186] Example 1 is a storage device comprising: a plurality of storage cells, including at least a first storage cell and a second storage cell; a first write port disposed in a first doped region of the first storage cell; and a first read port disposed in a second doped region of the first storage cell, the first read port being separated from the first write port by a second write port of the second storage cell.

[0187] Example 2 is the apparatus described in Example 1, wherein the first storage unit and the second storage unit are storage units located in adjacent rows of the same column.

[0188] Example 3 is the apparatus described in Example 1, wherein the second memory cell includes: a second write port and a second read port arranged in the second doped region.

[0189] Example 4 is the apparatus described in Example 1, wherein the second memory cell includes: a second write port disposed in the first doped region; and a second read port disposed in the second doped region.

[0190] Example 5 is the apparatus described in Example 1, wherein the first write port includes an n-type transistor, and the first doped region and the second doped region are n+ (NP) regions.

[0191] Example 6 is the apparatus described in Example 1, wherein the first write port includes a p-type transistor, the first doped region is a p+ (PP) region, and the second doped region is an NP region.

[0192] Example 7 is the apparatus described in Example 1, wherein the first memory cell further includes another first read port disposed in the first doped region, and the second memory cell further includes another second read port disposed in the first doped region.

[0193] Example 8 is a semiconductor device comprising: a first memory cell, including: a first memory unit comprising an n-type transistor formed in a first n+ (NP) region and a p-type transistor formed in a first p+ (PP) region between the first NP region and the second NP region; a plurality of first write access transistors formed in the first NP region or the first PP region; and a plurality of first read access transistors formed in the second NP region.

[0194] Example 9 is the semiconductor device described in Example 8, further comprising: a second memory cell, including: an n-type transistor formed in the second NP region and a p-type transistor formed in the first PP region; a plurality of second write access transistors formed in the second NP region or the first PP region; and a plurality of second read access transistors formed in the second NP region.

[0195] Example 10 is the semiconductor device described in Example 9, wherein a first read access transistor of the first read access transistor is connected to a corresponding second read access transistor of the second read access transistor by one or more conductive features in one or more conductive layers formed over the first read access transistor and the second read access transistor.

[0196] Example 11 is the semiconductor device described in Example 9, wherein a first write access transistor of the first write access transistor is connected to a corresponding second write access transistor of the second write access transistor by one or more conductive features in one or more conductive layers formed over the first write access transistor and the second write access transistor.

[0197] Example 12 is the semiconductor device described in Example 9, wherein the second memory cell further includes a plurality of third read access transistors formed in the first NP region.

[0198] Example 13 is the semiconductor device described in Example 8, wherein the first memory cell further includes a plurality of fourth read access transistors formed in the first NP region.

[0199] Example 14 is a method of forming an SRAM memory cell structure, comprising: forming a first write access transistor for a first memory cell in a first region; forming a first read access transistor for the first memory cell in a second region; and forming a second write transistor for a second memory cell in a third region between the first region and the second region, wherein the first memory cell and the second memory cell are memory cells located in adjacent rows in the same column.

[0200] Example 15 is the method of Example 14, further comprising: forming a second read access transistor for the second memory cell in the second region.

[0201] Example 16 is the method of Example 15, further comprising: forming the second read access transistor and the second write transistor in the same n+ (NP) region overlapping the second region and the third region.

[0202] Example 17 is the method of Example 15, further comprising: forming a second read access transistor in an NP region within the second region; and forming a second write transistor in a p+ (PP) region adjacent to the NP region, the PP region overlapping the first region and the third region.

[0203] Example 18 is the method of Example 14, further comprising: forming the first write access transistor in an NP region; and forming the first read access transistor in another NP region.

[0204] Example 19 is the method of Example 14, further comprising: forming a third read access transistor for the first memory cell in a fourth region, the first region being located between the third region and the fourth region; and forming a fourth read access transistor for the second memory cell in the fourth region.

[0205] Example 20 is the method of Example 19, further comprising: forming the third read access transistor and the fourth read access transistor in an NP region overlapping the first region and the fourth region.

Claims

1. A storage device, comprising: Multiple storage units, including at least a first storage unit and a second storage unit; The first write port includes a plurality of first write access transistors formed in a first region and is arranged in a first doped region of the first memory cell; as well as A first read port includes a plurality of first read access transistors formed in a second region and is disposed in a second doped region of the first memory cell. The first read port is separated from the first write port by a second write port of the second memory cell. The second write port includes a plurality of second write access transistors formed in a third region between the first region and the second region.

2. The apparatus according to claim 1, wherein, The first storage unit and the second storage unit are storage units located in adjacent rows of the same column.

3. The apparatus according to claim 1, wherein, The second storage unit includes: The second write port and the second read port are arranged in the second doped region.

4. The apparatus according to claim 1, wherein, The second storage unit includes: The second write port arranged in the first doped region; and The second read port is arranged in the second doped region.

5. The apparatus according to claim 1, wherein, The first write port includes an n-type transistor, and the first doped region and the second doped region are n plus NP regions.

6. The apparatus according to claim 1, wherein, The first write port includes a p-type transistor, the first doped region is a p plus PP region, and the second doped region is an NP region.

7. The apparatus according to claim 1, wherein, The first storage unit further includes another first read port arranged in the first doped region, and the second storage unit further includes another second read port arranged in the first doped region.

8. A semiconductor device, comprising: A first storage unit and a second storage unit, wherein the first storage unit includes: The first storage unit includes an n-type transistor formed in a first NP region and a p-type transistor formed in a first PP region between the first NP region and the second NP region; Multiple first write access transistors are formed in a first region of the first NP region; and Multiple first read access transistors are formed in a second region of the second NP region; The second storage unit includes: Multiple second write access transistors are formed in a third region located between the first region and the second region in the second NP region; The plurality of first write access transistors are separated from the plurality of first read access transistors by the plurality of second write access transistors of the second memory cell.

9. The semiconductor device according to claim 8, wherein, The second storage unit also includes: The second storage unit includes an n-type transistor formed in the second NP region and a p-type transistor formed in the first PP region; and Multiple second read access transistors are formed in the second NP region.

10. The semiconductor device according to claim 9, wherein, A first read access transistor in the first read access transistor is connected to a corresponding second read access transistor in the second read access transistor via one or more conductive features in one or more conductive layers formed over the first read access transistor and the second read access transistor.

11. The semiconductor device according to claim 9, wherein, A first write access transistor in the first write access transistor is connected to a corresponding second write access transistor in the second write access transistor via one or more conductive features in one or more conductive layers formed over the first write access transistor and the second write access transistor.

12. The semiconductor device according to claim 9, wherein, The second memory cell also includes a plurality of third read access transistors formed in the first NP region.

13. The semiconductor device according to claim 8, wherein, The first memory cell further includes a plurality of fourth read access transistors formed in the first NP region.

14. A method for forming an SRAM memory cell structure, comprising: A plurality of first write access transistors for a first memory cell are formed in the first region; A plurality of first read access transistors for the first memory cell are formed in the second region; as well as A plurality of second write access transistors for second memory cells are formed in a third region between the first region and the second region, wherein the first memory cell and the second memory cell are memory cells located in adjacent rows of the same column. The plurality of first write access transistors are separated from the plurality of first read access transistors by the plurality of second write access transistors of the second memory cell.

15. The method of claim 14, further comprising: A second read access transistor for the second memory cell is formed in the second region.

16. The method of claim 15, further comprising: The second read access transistor and the second write access transistor are formed in the same NP region that overlaps with the second region and the third region.

17. The method of claim 15, further comprising: The second read access transistor is formed in the NP region of the second region; as well as The second write access transistor is formed in the PP region adjacent to the NP region, the PP region overlapping the first region and the third region.

18. The method of claim 14, further comprising: The first write access transistor is formed in the NP region; as well as The first read access transistor is formed in another NP region.

19. The method of claim 14, further comprising: A third read access transistor for the first memory cell is formed in a fourth region, the first region being located between the third region and the fourth region; as well as A fourth read access transistor for the second memory cell is formed in the fourth region.

20. The method of claim 19, further comprising: The third read access transistor and the fourth read access transistor are formed in the NP region that overlaps with the first region and the fourth region.

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