semiconductor element

Abstract

A semiconductor device includes an array region defined on a substrate, a dummy pattern ring surrounding the array region, and a gap between the array region and the dummy pattern ring, wherein the dummy pattern ring includes a magnetic tunneling junction (MTJ) pattern ring surrounding the array region and a metal interconnect pattern ring overlapping the MTJ pattern ring and surrounding the array region.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device, and more particularly to a magnetoresistive random access memory (MRAM) device. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with the application of a magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, and is used to represent the resistance change rate. At present, the magnetoresistance effect has been successfully applied in the production of magnetic disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made, which has the advantage of being able to continue to retain stored data without power.

[0003] The above-mentioned magnetoresistance effect is also applied in the field of magnetic field sensors, for example, an electronic compass component for a global positioning system (GPS) in a mobile phone, which is used to provide information such as the user's moving direction. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] An embodiment of the present application discloses a semiconductor device, which mainly comprises an array region defined on a substrate, a dummy pattern ring surrounding the array region, and a gap between the array region and the dummy pattern ring, wherein the dummy pattern ring comprises a magnetic tunneling junction (MTJ) pattern ring surrounding the array region and a metal interconnection pattern ring overlapping the MTJ pattern ring and surrounding the array region. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 A top view of a semiconductor device according to an embodiment of the present application;

[0006] Figure 2 Figure 1 is a schematic diagram of a cross-section along the tangent AA' in a first embodiment of the application; Figure 1 Figure 2 is a schematic diagram of a cross-section along the tangent BB' in the first embodiment of the application;

[0007] Figure 3 Figure 3 is a schematic diagram of a cross-section along the tangent AA' in a second embodiment of the application; Figure 1 Figure 4 is a schematic diagram of a cross-section along the tangent BB' in the second embodiment of the application.

[0008] Legend of main elements

[0009] 12: substrate

[0010] 14: array area

[0011] 16: dummy pattern

[0012] 18: MRAM area

[0013] 20: logic area

[0014] 22: metal interconnect pattern

[0015] 24: MTJ pattern

[0016] 26: gap

[0017] 28: first metal interconnect pattern

[0018] 30: second metal interconnect pattern

[0019] 32: third metal interconnect pattern

[0020] 34: fourth metal interconnect pattern

[0021] 36: first corner

[0022] 38: second corner

[0023] 40: third corner

[0024] 42: fourth corner

[0025] 52: interlayer dielectric layer

[0026] 54: metal interconnect structure

[0027] 56: metal interconnect structure

[0028] 60: metal interconnect

[0029] 62: spacer

[0030] 64: intermetal dielectric layer

[0031] 66: metal interconnect structure

[0032] 68: stop layer

[0033] 70: intermetal dielectric layer

[0034] 72: metal interconnect

[0035] 74: stop layer

[0036] 76: intermetal dielectric layer

[0037] 78: metal interconnect

[0038] 80: stop layer

[0039] 82: intermetal dielectric layer

[0040] 84: metal interconnect

[0041] 86: barrier layer

[0042] 88: metal layer

[0043] 90: lower electrode

[0044] 92: fixed layer

[0045] 94: barrier layer

[0046] 96: free layer

[0047] 98: upper electrode

[0048] 128: first MTJ pattern

[0049] 130: second MTJ pattern

[0050] 132: third MTJ pattern

[0051] 134: fourth MTJ pattern DETAILED DESCRIPTION

[0052] Reference will now be made to Figures 1 to 3 , Figure 1 is a top view of a semiconductor element, or more specifically an MRAM element, according to an embodiment of the present invention, Figure 2 is Figure 1 is a cross-sectional view along the tangent AA' in Figure 3 is Figure 1 is a cross-sectional view along the tangent BB' in Figures 1 to 3As shown, the MRAM element of the present application mainly comprises a substrate 12, for example, a substrate 12 composed of a semiconductor material selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc. The substrate 12 is preferably defined with an array region 14, which can also be referred to as a MRAM macro region in the present embodiment, and a dummy pattern 16 surrounding the array region 14. The array region 14 can further comprise a MRAM region 18 and a logic region 20.

[0053] In the present embodiment, the dummy pattern 16 further comprises a magnetic tunneling junction (MTJ) pattern 24 and a metal interconnect pattern 22 surrounding the MTJ pattern 24 and surrounding the array region 14. The MRAM region 18 comprises a plurality of MTJ patterns 24 arranged in an array. In addition, the MRAM element comprises a gap 26 between the array region 14 and the dummy pattern 16, so that the dummy pattern 16 does not directly contact the array region 14. In detail, the MTJ pattern 24 comprises a first MTJ pattern 128 and a second MTJ pattern 130 extending along a first direction, for example, the X direction, and a third MTJ pattern 132 and a fourth MTJ pattern 134 extending along a second direction, for example, the Y direction. The first MTJ pattern 128 overlaps the third MTJ pattern 132 at a first corner 36, the first MTJ pattern 128 overlaps the fourth MTJ pattern 134 at a second corner 38, the second MTJ pattern 130 overlaps the third MTJ pattern 132 at a third corner 40, and the second MTJ pattern 130 overlaps the fourth MTJ pattern 134 at a fourth corner 42.

[0054] Similarly, the metal interconnect pattern 22 surrounding the MTJ pattern 24 comprises a first metal interconnect pattern 28 and a second metal interconnect pattern 30 extending along the first direction, for example, the X direction, and a third metal interconnect pattern 32 and a fourth metal interconnect pattern 34 extending along the second direction, for example, the Y direction. The first metal interconnect pattern 28 overlaps the third metal interconnect pattern 32 at the first corner 36, the first metal interconnect pattern 28 overlaps the fourth metal interconnect pattern 34 at the second corner 38, the second metal interconnect pattern 30 overlaps the third metal interconnect pattern 32 at the third corner 40, and the second metal interconnect pattern 30 overlaps the fourth metal interconnect pattern 34 at the fourth corner 42.

[0055] In other words, the first MTJ pattern 128, the second MTJ pattern 130, the third MTJ pattern 132, and the fourth MTJ pattern 134 together form a ring-shaped surrounding array region 14, and likewise, the first metal interconnect pattern 28, the second metal interconnect pattern 30, the third metal interconnect pattern 32, and the fourth metal interconnect pattern 34 together also form a ring-shaped surrounding array region 14, and the ring-shaped formed by the first MTJ pattern 128, the second MTJ pattern 130, the third MTJ pattern 132, and the fourth MTJ pattern 134 preferably completely overlaps the ring-shaped formed by the first metal interconnect pattern 28, the second metal interconnect pattern 30, the third metal interconnect pattern 32, and the fourth metal interconnect pattern 34. It is noted that although the present embodiment forms only a single ring of dummy patterns 16 around the array region 14, the number of dummy patterns 16 around the array region 14 can be adjusted according to other embodiments of the present application, for example, more than one ring of dummy patterns 16, such as two rings or even three rings, can be formed around the array region 14, and such variations are within the scope of the present application. It is further noted that although the MTJ patterns 24 in the dummy patterns 16 form a ring-shaped surrounding array region 14 from a top view, the MTJ patterns 24 in the MRAM region 18 are arranged in an array and preferably each MTJ pattern 24 comprises a rectangle, such as a square or a rectangle.

[0056] As Figures 2 to 3 From a cross-sectional view, the substrate 12 can include active (finfet) elements such as metal-oxide semiconductor (MOS) transistors, passive (passive) elements, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 52, which are formed on the substrate 12. More specifically, the substrate 12 can include MOS transistor elements, which can be planar or non-planar (e.g., fin structure transistors), where the MOS transistors can include gate structures (e.g., metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other standard transistor elements, and the interlayer dielectric 52 can be formed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric 52 can have contact plugs (not shown) electrically connected to the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes related to planar or non-planar transistors and interlayer dielectric are well known in the art, they will not be described here.

[0057] In addition, the semiconductor device further includes a metal interconnect structure 54, 56 disposed on the ILD layer 52, the MTJ pattern 24 disposed on the dummy pattern 16 and the metal interconnect structure 56 of the MRAM region 18, the metal interconnect 60 disposed on the metal interconnect structure 56 of the array region 14, a spacer 62 disposed on the sidewall of each MTJ pattern 24, an IMD layer 64 disposed on the spacer 62, and another metal interconnect structure 66 disposed on the MTJ pattern 24 and the metal interconnect 60.

[0058] In the present embodiment, the metal interconnect structure 54 includes a stop layer 68, an IMD layer 70, and a plurality of metal interconnects 72 embedded in the stop layer 68 and the IMD layer 70, the metal interconnect structure 56 includes a stop layer 74, an IMD layer 76, and a plurality of metal interconnects 78 embedded in the stop layer 74 and the IMD layer 76, and the metal interconnect structure 66 includes a stop layer 80, an IMD layer 82, and a metal interconnect 84 embedded in the stop layer 80 and the IMD layer 82.

[0059] In the present embodiment, each of the metal interconnects 72, 78, 84 of the metal interconnect structures 54, 56, 66 and the metal interconnect 60 can be embedded in the IMD layers 70, 76, 82 and / or the stop layers 68, 74, 80 and electrically connected to each other according to a single damascene process or a dual damascene process. For example, each of the metal interconnects 72 preferably includes a trench conductor, each of the metal interconnects 78 preferably includes a via conductor, each of the metal interconnects 84 preferably includes a via conductor, and the metal interconnect 60 preferably includes a trench conductor.

[0060] In addition, each of the metal interconnects 72, 78, 84 can further include a barrier layer 86 and a metal layer 88, wherein the barrier layer 86 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 88 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), etc., but not limited thereto. Since the single damascene or dual damascene process is well known in the art, no further elaboration is provided herein. In the present embodiment, the metal layer 88 preferably includes copper, the IMD layers 70, 76, 82 preferably include silicon oxide, and the stop layers 68, 74, 80 include a nitrogen doped carbide (NDC) layer, silicon nitride, or silicon carbon nitride (SiCN), but not limited thereto.

[0061] In this embodiment, the MTJ pattern 24 is formed by first forming a bottom electrode 90, an MTJ stack structure, preferably including a pinned layer 92, a barrier layer 94, and a free layer 96, on the bottom electrode 90, a top electrode 98, and a patterned mask (not shown) on the metal interconnect structure 56. In this embodiment, the bottom electrode 90 and the top electrode 98 preferably comprise a conductive material, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al). The pinned layer 92 can comprise a ferromagnetic material, such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), cobalt (Co), etc. Alternatively, the pinned layer 92 can also be formed of an antiferromagnetic (AFM) material, such as, but not limited to, iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to pin or fix the magnetic moment direction of the adjacent layer. The barrier layer 94 can be formed of an insulating material comprising an oxide, such as, but not limited to, aluminum oxide (AlO x ) or magnesium oxide (MgO). The free layer 96 can be formed of a ferromagnetic material, such as, but not limited to, iron, cobalt, nickel, or an alloy thereof, such as cobalt-iron-boron (CoFeB). The free layer 96 is "free" to change its magnetization direction in response to an external magnetic field.

[0062] A pattern transfer fabrication process or a photoresist etch fabrication process is then performed, such as by using a patterned mask, such as a patterned photoresist, to remove portions of the top electrode 98, portions of the MTJ stack structure, and portions of the bottom electrode 90 to form the MTJ pattern 24 in the whole circle of the dummy pattern 16, wherein the MTJ pattern 24 or the bottom electrode 90 contacts and electrically connects to the whole circle of the metal interconnect 78 disposed thereunder. It is noted that, although the bottom electrode 90 of the MTJ pattern 24 of the dummy pattern 16 and the MRAM region 18 directly contacts or electrically connects to the metal interconnect 78 of the metal interconnect structure 56, only the MTJ pattern 24 disposed in the MRAM region 18 is actually connected to other MOS transistor elements disposed on the surface of the substrate 12 through the metal interconnect 78 disposed thereunder to become an actually operating MTJ. The MTJ pattern 24 in the dummy pattern 16 is a dummy MTJ pattern, wherein the metal interconnects 78, 84 above and below thereof are dummy metal interconnects and do not electrically connect downward to other elements or conductive lines, such that the MTJ pattern 24 and the metal interconnects 78, 84 in the dummy pattern 16 together form a dummy spacer around the array region 14.

[0063] It is also noted that in Figure 2 With Figure 3 The metal interconnects above the MTJ patterns 24, such as the metal interconnects 84, are Figure 1 The metal interconnect pattern 22 encircles the array region 14, and since both the MTJ patterns 24 and the metal interconnects 84 are arranged in a full circle around the periphery of the array region 14, the Figure 3 The bottom of the single metal interconnect 84 is preferably electrically connected and / or contacts the upper electrode 98 above the single MTJ pattern 24 as viewed along the structure of the BB' section.

[0064] In summary, the present application mainly utilizes a full circle of MTJ patterns and a plurality of stacked metal interconnect pattern layers to form at least one circle of dummy patterns around the array region or logic region of a semiconductor device for blocking electromagnetic waves. According to the preferred embodiment of the present application, the dummy patterns encircling the entire array region or logic region are mainly used as a barrier wall for shielding electromagnetic waves, which details include a full circle of MTJ patterns encircling around the array region and a full circle of metal interconnect patterns arranged directly above the MTJ patterns, wherein both the MTJ patterns and the metal interconnect patterns exhibit a circular shape when viewed from the top, rather than being arranged in an array of multiple rectangular patterns as in the prior art.

[0065] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application should be included in the scope of the present application.

Claims

1. A semiconductor element characterized by comprising: Comprising: a substrate comprising an array region disposed thereon; and a loop dummy pattern surrounding the array region, wherein the loop dummy pattern comprises: a loop magnetic tunneling junction (MTJ) pattern surrounding the array region; and a loop metal interconnect pattern fully overlapping the loop MTJ pattern and surrounding the array region.

2. The semiconductor element of claim 1, further comprising a gap disposed between the array region and the loop dummy pattern.

3. The semiconductor element of claim 1, wherein the loop MTJ pattern comprises: a first MTJ pattern and a second MTJ pattern extending along a first direction; and a third MTJ pattern and a fourth MTJ pattern extending along a second direction.

4. The semiconductor element of claim 3, wherein the first MTJ pattern overlaps the third MTJ pattern at a first corner, the first MTJ pattern overlaps the fourth MTJ pattern at a second corner, the second MTJ pattern overlaps the third MTJ pattern at a third corner, and the second MTJ pattern overlaps the fourth MTJ pattern at a fourth corner.

5. The semiconductor element of claim 1, wherein the loop metal interconnect pattern comprises: a first metal interconnect pattern and a second metal interconnect pattern extending along a first direction; and a third metal interconnect pattern and a fourth metal interconnect pattern extending along a second direction.

6. The semiconductor element of claim 5, wherein the first metal interconnect pattern overlaps the third metal interconnect pattern at a first corner, the first metal interconnect pattern overlaps the fourth metal interconnect pattern at a second corner, the second metal interconnect pattern overlaps the third metal interconnect pattern at a third corner, and the second metal interconnect pattern overlaps the fourth metal interconnect pattern at a fourth corner.

Images