Preparation method of metal interconnection structure and metal interconnection structure

Abstract

The invention provides a preparation method of a metal interconnection structure and the metal interconnection structure, and the method comprises the steps: forming a first dielectric layer and a plurality of through holes in the first dielectric layer on a substrate on which a semiconductor device layer and a first metal wiring layer are formed, and then employing a flowable organic material as a second dielectric layer on the first dielectric layer, and a plurality of metal grooves are formed in the second dielectric layer, and after the remaining second dielectric layer is cured, the through holes and the metal grooves are filled with second metal to form a metal interconnection structure. The preparation process of the through hole and the metal wire is divided into independent parts according to the sequence, so that the depth-to-width ratio of through hole etching is reduced during preparation of the through hole, and the etching process window is increased; in addition, a curable organic matter is adopted as a dielectric layer of the metal wire, the thickness of photoresist is reduced during preparation of the metal wire, a photoetching process window is increased, and meanwhile, due to the low dielectric constant of the organic matter, the parasitic capacitance between the metal interconnection wires is effectively reduced.

Description

Technical Field

[0001] The invention relates to the field of semiconductor device technology, and in particular to a method for fabricating a metal interconnect structure and the metal interconnect structure itself. Background Technology

[0002] In semiconductor manufacturing, metal interconnect technology plays a crucial role, connecting different circuit components, transmitting electronic signals, and powering these components. With the continuous advancement of semiconductor technology and the challenges brought about by the shrinking feature sizes, such as deteriorating RC delay, electromigration failure, and increased process complexity, the Dual-Damascene Cu interconnect process has emerged. With its lower RC delay, simplified process flow, and higher interconnect reliability, it has become the mainstream technology for back-end metal interconnects at deep submicron and below process nodes.

[0003] There are two main integration schemes for existing dual damasc Cu interconnect processes: via-first and line trench-first.

[0004] In the via-first integration scheme, after depositing the via dielectric layer and the metal line dielectric layer sequentially from bottom to top, the via groove is first formed by photolithography-etching. Then, new photoresist is coated to define the metal line pattern, and the metal line groove is formed by photolithography-etching. Finally, Cu is filled in one pass to simultaneously fill the via and the metal line groove with metal. However, in this scheme, the via etching requires etching through both the via dielectric layer and the metal line dielectric layer in one pass, resulting in an excessively large aspect ratio of the via etching. This greatly increases the difficulty of the etching process and easily leads to a reduction in the bottom size of the via. At the same time, when defining the groove pattern with photoresist, the photoresist also fills into the bottom of the via, which is difficult to remove. Ultimately, this leads to an increase in the resistance of the via itself and the contact resistance between the via and the underlying metal layer, worsening the RC delay.

[0005] In the trench-first integration scheme, after depositing the via dielectric layer and the metal line dielectric layer sequentially from bottom to top, the trench is first formed through a photolithography-etching process. Then, new photoresist is coated to define the via pattern, and the via is formed through photolithography-etching again. Finally, a single Cu filling process simultaneously fills both the via and the metal trench with metal. However, in this scheme, when coating new photoresist to define the via pattern, the photoresist needs to cover the depth of the trench simultaneously, resulting in excessively thick photoresist. This significantly increases the difficulty of exposure and development processes, reduces the photolithography window, and easily leads to via pattern distortion, pinholes, and other defects, ultimately resulting in increased via resistance and decreased process yield.

[0006] Therefore, how to integrate the through-hole and groove forming processes to overcome the defects in the above solutions has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0007] In view of the above problems, the present invention provides a method for fabricating a metal interconnect structure and a metal interconnect structure to overcome the defects of existing process solutions, such as excessively large aspect ratio of through-hole etching and excessively small photolithography process window caused by thick photoresist.

[0008] According to a first aspect of the present invention, a method for fabricating a metal interconnect structure is provided, comprising: A substrate is provided, on which a semiconductor device layer and a first metal wiring layer are formed, wherein the first metal wiring layer includes a plurality of first metals and a first interconnect dielectric layer filled between the first metals; A first dielectric layer is formed on the first metal wiring layer, and a plurality of vias are formed in the first dielectric layer; each via penetrates the first dielectric layer, and each via corresponds to a first metal. A second dielectric layer is formed on the first dielectric layer, the second dielectric layer covering the surface of the first dielectric layer and filling the plurality of through holes; wherein, the material of the second dielectric layer is a fluid organic material; A plurality of metal grooves are formed in the second dielectric layer, each of the through holes corresponds to a metal groove, and the second dielectric layer filling each of the through holes is removed; The remaining second dielectric layer is then cured. A second metal is filled into the through hole and the metal groove to form a metal interconnect structure.

[0009] Optionally, the organic material is an organic resin or spin-coated carbon.

[0010] Optionally, the curing process includes high-temperature curing or UV curing.

[0011] Optionally, the high-temperature curing temperature does not exceed 400°C.

[0012] Optionally, forming a plurality of through-holes in the first dielectric layer includes: A first patterned mask layer is formed on the surface of the first dielectric layer; wherein the first patterned mask layer includes a plurality of first openings, each first opening corresponding to a first metal; The first dielectric layer is etched using the first patterned mask layer as a mask to form a plurality of vias in the first dielectric layer.

[0013] Optionally, forming a plurality of metal trenches in the second dielectric layer includes: A second patterned mask layer is formed on the surface of the second dielectric layer; wherein the second patterned mask layer includes a plurality of second openings, and each of the vias corresponds to a second opening; The second dielectric layer is etched using the second patterned mask layer as a mask to form a plurality of metal trenches in the second dielectric layer, and the second dielectric layer filling each of the vias is removed.

[0014] Optionally, a second patterned mask layer is formed on the surface of the second dielectric layer, including: A passivation layer and a photoresist layer are sequentially formed on the surface of the second dielectric layer; The photoresist layer is subjected to a second patterning process to form a second patterned photoresist layer; Using the second patterned photoresist layer as a mask, the passivation layer is patterned to form the second patterned passivation layer; the second patterned photoresist layer and the second patterned passivation layer constitute the second patterned mask layer.

[0015] Optionally, the passivation layer is a low-temperature silicon oxide layer.

[0016] Optionally, a second metal is filled into the through-hole and the metal groove to form a metal interconnect structure, including: A second metal is formed, which covers the surface of the cured second dielectric layer and fills the through holes and the metal grooves; The second metal on the surface of the cured second dielectric layer is removed to form a metal interconnect structure in the through hole and the metal groove, the upper surface of the metal interconnect structure being flush with the upper surface of the cured second dielectric layer.

[0017] According to a second aspect of the present invention, a metal interconnect structure is also provided, which is prepared by the aforementioned method for preparing a metal interconnect structure.

[0018] The method for fabricating a metal interconnect structure provided by this invention involves forming a first dielectric layer and several vias on a substrate having a semiconductor device layer and a first metal wiring layer. A flowable organic material is then used as a second dielectric layer on the first dielectric layer, and several metal trenches are formed within the second dielectric layer. After curing the remaining second dielectric layer, a second metal is filled into the vias and metal trenches to form a metal interconnect structure. By dividing the via and metal line fabrication processes into independent parts according to their sequence, the aspect ratio of the via etching is effectively reduced, increasing the etching process window. Furthermore, using a curable organic material as the dielectric layer for the metal lines effectively reduces the photoresist thickness during metal line fabrication, increasing the photolithography process window. Additionally, the low dielectric constant of the organic material effectively reduces the parasitic capacitance between metal interconnects and lowers the RC delay of the metal structure. Therefore, while reducing the difficulty of the subsequent metal interconnect structure fabrication process, the signal transmission rate of the metal interconnect structure is effectively improved. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of the steps of a method for fabricating a metal interconnect structure according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of the steps for forming a plurality of through holes in a first dielectric layer according to an embodiment of the present invention; Figure 3 This is a schematic flowchart of the steps for forming a plurality of metal trenches in a second dielectric layer according to an embodiment of the present invention; Figure 4 This is a schematic flowchart of the steps for forming a second patterned mask layer on the surface of a second dielectric layer according to an embodiment of the present invention; Figure 5 This is a schematic flowchart of the steps of filling a through hole and a metal groove with a second metal to form a metal interconnect structure according to an embodiment of the present invention. Figure 6A ~ Figure 9C This is a schematic diagram of the structure corresponding to each step of the preparation method of the metal interconnect structure provided in an embodiment of the present invention; Explanation of reference numerals in the attached figures: 001 – Substrate; 002 – Semiconductor device layer; 003 – First metal wiring layer; 0031 – First Metal; 0032 – First interconnect dielectric layer; 004 – Protective layer; 100 – First dielectric layer; 101 – First patterned mask layer; 102 – Through hole; 200 – Second dielectric layer; 201 – Passivation layer; 202 – Photoresist layer; 203 – Metal channel; 300 – Second metal; 301 – Metal interconnect structure. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] As described in the background section, in existing back-end metal interconnect integration solutions, the via-first integration solution has the problem that when etching vias, it is necessary to etch through both the via dielectric layer and the metal line dielectric layer at once, resulting in an excessively large aspect ratio of the via etching, which greatly increases the difficulty of the etching process. The slot-first integration solution has the problem that when coating new photoresist to define the via pattern, the photoresist needs to cover the depth of the slot at the same time, resulting in an excessively thick photoresist, which greatly increases the difficulty of the exposure and development processes and reduces the photolithography process window.

[0024] In view of this, the present invention provides a method for fabricating a metal interconnect structure. On a substrate having a semiconductor device layer and a first metal wiring layer, a first dielectric layer and several vias are formed therein. A flowable organic material is then used as a second dielectric layer on the first dielectric layer, and several metal trenches are formed within the second dielectric layer. After curing the remaining second dielectric layer, a second metal is filled into the vias and metal trenches to form a metal interconnect structure. By dividing the via and metal line fabrication processes into independent parts according to their sequence, the aspect ratio of the via etching is effectively reduced during via fabrication, increasing the etching process window. Furthermore, using a curable organic material as the dielectric layer for the metal lines effectively reduces the photoresist thickness during metal line fabrication, increasing the photolithography process window. Additionally, the low dielectric constant of the organic material effectively reduces the parasitic capacitance between metal interconnects and lowers the RC delay of the metal structure. Therefore, while reducing the difficulty of the subsequent metal interconnect structure fabrication process, the signal transmission rate of the metal interconnect structure is effectively improved.

[0025] Please refer to Figures 1 to 5 and combined Figures 6A to 9C The method for fabricating the metal interconnect structure provided in this embodiment of the invention may include the following steps: S1: A substrate is provided, on which a semiconductor device layer and a first metal wiring layer are formed, the first metal wiring layer including a plurality of first metals and a first interconnect dielectric layer filling between each of the first metals.

[0026] As a specific implementation method, such as Figure 6A As shown, a substrate 001 is provided, on which a semiconductor device layer 002 is formed.

[0027] As an example, substrate 001 may be a silicon substrate, and semiconductor device layer 002 may include CMOS devices and corresponding interconnect vias. Of course, this invention is not limited thereto, and other types of substrates and other types of semiconductor devices in the semiconductor device layer are also within the scope of this invention.

[0028] In this embodiment, a first metal wiring layer 003 is formed on the semiconductor device layer 002, wherein the first metal wiring layer 003 includes a plurality of first metals 0031 and a first interconnect dielectric layer 0032 filled between each of the first metals 0031.

[0029] As an example, the first metal 0031 may be copper, and the first metal 0031 forms an electrical connection with the semiconductor device layer 002; the first interconnect dielectric layer 0032 may be a silicon oxide dielectric layer.

[0030] In this embodiment, the formation process of the first metal wiring layer may include: forming a dielectric material layer covering the surface of the semiconductor device layer; forming a mask layer on the dielectric material layer, the mask layer having a plurality of patterned openings, the patterned openings defining the formation positions of the first metal, the material of the mask layer may include photoresist; using the mask layer as a mask, etching away the dielectric material layer exposed by the patterned openings until the surface of the semiconductor device layer is exposed, so as to form a plurality of metal openings corresponding to the plurality of patterned openings in the dielectric material layer; removing the mask layer and filling the metal openings with metal material to form a plurality of first metals and a first interconnect dielectric layer.

[0031] In this embodiment, the opening sizes of the plurality of patterned openings may not be the same, the sizes of the plurality of first metals formed may be different, and the sizes between the first metals may not be the same, that is, the widths of the first interconnect dielectric layers between different first metals may not be the same.

[0032] As a preferred implementation method, such as Figure 6B As shown, a protective layer 004 is also formed on the first metal wiring layer 003.

[0033] As an example, the protective layer 004 can be a nitrogen-doped silicon carbide (NDC) layer. As a diffusion barrier layer and an etching stop layer, the protective layer 004 can effectively prevent the diffusion of copper atoms in the upper interconnect and precisely stop the etching of the upper interconnect, thus providing good protection for the first metal wiring layer 003. At the same time, the protective layer 004 can also effectively prevent the first metal 0031 in the first metal wiring layer 003 from oxidizing during the waiting interval before the start of the next process, thereby extending the shelf life of the first metal wiring layer after its preparation and improving the flexibility of the process.

[0034] S2: A first dielectric layer is formed on the first metal wiring layer, and a plurality of vias are formed in the first dielectric layer; each via penetrates the first dielectric layer, and each via corresponds to a first metal.

[0035] As an example, such as Figure 7A As shown, the material of the first dielectric layer 100 formed on the first metal wiring layer 003 can be, for example, silicon oxide or Low-K material. The first dielectric layer 100 formed on the first metal wiring layer 003 can be formed by chemical vapor deposition (CVD). Of course, the present invention is not limited thereto, and other types of materials and formation processes of the first dielectric layer 100 are also within the protection scope of the present invention.

[0036] As an example, the thickness of the first dielectric layer 100 can be, for example, 1000 Å to 3000 Å to adapt to the requirements of the process node.

[0037] As one specific implementation, a plurality of through holes are formed in the first dielectric layer 100, such as Figure 2 As shown, for example, it may include: S201: A first patterned mask layer is formed on the surface of the first dielectric layer; wherein the first patterned mask layer includes a plurality of first openings, each first opening corresponding to a first metal.

[0038] As an example, the first patterned mask layer 101 can be a photoresist mask layer. For example, a photolithography process can be used to spin-coat photoresist onto the surface of the first dielectric layer 100, followed by exposure and development of the photoresist to form the first patterned mask layer 101. Figure 7B As shown.

[0039] The first patterned mask layer 101 may include a plurality of first openings, each of which corresponds to a first metal 0031.

[0040] In this embodiment, the number of first openings can be less than or equal to the number of first metals, and can be determined based on actual application requirements. Each first opening corresponds to one first metal, that is, each first opening is formed above the corresponding first metal, and some first metals do not have a first opening formed above them.

[0041] In this embodiment, the opening size of each first opening can correspond to the size of the corresponding first metal; that is, the larger the size of the first metal, the larger the opening size of its corresponding first opening.

[0042] In a preferred embodiment, the photolithography process may be, for example, deep ultraviolet lithography (DUV) to improve the resolution of the first patterned photolithography pattern and reduce the alignment error between each first opening of the first patterned mask layer 101 and the first metal 0031, thereby adapting to the requirements of deep submicron processes.

[0043] S202: Using the first patterned mask layer as a mask, the first dielectric layer is etched to form several vias in the first dielectric layer. The structural schematic diagram after this step is as follows: Figure 7C As shown, each via penetrates the first dielectric layer, and each via corresponds to a first metal.

[0044] As a specific implementation, the first dielectric layer 100 is etched using the first patterned mask layer 101 as a mask, for example, by using reactive ion etching (RIE) process to ensure the vertical morphology of the via 102.

[0045] Each through-hole 102 penetrates the first dielectric layer 100, and each through-hole 102 corresponds to a first metal 0031.

[0046] In a preferred embodiment, such as Figure 7C As shown, after each via 102 penetrates the first dielectric layer 100, the bottom of the via 102 stops at the surface of the protective layer 004. The preferred reactive ion etching process is a reactive ion etching process with a high etching selectivity ratio (e.g., greater than 50:1) between the first dielectric layer 100 and the protective layer 004, in order to prevent damage to the protective layer 004 during the etching process of the via 102, thereby avoiding damage and oxidation of the first metal 0031 caused by premature opening of the protective layer 004.

[0047] In one specific implementation, after etching the first dielectric layer 100 using the first patterned mask layer 101 as a mask to form a plurality of vias in the first dielectric layer 100, the method further includes removing the residual photoresist mask layer. The removal of the residual photoresist mask layer can be achieved, for example, by a wet stripping process. The solvent used in the wet process can be, for example, N-methylpyrrolidone (NMP). The residual photoresist mask layer is removed by immersion in an NMP solution combined with ultrasonic cleaning.

[0048] S3: A second dielectric layer is formed on the first dielectric layer, covering the surface of the first dielectric layer and filling several through-holes; wherein, the material of the second dielectric layer is a fluid organic material. A schematic diagram of the structure after this step is shown below. Figure 8A As shown.

[0049] As an example, the material of the second dielectric layer 200 may be, for example, an organic resin or spin-coated carbon, and the thickness of the second dielectric layer 200 may be, for example, 500 Å to 1000 Å to adapt to the requirements of the process node.

[0050] In a preferred embodiment, the material of the second dielectric layer 200 may be, for example, porous fluorinated polyimide (FPI) or a high proportion of SP. 3 Carbon-doped porous spin-coated carbon (SOC), porous FPI, and the dielectric constant of SOC materials can be reduced to below 2, which is much lower than the dielectric constant of conventional interconnect dielectric layer SiO2 (>3.5). This effectively reduces the inter-line parasitic capacitance of metal interconnect structures and significantly optimizes RC delay, thereby improving the signal transmission rate of metal interconnect structures. Simultaneously, the fluidity of organic materials enables high surface flatness and step coverage, providing a high-quality substrate surface for subsequent metal trench photolithography processes. This effectively avoids defocus defects during metal trench exposure and development caused by surface unevenness, ensuring the quality of the metal trench photoresist pattern, improving the process window of metal trench photolithography, and better adapting to deep submicron metal interconnect processes.

[0051] Furthermore, the material of the second dielectric layer 200 can be cured after curing treatment. The cured second dielectric layer 200 can withstand high temperature and has sufficient mechanical strength, so that it can withstand the high temperature processing in subsequent metal interconnect processes (such as CVD deposition process) and withstand the grinding of chemical mechanical polishing (CMP) process without damage, thus providing sufficient structural support strength for the metal interconnect structure.

[0052] In a preferred embodiment, for example, porous fluorinated polyimide (FPI) or a high proportion of SP is used as the material of the second dielectric layer 200. 3 Carbon-doped porous spin-on carbon (SOC) can withstand high temperatures of around 450°C after curing and has sufficient mechanical strength to withstand CMP grinding without damage. Therefore, it can withstand high-temperature processes (such as CVD processes with a maximum temperature of 420°C) in subsequent metal interconnect processes and provide sufficient interlayer dielectric support strength for metal lines.

[0053] Of course, this invention is not limited to this, and other organic materials that are fluid and can be cured after curing are also within the scope of protection of this invention.

[0054] S4: Several metal grooves are formed in the second dielectric layer, each through hole corresponds to a metal groove, and the second dielectric layer filling each through hole is removed.

[0055] As a specific implementation method, such as Figure 3 As shown, forming several metal grooves in the second dielectric layer 200 may include, for example: S401: A second patterned mask layer is formed on the surface of the second dielectric layer; wherein the second patterned mask layer includes a plurality of second openings, and each through hole corresponds to a second opening.

[0056] As an example, the second patterned mask layer can be a photoresist mask layer. For example, a photolithography process can be used to spin-coat photoresist onto the surface of the second dielectric layer 200, followed by exposure and development of the photoresist to form the second patterned mask layer.

[0057] In a preferred embodiment, a second patterned mask layer is formed on the surface of the second dielectric layer 200, such as... Figure 4 As shown, for example, it may include: S4011: A passivation layer 201 and a photoresist layer 202 are sequentially formed on the surface of the second dielectric layer. A schematic diagram of the structure after this step is shown below. Figure 8B As shown.

[0058] As an example, the passivation layer 201 can be an oxide layer, for example. In a preferred embodiment, the oxide layer can be a low-temperature silicon oxide (LTO) layer, with a thickness of 50 Å to 100 Å, for example. The LTO can be formed using plasma-enhanced chemical vapor deposition (PECVD) at a temperature of 150°C to 300°C. Of course, this invention is not limited to this; other types of passivation layer 201 materials and formation methods are also within the scope of this invention. S4012: Perform a second patterning process on the photoresist layer 202 to form a second patterned photoresist layer 202. The structural schematic diagram after this step is shown below. Figure 8C As shown.

[0059] As an example, the second patterning of the photoresist layer 202 can be performed using a photolithography process, through exposure and development, to form the second patterned photoresist layer 202. In a preferred embodiment, the photolithography process is deep ultraviolet (DUV) lithography to improve the resolution of the second patterned photolithography pattern and the alignment accuracy of the second opening and via in the second patterned mask layer, thereby adapting to the requirements of deep submicron processes.

[0060] S4013: Using the second patterned photoresist layer 202 as a mask, the passivation layer 201 is patterned to form the second patterned passivation layer 201; the second patterned photoresist layer 202 and the second patterned passivation layer 201 constitute the second patterned mask layer, wherein the second patterned mask layer includes a plurality of second openings, and each via 102 corresponds to a second opening. The structural schematic diagram after this step is shown below. Figure 8D As shown.

[0061] As an example, using the second patterned photoresist layer 202 as a mask, the passivation layer 201 can be patterned using, for example, an plasma dry etching process (ICP / RIE). The plasma power is, for example, 500W~800W, the pressure is, for example, 5mTorr~20mTorr, and the temperature is, for example, 60℃~80℃. By using an ICP / RIE etching process with a high etching selectivity (e.g., an etching selectivity ratio of 20:1 or higher between the passivation layer and the second dielectric layer), damage to the second dielectric layer 200 can be effectively avoided. In addition, the linewidth control accuracy of the ICP / RIE etching process can reach ±0.1μm, and the edge perpendicularity is >85°, which can effectively ensure the vertical morphology of the second patterned passivation layer 201, thereby ensuring the vertical morphology of the subsequently formed metal trench, to meet the patterning requirements of deep submicron dimensions, and thus to adapt to the fabrication of smaller metal interconnect structures.

[0062] In this preferred embodiment, a second patterned mask layer is formed by using a second patterned passivation layer 201 and a second patterned photoresist layer 202 together. By utilizing the high mechanical strength, high linewidth control precision, and high etching selectivity of the passivation layer 201, the inherent defects of a single photoresist mask, such as poor stability and easy deformation during etching, can be effectively avoided. This effectively ensures the linewidth precision and vertical morphology of the metal trench, and can better adapt to the fabrication of deep submicron metal interconnect structures.

[0063] S402: Using the second patterned mask layer as a mask, the second dielectric layer is etched to form several metal trenches in the second dielectric layer, and the second dielectric layer filling each via is removed. The structural diagram after this step is shown below. Figure 8E As shown.

[0064] In one specific implementation, the second dielectric layer 200 is etched using the second patterned mask layer as a mask, and the second dielectric layer 200 filling each via is removed. For example, a dry etching process can be used.

[0065] As a preferred embodiment, the dry etching process can be, for example, a combination of fluorine-based plasma dry etching and oxygen plasma ashing: First, a fluorine-based plasma dry etching process is used to etch the second dielectric layer 200 to form several metal trenches 203, and to initially remove the second dielectric layer 200 filling the via 102. The etching gas ratio can be, for example, CF4:O2:Ar:CHF3 = 50:10:35:5, the chamber pressure can be, for example, 8mTorr~12mTorr, and the bias power can be, for example, 80W~120W. By utilizing a high CHF3 gas ratio to generate a sidewall polymer, the sidewalls of the metal trenches 203 are protected. At the same time, the vertical ion bombardment is enhanced to ensure the verticality of the metal trenches 203 (>85°) and the vertical etching of the second dielectric layer 200 filling the via 102, avoiding damage to the sidewalls of the via 102.

[0066] Next, an oxygen plasma ashing process is used to remove the residual second dielectric layer 200 in the through hole 102. By utilizing the high selectivity of the oxygen plasma ashing process for organic dielectric layers and the low damage to the lower dielectric / through hole sidewall (oxide), the residual second dielectric layer 200 in the through hole 102 is effectively removed while avoiding damage to the sidewall of the second dielectric layer, the sidewall of the through hole, and the bottom of the through hole.

[0067] Of course, the present invention is not limited to one method. Other processes, such as forming several metal grooves in the second dielectric layer and removing the second dielectric layer filling each through hole, are also within the protection scope of the present invention.

[0068] S5: Curing process is performed on the remaining second dielectric layer.

[0069] As an example, the remaining second dielectric layer 200 is cured, for example by high-temperature curing or UV curing.

[0070] As a specific implementation method, the curing temperature of high-temperature curing does not exceed 400℃, so as to avoid excessively high temperatures causing defects such as blistering and pinholes in the film layer of the second dielectric layer 200, which would affect the quality of the cured second dielectric layer.

[0071] In a preferred embodiment, the high-temperature curing process can be divided into two stages: a low-temperature baking stage (80°C~150°C) to remove organic solvents from the second medium layer 200; and a molecular chain curing stage (200°C~380°C) to allow the second medium layer 200 to undergo deep cross-linking and form a three-dimensional network porous structure.

[0072] The entire high-temperature curing process is carried out under an inert atmosphere (N2 / Ar) to prevent oxidation of the second dielectric layer 200, while the heating rate is precisely controlled to avoid stress cracking.

[0073] Of course, this invention is not limited to this, and other high-temperature curing processes are also within the scope of protection of this invention.

[0074] As a specific implementation method, UV curing can be achieved by using a light source with a wavelength of 365nm~405nm under an inert atmosphere (e.g., N2) at a concentration of 50 mW / cm². 2 ~200mW / cm 2 The light intensity is used for curing, and the specific curing time is set according to the thickness of the second dielectric layer 200.

[0075] Of course, this invention does not take this as an example; other methods of curing the remaining second dielectric layer 200 are also within the scope of protection of this invention.

[0076] The cured second dielectric layer 200 is heat-resistant and has sufficient mechanical strength, thus it can withstand the high-temperature processing (such as CVD deposition process) in subsequent metal interconnect processes and withstand the grinding of chemical mechanical polishing (CMP) without damage, providing sufficient structural support strength for the metal interconnect structure.

[0077] S6: Fill the through hole and metal groove with a second metal to form a metal interconnect structure.

[0078] As one specific implementation, a second metal is filled into the through-hole and the metal groove to form a metal interconnect structure, such as... Figure 5 As shown, for example, it may include: S601: Forming a second metal 300, the second metal 300 covers the surface of the cured second dielectric layer 200 and fills the through holes 102 and metal grooves 203. A schematic diagram of the structure after this step is shown below. Figure 9B As shown.

[0079] In a preferred embodiment, a second metal 300 is formed on the substrate surface, for example, by electroplating copper (ECP). By utilizing the ECP process, the copper deposition rate at the bottom of the trench and via can be effectively increased, while the copper deposition rate on the sidewalls can be suppressed to avoid void defects caused by premature closure of copper in the trench and via. At the same time, the good high aspect ratio (>10:1) filling characteristics of ECP can ensure that copper is filled without voids or gaps in the via 102 and the metal trench 203, thereby ensuring the electrical reliability of the metal interconnect structure.

[0080] Of course, this invention is not limited thereto, and other processes for forming the second metal 300 are also within the scope of protection of this invention.

[0081] In a preferred embodiment, before step S601, the method may further include, for example, removing the protective layer 004 at the bottom of the through hole 102 to expose the first metal 0031 at the bottom of the through hole 102. A schematic diagram of the structure after this step is shown below. Figure 9A As shown. By opening the protective layer 004 at the bottom of the through hole 102 before the second metal 300 is filled, oxidation defects caused by premature exposure of the first metal 0031 to air can be avoided, thereby effectively protecting the first metal 0031.

[0082] S602: Remove the second metal 300 from the surface of the cured second dielectric layer 200 to form a metal interconnect structure 301 in the through-hole and metal trench. The upper surface of the metal interconnect structure 301 is flush with the upper surface of the cured second dielectric layer 200. The structural diagram after this step is shown in the figure. Figure 9C As shown.

[0083] In a preferred embodiment, the remaining second metal 300 on the surface of the second dielectric layer 200 can be removed, for example, by chemical mechanical polishing (CMP). The CMP process, with its characteristics of "low-hardness abrasive + chemical selectivity control + inhibitor passivation protection," achieves a high selectivity ratio between the removal rate of the second metal 300 and the removal rate of the second dielectric layer 200, for example, a selectivity ratio of 100:1 to 500:1. This effectively removes the remaining second metal 300 from the surface of the second dielectric layer 200 while avoiding damage to the second dielectric layer 200. Simultaneously, the CMP process ensures high flatness of the polished surface (e.g., thickness deviation rate less than 2%), ensuring that the upper surface of the final metal interconnect structure 301 is flush with the upper surface of the remaining second dielectric layer 200. This provides a high-quality substrate surface for subsequent photolithography processes, effectively avoiding defocus defects during exposure and development due to surface unevenness. This guarantees the quality of the photolithography pattern in subsequent processes, improves the process window of the photolithography process, and better adapts to deep submicron-sized metal interconnect processes.

[0084] Of course, the present invention is not limited thereto, and other methods of removing the second metal 300 from the surface of the second dielectric layer 200 after curing are also within the protection scope of the present invention.

[0085] In a specific embodiment, the interconnect layer needs to contain multiple layers of metal to ensure that all device ports in the semiconductor device layer can be brought out by the interconnect metal. Therefore, after completing step S6 to form the metal interconnect structure, the process of steps S2 to S6 can be repeated multiple times along the direction perpendicular to the substrate to complete the fabrication of the multilayer metal interconnect structure until the top layer of the interconnect layer.

[0086] The method for fabricating a metal interconnect structure provided by this invention involves forming a first dielectric layer and several vias on a substrate with a semiconductor device layer and a first metal wiring layer. A flowable organic material is then used as a second dielectric layer on the first dielectric layer, and several metal trenches are formed within the second dielectric layer. After curing the remaining second dielectric layer, a second metal is filled into the vias and metal trenches to form a metal interconnect structure. By dividing the via and metal line fabrication processes into independent parts according to their sequence, the aspect ratio of the via etching is effectively reduced, increasing the etching process window. Furthermore, using a curable organic material as the dielectric layer for the metal lines effectively reduces the photoresist thickness during metal line fabrication, increasing the photolithography process window. Additionally, the low dielectric constant of the organic material effectively reduces the parasitic capacitance between metal interconnects and lowers the RC delay of the metal structure. Therefore, while reducing the difficulty of the subsequent metal interconnect structure fabrication process, the signal transmission rate of the metal interconnect structure is effectively improved.

[0087] According to one embodiment of the present invention, a metal interconnect structure is also provided, wherein the metal interconnect structure is prepared by the above-described method for preparing a metal interconnect structure.

[0088] Those skilled in the art will understand that the embodiments provided by the present invention can be provided as methods, apparatus, or electronic devices. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a metal interconnect structure, characterized in that, include: A substrate is provided, on which a semiconductor device layer and a first metal wiring layer are formed, wherein the first metal wiring layer includes a plurality of first metals and a first interconnect dielectric layer filling the spaces between the first metals. A first dielectric layer is formed on the first metal wiring layer, and a plurality of vias are formed in the first dielectric layer; each via penetrates the first dielectric layer, and each via corresponds to a first metal. A second dielectric layer is formed on the first dielectric layer, the second dielectric layer covering the surface of the first dielectric layer and filling the plurality of through holes; wherein, the material of the second dielectric layer is a fluid organic material; A plurality of metal grooves are formed in the second dielectric layer, each of the through holes corresponds to a metal groove, and the second dielectric layer filling each of the through holes is removed; The remaining second dielectric layer is then cured. A second metal is filled into the through hole and the metal groove to form a metal interconnect structure.

2. The method for fabricating the metal interconnect structure according to claim 1, characterized in that, The organic material is an organic resin or spin-coated carbon.

3. The method for fabricating the metal interconnect structure according to claim 1 or 2, characterized in that, The curing process includes high-temperature curing or UV curing.

4. The method for fabricating the metal interconnect structure according to claim 3, characterized in that, The high-temperature curing temperature does not exceed 400℃.

5. The method for fabricating a metal interconnect structure according to claim 1, characterized in that, The formation of a plurality of through holes in the first dielectric layer includes: A first patterned mask layer is formed on the surface of the first dielectric layer; wherein the first patterned mask layer includes a plurality of first openings, each first opening corresponding to a first metal; The first dielectric layer is etched using the first patterned mask layer as a mask to form a plurality of vias in the first dielectric layer.

6. The method for fabricating a metal interconnect structure according to claim 1, characterized in that, The formation of a plurality of metal trenches in the second dielectric layer includes: A second patterned mask layer is formed on the surface of the second dielectric layer; wherein the second patterned mask layer includes a plurality of second openings, and each of the vias corresponds to a second opening; The second dielectric layer is etched using the second patterned mask layer as a mask to form a plurality of metal trenches in the second dielectric layer, and the second dielectric layer filling each of the vias is removed.

7. The method for fabricating a metal interconnect structure according to claim 6, characterized in that, Forming a second patterned mask layer on the surface of the second dielectric layer includes: A passivation layer and a photoresist layer are sequentially formed on the surface of the second dielectric layer; The photoresist layer is subjected to a second patterning process to form a second patterned photoresist layer; Using the second patterned photoresist layer as a mask, the passivation layer is patterned to form the second patterned passivation layer; the second patterned photoresist layer and the second patterned passivation layer constitute the second patterned mask layer.

8. The method for fabricating a metal interconnect structure according to claim 7, characterized in that, The passivation layer is a low-temperature silicon oxide layer.

9. The method for fabricating a metal interconnect structure according to claim 1, characterized in that, Filling the through-hole and the metal trench with a second metal to form a metal interconnect structure includes: A second metal is formed, which covers the surface of the cured second dielectric layer and fills the through holes and the metal grooves; The second metal on the surface of the cured second dielectric layer is removed to form a metal interconnect structure in the through hole and the metal groove, the upper surface of the metal interconnect structure being flush with the upper surface of the cured second dielectric layer.

10. A metal interconnect structure, characterized in that, The metal interconnect structure is prepared by the method for preparing a metal interconnect structure as described in any one of claims 1 to 9.

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