A low-voltage terminal device based on field modulation under a grid and a preparation method thereof

Abstract

The present invention relates to a low-voltage terminal device based on field modulation under a gate and a preparation method thereof. The device includes: a substrate layer; a buffer layer located on the substrate layer; a channel layer located on the buffer layer; a source electrode located at one end of the channel layer; a drain electrode located at the other end of the channel layer; an insertion layer located on the channel layer and between the source electrode and the drain electrode; a barrier layer located on the insertion layer; wherein, along the gate width direction, a plurality of grooves are arranged at intervals in the barrier layer, the insertion layer and the channel layer, and the bottom of the groove is located in the channel layer; a passivation layer is located on the barrier layer, and a gate groove penetrating the passivation layer is arranged along the gate width direction, and a plurality of grooves are located under the gate groove; a gate electrode is located in a plurality of grooves and the gate groove, and on the surface of a part of the passivation layer; the side length of the groove close to the source electrode is greater than the side length thereof close to the drain electrode. The device of the present invention can reduce the intrinsic knee-point voltage by forming an asymmetric divergent nano-channel, and can achieve a greater output power at a lower operating voltage.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor devices, and particularly relates to a low-voltage terminal device based on gate field modulation and a preparation method thereof. Background Art

[0002] For various mobile terminals, RF devices need to operate at medium and low voltage levels of a portable power source (such as a battery pack) to provide high power added efficiency (PAE) and medium radio frequency output power density (Pout). Low-voltage GaN technology can provide higher PAE than GaAs technology at the same output power level, thereby achieving lower power consumption, demonstrating that the application space of GaN technology can be extended beyond the existing high voltage. More importantly, GaN has an advantage over GaAs in terms of bandwidth, which makes it possible to achieve high-speed broadband communication and can significantly reduce the number of power amplifiers (PAs), chip area, and cost of mobile terminals. Therefore, in low-voltage terminal applications, GaN technology may become a strong competitor to GaAs technology.

[0003] GaN crystals have good electrical properties, such as a wide bandgap width, high breakdown electric field, etc. More importantly, GaN can form an AlGaN / GaN heterojunction. Due to the existence of extremely strong piezoelectric polarization and spontaneous polarization electric fields, even without any doping, a high-concentration two-dimensional electron gas can be formed at the AlGaN / GaN heterojunction interface. At the same time, this two-dimensional electron gas has a very high mobility (>1500 cm2 / Vs) and can obtain extremely high peak electron velocity (3x107 cm / s) and saturation electron velocity (2x107 cm / s), that is, a HEMT device.

[0004] In order to achieve high-performance GaN HEMT in a low-voltage range, the parasitic resistance composed of contact resistance and access resistance should be reduced, thereby improving Pout and knee point voltage (Vknee) by increasing the maximum output current density (Id.max) and reducing the on-resistance (Ron), and improving PAE by reducing Joule heat dissipation.

[0005] The Fin structure can effectively reduce the knee point voltage of the device, enabling GaN-HEMT to reach saturation at a smaller source-drain bias, making the device more suitable for application in high-frequency (radio frequency / microwave) fields with low power supply voltages. Applied to low-voltage power amplifiers, it can effectively improve the comprehensive performance of PAE and linearity, contributing to wide application in the next-generation wireless mobile terminals. However, in order to obtain high gain, good linearity, and reasonable power added efficiency at relatively low voltages, how to further reduce the knee point voltage of the device is the key. Summary of the Invention

[0006] To solve the above problems existing in the prior art, the present invention provides a low-voltage terminal device based on gate field modulation and a preparation method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0007] The present invention provides a low-voltage terminal device based on gate field modulation, including:

[0008] A substrate layer;

[0009] A buffer layer, located on the substrate layer;

[0010] A channel layer, located on the buffer layer;

[0011] A source electrode, located at one end of the channel layer;

[0012] A drain electrode, located at the other end of the channel layer;

[0013] An insertion layer, located on the channel layer and between the source electrode and the drain electrode;

[0014] A barrier layer, located on the insertion layer; wherein, along the gate width direction, a plurality of grooves are arranged at intervals in the barrier layer, the insertion layer and the channel layer, and the bottom of the groove is located in the channel layer;

[0015] A passivation layer, located on the barrier layer; wherein, along the gate width direction, a gate groove penetrating through the passivation layer is provided, and a plurality of the grooves are located under the gate groove;

[0016] A gate electrode, located in a plurality of the grooves and the gate groove, and on the surface of a part of the passivation layer;

[0017] Wherein, the side length of the groove close to the source electrode is greater than the side length of the groove close to the drain electrode.

[0018] In an embodiment of the present invention, the grooves and the unetched areas are arranged periodically.

[0019] In an embodiment of the present invention, the area ratio of the grooves to the unetched areas within one period is 1:1.

[0020] In an embodiment of the present invention, the included angle between the side of the groove close to the source electrode and its adjacent side ranges from 70° to 90°.

[0021] The present invention provides a preparation method of a low-voltage terminal device based on gate field modulation, including:

[0022] S1: Grow a buffer layer, a channel layer, an insertion layer and a barrier layer on the substrate layer in sequence;

[0023] S2: Prepare a source electrode at one end of the channel layer and a drain electrode at the other end;

[0024] S3: Grow a passivation layer on the barrier layer;

[0025] S4: Along the gate width direction, etch the passivation layer located between the source and the drain to form a gate trench penetrating the passivation layer;

[0026] S5: Etch the barrier layer, the insertion layer and the channel layer located below the gate trench to form a plurality of grooves arranged at intervals along the gate width direction;

[0027] S6: Deposit gate metal in the plurality of grooves, in the gate trench and on part of the passivation layer to form a gate electrode;

[0028] S7: Fabricate a metal interconnection layer between the source and the drain;

[0029] Wherein, the bottom of the groove is located in the channel layer, and the side length of the groove close to the source is greater than the side length of the groove close to the drain.

[0030] In an embodiment of the present invention, in the S5, the grooves and the unetched regions are arranged periodically, and the area ratio of the grooves to the unetched regions within one period is 1:1.

[0031] In an embodiment of the present invention, in the S5, the included angle between the side of the groove close to the source and its adjacent side ranges from 70° to 90°.

[0032] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0033] The low-voltage terminal device based on gate field modulation of the present invention is provided with an asymmetric divergent nano-channel. When the channel is narrower near the source end and wider near the drain end, its knee voltage is lower than that of the Fin-HEMT device with a traditional rectangular symmetric channel. Moreover, as the degree of channel divergence increases, the electric field component in the source-drain direction in the channel further increases, and the knee voltage further decreases.

[0034] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following specific embodiments are given, and in conjunction with the drawings, the details are described as follows. Brief Description of the Drawings

[0035] Figure 1 It is a top view schematic diagram of a low-voltage terminal device based on gate field modulation provided by an embodiment of the present invention;

[0036] Figures 2a - 2bIt is a cross-sectional schematic diagram of a low-voltage terminal device based on field modulation under the gate provided by an embodiment of the present invention;

[0037] Figure 3 It is a schematic diagram of a preparation method of a low-voltage terminal device based on field modulation under the gate provided by an embodiment of the present invention. Detailed implementation manners

[0038] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the following will, in conjunction with the accompanying drawings and specific implementation manners, provide a detailed description of a low-voltage terminal device based on field modulation under the gate and its preparation method according to the present invention.

[0039] The foregoing and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description in conjunction with the accompanying drawings. Through the description of the specific implementation manners, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are only for reference and illustration, and are not used to limit the technical solutions of the present invention.

[0040] Embodiment 1

[0041] Please refer to Figure 1 , Figure 2a and Figure 2b , Figure 1 which is a top view schematic diagram of a low-voltage terminal device based on field modulation under the gate provided by an embodiment of the present invention, Figures 2a - 2b which is a cross-sectional schematic diagram of a low-voltage terminal device based on field modulation under the gate provided by an embodiment of the present invention. As shown in the figure, the low-voltage terminal device based on field modulation under the gate of this embodiment includes: a substrate layer 1, a buffer layer 2, a channel layer 3, a source electrode 4, a drain electrode 5, an insertion layer 6, a barrier layer 7, a passivation layer 8 and a gate electrode 9. A two-dimensional electron gas channel is formed between the channel layer 3 and the insertion layer 6.

[0042] Specifically, the substrate layer 1 includes one of sapphire, SiC or Si. The buffer layer 2 is located on the substrate layer 1, and its material can be GaN. The channel layer 3 is located on the buffer layer 2, and its material is i-GaN. The source electrode 4 is located at one end of the channel layer 3; the drain electrode 5 is located at the other end of the channel layer 3. The materials of the source electrode 4 and the drain electrode 5 are ohmic metals, which are Ti / Al / Ni / Au from bottom to top in sequence. The insertion layer 6 is located on the channel layer 3 and between the source electrode 4 and the drain electrode 5, and the material of the insertion layer 6 is AlN. The barrier layer 7 is located on the insertion layer 6, and the material of the barrier layer 7 can be AlGaN or InAlN, etc. The passivation layer 8 is located on the barrier layer 7, and the material of the passivation layer 8 is SiN, and its thickness is 120 nm.

[0043] Further, along the gate width direction, a plurality of grooves 10 are arranged at intervals in the barrier layer 7, the insertion layer 6, and the channel layer 3, and the bottom of the groove 10 is located in the channel layer 3.

[0044] Further, along the gate width direction, a gate groove 11 penetrating the passivation layer 8 is provided to expose the surface of the barrier layer 7, and a plurality of grooves 10 are located under the gate groove 11.

[0045] Further, a gate electrode 9 is provided in a plurality of grooves 10 and the gate groove 11, and on the surface of a part of the passivation layer 8. As Figure 2a and 2b shown, the gate feet of the gate electrode 9 in the groove 10 are in contact with the channel layer 3, and the gate feet of the gate electrode 9 in the gate groove 11 are in contact with the barrier layer 7.

[0046] In this embodiment, the side length of the groove 10 close to the source electrode 4 is greater than its side length close to the drain electrode 5. The groove 10 forms an asymmetric nano-channel (unetched area) for the two-dimensional electron gas channel, that is, the channel close to the source end is narrower, and the channel close to the drain end is wider.

[0047] In a specific embodiment, the groove 10 has a trapezoidal structure, and the lower base of the trapezoid is on the side close to the source electrode 4, and the upper base is on the side close to the drain electrode 5.

[0048] Further, in this embodiment, the range of the angle between the side of the groove 10 close to the source electrode 4 and its adjacent side is 70° to 90°

[0049] Further, the grooves 10 (i.e., the etched areas) and the unetched areas are arranged periodically. Specifically, along the gate width direction, the barrier layer 7 is divided into a plurality of periods. Preferably, the lengths of each period are the same. In each period, a part of the barrier layer 7, the insertion layer 6, and the channel layer 3 are etched away to form at least one groove 10, and another part of the barrier layer 7, the insertion layer 6, and the channel layer 3 are not etched away to form at least one unetched area.

[0050] It should be noted that the area ratio of the groove 10 (i.e., the etched area) to the unetched area within one period is 1:1.

[0051] The low-voltage terminal device based on gate field modulation in this embodiment forms an asymmetric divergent nano-channel by etching, affects the distribution of the channel electric field by changing the shape of the side gate, and further regulates the knee voltage, so that its knee voltage is lower than that of the Fin-HEMT device with a traditional rectangular symmetric channel, so as to achieve a larger output power.

[0052] Specifically, in this embodiment, the nanoscale channel is designed to be divergent, that is, the channel is narrower near the source end and wider near the drain end. Due to its unique channel shape design, the electric field component in the source-drain direction of the effective electron acceleration region in the channel is greater than that of the traditional rectangular symmetric channel. It has the effect of enhancing the electric field component in the source-drain direction of the effective electron acceleration region in the channel, and can better promote the drift motion of electrons from the source to the drain, enabling electrons to reach velocity saturation under a small source-drain bias, and the device enters the saturation state, thereby reducing the intrinsic knee voltage of the device.

[0053] Furthermore, as the divergence degree of the channel increases, the electric field component in the source-drain direction of the effective electron acceleration region in the channel is further enhanced, enabling the device to reach the saturation state under a smaller source-drain bias, and the knee voltage of the device is further reduced.

[0054] Embodiment 2

[0055] Based on Embodiment 1, this embodiment provides a preparation method for a low-voltage terminal device based on gate field modulation. Please refer to Figure 3 , Figure 3 which is a schematic diagram of a preparation method for a low-voltage terminal device based on gate field modulation provided by an embodiment of the present invention. As shown in the figure, the preparation method for a low-voltage terminal device based on gate field modulation in this embodiment includes:

[0056] S1: Sequentially grow a buffer layer, a channel layer, an insertion layer, and a barrier layer on the substrate layer;

[0057] Specifically, use MOCVD equipment to grow a heterojunction material on the SiC substrate. The structure of the heterojunction material from top to bottom is: 20nm Al 0.25 GaN / 1nm AlN / 400nm i-GaN / buffer / SiC substrate.

[0058] S2: Prepare a source electrode at one end of the channel layer and a drain electrode at the other end;

[0059] Specifically, use electron beam evaporation equipment to deposit an ohmic stack metal Ti / Al / Ni / Au = 20 / 160 / 55 / 45nm on the channel layer, and perform rapid thermal annealing at 820°C for 50s in an N2 atmosphere to form the source electrode and the drain electrode.

[0060] It should be noted that lithographic etching of alignment marks needs to be performed before preparing the source and drain electrodes.

[0061] S3: Grow a passivation layer on the barrier layer;

[0062] Specifically, use PECVD equipment to deposit 120nm SiN on the device surface as the passivation layer.

[0063] It should be noted that before growing the passivation layer, an ion implantation device is used to achieve device isolation.

[0064] S4: Along the gate width direction, etch the passivation layer between the source and drain to form a gate trench penetrating the passivation layer;

[0065] Specifically, first, use an ICP etching device to perform opening etching by dry etching method, and the etching gas is CF4 / O2. Secondly, use an ICP etching device to remove SiN in the gate foot region by F-based etching method, the etching gas is CF4 / O2, the flow rate is 25 / 5 sccm, the chamber pressure is 5 mTorr, the ICP upper electrode power is 80 W, the lower electrode power is 10 W, and the bias voltage is 46 V.

[0066] S5: Etch the barrier layer, insertion layer and channel layer under the gate trench to form a number of grooves arranged at intervals along the gate width direction;

[0067] In this embodiment, the bottom of the groove is located in the channel layer, and the side length of the groove close to the source is greater than the side length close to the drain. Optionally, the groove has a trapezoidal structure, and the lower base of the trapezoid is on the side close to the source, and the upper base is on the side close to the drain.

[0068] Specifically, use electron beam lithography and Cl-based etching method to completely etch away the barrier layer, that is, perform Fin pattern etching. The etching pattern inclination angle α (the angle between the side of the groove close to the source and its adjacent side) is between 90 degrees and 70 degrees, and the area ratio of the groove (i.e., the etching area) to the non-etching area in one period along the gate width direction is 1:1.

[0069] S6: Deposit gate metal in a number of grooves, in the gate trench and on part of the passivation layer to form a gate electrode;

[0070] Specifically, use an electron beam evaporation device to deposit gate stack metal on the groove, in the gate trench and on part of the passivation layer to form a gate electrode.

[0071] It should be noted that before preparing the gate electrode, it is necessary to use a PECVD device to perform N2O plasma oxidation treatment on the gate-under barrier layer material.

[0072] S7: Prepare the metal interconnection layer between the source and drain.

[0073] Specifically, use an electron beam evaporation device to deposit the interconnection metal to form the metal interconnection layer between the source and drain.

[0074] It should be noted that in this text, the terms "include", "comprise" or any other variant are intended to cover non-exclusive inclusion, so that an article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the article or device including the said element. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention.

[0075] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A low-voltage terminal device based on field modulation under the gate, characterized in that Comprising: Substrate layer; Buffer layer, located on the substrate layer; Channel layer, located on the buffer layer; Source electrode, located at one end of the channel layer; Drain electrode, located at the other end of the channel layer; Insertion layer, located on the channel layer and between the source electrode and the drain electrode; Barrier layer, located on the insertion layer; wherein, along the gate width direction, a plurality of grooves are arranged at intervals in the barrier layer, the insertion layer and the channel layer, and the bottom of the groove is located in the channel layer; Passivation layer, located on the barrier layer; wherein, along the gate width direction, a gate groove penetrating through the passivation layer is provided, and a plurality of the grooves are located under the gate groove; Gate electrode, located in a plurality of the grooves and the gate groove, and on the surface of a part of the passivation layer; Wherein, among the side lengths of the groove extending along the gate width direction, the side length close to the source electrode is greater than the side length close to the drain electrode, the unetched regions between the groove and the adjacent grooves are arranged periodically, and the area ratio of the groove and the unetched region in one period is 1:

1.

2. The low-voltage terminal device based on under-gate field modulation according to claim 1, characterized in that The included angle range between the side of the groove close to the source electrode and its adjacent side is 70° - 90°.

3. A preparation method of a low-voltage terminal device based on field modulation under a gate, characterized in that, Comprising: S1: Growing a buffer layer, a channel layer, an insertion layer and a barrier layer on the substrate layer in sequence; S2: Preparing a source electrode at one end of the channel layer and a drain electrode at the other end; S3: Growing a passivation layer on the barrier layer; S4: Etching the passivation layer located between the source electrode and the drain electrode along the gate width direction to form a gate groove penetrating through the passivation layer; S5: Etching the barrier layer, the insertion layer and the channel layer located under the gate groove to form a plurality of grooves arranged at intervals along the gate width direction; S6: Depositing gate metal in a plurality of the grooves, the gate groove and a part of the passivation layer to form a gate electrode; S7: Preparing a metal interconnection layer between the source electrode and the drain electrode; Wherein, the bottom of the groove is located in the channel layer, among the side lengths of the groove extending along the gate width direction, the side length close to the source electrode is greater than the side length close to the drain electrode, the unetched regions between the groove and the adjacent grooves are arranged periodically, and the area ratio of the groove and the unetched region in one period is 1:

1.

4. The manufacturing method of the low-voltage terminal device based on the under-gate field modulation according to claim 3, characterized in that, In the S5, the included angle range between the side of the groove close to the source electrode and its adjacent side is 70° - 90°.

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