Apparatus and related method for offset correction in electronic circuits

Abstract

The application is entitled "Device and Related Method for Offset Correction in Electronic Circuits". Specifically, a device is disclosed, which includes a first field effect transistor (FET) having a body and coupled in a circuit. The device also includes a second field FET having a body and coupled in the circuit. The circuit has an offset due to mismatch. The device further includes an offset correction circuit coupled to the body of the first FET and coupled to the body of the second FET. The offset correction circuit provides a first offset correction signal to the body of the first FET and provides a second offset correction signal to the body of the second FET.

Description

[0001] This application is a divisional application of Chinese patent application No. 201611102664.4, filed on November 29, 2016, entitled “Device and related method for offset correction in electronic circuits”. Technical Field

[0002] The present disclosure relates generally to improving the performance of electronic circuit systems and, more particularly, to apparatus and related methods for offset correction or trimming in electronic circuits. Background Art

[0003] Digital circuits and technologies have proliferated over time and become ubiquitous with advances in semiconductor processes, circuit and system technologies, etc. However, in reality, the physical world and phenomena include analog quantities. Sensing, detecting, and processing analog quantities must use a variety of analog circuits.

[0004] The performance of circuits, subsystems, and systems that include such analog circuitry depends, in part, on the performance of the analog circuitry. In practice, real-world implementations of electronic circuits, such as integrated circuits (ICs), including analog circuitry contained within the ICs, deviate from ideal behavior, with corresponding effects on their performance. Various performance measurements exist and are used to measure the performance of analog circuitry. Examples include offset, distortion, gain, noise figure, power consumption, etc.

[0005] The description in this section and any corresponding drawings are included as background information materials. The materials in this section should not be construed as an admission that such materials constitute prior art to the present patent application. Summary of the invention

[0006] Various devices and related methods are contemplated for use in offset trimming in electronic circuit systems. According to an exemplary embodiment, a device includes a first field effect transistor (FET) having a body and coupled in a circuit. The device also includes a second FET having a body and coupled in the circuit. The circuit has an offset due to a mismatch. The device further includes an offset correction circuit coupled to the body of the first FET and to the body of the second FET. The offset correction circuit provides a first correction signal to the body of the first FET and provides a second correction signal to the body of the second FET.

[0007] According to another exemplary embodiment, an electronic device includes a differential amplifier including first and second transistors, each transistor having a respective body. An electrical characteristic of the first transistor is different from an electrical characteristic of the second transistor. The electronic device also includes an offset correction circuit, the offset correction circuit including a current source and third and fourth transistors coupled to the first current source. The offset correction circuit further includes a network of a set of switches and a set of resistors, the set of switches and the set of resistors coupled to the third and fourth transistors to provide first and second offset correction signals to the body of the first transistor and the body of the second transistor, respectively.

[0008] According to another illustrative embodiment, a method of correcting offset in a circuit including first and second field effect transistors (FETs) is disclosed, wherein the circuit has an offset due to mismatch. The method includes generating a first offset correction signal, and generating a second offset correction signal. The method also includes applying the first offset correction signal to a body of the first FET, and applying the second offset correction signal to a body of the second FET. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings illustrate only exemplary embodiments and therefore should not be considered to limit the scope of the present application or claims. One of ordinary skill in the art recognizes that the disclosed concepts lend themselves to other embodiments with the same effect. In the accompanying drawings, the same numerical designator used in more than one drawing represents the same, similar or equivalent function, component or box.

[0010] Figure 1 A circuit arrangement for offset correction is described according to an exemplary embodiment.

[0011] Figure 2 Applying an offset correction voltage to the bulk or body of transistors is described in accordance with an exemplary embodiment.

[0012] Figure 3 According to a further exemplary embodiment, a circuit arrangement for offset correction is shown.

[0013] Figure 4 According to a further exemplary embodiment, a circuit arrangement for offset correction is described.

[0014] Figure 5 According to a further exemplary embodiment, a circuit arrangement for offset correction is described.

[0015] Figure 6 According to a further exemplary embodiment, a circuit arrangement for offset correction is described. DETAILED DESCRIPTION

[0016] The disclosed concepts generally relate to apparatus and methods for offset trimming in electronic circuit systems. An offset (such as an offset voltage) exists in an electronic circuit system due to mismatches between various components (such as transistors, resistors, capacitors, various semiconductors (e.g., diodes), manufacturing defects, etc. For example, when two transistors (such as field effect transistors (FETs), metal oxide semiconductor (MOS) transistors, or metal oxide FETs (MOSFETs)) have different characteristics, a circuit including the transistors may exhibit a mismatch that produces an offset in the circuit including the two transistors. In addition or alternatively, mismatches between various elements or components (or sets of mismatch conditions between or among various groups of components or elements) may cause an offset that increases or contributes to an offset caused by mismatches between other components or elements, thereby producing an overall or cumulative offset of the circuit including these components or elements.

[0017] As an example, if two transistors are coupled as a differential pair (or differential amplifier), if the input voltages are equal (e.g., zero or grounded), then the output voltage of the differential pair should be zero. However, due to actual non-ideal implementations of transistors (such as MOSFETs), actual differential pairs may have a finite (i.e., non-zero) output voltage even when the inputs of the differential pair have the same voltage. This finite output voltage caused by the mismatch between the transistors constitutes an offset voltage. Other types of mismatches or other mismatch conditions between or among various elements or components may also produce offsets. For example, in the case of a differential pair, the load circuits (e.g., resistors) for the corresponding two transistors in the differential pair may also produce or contribute to the offset.

[0018] As another example, consider an operational amplifier coupled in a unity gain configuration (i.e., the output is coupled to the inverting input). In such a configuration, grounding the non-inverting input should ideally produce a zero output. However, in practice, a grounded (i.e., zero volts) non-inverting input typically produces a finite (non-zero) output signal. This output signal constitutes the output offset voltage of the unity gain configuration.

[0019] Generally, one can think of the offset voltage as a voltage applied at the input to produce a zero output. More specifically, considering a differential pair as described above, the offset voltage constitutes a differential voltage applied at the input of the differential pair that will produce a zero signal at the output of the differential pair.

[0020] As described above, the offset voltage can be taken as an input to the circuit by considering the unity gain of the operational amplifier whose output is coupled to its inverting input. In other words, due to the non-inverting nature of the circuit, an input signal equal to the offset voltage will produce a zero output signal.

[0021] One aspect of the disclosed concept relates to apparatus and methods for offset correction or trimming (such as the offset voltage described above) in electronic circuit systems. The disclosed offset correction or trimming techniques do not use clock signals, which results in relatively low power consumption of such circuits. The lower power consumption of the offset correction or trimming circuit beneficially affects the overall power consumption of the device including the offset trimming circuit.

[0022] Furthermore, the disclosed techniques have less impact on performance metrics in certain applications. For example, when applied to a differential pair, the disclosed offset trimming techniques affect the common mode rejection performance of the differential pair when compared to techniques such as trimming transistor geometry or the magnitude of transistor drain current.

[0023] Figure 1 A circuit arrangement 100 for offset correction is described according to an exemplary embodiment. Circuit arrangement 100 includes an IC 103, which includes various types of circuitry, including transistors 106A-106B. Each of transistors 106A-106B has a drain, a source, a gate, and a bulk or body. The drains of transistors 106A-106B are coupled to other circuitry in IC 103, which are labeled 109A and 109D, respectively. The sources of transistors 106A-106B are coupled to other circuitry in IC 103, which are labeled 109B and 109C, respectively.

[0024] As will be appreciated by one of ordinary skill in the art, other circuitry 109A-109D may include various circuits, devices, subsystems, systems, blocks of transistors, circuit blocks, etc., as desired. As will be appreciated by one of ordinary skill in the art, the quality and quantity of the circuitry in other circuitry 109A-109D depends on factors such as the desired or particular functionality of circuit arrangement 100. Examples include bias circuits, decoupling circuits, coupling circuits, power supply circuits, current mirrors, current and / or voltage sources, filters, amplifiers, converters (e.g., analog-to-digital converters (ADCs) and digital-to-analog converters (DACs)), signal processing circuits (e.g., multipliers), detectors, etc.

[0025] As one of ordinary skill in the art will appreciate, the gates of transistors 106A-106B are driven by circuitry (not shown) to provide bias, input voltage, etc. As one of ordinary skill in the art will appreciate, the details of the circuitry that drives the gates of transistors 106A-106B depend on factors such as the desired or particular functionality of circuit arrangement 100.

[0026] As just one example, in some embodiments, transistors 106A-106B may be used in an amplifier. In such scenarios, one or more input voltages (e.g., differential input voltages including positive and negative voltages with respect to power supply ground (Vss)) may drive the gates of transistors 106A-106B. As will be appreciated by one of ordinary skill in the art, other configurations may be used depending on factors such as the desired functionality, specifications, or overall performance of circuit arrangement 100.

[0027] As will be appreciated by one of ordinary skill in the art, transistors 106A-106B are similar to one another, but in actual implementations, they have limited differences from one another that produce an offset signal, such as an offset voltage. In other words, although circuit designers typically attempt to match transistors 106A-106B so that they have the same characteristics, such as electrical characteristics (e.g., threshold voltage), in actual implementations, transistors 106A-106B often do not have the same characteristics, i.e., there is a mismatch between transistors 106A-106B. As discussed above, one or more offset signals may also be caused by mismatches between other circuit components or elements. For example, mismatches between other circuit systems 109A and 109D, between other circuit systems 109B and 109C, and / or between other circuit components or elements in the circuit may produce one or more offset signals. Therefore, in general, the mismatch between transistors 106A-106B may constitute only one source of offset in the circuit, and other sources of offset may exist and contribute to the overall or cumulative offset of the circuit. As will be appreciated by one of ordinary skill in the art, similar comments apply to Figure 2-Figure 6 The circuit layout in, and almost all practical circuit implementations.

[0028] As described above, due to differences in the characteristics of transistors 106A-106B and / or other circuit components or elements, one or more offset signals, such as an offset voltage, may be caused. As described in detail below, offset correction circuit 112 trims or corrects the offset voltage (or substantially trims or corrects the offset in actual real-world implementations).

[0029] As noted, as described above, in various embodiments, some circuits in IC 103 use transistors, such as MOSFETs 106A-106B. The drain current of a MOSFET in the saturation region of operation depends on the threshold voltage and gate-to-source voltage of the transistor, i.e.

[0030] i D =K(v GS -V T ) 2 ,

[0031] where i Dconstitutes the total drain current (i.e., including both AC and DC components), K represents a constant, v GS constitutes the total gate-to-source voltage (i.e., including both AC and DC components), and V T represents the threshold voltage. (Note that for the purpose of clarity of the present concept, the above equation omits the dependence of the drain current on the drain-source voltage).

[0032] MOSFETs typically have two transconductance quantities associated with them. One transconductance depends on the gate-source voltage v GS The other transconductance depends on the stack-source voltage v BS The total transconductance of the MOSFET depends on v GS and v BS Both.

[0033] More specifically, the total transconductance g m,overall can be expressed as:

[0034]

[0035] (Assume that the partial derivative constant v GS and the constant v BS ).

[0036] Differently expressed as,

[0037] g m,overall =g m +g mbs ,

[0038] in

[0039]

[0040] as well as

[0041]

[0042] Therefore, as mentioned above, the transconductance of a MOSFET depends not only on the gate-source voltage (v GS ), and also depends on the bulk-gate (or stack-gate) voltage (v BS ).

[0043] Therefore, the drain current depends on the gate-source voltage (v GS ) and the bulk-gate (or stack-gate) voltage (v BS ):

[0044] i D =g m v GS +g mbs v BS .

[0045] If the offset voltage is referred to as the gate voltage v osi , then the additional offset trimming or correction voltage v applied to the stack btrim can be used for offset correction. The effect on the drain current can be expressed as:

[0046] i D =g m (v GS +v osi )+g mbs (v GS +v btrim ).

[0047] Select v btrim A specific value of may cause the offset to be trimmed or corrected. More specifically, the offset is trimmed or corrected if the following conditions exist:

[0048]

[0049] The offset correction circuit 112 converts v btrim The value of is applied to the stack or body of the MOSFET, thereby trimming or correcting the offset voltage (or in actual real-world implementations, fully trimming or correcting the offset, i.e., trimming or correcting to a value close to zero, or reducing the offset voltage by a percentage such as 70%, 80%, 90%, etc.).

[0050] In some embodiments, the offset correction voltage v btrim The offset correction voltage may be applied to the two transistors as a differential voltage, the difference between the two transistors producing the offset. In some embodiments, the offset correction voltage may be applied to one transistor (e.g., as a single-ended voltage about a ground potential (e.g., Vss)), the difference between the transistor and the other transistor producing the offset.

[0051] Figure 2 The application of an offset correction voltage to a stack or body of two transistors is described in accordance with an exemplary embodiment. More specifically, Figure 2 A cross section of IC 103 is illustrated including transistors 106A and 106B and offset correction circuit 112. The difference between transistors 106A-106B produces an offset, such as an offset voltage.

[0052] Reference again Figure 2 , in IC 103, transistor 106A is implemented in a semiconductor stack that constitutes the body of transistor 106A. As will be appreciated by one of ordinary skill in the art, the stack or body of transistor 106A is appropriately doped to provide the desired characteristics of transistor 106A. For example, for n-channel transistor 106A, the body is doped with p-type impurities or additives.

[0053] Transistor 106A also includes a source region and a drain region, denoted as "S" and "D," respectively. As will be appreciated by one of ordinary skill in the art, the source region and the drain region have a doping type opposite to the doping of the body of transistor 106A. For example, for an n-channel transistor 106A, the source region and the drain region will have an n-type doping.

[0054] Transistor 106A also includes a gate. Figure 2 As will be appreciated by one of ordinary skill in the art, the gate of transistor 106A is formed over an insulating layer (eg, silicon dioxide).

[0055] Offset correction circuit 112 provides offset correction voltage 112A to transistor 106A. More specifically, offset correction circuit 112 applies offset correction voltage 112A to the body or stack of transistor 106A to correct the offset described above.

[0056] As noted, IC 103 also includes transistor 106B. In IC 103, transistor 106B is implemented in a semiconductor stack that constitutes the body of transistor 106B. As will be appreciated by one of ordinary skill in the art, the stack or body of transistor 106B is appropriately doped to provide the desired characteristics of transistor 106B. For example, for n-channel transistor 106B, the body is doped with p-type impurities or additives.

[0057] Transistor 106B also includes a source region and a drain region, denoted as "S" and "D," respectively. As will be appreciated by one of ordinary skill in the art, the source and drain regions have a doping type opposite to the doping of the body of transistor 106B. For example, for an n-channel transistor 106B, the source and drain regions would have an n-type doping.

[0058] Transistor 106B also includes a gate. Figure 2 As will be appreciated by one of ordinary skill in the art, the gate of transistor 106B is formed over an insulating layer (eg, silicon dioxide).

[0059] The offset correction circuit 112 provides an offset correction voltage 112B to the transistor 106B. More specifically, the offset correction circuit 112 applies the offset correction voltage 112B to the body or stack of the transistor 106B to correct the offset.

[0060] Note that for clarity purposes, Figure 2 The offset correction circuit 112 is shown as a block rather than a collection of mutually coupled transistors, devices (eg, resistors), interconnects, etc. However, as one of ordinary skill in the art will appreciate, in a physical implementation, the offset correction circuit 112 includes a set of transistors, devices, etc.

[0061] Note further that although Figure 2 Transistors 106A-106B are shown implemented in a stack of IC 103, but the structure used to implement transistors 106A-106B may include features to provide isolation (e.g., isolation islands) between the bodies or stacks of transistors 106A-106B. The isolation between the bodies of transistors 106A-106B allows offset correction circuit 112 to provide different offset correction signals (e.g., signals 112A and 112B, respectively, in the exemplary embodiment shown) to transistors 106A-106B, respectively.

[0062] Note further that although Figure 1-Figure 2 The circuit arrangement in FIG. 1 uses N-type MOS (NMOS) transistors 106A-106B, however other variations are possible and contemplated. For example, as will be appreciated by one of ordinary skill in the art, in some embodiments, rather than using NMOS transistors, P-type MOS (PMOS) transistors 106A-106B may be used with appropriate modifications. Such modifications may include reversing the drain and source of transistors 106A-106B, changing the polarity of offset correction signals 112A-112B, etc.

[0063] Another aspect of the present disclosure relates to the generation of (multiple) offset correction signals (such as the offset correction voltage v btrim ) is a refinement of the transistor stack or body. This refinement takes into account the btrim Caused by changes in MOSFET characteristics.

[0064] More specifically, as noted above, offset correction circuit 112 applies a voltage to a MOSFET in IC 103 (such as Figure 1 106A-106B in the exemplary embodiment shown in FIG. 10A . Changing the bulk or stack voltage of a MOSFET affects its various performance characteristics, such as leakage level (and therefore power consumption), threshold voltage, operating speed, etc. In some embodiments, as described in detail below, those changes are useful in setting the value of the offset correction or trim voltage (e.g., v btrim ) is considered.

[0065] Threshold voltage V T This in turn depends on several factors, such as the voltage between the body and source of the MOSFET, which is mathematically expressed as

[0066]

[0067] Or alternatively, according to the source to body voltage v SBIt is expressed as:

[0068]

[0069] In the above equation, V T(0) represents the threshold voltage when the source-to-body voltage (or body-to-source voltage) is set to zero, γ represents the body factor (a constant that depends on the doping level of the body of the MOSFET), and φ F represents a constant, v BS represents the total body-to-source voltage (i.e., including both AC and DC components), and V SB represents the total source-to-bulk voltage (i.e., including both AC and DC components). As proposed above, and as shown in the above equation, when the bulk-to-source voltage v BS When the threshold voltage V T Equal to V T(0) .

[0070] Also note that according to the above equation, for a finite non-zero body factor γ, the threshold voltage increases with the body-to-source voltage v BS The threshold voltage V T The decrease in drain current i D (Assuming that the given v GS value). Therefore, considering the constant gate-to-source voltage v GS , increasing the body-to-source voltage v BS , resulting in a transconductance g m (That is, the amount {2K(v GS -V T )})Increase.

[0071] In general, a change in the bulk-to-source voltage of a transistor (e.g., by applying an offset correction signal such as v btrim ) causes a change in the threshold voltage of the transistor. Considering the transconductance (i.e., g) related to the gate-to-source voltage m ) depends on the threshold voltage. Applying an offset correction signal will result in g m change.

[0072] In addition, as mentioned above, due to v btrim Selected as g m function, so since v btrim g applied to the body of the transistor m The change in v can be taken into account when selecting the value of the offset correction signal provided by the offset correction circuit 112. Therefore, the selected v btrim The value of can be refined to include a finite body-to-source voltage v BS impact.

[0073] Offsets (such as offset voltages) occur in various analog circuits. Therefore, offset correction techniques according to various embodiments can be used in various electronic circuit systems including analog circuit systems (e.g., amplifiers, adders, current and voltage sources, etc.) or mixed signal circuit systems (e.g., analog-to-digital converters (ADCs), digital-to-analog converters (DACs), etc.).

[0074] In some embodiments, the offset correction circuit system can be used in a circuit system integrated in an IC, which can be used in various circuits, blocks, subsystems, and systems as needed. In a non-limiting case, examples include general amplifiers, rail-to-rail amplifiers, low noise amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), comparators, filters, analog signal processing circuit systems, power amplifiers, etc.

[0075] One aspect of the present disclosure relates to offset correction in an amplifier. Figure 3 A circuit configuration 120 for offset correction in an amplifier is shown according to an exemplary embodiment.

[0076] More specifically, circuit configuration 120 includes a differential amplifier (or differential pair) integrated in IC 103. The differential amplifier includes transistors 106A-106B. A differential input voltage is applied to the gates of transistors 106A-106B, respectively. In other words, the input voltage v in+ The gate of the driving transistor 106A is driven by the input voltage v in- The gate of the driving transistor 106B.

[0077] The sources of transistors 106A-106B are driven by current source 123. Note that in some embodiments, instead of using current source 123, MOSFETs are typically used to provide tail current for transistors 106A-106B. Similar descriptions apply to Figure 4-Figure 6 The circuit layout in .

[0078] Reference again Figure 3 , the drains of transistors 106A-106B are coupled to other circuit systems 109B and 109C, respectively. The differential output voltage v o is provided between the drains of transistors 106A-106B.

[0079] As noted above, the differences between transistors 106A-106B (i.e., not being perfectly matched, which is the case in real-world implementations) produce an offset voltage in the differential amplifier. As noted above, other mismatches in the circuit may also contribute to an overall or cumulative offset in the circuit. Offset correction circuit 112 may be used to trim or correct an offset voltage, e.g., an input-referred offset of the differential amplifier.

[0080] More specifically, offset correction circuit 112 provides an offset correction signal (voltage in the example shown) 112A to the stack or body of transistor 106A. Similarly, offset correction circuit 112 provides an offset correction signal (voltage in the example shown) 112B to the stack or body of transistor 106B.

[0081] As described above, the magnitude of the offset correction signals 112A-112B may be derived, set, configured, or programmed. Applying the offset correction signals 112A-112B to the stack or body of transistors 106A-106B, respectively, trims or corrects the offset in the differential amplifier.

[0082] Note that although Figure 3 The circuit arrangement 120 in the embodiment uses PMOS transistors 106A-106B, however other variations are possible or contemplated. For example, as will be appreciated by one of ordinary skill in the art, in some embodiments, rather than using PMOS transistors, NMOS transistors 106A-106B may be used with appropriate modifications. Such modifications may include reversing the role of supply voltage and ground, changing the polarity of offset correction signals 112A-112B, and reversing the current through overcurrent source 123, etc.

[0083] In an exemplary embodiment, the offset correction circuit 112 may be implemented in a variety of ways to accommodate various desired features, specifications, performance criteria, and the like. Figure 4-Figure 6 Provide some examples.

[0084] Figure 4 A circuit arrangement 130 for offset correction is described according to an exemplary embodiment. The circuit arrangement 130 applies offset correction to a differential amplifier. The differential amplifier includes a Figure 3 The drains of transistors 106A-106B are coupled to other circuitry 109B-109C, respectively.

[0085] Reference again Figure 4, offset correction circuit 112 provides offset correction signal 112A to the stack or body of transistor 106A. Similarly, offset correction circuit 112 provides offset correction signal 112B to the stack or body of transistor 106B. As described in detail above, offset correction signals 112A-112B trim or correct the offset voltage of the differential amplifier.

[0086] Figure 4 Details of offset correction circuit 112 are shown according to the illustrated exemplary embodiment. More specifically, offset correction circuit 112 includes transistors 136A-136B, a network of switches and resistors including a set of switches 112S coupled to a set of resistors 112R, and current source 133.

[0087] Transistors 136A-136B are configured, designed, and / or manufactured to relatively closely match transistors 106A-106B. In some embodiments, transistors 136A-136B are configured, designed, and / or manufactured to match transistors 106A-106B as closely as possible. As will be appreciated by one of ordinary skill in the art, the degree of matching between transistors 136A-136B and transistors 106A-106B depends on a variety of factors. These factors include design and performance specifications, available technology (e.g., semiconductor or IC manufacturing technology), cost constraints, and the like.

[0088] Reference again Figure 4 , transistors 136A-136B are coupled to receive the same input voltage as transistors 106A-106B. As mentioned above, transistors 106A-106B receive a differential voltage, namely v in+ is applied to the gate of transistor 106A and v in- is applied to the gate of transistor 106B.

[0089] Similarly, transistors 136A-136B are coupled to receive the differential voltage applied to the gates of transistors 106A-106B. Thus, the gate of transistor 136A is coupled to receive the voltage v in+ , and the gate of transistor 136B is coupled to receive a voltage v in- .

[0090] Since transistors 136A-136B have respective gate voltages that are the same as the gate voltages of transistors 106A-106B, offset correction circuit 112 is able to adjust the input voltage of the differential amplifier (i.e., v in =v in+ -v in-) changes. Thus, offset correction circuit 112 is capable of trimming or correcting the offset in an adaptive manner, i.e., offset correction voltages 112A-12B adapt to or respond to changes in the voltage applied to the gates of transistors 106A-106B (as described above, and also applied to the gates of transistors 136A-136B).

[0091] In other words, transistors 136A-136B are arranged in a differential source follower configuration. Thus, the offset correction voltages 112A-112B move or swing with or follow or adapt to the common mode voltage of the input voltage of the differential amplifier. Thus, the offset in the differential amplifier is trimmed or corrected.

[0092] As noted, the offset correction circuit 112 includes a network of switches and resistors, including a set of switches 112S coupled to a set of resistors 112R, such as Figure 4 Current source 133 provides a current that flows through the network of switches and resistors, i.e., through the set of switches 112S and the set of resistors 112R, and through transistor 136A and / or transistor 136B (depending on the magnitude of the voltage applied to the respective gates of transistors 136A-136B, i.e., the input voltage to the differential amplifier).

[0093] In some embodiments, current source 133 provides an output current I given by the following equation:

[0094]

[0095] Among them, V BG and R represent the bandgap voltage and resistance of one resistor (or any resistor if they have equal resistance) in the set of resistors 112R, respectively.

[0096] The offset correction voltages 112A-112B (respectively represented by v b+ and v b- ) is derived from a tap node in a network of switches and resistors including a set of switches 112S coupled to a set of resistors 112R. As noted above, offset correction voltages 112A-112B are coupled to respective bodies or stacks of transistors 106A-106B. Thus, offset correction voltage 112A is coupled to the body of transistor 106A, while offset correction voltage 112B is coupled to the body of transistor 106B.

[0097] The magnitude of the offset correction voltages 112A-112B is determined in part by the number and position of open and closed switches in the network of switches 112S and resistors 112R. Opening or closing individual switches in the set of switches 112S produces a corresponding voltage drop across one or more resistors in the set of resistors 112R due to the current I provided by the current source 133. Thus, by closing or opening appropriate switches in the set of resistors 112S, the magnitude of the offset trim voltages 112A-112B may be set, configured, adjusted, modified, etc.

[0098] Various alternatives are contemplated according to exemplary embodiments. For example, in some embodiments, resistors 112R have the same resistance, R, while in some embodiments, resistors 112R have different resistance values, or some resistors have the same value while others have different values, and so on.

[0099] Furthermore, as will be appreciated by one of ordinary skill in the art, although switches 112S are illustrated as general single-pole single-throw switches, these switches may be implemented in a variety of ways depending on factors such as design and performance specifications, available technology, cost and / or complexity considerations, available IC area, etc. As illustrative examples, switches 112S may be implemented using MOSFETs, fuses, antifuses, laser trimmed link, etc.

[0100] In addition, the state of the switches 112S (i.e., whether they are open or closed) can be controlled or set during the manufacture, testing, and / or operation of the circuit. For example, in some embodiments, the state of the switches 112S can be controlled or set during manufacture based on the desired setting of each switch 112S. Similarly, the state of the switches 112S can be controlled or set during the testing phase of the circuit based on the measured characteristics of various circuit elements (such as transistors 106A-106B, transistors 136A-136B, etc.).

[0101] As another example, the state of switch 112S can be controlled or set during operation of the circuit (e.g., by a user of the circuit, IC, etc.) to provide additional flexibility (e.g., if the user decides to change the operating point of transistors 106A-106B, and thus change their respective transconductances). Combinations of the above techniques can also be used, as desired.

[0102] As will be appreciated by those skilled in the art, although Figure 4 The offset correction circuit 112 in the embodiment is described with respect to an amplifier, however, the offset correction circuit 112 can be used in other types of circuit systems by making appropriate modifications. As will be understood by those skilled in the art, such modifications may include changes in the number and / or value of the resistor 112R and / or the switch 112S, etc.

[0103] Note that although circuit arrangement 130 shows a differential amplifier implemented using PMOS transistors 106A-106B, other circuit arrangements are possible. For example, the offset correction technique may be applied to a differential amplifier implemented using NMOS transistors. Figure 5 A circuit arrangement 140 is illustrated for this scenario.

[0104] More specifically, circuit arrangement 140 includes a differential amplifier implemented using NMOS transistors. Circuit arrangement 140 is similar to circuit arrangement 130 (see Figure 4 ), with appropriate modifications to accommodate NMOS transistors. Figure 5 , transistors 106A-106B are NMOS transistors, as are transistors 136A-136B. The directions of current flow of current source 123 and current source 133 are reversed, etc. Offset correction circuit 112 provides offset correction signals 112A-112B to the stack or body of transistors 106A-106B, respectively.

[0105] As will be appreciated by those skilled in the art, although Figure 5 The offset correction circuit 112 in the embodiment is described with respect to an amplifier, however, the offset correction circuit 112 can be used in other types of circuit systems by making appropriate modifications. As will be understood by those skilled in the art, such modifications may include changes in the number and / or value of the resistor 112R and / or the switch 112S, etc.

[0106] The disclosed offset correction technique can also be applied to circuits including both PMOS and NMOS transistors. For example, the offset correction technique can be applied to rail-to-rail (i.e., the input can be from one supply rail (e.g., supply voltage V DD ) to another supply rail (e.g., supply ground V ss ))PMOS and NMOS transistors in differential amplifiers. Figure 6 A circuit arrangement 150 for this scenario is depicted.

[0107] The circuit arrangement 150 includes a differential amplifier or differential pair implemented using PMOS transistors 106AP-106BP. The circuit arrangement 150 also includes a differential amplifier or differential pair implemented using NMOS transistors 106AN-106BN. The use of two differential amplifiers allows the circuit arrangement 150 to provide rail-to-rail functionality.

[0108] In addition, as will be appreciated by one of ordinary skill in the art, circuit arrangement 150 includes PMOS transistors 155 and 160 and NMOS transistors 165 and 170 to facilitate rail-to-rail functionality. In response to a DC bias, PMOS transistor 155 provides a tail current. When the input signal swings from one supply rail to another, PMOS transistor 160 is used to steer the tail current between the above-mentioned PMOS and NMOS differential pairs.

[0109] The diode-connected NMOS transistor 165 has the same drain current as the PMOS transistor 160 (or approximately the same due to a circuit defect). The NMOS transistor 165 and the PMOS transistor 170 are coupled in a current mirror configuration. Therefore, the NMOS transistor 170 has the same drain current as the NMOS transistor 165 (or approximately the same due to a circuit defect).

[0110] The current arrangement 150 also includes an offset correction circuit 112P and an offset correction circuit 112N. The offset correction circuit 112P provides offset correction signals 112AP and 112BP to a differential amplifier including PMOS transistors 106AP-106BP. Conversely, the offset correction circuit 112N provides offset correction signals 112AN and 112BN to a differential amplifier including NMOS transistors 106AN-106BN.

[0111] Generally, the offset correction circuit 112P can be implemented in various ways. For example, the offset correction circuit 112P can be implemented as follows: Figure 4 Again, refer to Figure 6 In general, the offset correction circuit 112N can be implemented in various ways. For example, the offset correction circuit 112N can be implemented as follows: Figure 5 Implement as shown.

[0112] Reference again Figure 6 , considering the offset correction circuit 112P as Figure 4 The offset correction circuit 112N is implemented as shown and Figure 5 When the tail current is steered between the differential amplifier including PMOS transistors 106AP-106BP and the differential amplifier including NMOS transistors 106AN-106BN, the DC bias of the corresponding PMOS and NMOS transistors in offset correction circuit 112P and offset correction circuit 112N, respectively, does not change. Therefore, offset correction voltages 112AP, 112BP, 112AN, 112BN trim or correct the offset correction of the corresponding PMOS implemented differential amplifier and NMOS implemented differential amplifier.

[0113] As will be appreciated by those skilled in the art, although Figure 6 The offset correction circuits 112P-112N in the embodiment are described with respect to amplifiers, however, the offset correction circuits 112P-112N can be used in other types of circuit systems by making appropriate modifications. For example, as will be understood by one of ordinary skill in the art, such modifications may include changes in the number and / or value of resistors 112R and / or switches 112S, etc.

[0114] The offset correction circuit in various embodiments according to the present disclosure provides a variety of benefits. Because the offset correction circuit does not use clock or digital switching circuitry, it allows operation with low power consumption or in low power consumption circuitry. More specifically, as the switching frequency of transistors in the circuitry increases, MOS circuitry (including complementary MOS (CMOS) circuitry) uses more power. By using static circuitry rather than using switching circuitry, the offset correction circuit according to the present disclosure provides lower power operation.

[0115] Furthermore, the offset correction circuit according to the present disclosure provides less impact on common mode rejection performance.As will be appreciated by those of ordinary skill in the art, common mode rejection is an index of the strength or characteristic of electronic circuit systems, such as amplifiers, particularly differential amplifiers.

[0116] As will be appreciated by those of ordinary skill in the art, one can effectively apply the concepts of the present disclosure to a variety of circuit arrangements and electronic circuit systems. Some of the examples described in this document (which relate to offset correction in amplifiers such as differential pairs) constitute only illustrative applications. As will be appreciated by those of ordinary skill in the art, such examples are not intended to limit the application of the concepts of the present disclosure to other circuits by making appropriate modifications.

[0117] With reference to the accompanying drawings, those of ordinary skill in the art will note that the various blocks shown may primarily describe conceptual functions and signal flows. Actual circuit implementations may or may not include individually identifiable hardware for various functional blocks, and may or may not use the specific circuits shown. For example, as desired, one may combine the functions of the various blocks into one circuit block. In addition, as desired, one may implement the functions of a single block in several circuit blocks. The selection of circuit implementations depends on various factors, such as the specific design and performance specifications for a given implementation. In addition to those described herein, other modifications or alternative embodiments will be apparent to those of ordinary skill in the art. Therefore, this specification teaches those skilled in the art how to implement the disclosed concepts, and is interpreted as being illustrative only. As will be appreciated by those of ordinary skill in the art, the drawings may be drawn to scale or may not be drawn to scale, as the case may be.

[0118] The forms and embodiments shown and described should be taken as illustrative embodiments. Those skilled in the art may make various modifications in the shapes, sizes and arrangements of the parts without departing from the scope of the concepts disclosed in this document. For example, those skilled in the art may replace the elements illustrated or described herein with equivalent elements. In addition, those skilled in the art may use certain features of the disclosed concepts independently of the use of other features without departing from the scope of the disclosed concepts.

Claims

1. A device for offset correction in an electronic circuit, the device comprising: a differential amplifier comprising a first field effect transistor (i.e., a first FET) and a second field effect transistor (i.e., a second FET), wherein the differential amplifier has an offset between the first FET and the second FET due to mismatch; An offset correction circuit comprising a third FET and a fourth FET coupled in a source follower configuration, the offset correction circuit being coupled to the body of the first FET and to the body of the second FET so as to provide a first offset correction signal to the body of the first FET and a second offset correction signal to the body of the second FET.

2. The apparatus of claim 1, wherein applying the first offset correction to the body of the first FET changes a first transconductance of the first FET.

3. The apparatus of claim 2, wherein applying the second offset correction to the body of the second FET changes a first transconductance of the second FET.

4. The apparatus of claim 2, wherein the first transconductance of the first FET depends on a voltage between the body of the first FET and a gate of the first FET.

5. The apparatus of claim 3, wherein the first transconductance of the second FET depends on a voltage between the body of the second FET and a gate of the second FET.

6. The device of claim 1, wherein the first FET comprises a metal oxide semiconductor FET (MOSFET), and wherein the second FET comprises a MOSFET.

7. The apparatus of claim 1, wherein the differential amplifier is coupled to a current source and other circuits.

8. The apparatus of claim 1 , wherein the offset correction circuit further comprises a set of switches and a set of resistors coupled to the third FET and the fourth FET so as to provide the first offset correction signal to the body of the first FET and to provide the second offset correction signal to the body of the second FET.

9. An electronic device comprising: a first differential amplifier comprising a first PMOS transistor and a second PMOS transistor, the first transistor having a body and the second transistor having a body, wherein an electrical characteristic of the first transistor is different from an electrical characteristic of the second transistor; and A first offset correction circuit adaptively corrects an offset voltage of the first differential amplifier, wherein the first offset correction circuit includes a pair of field effect transistors (FETs) coupled in a source follower configuration.

10. The electronic device of claim 9, wherein the first offset correction circuit provides a first offset correction signal and a second offset correction signal to the body of the first PMOS transistor and the body of the second PMOS transistor, respectively, to change a body-to-source voltage of the first PMOS transistor and to change a body-to-source voltage of the second PMOS transistor. 11 . The electronic device of claim 10 , wherein the first offset correction signal and the second offset correction signal are responsive to changes in voltages applied to gates of the first PMOS transistor and the second PMOS transistor.

12. The electronic device according to claim 9, further comprising: a second differential amplifier coupled to the first differential amplifier to provide a differential amplifier rail-to-rail function, the second differential amplifier comprising a first N-type metal oxide semiconductor transistor, i.e., a first NMOS transistor, and a second N-type metal oxide semiconductor transistor, i.e., a second NMOS transistor; and A second offset correction circuit adaptively corrects an offset voltage of the second differential amplifier.

13. The electronic device of claim 12 , wherein the second offset correction circuit provides a first offset correction signal and a second offset correction signal to the body of the first NMOS transistor and the body of the second NMOS transistor, respectively, to change a body-to-source voltage of the first NMOS transistor and to change a body-to-source voltage of the second NMOS transistor.

14. The electronic device of claim 13, wherein the first offset correction signal and the second offset correction signal of the second offset correction circuit are responsive to changes in voltages applied to gates of the first NMOS transistor and the second NMOS transistor.

15. A method of correcting an offset in a differential amplifier comprising a first field effect transistor (a first FET) and a second field effect transistor (a second FET), wherein the differential amplifier has an offset due to a mismatch, the method comprising: generating a first offset correction signal by using an offset correction circuit including a third FET and a fourth FET coupled in a source follower configuration; generating a second offset correction signal by using the offset correction circuit; applying the first offset correction signal to a body of the first FET in the differential amplifier; as well as The second offset correction signal is applied to the body of the second FET in the differential amplifier.

16. The method of claim 15, wherein applying the first offset correction to the body of the first FET changes a transconductance of the first FET.

17. The method of claim 16, wherein applying the second offset correction to the body of the second FET changes the transconductance of the second FET.

18. The method of claim 17, wherein the transconductance of the first FET depends on a voltage between the body of the first FET and a gate of the first FET.

19. The method of claim 18, wherein the transconductance of the second FET depends on a voltage between the body of the second FET and a gate of the second FET.

20. The method of claim 15, wherein the differential amplifier is coupled to a current source and other circuits.

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