MASH Structure ΔΣ Modulator with Inter-Stage Noise Coupling Technology

Abstract

The present invention belongs to the technical field of integrated circuits, and discloses a MASH structure ΔΣ modulator using inter-stage noise coupling technology, which includes a ΔΣ double-loop module, an inter-stage noise coupling module, and a digital filter module. The ΔΣ double-loop module includes a first-stage ΔΣ loop module and a second-stage ΔΣ loop module. The inter-stage noise coupling module includes the second-stage ΔΣ loop module and a digital delay topology unit. The quantization noise generated by the quantizer of the first-stage ΔΣ loop module is used as the input of the second-stage ΔΣ loop module. The output of the quantizer of the second-stage ΔΣ loop module passes through the digital delay topology unit and is coupled with the output of the quantizer of the first-stage ΔΣ loop module by means of a first digital subtractor. The output of the first digital subtractor is fed back to the input of the loop filter of the first-stage ΔΣ loop module through the DAC of the first-stage ΔΣ loop module.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a MASH structure ΔΣ modulator adopting an inter-stage noise coupling technique. Background Art

[0002] In the new generation of information and communication technologies, the development prospect of millimeter-wave communication base stations has given rise to a huge demand for high-speed, high-precision, and high-energy-efficiency analog-to-digital converters. The continuous time (CT) delta-sigma modulator (DSM) has achieved a good balance in terms of bandwidth, precision, and power consumption. In wireless communication applications, the continuous time delta-sigma modulator architecture has gradually replaced the pipelined architecture and has received continuous attention from the academic and industrial communities.

[0003] With the continuous advancement of CMOS process nodes, the sampling frequency allowed by the continuous time delta-sigma modulator architecture has increased year by year and is currently as high as several GHz or more. However, the bandwidth requirements of wireless communication are climbing at a faster rate, and the oversampling ratio is severely limited. Therefore, to meet the high-precision requirements, it is necessary to increase the order of the loop filter, thereby further increasing the order of noise shaping. If the order of the loop filter in the single-loop structure is blindly increased, problems of loop instability will occur. In contrast, the multi-stage noise-shaping (MASH) structure can effectively increase the order of noise shaping while ensuring stability. However, this often brings the inherent mismatch problem between analog and digital filters in the MASH architecture, resulting in a large amount of noise leakage.

[0004] Reference [1] achieved high precision of analog filter coefficients through an on-chip ultra-high-precision RC calibration network and multi-stage operational amplifiers with high gain and large bandwidth, and performed hard matching with the digital filter, achieving more than 12 effective bits without any digital calibration. However, its power consumption is relatively high, and the effect of this hard matching is greatly weakened as the signal bandwidth increases. References [2-4] adopted front-end and back-end digital calibration techniques based on the mainstream least mean square algorithm to alleviate the mismatch. However, their precision is severely limited by the calibration precision limit of the algorithm. In addition, the digital calibration network has high power consumption at a relatively high clock frequency.

[0005] [1] A. Edward et al., “A 43-mW MASH 2-2CTΔΣ Modulator Attaining 74.4dB / 75.8dB / 76.8dB SNDR / SNR / DR and 50MHz of BW in 40-nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 2, pp. 448-459, Feb. 2017.

[0006] [2] L.J. Breems et al., “A cascaded continuous-time modulator with 67-dB dynamic range in 10-MHz bandwidth,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2152-2160, Dec. 2004.

[0007] [3] Y.-S. Shu et al., “LMS-based noise leakage calibration of cascaded continuous-time ΔΣ modulators,” IEEE J. Solid-State Circuits, vol. 45, no. 2, pp. 368-379, Feb. 2010.

[0008] [4] M. Fukazawa et al., “Background multi-rate LMS calibration circuit for 15MHz-BW 74dB-DR CT 2-2MASHΔΣADC in 28nm CMOS,” in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC), pp. 166-167, Feb. 2020. Summary of the Invention

[0009] To solve the above problems, the present invention proposes a MASH - structured ΔΣ modulator using inter - stage noise coupling technology. With the help of an inter - stage noise coupling module, the quantization noise of the first - stage ΔΣ loop module is led out to the input end of the second - stage ΔΣ loop module, and then the output end of the quantizer of the second - stage ΔΣ loop module is led back to the first - stage ΔΣ loop module, that is, fed back to the output end of the quantizer of the first - stage ΔΣ loop module. The two are coupled through a subtractor to form a "self - coupling" - like branch. By reasonably selecting the transfer functions of the inter - stage noise coupling module and the digital filter module, the quantization noise generated in the first - stage ΔΣ loop module can be effectively resisted, the noise leakage caused by the mismatch between the analog and digital filters in the MASH - architecture ΔΣ modulator is greatly suppressed, the matching requirements between the analog and digital filters are significantly alleviated, and the accuracy of the MASH architecture is effectively improved while maintaining a high energy efficiency.

[0010] The present invention can be realized through the following technical solutions:

[0011] A MASH - structured ΔΣ modulator using inter - stage noise coupling technology, comprising a ΔΣ dual - loop module, an inter - stage noise coupling module, and a digital filter module.

[0012] The ΔΣ dual - loop module includes a first - stage ΔΣ loop module and a second - stage ΔΣ loop module, and the inter - stage noise coupling module includes a second - stage ΔΣ loop module and a digital delay topology unit.

[0013] Taking the quantization noise generated by the quantizer of the first - stage ΔΣ loop module as the input of the second - stage ΔΣ loop module, the output of the quantizer of the second - stage ΔΣ loop module passes through the digital delay topology unit and is coupled with the output of the quantizer of the first - stage ΔΣ loop module by means of a first digital subtractor. The output of the first digital subtractor is fed back to the input of the loop filter of the first - stage ΔΣ loop module through the DAC of the first - stage ΔΣ loop module;

[0014] The digital filter module includes a first digital filter and a second digital filter. Its input ends are respectively connected to the output ends of the first - stage ΔΣ loop module and the second - stage ΔΣ loop module, and its output ends are both connected to a second digital subtractor. The output of the second digital subtractor is used as the output of the entire MASH - structured ΔΣ analog - to - digital converter.

[0015] Further, the transfer function of the inter - stage noise coupling module is set as H NC =STF 2a ·H d =1-(1 - z -1 ) n , where n represents the order, which is specifically determined according to the design requirements of the MASH - structured ΔΣ analog - to - digital converter, and STF 2aRepresents the signal transfer function of the second - stage ΔΣ loop module, H d Represents the transfer function of the digital delay topology unit.

[0016] Furthermore, the signal transfer function of the second - stage ΔΣ loop module is set to STF 2a = 1-(1 - z -1 ) n , and the transfer function H d of the digital delay topology unit = 1, or the signal transfer function of the second - stage ΔΣ loop module is set to STF 2a = 1, and the transfer function H d of the digital delay topology unit = 1-(1 - z -1 ) n .

[0017] Furthermore, the transfer function of the first digital filter is set to H 1 = STF 2d , and the transfer function of the second digital filter is set to H 2 = NTF 1d (1 - STF 2d H d ).

[0018] Furthermore, the first - stage ΔΣ loop module includes a first loop filter, the first loop filter is successively connected to a first sample - and - hold circuit, a first quantizer, and a first digital subtractor. The output end of the first subtractor is coupled to a continuous input signal through a first DAC and a third digital subtractor, and is fed back to the input end of the first loop filter;

[0019] The second - stage ΔΣ loop module includes a second loop filter, the second loop filter is successively connected to a second sample - and - hold circuit and a second quantizer. The output end of the second quantizer is coupled to the output of the first quantizer through a second DAC and a fourth digital subtractor, and is fed back to the input end of the second loop filter;

[0020] Both the first loop filter and the first loop filter adopt continuous - time loop filters.

[0021] The beneficial technical effects of the present invention are as follows:

[0022] 1) The inter - stage noise coupling technology proposed by the present invention can generate high - order mismatch shaping, greatly suppressing the noise leakage caused by the mismatch between analog and digital filters in the MASH - architecture ΔΣ modulator, significantly alleviating the matching requirements between analog and digital filters, effectively improving the accuracy of the MASH architecture and maintaining high energy efficiency.

[0023] 2) The inter-stage noise coupling technology proposed by the present invention can be implemented in two ways (as described in the specific implementation manners): One is to implement by setting the digital delay topology unit to a special transfer function, and its performance can be improved with the evolution of semiconductor advanced process nodes, achieving optimization of chip power consumption and area; the other is to implement by setting the transfer function of the analog loop filter of the second-stage ΔΣ loop to a special form, which can achieve inter-stage noise coupling without adding any hardware overhead, effectively reducing the structural complexity and decreasing the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1a is a schematic structural diagram of a traditional continuous-time single-loop DSM;

[0025] Figure 1b is a schematic structural diagram of a traditional MASH DSM;

[0026] Figure 2 is a schematic structural diagram of a two-stage MASH DSM with inter-stage noise coupling provided by an embodiment of the present invention;

[0027] Figure 3 is a comparison diagram of the sensitivities of the inter-stage noise coupling MASH DSM and the traditional MASH DSM provided by an embodiment of the present invention to the deviation of the RC time constant;

[0028] Figure 4 is a comparison diagram of the sensitivities of the inter-stage noise coupling MASH DSM and the traditional MASH DSM provided by an embodiment of the present invention to the deviation of the finite gain of the operational amplifier. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] The following describes in detail the specific implementation manners of the present invention in conjunction with the accompanying drawings and preferred embodiments.

[0030] Figure 1a is a typical traditional continuous-time single-loop ΔΣ modulator. The direct derivation of the transfer function LF(s) of its loop filter is relatively complex. On the premise of using a non-return-to-zero feedback DAC, according to the impulse-invariant transformation (IIT), we can convert the transfer function LF(s) of the continuous system into a discrete-time transfer function LF(z):

[0031]

[0032] Thereby generating a signal transfer function STF and a noise transfer function NTF, where the form of the NTF is a high-pass filter function (1 - z -1 ) n, the noise in the output signal is shaped to the out-of-band, greatly suppressing the in-band noise and achieving high-precision analog-to-digital conversion. However, the most efficient method to improve the conversion accuracy is to increase the implementation order of the loop filter. However, implementing a high order in a single-loop ΔΣ modulator will lead to topological instability. Therefore, adopting a multistage noise shaping (MASH) architecture ΔΣ modulator is a solution that takes into account both topological stability and high-order shaping.

[0033] Figure 1b FIG. 4 is a schematic structural diagram of a traditional MASH architecture ΔΣ modulator. The main structure is the cascade of two low-order ΔΣ loops. The second ΔΣ loop takes the quantization noise generated by the quantizer in the first ΔΣ loop as the input. Finally, the outputs of the two ΔΣ loops are weighted and subtracted by a digital filter to obtain the output of the final modulator. However, due to the mismatch problem between the loop filter in the analog domain and the digital filter in the digital domain in circuit implementation, it will greatly limit the realization of high precision. Therefore, this problem can be greatly alleviated by the inter-stage coupling technology in the following invention content.

[0034] Therefore, as Figure 2 shown, the present invention provides a MASH structure ΔΣ modulator adopting the inter-stage noise coupling technology. Taking the second stage as an example, it includes a ΔΣ double-loop module, an inter-stage noise coupling module, and a digital filter module. The ΔΣ double-loop module includes a first-stage ΔΣ loop module and a second-stage ΔΣ loop module. The inter-stage noise coupling module includes the second-stage ΔΣ loop module and a digital delay topology unit.

[0035] Taking the quantization noise generated by the quantizer of the first-stage ΔΣ loop module as the input of the second-stage ΔΣ loop module, the output of the quantizer of the second-stage ΔΣ loop module passes through the digital delay topology unit and is coupled with the output of the quantizer of the first-stage ΔΣ loop module by means of a first digital subtractor. The output of the first digital subtractor is fed back to the input of the loop filter of the first-stage ΔΣ loop module through the DAC of the first-stage ΔΣ loop module.

[0036] The digital filter module includes a first digital filter and a second digital filter. Their input ends are respectively connected to the output ends of the first-stage ΔΣ loop module and the second-stage ΔΣ loop module, and their output ends are both connected to a second digital subtractor. The output of the second digital subtractor is used as the output of the entire MASH structure ΔΣ analog-to-digital converter.

[0037] In this way, with the help of the inter-stage noise coupling module, the quantization noise of the first-stage ΔΣ loop module is led out to the input end of the second-stage ΔΣ loop module, and then the output end of the quantizer of the second-stage ΔΣ loop module is led back to the first-stage ΔΣ loop module, that is, fed back to the output end of the quantizer of the first-stage ΔΣ loop module. The two are coupled through a subtractor to form a branch similar to "inter-stage coupling". By reasonably selecting the transfer functions of the inter-stage noise coupling module and the digital filter module, the quantization noise generated in the first-stage ΔΣ loop module can be effectively cancelled, the noise leakage caused by the mismatch between the analog and digital filters in the MASH architecture ΔΣ modulator is greatly suppressed, the matching requirements between the analog and digital filters are significantly alleviated, and the accuracy of the MASH architecture is effectively improved while maintaining high energy efficiency.

[0038] Specifically, both loops in the ΔΣ dual-loop module include a loop filter, a quantizer, and a digital-to-analog converter. That is, the first-stage ΔΣ loop module includes a first loop filter, which is successively connected to a first sample-and-hold circuit, a first quantizer, and a first digital subtractor. The output end of this first subtractor is coupled to the continuous input signal through a first DAC and a third digital subtractor, and fed back to the input end of the first loop filter; the second-stage ΔΣ loop module includes a second loop filter, which is successively connected to a second sample-and-hold circuit and a second quantizer. The output end of this second quantizer is coupled to the output of the first quantizer through a second DAC and a fourth digital subtractor, and fed back to the input end of the second loop filter; at the same time, both the first loop filter and the second loop filter adopt continuous-time loop filters. Due to the inherent low-pass filtering anti-aliasing characteristics of the continuous-time loop filter, the design requirements of the pre-stage anti-aliasing filter in practical applications are greatly reduced; in addition, the input impedance of the continuous-time loop filter is resistive and is easy to be driven by the pre-stage, so its bandwidth limit is significantly higher than that of the discrete-time loop filter.

[0039] The inter-stage noise coupling module shares the second-stage ΔΣ loop module with the ΔΣ dual-loop module, reducing the number of additional hardware components and effectively reducing the complexity of the entire structure. The function of this branch is to generate a quantization noise E q1 with a transfer function H NC acting on the first-stage ΔΣ loop module. This quantization noise E q1 is obtained through the second-stage ΔΣ loop module, and the digital output is then passed through a digital delay topology unit and injected into the first-stage ΔΣ loop module through a first digital subtractor.

[0040] The transfer function of the inter-stage noise coupling module is set to H NC = STF 2a ·H d = 1-(1 - z -1 ) n, where n represents the order, and STF 2a represents the signal transfer function of the second - stage ΔΣ loop module, and H d represents the transfer function of the digital delay topology unit, such that 1 - H NC =(1 - z -1 ) n , to achieve the shaping of the noise leakage term in Equation (10) described later. The specific shaping order achieved can be determined according to the design requirements of the MASH - structured ΔΣ analog - to - digital converter. Referring to Table 1, the inter - stage coupling function H NC can be adjusted here to set different mismatch shaping orders.

[0041] Table 1 Digital Delay Unit and Corresponding Mismatch Shaping Order

[0042]

[0043]

[0044] For the convenience of integrated circuit design, we can set the inter - stage coupling function H NC in the following two ways:

[0045] One way is to set the signal transfer function STF 2a of the second - stage ΔΣ loop module in the analog domain to a specific delay combination in the first column of Table 1, and set the transfer function H d of the digital delay topology unit to 1;

[0046] Another way is to set the transfer function H d of the digital delay topology unit in the digital domain to a specific delay combination in Table 1, and set STF 2a to 1.

[0047] Set the transfer function of the first digital filter to H 1 = STF 2d , and set the transfer function of the second digital filter to H 2 = NTF 1d (1 - STF 2d H d ).

[0048] First, the input continuous signal passes through the loop filter and quantizer in the first - stage ΔΣ loop module, generating a digital output with quantization noise E q1 , and receives the output signal H d Y 2After injection, the obtained digital signal is converted into an analog signal by the first DAC and fed back to the input end of the first loop filter. After the negative feedback loop stabilizes, the output signal of the first digital subtractor is the digital output signal Y of the first - stage ΔΣ loop module 1 Extract the quantization noise E of the first - stage quantizer q1 As the input signal of the second - stage ΔΣ loop module, this signal passes through the second loop filter and then enters the second quantizer in the second - stage ΔΣ loop module, generating a digital output containing the quantization noise E q1 After passing through the second DAC, it becomes an analog signal and is fed back to the input end of the second loop filter in the second - stage ΔΣ loop module. After the negative feedback loop stabilizes, the output signal of the second quantizer in the second - stage ΔΣ loop module is the digital output signal Y of the second - stage ΔΣ loop module 2 .

[0049] Y 1 = STF 1a X + NTF 1a (E q1 - H d Y 2 ) (3)

[0050] Y 2 = STF 2a E q1 + NTF 2a E q2 (4)

[0051] The digital outputs (Y 1 , Y 2 ) of the first and second - stage ΔΣ loop modules are respectively used as the input signals of the first and second digital filters, and then respectively processed by the first and second digital filters (H 1 , H 2 ). The two - stage digital signals obtained are subtracted by the fourth digital subtractor to eliminate the quantization noise E q1 to obtain the final modulator output signal Y MASH : (In the formula, the subscripts "a" and "d" respectively represent the analog domain and the digital domain, and this naming rule is adopted throughout the context)

[0052] Y MASH = H 1 Y 1 - H 2 Y 2 = STF 1a STF 2d X - NTF 1d NTF 2a E q2 (7)

[0053] For example Figure 1bAs shown, when there is a mismatch between the analog and digital filters in the traditional MASH architecture ΔΣ modulator, i.e., NTF 1a ≠NTF 1d , STF 2a ≠STF 2d , the actual output expression is as shown in Equation (8), and the quantization noise E q1 leaks into the final output:

[0054] Y MASH =STF 1a STF 2d X-NTF 1d NTF 2a E q2 +[NTF 1a STF 2d -NTF 1d STF 2a E q1 (8)

[0055] As Figure 2 shown, when there is a mismatch between the analog and digital filters in the novel MASH architecture ΔΣ modulator proposed by the present invention, the actual output expression is as follows:

[0056]

[0057] Its noise leakage term is:

[0058]

[0059] In the formula, LN 1 , LN 2 , LN 3 respectively represent (NTF 1a STF 2d -NTF 1d STF 2a )E q1 , (STF 2d -STF 2a )E q1 and (NTF 1d -NTF 1a )E q2 , and all three are leakage noises caused by the mismatch between the analog and digital filters. Obviously, the secondary leakage terms LN 2 and LN 3 have been shaped and suppressed by the inherent noise transfer functions of the first and second ΔΣ loop modules, i.e., the shaping functions NTF 1a and NTF 2a , while the nth-order mismatch shaping function (1-H 1 ) of the main leakage term LN NC ) is (1-z-1 ) n It is mainly formed by the inter-stage noise coupling module proposed in the present invention, and finally realizes the in-band suppression of all noise leakage terms, greatly alleviating the noise leakage problem of the MASH architecture ΔΣ modulator. In particular, for a continuous-time ΔΣ loop, its continuous-time loop filter is generally implemented based on a resistor-capacitor (RC) active integrator. Since the transfer function coefficients of the continuous-time filter are determined by the RC product that is severely affected by PVT (process-voltage-temperature), the influence of PVT variation on the coefficients in the filter transfer function is more severe than that of the typical capacitor-capacitor proportional integration scheme for the filter in the discrete-time ΔΣ loop. The degree to which the more severe filter coefficient mismatch problem caused by PVT variation is improved by the inter-stage coupling technology is more significant. Therefore, the MASH structure continuous-time ΔΣ modulator adopting the inter-stage noise coupling technology can achieve a larger bandwidth with less mismatch influence.

[0060] Taking the ΔΣ modulator with a 1-3 MASH architecture as an example, the sensitivity to mismatch of the MASH architecture with inter-stage noise coupling and the traditional MASH architecture can be verified through simulation. Here, the transfer function H of the inter-stage coupling branch will be set NC =(2z -1 -z -2 ), so that 1 - HNC=(1 - z -1 ), forming a second-order mismatch shaping for the main leakage term LN 2 , and at the same time forming a first-order and third-order mismatch shaping for LN 1 and LN 2 and LN 3 . Figure 3 And Figure 4 shows that the inter-stage noise coupling MASH architecture in this embodiment has lower sensitivity to the mismatch between the analog and digital filters caused by the deviation of the RC time constant and the finite gain variation of the operational amplifier through second-order mismatch shaping compared with the traditional MASH architecture.

[0061] Those skilled in the art should understand that these are only examples. Without departing from the principles and essence of the present invention, various changes or modifications can be made to these embodiments. Therefore, the protection scope of the present invention is defined by the appended claims.

Claims

1. A MASH - structured ΔΣ modulator using inter - stage noise coupling technology, characterized in that: it includes a ΔΣ dual - loop module, an inter - stage noise coupling module, and a digital filter module, the ΔΣ dual - loop module includes a first - stage ΔΣ loop module and a second - stage ΔΣ loop module, and the inter - stage noise coupling module includes the second - stage ΔΣ loop module and a digital delay topology unit, using the quantization noise generated by the quantizer of the first - stage ΔΣ loop module as the input of the second - stage ΔΣ loop module. The output of the quantizer of the second - stage ΔΣ loop module passes through the digital delay topology unit and is coupled with the output of the quantizer of the first - stage ΔΣ loop module by means of a first digital subtractor. The output of the first digital subtractor is fed back to the input of the loop filter of the first - stage ΔΣ loop module through the DAC of the first - stage ΔΣ loop module; the digital filter module includes a first digital filter and a second digital filter. Their input ends are respectively connected to the output ends of the first - stage ΔΣ loop module and the second - stage ΔΣ loop module, and their output ends are both connected to a second digital subtractor. The output of the second digital subtractor is used as the output of the entire MASH - structured ΔΣ analog - to - digital converter; The transfer function of the inter-stage noise coupling module is set to H NC = STF 2a ·H d = 1 - (1 - z -1 ) n , where n represents the order, which is specifically determined according to the design requirements of the MASH-structured ΔΣ analog-to-digital converter. STF 2a represents the signal transfer function of the second-stage ΔΣ loop module, and H d represents the transfer function of the digital delay topology unit.

2. The MASH - structured ΔΣ modulator using inter - stage noise coupling technology according to claim 1, characterized in that: The signal transfer function of the second - stage ΔΣ loop module is set to STF 2a = 1-(1 - z -1 ) n , the transfer function H of the digital delay topology unit d = 1, or the signal transfer function of the second - stage ΔΣ loop module is set to STF 2a = 1, the transfer function H of the digital delay topology unit d = 1-(1 - z -1 ) n .

3. The MASH - structured ΔΣ modulator using inter - stage noise coupling technology according to claim 1, characterized in that: The transfer function of the first digital filter is set to H 1 = STF 2d and the transfer function of the second digital filter is set to H 2 = NTF 1d (1 - STF 2d H d ).

4. The MASH - structured ΔΣ modulator using inter - stage noise coupling technology according to claim 1, characterized in that: the first - stage ΔΣ loop module includes a first loop filter, and the first loop filter is successively connected to a first sample - and - hold circuit, a first quantizer, and a first digital subtractor. The output end of the first subtractor is coupled with a continuous input signal through a first DAC and a third digital subtractor and fed back to the input end of the first loop filter; the second - stage ΔΣ loop module includes a second loop filter, and the second loop filter is successively connected to a second sample - and - hold circuit and a second quantizer. The output end of the second quantizer is coupled with the output of the first quantizer through a second DAC and a fourth digital subtractor and fed back to the input end of the second loop filter; both the first loop filter and the first loop filter adopt continuous - time loop filters.

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