Techniques for performing store-to-load forwarding

Abstract

A technique for performing store-to-load forwarding is provided. The technique includes: determining the virtual address of data to be loaded for a load instruction; identifying a matching store instruction from one or more store instruction memories by comparing a virtual address-based comparison value of the load instruction with one or more virtual address-based comparison values ​​of one or more store instructions; determining the physical address of the load instruction; and verifying the load instruction based on a comparison between the physical address of the load instruction and the physical address of the matching store instruction.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of pending U.S. non-provisional patent application No. 16 / 698,808, filed November 27, 2019, entitled “TECHNIQUES FOR PERFORMINGSTORE-TO-LOAD FORWARDING”, the entire contents of which are incorporated herein by reference. Background Technology

[0003] Out-of-order processors execute instructions out of order, but adhere to certain constraints to ensure execution proceeds as specified by the program. Specifically, a newer load executed on the same address as older memory is sometimes executed out of order and shut down together in a timely manner. If the value stored by a store instruction has not yet been committed to the memory system (including caches supported by higher-level caches and system memory) when the load instruction is executed, store-to-load forwarding is performed, where the instruction pipeline directly provides the data stored by the store instruction to the load instruction. Attached Figure Description

[0004] A more detailed understanding can be obtained from the following description, given by way of example in conjunction with the accompanying drawings:

[0005] Figure 1 This is a block diagram of an exemplary apparatus for implementing various aspects of the present disclosure;

[0006] Figure 2 It is based on the example located at Figure 1 A block diagram of the instruction execution pipeline within the processor;

[0007] Figure 3A It is a diagram illustrating the store-to-load forwarding operation based on the example;

[0008] Figure 3B This is a diagram illustrating the operation of performing store-to-load forwarding, based on another example; and

[0009] Figure 4 This is a flowchart based on an example of a method for performing a store-to-load forwarding of a load instruction. Detailed Implementation

[0010] A technique for performing store-to-load forwarding is provided. The technique includes: determining the virtual address of data to be loaded for a load instruction; identifying a matching store instruction from one or more store instruction memories by comparing a virtual address-based comparison value of the load instruction with one or more virtual address-based comparison values ​​of one or more store instructions; determining the physical address of the load instruction; and verifying the load instruction based on a comparison between the physical address of the load instruction and the physical address of the matching store instruction. A processing unit and a load / store subsystem are also provided.

[0011] Figure 1 This is a block diagram of an exemplary apparatus 100 implementing various aspects of the present disclosure. Apparatus 100 includes, for example, a computer, gaming device, handheld device, set-top box, television, mobile phone, or tablet computer. Apparatus 100 includes a processor 102, a memory 104, a storage device 106, one or more input devices 108, and one or more output devices 110. Apparatus 100 may also optionally include an input driver 112 and an output driver 114. In some embodiments, apparatus 100 includes... Figure 1 Additional components not shown.

[0012] In some examples, processor 102 includes a central processing unit (CPU), a graphics processing unit (GPU), a CPU and GPU located on the same die, or one or more processor cores, where each processor core is a CPU or a GPU. In various examples, memory 104 is located on the same die as processor 102, or is located separately from processor 102. Memory 104 includes volatile or non-volatile memory, such as random access memory (RAM), dynamic RAM, or cache.

[0013] In various examples, storage device 106 includes, but is not limited to, fixed or removable storage devices such as hard disk drives, solid-state drives, optical disks, or flash drives. In various examples, input device 108 includes, but is not limited to, a keyboard, keypad, touchscreen, touchpad, detector, microphone, accelerometer, gyroscope, biometric scanner, or network connection (e.g., a wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals). In various examples, output device 110 includes, but is not limited to, a display, speaker, printer, haptic feedback device, one or more lights, antenna, or network connection (e.g., a wireless LAN card for transmitting and / or receiving wireless IEEE 802 signals).

[0014] Input driver 112 communicates with processor 102 and input device 108 and allows processor 102 to receive input from input device 108. Output driver 114 communicates with processor 102 and output device 110 and allows processor 102 to send output to output device 110. Note that input driver 112 and output driver 114 are optional components, and if input driver 112 and output driver 114 are not present, device 100 will operate in the same manner.

[0015] Figure 2 It is based on the example located at Figure 1 The block diagram of the instruction execution pipeline 200 within the processor 102 is shown. The instruction execution pipeline 200 retrieves instructions from memory and executes them, thereby outputting data to memory and modifying the state of elements within the instruction execution pipeline 200 (e.g., registers in register file 218).

[0016] The instruction execution pipeline 200 includes: an instruction fetch unit 204 that fetches instructions from system memory (e.g., memory 104) via an instruction cache 202; a decoder 208 that decodes the fetched instructions; a function unit 216 that performs computations to process the instructions; a load / store unit 214 that loads data from system memory or stores data in system memory via a memory system 220; and a register file 218 that includes registers for storing working data for the instructions. The memory system 220 includes one or more memories at memory levels, including, for example, a data cache (e.g., level 0), other caches, memory, and other memories. A reordering buffer 210 tracks currently running instructions and ensures ordered instruction exits, although out-of-order execution is allowed during runtime. A “running” instruction is an instruction that has been received by the reordering buffer 210 but whose architectural state has not yet been committed to the processor (e.g., non-speculatory results written to the register file, etc.). A reservation station 212 holds instructions waiting to be executed on function unit 216 and tracks instruction operands. When all operands are ready to execute a specific instruction, reservation station 212 sends the instruction to function unit 216 or load / store unit 214 for execution. Completed instructions are marked as exited in reorder buffer 210 and exit when they are at the front of the reorder buffer queue 210. Exit refers to the act of submitting the result of an instruction to the processor's architectural state. Examples of instruction exit include writing the appended result to the latest non-speculative copy of the architectural register by an add instruction, writing the loaded value to the latest non-speculative copy of the architectural register by a load instruction, or non-speculatively causing the instruction flow to jump to a new location by a branch instruction.

[0017] Various components of the instruction execution pipeline 200 communicate via a common data bus 222. For example, functional unit 216 and load / store unit 214 write results to the common data bus 222, which can be read by the holding station 212 to execute related instructions and by the reordering buffer 210 as the final processing result of running instructions that have been completed. Load / store unit 214 also reads data from the common data bus 222. For example, load / store unit 214 reads results from completed instructions from the common data bus 222 and writes the results to memory via memory system 220 for stored instructions.

[0018] Instruction execution pipeline 200 is capable of executing load instructions and store instructions (as well as other instructions). A load instruction is an instruction that loads data from memory and places said data into registers in register file 218. A store instruction is an instruction that stores data from a register into a memory location. For store or load, in many cases, the specified address (the address where the data is stored or from which the data is loaded) is calculated based on the contents of one or more registers and / or one or more values ​​specified in the instruction itself. Furthermore, for load or store operations specifying virtual memory addresses, those addresses are translated into physical addresses.

[0019] More specifically, the store instruction is executed as follows: Instruction fetch unit 204 fetches the store instruction. Decoder 208 decodes the store instruction and transmits it to reorder buffer 210, which provides the store instruction to load / store unit 214. Reservation station 212 issues the store instruction to function unit 216 to generate a virtual address (e.g., calculate the virtual address in the manner specified by the store instruction, e.g., by adding the contents of one register to the contents of another register). Function unit 216 then transmits the virtual address to load / store unit 214 to execute the store instruction. Load / store unit 214 executes the store instruction by translating the virtual address to a physical address via data translation back buffer (TLB) 226 and by internally buffering the data to be stored in the store instruction within load / store unit 214. Reorder buffer 210 causes the store instruction to exit, meaning the store instruction is not executed speculatively and will eventually be submitted to memory system 220. Load / store unit 214 transmits the store instruction to store submission queue 230. Then, the load / store unit 214 submits the storage to the storage system 220 and removes the storage instruction from the storage submission queue 230 in response to receiving a notification that the data specified by the storage instruction has been actually written to the storage system 220. In some embodiments, the storage submission queue 230 is not used.

[0020] More specifically, the load instruction is executed as follows: Instruction fetching unit 204 fetches the load instruction. Decoder 208 decodes the load instruction and transmits it to reordering buffer 210, which provides the load instruction to load / store unit 214. Reservation station 212 issues a load instruction to function unit 216 to generate a virtual address for the load instruction (e.g., calculating the virtual address in the manner specified by the load instruction, e.g., by adding the contents of one register to the contents of another register). Subsequently, function unit 216 transmits the virtual address to load / store unit 214, which executes the load instruction. Load / store unit 214 executes the load instruction by translating the virtual address to a physical address via data TLB 226 and by loading the data specified at the physical address from memory system 220.

[0021] For performance reasons, load / store unit 214 performs store-to-load forwarding for store and load instructions that access the same address and are executed within at least partially overlapping time periods. More specifically, in some cases, a load instruction and a store instruction are executed for the same address, and the load instruction is newer than the store instruction. The load instruction executed in load / store unit 214 attempts to load requested data. If the store instruction has not yet committed its data to memory system 220, it is impossible to read from the memory system via the load instruction because such a read would result in stale data. Therefore, load / store unit 214 forwards data from the store instruction to the load instruction.

[0022] As described above, if the physical addresses of the load instruction and the older store instruction are the same, a store-to-load forwarding is performed. If the physical addresses are different, a store-to-load forwarding should not be performed. Therefore, in one technique, after executing a load instruction, the load / store unit 214 checks whether the physical address of the load instruction is the same as any uncommitted store instruction. However, this technique leads to a potential delay associated with the fact that, in some cases, one or both of the physical addresses of the store instruction or the load instruction are unknown when such a check is to be performed. Therefore, this technique will result in a delay in the successful execution of the load instruction until such a physical address becomes available.

[0023] Therefore, in one technique, load / store unit 214 uses a virtual address-based comparison value (sometimes simply referred to herein as a "comparison value") to check for a match between a load instruction and an uncommitted store instruction, the comparison value being the virtual address of the data to be loaded by the load instruction. In some embodiments, the virtual address-based comparison value is the complete virtual address. In other embodiments, the virtual address-based comparison value is a portion of the complete virtual address. In yet another embodiment, the virtual address-based comparison value is a value derived from the complete virtual address using a transformation function (wherein some embodiments, the transformation function is a hash function). In still other embodiments, the virtual address-based comparison value is a value derived from a portion of the virtual address using a transformation function (wherein some embodiments, the transformation function is a hash function). The virtual address-based comparison value is calculated for both the load instruction and the store instruction to allow comparison of these values. In some embodiments, a "match" means that the virtual address-based comparison value of the store instruction is the same as the virtual address-based comparison value of the load instruction. In other embodiments, a match means that a portion of the comparison value is the same.

[0024] Note that a match between the virtual address-based comparison value of a load instruction and the virtual address-based comparison value of a store instruction does not necessarily indicate that the physical addresses of the load and store instructions are the same. Rather, a match in the comparison values ​​indicates that these physical addresses may be the same. Therefore, the execution of a load instruction (including retrieving data from a store instruction with a matching comparison value) is considered speculative. For this reason, load / store unit 214 verifies that the load has been correctly executed at some point after retrieving data based on a matching comparison value. The event that triggers this verification of the load instruction is referred to herein as a "verification trigger event". In some examples, the verification trigger event is the successful completion of the load instruction, meaning that the load instruction has completed all other steps, such as address translation and actually receiving the loaded data, which would make the load instruction considered complete. In other examples, the verification trigger event is the successful completion of the store instruction after the load instruction has completed. If the verification is successful, the data loaded by the load instruction is considered correct, and the load instruction is no longer considered to have been speculatively executed for the purpose of verifying store-to-load forwarding (in some cases, the load instruction is still being speculatively executed for other reasons). If the verification fails, the pipeline 200 refresh load instruction is executed. This means that the load instruction is removed from the pipeline (and in some examples, other instructions, such as those newer than the load instruction, are removed), and the refreshed load instruction does not affect the pipeline's architectural state. The load instruction (and other instructions) is then replayed.

[0025] Store-to-load forwarding verification based on virtual address comparisons is performed as follows. During verification, the store instruction may have successfully completed the virtual-to-physical address translation to the address where the data is to be stored. In that case, verification includes checking whether the physical address of the store instruction is the same as the physical address from which the load instruction reads the loaded data. If the physical addresses are the same, the load instruction is successfully verified; otherwise, it is not verified. Note that this verification occurs a little later than the execution of the load instruction to hide the delay in obtaining the physical addresses of both the load and store instructions.

[0026] It is also possible that during the verification of the load instruction, the store instruction has not yet successfully completed the virtual-to-physical address translation to the address where the data is to be stored. In that case, in response to the load / store unit 214 completing the load instruction, the load / store unit 214 places the load instruction into the load wait buffer 228. When the load / store unit 214 obtains the physical address of the store instruction whose comparison value matches the load instruction through address translation, the load / store unit 214 compares the physical address with the physical address of the load instruction. If the physical addresses are the same, the verification is considered to have been successfully completed. If the physical addresses are not the same, the verification is considered to have failed.

[0027] In some implementations, the load wait buffer 228 is also an out-of-order buffer used to verify the store-to-load memory ordering. More specifically, store-to-load ordering is a memory ordering rule that requires all loads to receive data from store operations defined by program order (i.e., the order in which instructions should be executed based on the control flow of the software executing those instructions). Because the instruction execution pipeline 200 can execute instructions (including load and store instructions) out of order, store-to-load ordering is implemented between instructions in the same thread to prevent load instructions from consuming stale data.

[0028] In some examples, violations of the store-to-load ordering are checked in the following manner. In response to a load instruction completing and being eligible for placement in the out-of-order buffer, load / store unit 214 places the load instruction in the out-of-order buffer. A load instruction is eligible for placement in the out-of-order buffer if it may violate the store-to-load ordering rules. Such a violation is possible if there is at least one older store instruction than the load instruction, and load / store unit 214 has not yet determined the physical address of the older store instruction. If the load instruction is not eligible for placement in the out-of-order buffer, load / store unit 214 will not place the load instruction in the out-of-order buffer.

[0029] When in the out-of-order buffer, load / store unit 214 checks for violations of the store-to-load ordering rules in the following manner: After determining the physical address of a store instruction older than the load instruction, load / store unit 214 compares the physical address with the physical address of the load instruction. If a match is found, load / store unit 214 determines that a violation has occurred, and if a mismatch is found, load / store unit 214 determines that the store instruction has not violated the rules. In response to the absence of any store instructions older than the load instruction whose physical address has not yet been determined, load / store unit 214 determines that a violation is no longer possible with the load instruction, and removes the load instruction from the out-of-order buffer if there is no other reason to keep it in the out-of-order buffer.

[0030] Therefore, in some implementations, the load wait buffer 228 is used to perform store-to-load forwarding verification and to perform checks for violations of store-to-load ordering rules. If both checks are required, the load / store unit 214 removes the load instruction from the load wait buffer 228 in response to both checks being completed.

[0031] In some implementations, the load / store unit 214 implements a technique involving initial candidate store instruction selection based on a portion of the virtual address of the load instruction, followed by preliminary verification based on comparison values, and then final verification based on physical addresses. More specifically, during the execution of a load instruction, the load / store unit 214 selects candidate uncommitted store instructions based on the least significant X bits (in some examples, X is 12) of the virtual address of the store instruction. More specifically, the load / store unit 214 identifies uncommitted store instructions whose least significant X bits are the same as those of the load instruction as candidate uncommitted store instructions. The load / store unit 214 then attempts to preliminarily verify that the store instruction is the correct instruction to obtain the data from the load instruction by comparing the virtual address-based comparison value of the store instruction with the virtual address-based comparison value of the load instruction. If a match is found, the load / store unit 214 allows the load instruction to execute using the data from the matching store instruction.

[0032] Later, load / store unit 214 performs final verification using the physical addresses of the matching store instruction and load instruction, as described elsewhere in this document. If, after identifying a candidate uncommitted store instruction, the comparison value based on the virtual address does not match, there are two possibilities: a false miss or a true miss. A false miss occurs when the virtual addresses of the candidate uncommitted store instruction and the load instruction have the same X least significant bits, where the virtual addresses themselves are different (and therefore have different comparison values, e.g., the hashes of the different virtual addresses are different), but despite this, the different virtual addresses point to the same physical address. A true miss occurs when the X least significant bits match but the remaining virtual address does not match and the physical address does not match either. Therefore, if, after identifying a candidate uncommitted store instruction, the comparison value based on the virtual address does not match, load / store unit 214 identifies whether this match failure indicates a true miss or a false miss by comparing the physical address, as described elsewhere in this document (e.g., regarding...). Figure 4 (as described in step 408).

[0033] A true miss occurs if the physical addresses are different. A false miss occurs if the physical addresses are the same. In both cases, the load instruction is replayed. If a true miss occurs, the candidate store instruction does not store the correct data for the load instruction, and the load instruction does not receive data from the store instruction in subsequent replays. If a false miss occurs, the candidate store instruction does store the correct data for the load instruction, and the load instruction receives data from the store instruction in subsequent replays.

[0034] In some implementations, a false miss is detected after a preliminary verification of a match with a candidate store instruction has been deemed invalid. More specifically, as described elsewhere herein, the preliminary verification based on a virtual address-based comparison occurs relatively early in the execution of a load instruction, at which point the physical address of either or both of the load and store instructions is unavailable. A subsequent final verification is performed when the physical address becomes available. In the case of a true miss, load / store unit 214 remembers that the store instruction is a mismatch and replays the load instruction. Using this remembered information, load / store unit 214 excludes the store instruction from the initial candidates, and the load instruction does not receive data from the store instruction. In the case of a false miss, load / store unit 214 remembers that the store is a match and replays the load. Using this remembered information, load / store unit 214 forces a verification that failed due to a comparison mismatch to succeed. The final verification also succeeds because the physical addresses are the same.

[0035] Figure 3A This is a diagram illustrating the store-to-load forwarding operation, based on an example. Figure 3AIn this context, a load instruction that loads from an address is executed when a store instruction that writes to the same address has been at least partially executed but has not yet committed its result.

[0036] At operation 320, the reservation station 212, having received the load instruction from the reordering buffer 210, transmits the load instruction to the load / store unit 214 for execution via the decoder 208 and the instruction fetch unit 204. At operation 322, the reservation station 212 transmits the load instruction to the functional unit 216 to determine the virtual address of the load instruction. Because many load instructions include indirectly specified virtual addresses (e.g., as the sum of two or more values ​​such as a base address and an offset), operation 322 involves performing an operation in the functional unit 216 to obtain the virtual address from which the data specified by the load instruction is to be loaded.

[0037] In operation 324, load / store unit 214 performs the following sub-operations. The load store unit determines a virtual address-based comparison value based on the virtual address obtained at operation 322. In various examples, this determination is made by performing a hash on the complete or partial virtual address obtained at operation 322, or by performing an operation other than hashing on the complete or partial virtual address obtained at operation 322. The match lookup involves searching for a store operation that has not yet committed a result to the memory system and has a virtual address-based comparison value that matches the virtual address-based comparison value of the load instruction. In some examples, a match between two virtual address-based comparison values ​​means that the two values ​​are the same. In other examples, a match between two virtual address-based comparison values ​​means that a portion of the two values ​​is the same. In still other examples, a match means that the function applied to the two values ​​produces the same value. Operation 326 illustrates the search for a match in store queue 304 and store commit queue 230, but alternatively or additionally, it is possible to search other structures of stored data to obtain a store instruction that has not yet been committed to memory. Storage queue 304 is a memory that stores pending storage instructions from when a storage instruction is received from load / storage unit 214 until the storage instruction is exited and placed in storage commit queue 230. Storage commit queue 230 is a memory that stores storage instructions from when a storage instruction is received from storage queue 304 until the data stored by the storage instruction has been committed (i.e., stored) into memory system 220.

[0038] Additionally, at operation 324, load / store unit 214 provides the address of the load instruction to the address translation system (i.e., data TLB 226, which attempts to translate the address via the contents of the TLB cache memory and, if necessary, with the help of higher levels in the memory hierarchy), which returns the translated address. At operation 324, in some cases, the match lookup and address translation occur within at least partially overlapping time cycles. In some cases, load / store unit 214 issues the operation of finding a match and the operation of translating the virtual address to a physical address approximately at the same time. In this example, "approximately at the same time" means within the same clock cycle. In another example, "approximately at the same time" means that both begin in response to obtaining the virtual address. Generally, at operation 324, each operation begins without waiting for the other to complete.

[0039] Note that because the search for a match between comparison values ​​begins before the physical address is completed, the load instruction can obtain the loaded data earlier than if the load instruction were to wait for the physical address to complete. However, because the match that occurs at operation 324 is not based on the physical address, a verification operation (operation 326) is performed to verify the loaded data. Additionally, in Figure 3A In the process of verification, the matched store instruction has not yet received its translated address (where the term "matched store instruction" means the store instruction whose virtual address-based comparison value is found at operation 324 to match the virtual address-based comparison value of the load instruction). More specifically, the process of executing a store instruction older than the load instruction also involves obtaining the address translation. However, the address translation of the load instruction may be obtained earlier than the address translation of the matched store instruction. Figure 3A In the case reiterated in the diagram, at operation 326, load / store unit 214 places a load instruction into load wait buffer 228. At operation 328, in response to obtaining the physical address translation of the store instruction, the load / store unit applies the physical address to load wait buffer 228 to verify the speculatively executed load instruction. If the physical address of the load instruction does not match the physical address of the store instruction, load / store unit 214 determines that the speculative execution of the load instruction has failed, and load / store unit 214 refreshes the load instruction from instruction execution pipeline 200 and causes the load instruction to be replayed. If the physical address of the load instruction matches the physical address of the store instruction, load / store unit 214 determines that the speculative execution has completed successfully.

[0040] Figure 3B This is a diagram illustrating the store-to-load forwarding operation, based on another example. This example is similar to... Figure 3AIn this example, except that when verifying a load instruction, the load instruction is not placed in the load wait buffer 228 because the physical address of the stored instruction is already available. More specifically, at operation 342, reservation station 212 dispatches the load instruction to load / store unit 214 in a manner similar to operation 322. At operation 344, reservation station 212 determines the virtual address of the load instruction in a manner similar to operation 324. At operation 346, the load / store unit searches for a match between the comparison values ​​of the load instruction and the stored instruction in a manner similar to operation 326. At operation 348, load / store unit 214 compares the physical address of the stored instruction with the physical address of the load instruction. If the addresses are the same, the load instruction is verified. If the addresses are different, the load instruction is not verified and is flushed and replayed.

[0041] Figure 4 This is a flowchart of method 400 for executing a load instruction and storing it to a load forwarder, based on an example. Although regarding... Figures 1 to 3B The system described herein is provided, but those skilled in the art will understand that any system configured to perform the steps of method 400 in any technically feasible order falls within the scope of this disclosure.

[0042] At step 402, the load / store unit determines the virtual address of the data to be loaded in response to the load instruction. As described elsewhere in this document, the load instruction specifies the address from which data is to be loaded. The address is typically specified indirectly, such as based on an offset added to the base address, or in another manner. Step 402 involves performing any steps necessary to determine the virtual address based on the information specified by the load instruction.

[0043] At step 404, load / store unit 214 identifies matching store instructions by comparing the virtual address-based comparison value of a load instruction with one or more virtual address-based comparison values ​​of one or more store instructions. The store instructions whose comparison values ​​are compared are those that have begun execution and have not yet committed their results to memory, as these store instructions are available for comparison. After a store instruction has committed its store value to memory, the value can be directly used in memory. In some embodiments, load / store unit 214 attempts to identify matching store instructions from store instructions in store queue 304 and store commit queue 230, both of which are described elsewhere herein. Note that if no matching store instruction is found, store-to-load forwarding is not performed, and method 400 ends.

[0044] At step 406, load / store unit 214 determines the physical address of the load instruction via address translation. In various embodiments, step 406 is performed in a time period that at least partially overlaps with step 404. More specifically, in these embodiments, load / store unit 214 identifies a matching store without waiting to receive a physical address translation, which speeds up the process compared to techniques where load / store unit 214 uses a physical address to perform store-to-load forwarding.

[0045] At step 408, the load / store unit 214 verifies the load instruction based on a comparison of the physical address of the load instruction with the physical address of a matching store instruction. In some cases, the load instruction completes before the store instruction has received a physical address. In these cases, the load / store unit 214 places the load instruction in the load wait buffer 228. When the store instruction receives a physical address, the load / store unit 214 applies the physical address to the load instruction in the load wait buffer 228 for verification. In other cases, the load instruction completes and the store instruction has received a physical address. In these cases, the load / store unit 214 compares the physical address of the load instruction with the physical address of the store instruction for verification. Regardless of whether the load wait buffer 228 is used, if a match exists between physical addresses, the load / store unit 214 successfully verifies the load instruction; if no match exists between physical addresses, the load / store unit 214 fails to verify the load instruction and causes the load instruction to be refreshed and replayed.

[0046] In some alternatives to the techniques described above, if a store instruction with a matching virtual address-based comparison value already has a translated physical address when the load instruction attempts to find such a store instruction, then the load instruction is allowed to be executed and completed. However, if such a matching store instruction does not yet have a translated physical address, then the load instruction cannot be completed and replayed.

[0047] It should be understood that many variations are possible based on the disclosure herein. Although features and elements have been described above in specific combinations, each feature or element may be used alone without other features and elements, or in various combinations with or without other features and elements.

[0048] The various elements described herein are implemented as circuits configured to perform the functions described herein, software executed on a processor, or a combination thereof. Figure 1In this document, processor 102 is a computer processor configured to perform the operations described herein. Input driver 112, output driver 114, input device 108, and output device 110 are software executed on one or more processors, hardware, or combinations thereof. The various elements of instruction pipeline 200 are hardware circuits.

[0049] The provided methods can be implemented in a general-purpose computer, processor, or processor core. Suitable processors include, for example, general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), any other type of integrated circuit (IC), and / or state machines. Such processors can be manufactured by configuring the manufacturing process using the results of processed hardware description language (HDL) instructions and other intermediate data, including netlists (such instructions can be stored on a computer-readable medium). The result of such processing can be a mask, which is then used in a semiconductor manufacturing process to manufacture processors of various aspects of the embodiments.

[0050] The methods or flowcharts provided herein can be implemented in a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media, and optical media (such as CD-ROM disks and digital versatile disks (DVDs)).

Claims

1. A method for performing store-to-load forwarding on a load instruction, the method comprising: Determine the virtual address of the data to be loaded in response to the load instruction; A matching memory instruction is identified from one or more memory instructions by comparing the virtual address-based comparison value of the load instruction with one or more virtual address-based comparison values ​​of one or more memory instructions. In response to the detection that the matching storage instruction has not yet been translated into an address when the verification of the load instruction is initiated, the load instruction is placed in the load wait buffer; as well as The loading instruction is verified by comparing the physical address of the loading instruction with the physical address of the matching storage instruction.

2. The method of claim 1, wherein determining the virtual address of the data to be loaded for the load instruction comprises: The virtual address is obtained by performing one or more calculations on the address value specified by the load instruction.

3. The method of claim 1, wherein the one or more instruction storage memories comprise at least one of the following: A storage queue, configured to store stored instructions that are being executed and have not yet exited; and A storage commit queue is configured for storage instructions that have exited but whose stored data has not yet been committed to the storage system.

4. The method of claim 1, further comprising determining the physical address of the load instruction by performing address translation to translate the virtual address of the data to be loaded for the load instruction into the physical address of the load instruction.

5. The method according to claim 1, further comprising: In response to receiving the physical address of the storage instruction, the physical address of the storage instruction is applied to the load wait buffer to determine whether the physical address of the storage instruction matches the physical address of the load instruction.

6. The method of claim 1, wherein verifying the loading instruction comprises: When the verification is initiated, it is detected that the matching storage instruction has been received via address translation; as well as The physical address of the load instruction is compared with the physical address of the matching store instruction.

7. The method of claim 1, wherein the virtual address of the data based on the load instruction, the comparison value based on the virtual address of the load instruction includes one of the following: A hash of a portion of the virtual address of the load instruction; The hash of the complete virtual address of the load instruction; A portion of the virtual address of the load instruction; and The complete virtual address of the loading instruction.

8. The method according to claim 1, further comprising: In response to successful verification of the load instruction, the load instruction is allowed to complete execution without being refreshed; or In response to the failure to successfully verify the load instruction, the load instruction is refreshed and replayed.

9. A load / store subsystem for performing store-to-load forwarding on load instructions, the load / store subsystem comprising: One or more instruction storage memories; as well as The load / store unit is configured as follows: Determine the virtual address of the data to be loaded in response to the load instruction; A matching memory instruction is identified from the one or more memory instructions by comparing the virtual address-based comparison value of the load instruction with one or more virtual address-based comparison values ​​of one or more memory instructions. In response to the detection that the matching storage instruction has not yet been translated into an address when the verification of the load instruction is initiated, the load instruction is placed in the load wait buffer; and The loading instruction is verified by comparing the physical address of the loading instruction with the physical address of the matching storage instruction.

10. The load / store subsystem of claim 9, wherein determining the virtual address of the data to be loaded for the load instruction comprises: The virtual address is obtained by performing one or more calculations on the address value specified by the load instruction.

11. The load / store subsystem of claim 9, wherein the one or more memory stores instruction memories comprises at least one of the following: A storage queue, configured to store stored instructions that are being executed and have not yet exited; and A storage commit queue is configured for storage instructions that have exited but whose stored data has not yet been committed to the storage system.

12. The load / store subsystem of claim 9, wherein the load / store unit is further configured to determine the physical address of the load instruction by performing address translation to translate the virtual address of the data to be loaded for the load instruction into the physical address of the load instruction.

13. The load / store subsystem according to claim 9, wherein the load / store unit is further configured to: In response to receiving the physical address of the storage instruction, the physical address of the storage instruction is applied to the load wait buffer to determine whether the physical address of the storage instruction matches the physical address of the load instruction.

14. The load / store subsystem of claim 9, wherein verifying the load instruction comprises: When the verification is initiated, it is detected that the matching storage instruction has been received via address translation; as well as The physical address of the load instruction is compared with the physical address of the matching store instruction.

15. The load / store subsystem of claim 9, wherein the virtual address of the data based on the load instruction, the comparison value based on the virtual address of the load instruction includes one of the following: A hash of a portion of the virtual address of the load instruction; The hash of the complete virtual address of the load instruction; A portion of the virtual address of the load instruction; and The complete virtual address of the loading instruction.

16. The load / store subsystem according to claim 9, wherein the load / store unit is further configured to: In response to successful verification of the load instruction, the load instruction is allowed to complete execution without being refreshed; or In response to the failure to successfully verify the load instruction, the load instruction is refreshed and replayed.

17. A processing unit for executing a load instruction stored in a load forwarding process, the processing unit comprising: One or more instruction storage memories; The load / store unit is configured as follows: Determine the virtual address of the data to be loaded in response to the load instruction; A matching memory instruction is identified from the one or more memory instructions by comparing the virtual address-based comparison value of the load instruction with one or more virtual address-based comparison values ​​of one or more memory instructions. In response to the detection that the matching storage instruction has not yet been translated into an address when the verification of the load instruction is initiated, the load instruction is placed in the load wait buffer; and The loading instruction is verified by comparing the physical address of the loading instruction with the physical address of the matching storage instruction. as well as A data translation backup buffer is configured to translate the virtual address of the load instruction into the physical address of the load instruction.

18. The processing unit of claim 17, wherein determining the virtual address of the data to be loaded for the load instruction comprises: The virtual address is obtained by performing one or more calculations on the address value specified by the load instruction.

19. The processing unit of claim 17, wherein the one or more instruction storage memories comprise at least one of the following: A storage queue, configured to store stored instructions that are being executed and have not yet exited; and A storage commit queue is configured for storage instructions that have exited but whose stored data has not yet been committed to the storage system.

20. The processing unit of claim 17, further comprising determining the physical address of the load instruction by performing address translation to translate the virtual address of the data to be loaded for the load instruction into the physical address of the load instruction.

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