Pixel driving circuit, display device and pixel driving method

Abstract

A pixel driving circuit (PDC) is provided. The pixel driving circuit (PDC) includes a data writing subcircuit (SCdw) connected to a data line (DL) and to a second capacitor electrode (Ce2), wherein the data writing subcircuit (SCdw) is configured to write the voltage of a data voltage signal and the threshold voltage of a driving transistor (Td) to the second capacitor electrode (Ce2) in a data writing phase (III); a light emitting control subcircuit (SClec) connected to a driving transistor (Td), wherein the light emitting control subcircuit (SClec) is configured to control a voltage power supply signal of a voltage power supply line (Vdd) to be written to the driving transistor (SClec) in a light emitting phase (V) to generate a driving signal; and a first reset transistor (Tr1) having a gate connected to a reset control signal line (rst), a source connected to a first reset signal line (SLr1), and a gate connected to the driving transistor (Td) and a drain connected to the second capacitor electrode (Ce2).

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit, a display device and a pixel driving method. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor-liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control illumination. The OLED display panel includes a plurality of pixel units, which are configured with a pixel driving circuit arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line for each row and a drain terminal connected to a data line for each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] In one aspect, the present disclosure provides a pixel driving circuit, comprising: a storage capacitor, which includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode is connected to a voltage power supply line; a driving transistor, which is configured to generate a driving current for driving a light-emitting element to emit light when the voltage of the second capacitor electrode is greater than the threshold voltage of the driving transistor, and the gate of the driving transistor is connected to the second capacitor electrode; a data writing subcircuit, which is connected to a data line and connected to the second capacitor electrode, and the data writing subcircuit is configured to write the voltage of a data voltage signal and the threshold voltage of the driving transistor to the second capacitor electrode during a data writing phase; a light emitting control subcircuit, which is connected to the driving transistor, and the light emitting control subcircuit is configured The invention is configured to control the voltage power supply signal of the voltage power supply line to be written to the driving transistor to generate a driving signal during the light emitting stage; and a first reset transistor having a gate connected to the reset control signal line, a source connected to the first reset signal line, and a drain connected to the gate of the driving transistor and the second capacitor electrode; wherein the first reset transistor is configured to be turned on during the reset stage to allow the first initialization voltage signal provided by the first reset signal line to be written to the second capacitor electrode; during the voltage holding stage, the first reset transistor is configured to be turned off, and the first reset signal line is configured to provide a voltage holding signal to the source of the first reset transistor; and the voltage holding signal is different from the first initialization voltage signal.

[0004] Optionally, the pixel driving circuit also includes a second reset transistor, the second reset transistor having a gate connected to the reset control signal line, a source connected to the second reset signal line, and a drain connected to the light emitting control subcircuit and the anode of the light emitting element, the second reset transistor being configured to write a second initialization voltage signal to the anode of the light emitting element during the reset phase; wherein the first reset signal line and the second reset signal line are independent of each other; and the voltage holding signal is different from the second initialization voltage signal.

[0005] Optionally, the pixel driving circuit also includes a dual-signal switch subcircuit connected to the first reset signal line; wherein the dual-signal switch subcircuit is configured to generate the first initialization voltage signal in the reset phase and to generate the voltage holding signal in the voltage holding phase.

[0006] Optionally, the dual-signal switch subcircuit includes: a first control transistor having a gate connected to a first control signal line, a source connected to a first switch signal line configured to provide the voltage hold signal, and a drain connected to the first reset signal line; and a second control transistor having a gate connected to a second control signal line, a source connected to a second switch signal line configured to provide the first initialization voltage signal, and a drain connected to the first reset signal line; wherein, in the reset phase and the data writing phase, the first control transistor is configured to be turned off, and the second control transistor is configured to be turned on; and in the voltage hold phase, the first control transistor is configured to be turned on, and the second control transistor is configured to be turned off.

[0007] Optionally, the pixel driving circuit also includes a reverse switch subcircuit connected to the dual-signal switch subcircuit; wherein, in the reset phase, the reverse switch subcircuit is configured to generate a first turn-off control signal, which reaches the gate of the first control transistor of the dual-signal switch subcircuit through the first control signal line to turn off the first control transistor, and generates a second turn-on control signal, which reaches the gate of the second control transistor of the dual-signal switch subcircuit through the second control signal line to turn on the second control transistor; and in the voltage holding phase, the reverse switch subcircuit is configured to generate a first turn-on control signal, which reaches the gate of the first control transistor of the dual-signal switch subcircuit through the first control signal line to turn on the first control transistor, and generates a second turn-off control signal, which reaches the gate of the second control transistor of the dual-signal switch subcircuit through the second control signal line to turn off the second control transistor.

[0008] Optionally, the reverse switch subcircuit includes: a third control transistor having a gate connected to the first control signal line, a source connected to a first voltage signal line configured to provide a first voltage signal, and a drain connected to the second control signal line; and a fourth control transistor having a gate connected to the third control signal line, a source connected to a second voltage signal line configured to provide a second voltage signal, and a drain connected to the second control signal line; wherein, in the reset phase and the data writing phase, the third control transistor is configured to be turned off, and the fourth control transistor is configured to be turned on; and in the voltage holding phase, the third control transistor is configured to be turned on, and the fourth control transistor is configured to be turned off.

[0009] Optionally, the data writing subcircuit includes a first transistor and a second transistor; the first transistor includes a gate connected to a gate line, a source connected to the data line, and a drain connected to the source of the driving transistor; and the gate of the second transistor is connected to the gate line, the source is connected to the second capacitor electrode of the storage capacitor and the gate of the driving transistor, and the drain is connected to the drain of the driving transistor.

[0010] Optionally, the light-emitting control subcircuit includes a third transistor and a fourth transistor; the gate of the third transistor is connected to the light-emitting control signal line, the source is connected to the voltage power supply line, and the drain is connected to the source of the driving transistor and the drain of the first transistor; and the fourth transistor includes a gate connected to the light-emitting control signal line, a source connected to the drain of the driving transistor and the drain of the second transistor, and a drain connected to the anode of the light-emitting element.

[0011] On the other hand, the present disclosure provides an array substrate, comprising: a first control array upper gate circuit, which includes a plurality of cascaded first shift registers; a second control array upper gate circuit, which includes a plurality of cascaded second shift registers; and a plurality of rows of dual-signal switch subcircuits and reverse switch subcircuits, each row including a dual-signal switch subcircuit and a reverse switch subcircuit; wherein the dual-signal switch subcircuits in each row are connected to a first reset signal line; and the reverse switch subcircuits in each row are connected to the dual-signal switch subcircuit; the dual-signal switch subcircuit is configured to generate a first initialization voltage signal in a reset phase, and to generate a voltage holding signal in a voltage holding phase; in the reset phase, the reverse switch subcircuit is configured to generate a first turn-off signal. a control signal, which reaches the gate of the first control transistor of the dual-signal switch subcircuit through the first control signal line to turn off the first control transistor, and generates a second on-control signal, which reaches the gate of the second control transistor of the dual-signal switch subcircuit through the second control signal line to turn on the second control transistor; and in the voltage holding stage, the reverse switch subcircuit is configured to generate a first on-control signal, which reaches the gate of the first control transistor of the dual-signal switch subcircuit through the first control signal line to turn on the first control transistor, and generates a second off-control signal, which reaches the gate of the second control transistor of the dual-signal switch subcircuit through the second control signal line to turn off the second control transistor.

[0012] Optionally, the multiple rows of dual-signal switch sub-circuits and reverse switch sub-circuits are respectively connected to multiple first shift registers of the gate circuit on the first control array, the number of rows of the multiple rows is the same as the number of the multiple first shift registers, and each first shift register in the multiple first shift registers is configured to provide the third turn-off control signal and the third turn-on control signal to the reverse switch sub-circuit in each row of the multiple rows; and the multiple rows of dual-signal switch sub-circuits and reverse switch sub-circuits are commonly connected to a single second shift register of the gate circuit on the second control array, and the single second shift register is configured to provide the first turn-on control signal and the first turn-off control signal to the reverse switch sub-circuit and the dual-signal switch sub-circuit in the multiple rows of dual-signal switch sub-circuits and reverse switch sub-circuits.

[0013] Optionally, the array substrate further includes: a gate circuit on a gate scanning array, which includes a plurality of cascaded third shift registers, and the plurality of cascaded third shift registers are configured to generate a plurality of gate driving signals; and a gate circuit on a light-emitting scanning array, which includes a plurality of cascaded fourth shift registers configured to generate a plurality of light-emitting control signals; wherein each first shift register in the plurality of cascaded first shift registers and each third shift register in the plurality of cascaded third shift registers have the same circuit structure; each second shift register in the plurality of cascaded second shift registers and each fourth shift register in the plurality of cascaded fourth shift registers have the same circuit structure; the ratio of the size of each output transistor in each first shift register in the plurality of cascaded first shift registers and each third shift register in the plurality of cascaded third shift registers is in the range of 1:3 to 1:2; and the ratio of the size of each output transistor in each second shift register in the plurality of cascaded second shift registers and each fourth shift register in the plurality of cascaded fourth shift registers is in the range of 1:3 to 1:2.

[0014] Optionally, the array substrate further comprises a plurality of rows of pixel driving circuits, which are electrically connected to the plurality of rows of dual-signal switch sub-circuits and the reverse switch sub-circuits respectively; wherein the plurality of rows of pixel driving circuits are located in the display area of ​​the array substrate; the first control array upper gate circuit, the second control array upper gate circuit, the gate scanning array upper gate circuit, the light emitting scanning array upper gate circuit, and the plurality of rows of dual-signal switch sub-circuits and the reverse switch sub-circuits are located in the peripheral area of ​​the array substrate; the light emitting scanning array upper gate circuit is located on a side of the gate scanning array upper gate circuit away from the display area; A column of dual-signal switch subcircuits among the multiple rows of dual-signal switch subcircuits and reverse switch subcircuits is located on a side of the gate circuit on the light-emitting scanning array away from the gate circuit on the gate scanning array; a column of reverse switch subcircuits from each of the multiple rows of dual-signal switch subcircuits and reverse switch subcircuits is located on a side of the column of dual-signal switch subcircuits away from the gate circuit on the light-emitting scanning array; the gate circuit on the first control array is located on a side of the column of reverse switch subcircuits away from the column of dual-signal switch subcircuits; and the gate circuit on the second control array is located on a side of the gate circuit on the first control array away from the column of reverse switch subcircuits.

[0015] On the other hand, the present disclosure provides a display device, comprising the pixel driving circuit described herein, a first control array upper gate circuit connected to the third control signal line, and a second control array upper gate circuit connected to the first control signal line; the display device comprises: a plurality of rows of pixel driving circuits; the pixel driving circuits are in each row of the plurality of rows of pixel driving circuits; each row in the plurality of rows of pixel driving circuits is connected to the dual-signal switch sub-circuit and the reverse switch sub-circuit; and the dual-signal switch sub-circuit is configured to generate the first initialization voltage signal in the reset phase, and to generate the voltage hold signal in the voltage hold phase, for each row in the plurality of rows of pixel driving circuits.

[0016] Optionally, the display device also includes a data driver integrated circuit; wherein the data driver integrated circuit is configured to: provide a data voltage signal to multiple sub-pixels in each frame image before displaying each frame image in multiple frame images; and designate a calculated value as the value of the voltage hold signal; wherein the calculated value is calculated by a function based on the data voltage signals of the multiple sub-pixels in each frame image.

[0017] Optionally, the function includes an averaging algorithm; and the calculated value is equal to the sum of the threshold voltage of the driving transistor and the average value of the data voltage signals of the plurality of sub-pixels.

[0018] Optionally, the averaging algorithm is selected from the group consisting of a root mean square algorithm, an arithmetic mean algorithm, a geometric mean algorithm and a weighted mean algorithm.

[0019] Optionally, the function is based on a data signal compensation model f(Vdata(1), Vdata(2), ..., Vdata(N)); and Vdata(1), Vdata(2), ..., Vdata(N) represent the data voltage signals of the multiple sub-pixels.

[0020] On the other hand, the present disclosure provides a pixel driving method, comprising: in a reset phase, turning on a first reset transistor to allow a first initialization voltage signal to be written to a second capacitor electrode of a storage capacitor; in a data writing phase, turning on a data writing subcircuit to allow a voltage of a data voltage signal and a threshold voltage of a driving transistor to be written to the second capacitor electrode; in a voltage holding phase, turning off the first reset transistor and providing a voltage holding signal from a first reset signal line to a source of the first reset transistor; and in a light emitting phase, turning on the light emitting control subcircuit to control a voltage power supply signal of a voltage power supply line to be written to the driving transistor, so that when the voltage of the second capacitor electrode is greater than the threshold voltage of the driving transistor, the driving transistor generates a driving current to drive the light emitting element to emit light; wherein the voltage holding signal is different from the first initialization voltage signal.

[0021] Optionally, the pixel driving method further comprises turning on a second reset transistor in the reset phase to write a second initialization voltage signal into the anode of the light-emitting element in the reset phase; wherein the voltage holding signal is different from the second initialization voltage signal.

[0022] Optionally, the pixel driving method further comprises using a dual signal switch subcircuit connected to the first reset signal line to generate the first initialization voltage signal in the reset phase and to generate the voltage holding signal in the voltage holding phase.

[0023] Optionally, generating the first initialization voltage signal in the reset phase includes: providing a first turn-off control signal to the gate of the first control transistor of the dual-signal switch sub-circuit through a first control signal line to turn off the first control transistor; providing the first initialization voltage signal to the source of the second control transistor through a second switch signal line; and providing a second turn-on control signal to the gate of the second control transistor of the dual-signal switch sub-circuit through a second control signal line to turn on the second control transistor, thereby allowing the first initialization voltage signal to be transmitted from the source of the second control transistor to the drain of the second control transistor, and then to the first reset signal line connected to the drain of the second control transistor.

[0024] Optionally, the pixel driving method also includes: in the reset stage, providing the first shutdown control signal to the gate of the third control transistor of the reverse switch subcircuit connected to the dual-signal switch subcircuit through the first control signal line to turn off the third control transistor of the reverse switch subcircuit, and simultaneously providing the first shutdown control signal to the gate of the first control transistor to turn off the first control transistor; providing the second voltage signal to the source of the fourth control transistor of the reverse switch subcircuit through the second voltage signal line; and providing the third turn-on control signal to the gate of the fourth control transistor of the reverse switch subcircuit through the third control signal line to turn on the fourth control transistor of the reverse switch subcircuit, thereby allowing the second voltage signal to be transmitted from the source of the fourth control transistor to the drain of the fourth control transistor, and then to the second control signal line connected to the gate of the second control transistor, and the second voltage signal is used as the second turn-on control signal to turn on the second control transistor in the reset stage.

[0025] Optionally, generating the voltage holding signal in the voltage holding stage includes: providing the voltage holding signal to the source of the first control transistor through the first switch signal line; providing a first turn-on control signal to the gate of the first control transistor of the dual-signal switch sub-circuit through the first control signal line to turn on the first control transistor, thereby allowing the voltage holding signal to be transmitted from the source of the first control transistor to the drain of the first control transistor, and then to the first reset signal line connected to the drain of the first control transistor; and providing a second turn-off control signal to the gate of the second control transistor of the dual-signal switch sub-circuit through the second control signal line to turn off the second control transistor.

[0026] Optionally, the pixel driving method also includes: in the voltage holding stage, providing the first voltage signal to the source of the third control transistor of the reverse switch sub-circuit connected to the dual-signal switch sub-circuit through the first voltage signal line; providing the first turn-on control signal to the gate of the third control transistor through the first control signal line to turn on the third control transistor, thereby allowing the first voltage signal to be transmitted from the source of the third control transistor to the drain of the third control transistor, and then to the second control signal line connected to the gate of the second control transistor, the first voltage signal being used as the second turn-off control signal to turn off the second control transistor during the voltage holding stage; and providing the third turn-off control signal to the gate of the fourth control transistor of the reverse switch sub-circuit through the third control signal line to turn off the fourth control transistor.

[0027] Optionally, the pixel driving method further comprises using the dual-signal switch subcircuit connected to the first reset signal line to generate the first initialization voltage signal during the data writing phase.

[0028] Optionally, the pixel driving method further comprises using the dual-signal switch subcircuit connected to the first reset signal line to generate the first initialization voltage signal in an initial stage.

[0029] Optionally, the pixel driving method further includes: before displaying each frame image in a plurality of frame images, obtaining data voltage signals of a plurality of sub-pixels of the display panel in each frame image; and designating a calculated value as the value of the voltage holding signal; wherein the calculated value is calculated by a function based on the data voltage signals of the plurality of sub-pixels in each frame image.

[0030] Optionally, the function includes an averaging algorithm; and the calculated value is equal to the sum of the threshold voltage of the driving transistor and the average value of the data voltage signals of the plurality of sub-pixels.

[0031] Optionally, the averaging algorithm is selected from the group consisting of a root mean square algorithm, an arithmetic mean algorithm, a geometric mean algorithm and a weighted mean algorithm.

[0032] Optionally, the function is based on a data signal compensation model f(Vdata(1), Vdata(2), ..., Vdata(N)); and Vdata(1), Vdata(2), ..., Vdata(N) represent the data voltage signals of the multiple sub-pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0034] Figure 1 is a plan view of a display panel having a pixel driving circuit according to some embodiments of the present disclosure.

[0035] Figure 2 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0036] Figure 3 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0037] Figure 4 is a timing diagram for operating a display panel having a pixel driving circuit according to some embodiments of the present disclosure.

[0038] Figure 5is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0039] Figure 6 is a timing diagram for operating a display panel having a pixel driving circuit according to some embodiments of the present disclosure.

[0040] Figure 7 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0041] Figure 8 is a timing diagram for operating a display panel having a pixel driving circuit according to some embodiments of the present disclosure.

[0042] Fig. 9 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0043] Fig.10 is a schematic diagram showing the structure of a display device in some embodiments of the present disclosure.

[0044] Fig.11 is an image of a layout of a peripheral area of ​​a display device in some embodiments according to the present disclosure.

[0045] Fig.12 is a circuit diagram showing the structure of a multi-row pixel driving circuit according to some embodiments of the present disclosure.

[0046] Fig.13 is a timing diagram for operating a display panel having a pixel driving circuit according to some embodiments of the present disclosure.

[0047] Fig.14 This is the circuit diagram of the light emitting control shift register.

[0048] Fig.15 is Fig.14 FIG. 1 is a timing diagram of signals in the case where the light emission control shift register operates.

[0049] Fig.16 It is a schematic diagram of the circuit structure of a shift register unit of a display substrate provided in some embodiments of the present disclosure.

[0050] Fig.17 is Fig.16 FIG. 1 is a timing diagram of signals in the case where the light emission control shift register operates. DETAILED DESCRIPTION

[0051] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0052] The present disclosure provides a pixel driving circuit, a display device and a pixel driving method, which substantially avoid one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the present disclosure provides a pixel driving circuit. In some embodiments, the pixel driving circuit includes: a storage capacitor having a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being connected to a voltage power supply line; a driving transistor configured to generate a driving current for driving a light-emitting element to emit light when the voltage of the second capacitor electrode is greater than the threshold voltage of the driving transistor, the gate of the driving transistor being connected to the second capacitor electrode; a data writing subcircuit connected to the data line and connected to the second capacitor electrode, the data writing subcircuit being configured to write the voltage of the data voltage signal and the threshold voltage of the driving transistor to the second capacitor electrode during the data writing phase; a light emitting control subcircuit connected to the driving transistor, the light emitting control subcircuit being configured to control the voltage power supply signal of the voltage power supply line to be written to the driving transistor during the light emitting phase to generate a driving signal; and a first reset transistor having a gate connected to a reset control signal line, a source connected to a first reset signal line, and a drain connected to the gate of the driving transistor and the second capacitor electrode. Optionally, the first reset transistor is configured to be turned on during a reset phase to allow a first initialization voltage signal provided by the first reset signal line to be written to the second capacitor electrode. Optionally, during a voltage holding phase, the first reset transistor is configured to be turned off, and the first reset signal line is configured to provide a voltage holding signal to the source of the first reset transistor. Optionally, the voltage holding signal is different from the first initialization voltage signal.

[0053] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1, the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a pixel driving circuit PDC. The array substrate includes a gate GL, a data line DL, a voltage power line (for example, a high voltage power line Vdd) and a second voltage power line (for example, a low voltage power line Vss), each of which is electrically connected to the pixel driving circuit PDC. The light emission of each sub-pixel in the sub-pixel Sp is driven by the pixel driving circuit PDC. In one example, a high voltage signal (for example, a VDD signal) is input to the pixel driving circuit PDC connected to the anode of the light-emitting element through the high voltage power line Vdd; a low voltage signal (for example, a VSS signal) is input to the cathode of the light-emitting element through the low voltage power line Vss. The voltage difference between the high voltage signal (for example, a VDD signal) and the low voltage signal (for example, a VSS signal) is a driving voltage ΔV, which drives the light emission of the light-emitting element.

[0054] Various suitable pixel driving circuits can be used in the present array substrate. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the present array substrate. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0055] Figure 2 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2In some embodiments, the pixel driving circuit PDC includes a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2, the first capacitor electrode Ce1 being connected to a voltage power supply line Vdd; a driving transistor Td having a gate connected to the second capacitor electrode Ce2; a data writing subcircuit SCdw connected to the data line DL and to the second capacitor electrode Ce2; a light emitting control subcircuit SClec connected to the driving transistor Td; and a first reset transistor Tr1 having a gate connected to a reset control signal line rst, a source connected to a first reset signal line SLr1, and a drain connected to the gate of the driving transistor Td and the second capacitor electrode Ce2. The driving transistor Td is configured to generate a driving current to drive the light emitting element LE to emit light when the voltage of the second capacitor electrode Ce2 is greater than the threshold voltage of the driving transistor Td. The data writing subcircuit SCdw is configured to write the voltage of the data voltage signal and the threshold voltage of the driving transistor Td to the second capacitor electrode Ce2 during the data writing phase. The light emission control sub-circuit SClec is configured to control the voltage supply signal of the voltage supply line Vdd to be written into the driving transistor Td in the light emission phase to generate a driving signal.

[0056] In some embodiments, the pixel driving circuit PDC further includes a second reset transistor Tr2 having a gate connected to the reset control signal line rst, a source connected to the second reset signal line SLr2, and a drain connected to the light emitting control sub-circuit SClec and the anode of the light emitting element LE. The second reset transistor Tr2 is configured to write the second initialization voltage signal to the anode of the light emitting element LE in the reset phase.

[0057] Figure 3 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2 and Figure 3 In some embodiments, the data writing sub-circuit SCdw includes a first transistor T1 and a second transistor T2; the light emitting control sub-circuit SClec includes a third transistor T3 and a fourth transistor T4.

[0058] Reference Figure 3In some embodiments, the pixel driving circuit PDC includes a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first reset transistor Tr1 having a gate connected to a reset control signal line rst, a source connected to a first reset signal line SLr1, and a drain connected to the second capacitor electrode Ce2 of the storage capacitor Cst and the gate of the driving transistor Td; a first transistor T1 having a gate connected to a gate line GL, a source connected to a data line DL, and a drain connected to the source of the driving transistor Td; a second transistor T2 having a gate connected to the gate line GL, a source connected to the second capacitor electrode Ce2 of the storage capacitor Cst and the drain connected to the gate of the driving transistor Td; The first capacitor electrode Ce1 is connected to the voltage power supply line Vdd and the source of the third transistor T3. The first capacitor electrode Ce1 is connected to the voltage power supply line Vdd and the source of the third transistor T3. The first capacitor electrode Ce1 is connected to the voltage power supply line Vdd and the source of the third transistor T3. The first capacitor electrode Ce1 is connected to the voltage power supply line Vdd and the source of the third transistor T3. The first capacitor electrode Ce1 is connected to the voltage power supply line Vdd and the source of the third transistor T3. The first capacitor electrode Ce1 is connected to the voltage power supply line Vdd and the source of the third transistor T3. The first capacitor electrode Ce1 is connected to the voltage power supply line Vdd and the source of the third transistor T3.

[0059] Figure 4 is a timing diagram for operating a display panel having a pixel driving circuit according to some embodiments of the present disclosure. Figure 4 In some embodiments, the timing sequence includes five phases: initial phase I, reset phase II, data writing phase III, voltage holding phase IV, and light emitting phase V. In some embodiments, the data writing phase III includes a first sub-phase IIIa and a second sub-phase IIIb. In the first sub-phase IIIa, the threshold voltage of the driving transistor is extracted.

[0060] Reference Figure 3 and Figure 4 In the initial stage I, the gate of the first reset transistor Tr1 and the second reset transistor Tr2 is provided with an off reset control signal Voff-rc through the reset control signal line rst to turn off the first reset transistor Tr1 and the second reset transistor Tr2. In the initial stage I, the gate line GL is provided with an off signal, so the first transistor T1 and the second transistor T2 in the data writing sub-circuit are turned off. The light emission control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4 of the light emission control sub-circuit.

[0061] In the reset phase II, the on reset control signal Von-rc is provided to the gate of the first reset transistor Tr1 through the reset control signal line rst to turn on the first reset transistor Tr1; the first initialization voltage signal Vint1 is allowed to be transmitted from the source of the first reset transistor Tr1 to the drain of the first reset transistor Tr1, and then to the second capacitor electrode Ce2 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The on reset control signal Von-rc is also provided to the gate of the second reset transistor Tr2 through the reset control signal line rst to turn on the second reset transistor Tr2; the second initialization voltage signal Vint2 is allowed to be transmitted from the source of the second reset transistor Tr2 to the drain of the second reset transistor Tr2, and then to the anode of the light emitting element LE. The anode of the light emitting element LE is initialized to improve the contrast of the light emitting element LE. The first capacitor electrode Ce1 receives a high voltage signal from the voltage power supply line Vdd. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the second capacitor electrode Ce2 is charged in the reset phase II. In the reset phase II, the gate line GL is provided with a turn-off signal, so the first transistor T1 and the second transistor T2 in the data writing sub-circuit are turned off. The light emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4 of the light emitting control sub-circuit. The voltage level Gtd of the node N1 connecting the gate of the driving transistor Td and the second capacitor electrode Ce2 is equal to the voltage level of the first initialization voltage signal Vint1.

[0062] In the data writing phase III, the off reset control signal Voff-rc is again provided to the gates of the first reset transistor Tr1 and the second reset transistor Tr2 through the reset control signal line rst to turn off the first reset transistor Tr1 and the second reset transistor Tr2. In the first sub-phase IIIa of the data writing phase III, the gate line GL is provided with a turn-on signal, so the first transistor T1 and the second transistor T2 in the data writing sub-circuit are turned on. The gate and drain of the driving transistor Td are connected to the source and drain of the second transistor T2, respectively. Since the second transistor T2 is turned on in the first sub-phase IIIa of the data writing phase III, the gate and drain of the driving transistor Td are connected and short-circuited, and only the PN junction between the gate and the source of the driving transistor Td is effective, so that the driving transistor Td is in a diode connection mode. The first transistor T1 is turned on in the first sub-phase IIIa of the data writing phase III. The data voltage signal transmitted through the data line DL is received by the source of the first transistor T1 and then transmitted to the source of the driving transistor Td, which is connected to the drain of the first transistor T1. The node N2 connected to the source of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate and the source of the driving transistor Td is effective, in the first sub-stage IIIa, the voltage level Gtd at the node N1 gradually rises to (Vdata+Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst is discharged. The light emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4 of the light emitting control sub-circuit. In the second sub-stage IIIb, the gate line GL is provided with a shutdown signal, the first transistor T1 and the second transistor T2 in the data writing sub-circuit are turned off, and in the second sub-stage IIIb, the voltage level Gtd at the node N1 is maintained at (Vdata+Vth).

[0063] In the light-emitting phase V, the off reset control signal Voff-rc is again provided to the gates of the first reset transistor Tr1 and the second reset transistor Tr2 through the reset control signal line rst to turn off the first reset transistor Tr1 and the second reset transistor Tr2. The gate line GL is provided with a turn-off signal, and the first transistor T1 and the second transistor T2 in the data writing subcircuit are turned off. The light-emitting control signal line em is provided with a low voltage signal to turn on the third transistor T3 and the fourth transistor T4 of the light-emitting control subcircuit. In the light-emitting phase V, the voltage level Gtd at the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level Gtd and works in the saturation region. The following path is formed: through the third transistor T3, the driving transistor Td, and the fourth transistor T4 to the light-emitting element LE. The driving transistor Td generates a driving current to drive the light-emitting element LE to emit light. The voltage level at the node N3 connected to the drain of the driving transistor Td is equal to the light-emitting voltage of the light-emitting element LE.

[0064] A display panel with a light emitting diode is driven by a driving current to emit light. Usually, the driving current is generated by controlling the driving voltage of the driving transistor. The driving current can be calculated using the following formula:

[0065]

[0066] Wherein Id represents the driving current, Vdata represents the voltage level of the data voltage signal, Vref represents the voltage level of the reference voltage line, Vgs represents the voltage between the gate and the source of the driving transistor Td, μ represents the mobility of the driving transistor Td, Cox (W / L) represents the capacitance of the isolation layer of the gate, W represents the width of the channel of the TFT, and L represents the length of the channel of the TFT.

[0067] The storage capacitor Cst is usually used as a component for maintaining the voltage level at the gate of the driving transistor Td. In high-frequency displays (e.g., 60 Hz to 120 Hz), the typical duration required to maintain the voltage is 8.3 ms to 16.67 ms. However, in low-frequency displays (e.g., 1 Hz or lower), the typical duration required to maintain the voltage can be as long as 1 second or longer. Therefore, voltage maintenance is critical for low-frequency displays.

[0068] The inventors of the present disclosure have found that in the light emitting phase V, if the source of the first reset transistor Tr1 is provided with a low voltage signal, the voltage difference between the source of the first reset transistor Tr1 and the drain of the first reset transistor Tr1 may be a relatively large value, resulting in leakage from the drain to the source of the first reset transistor Tr1, reducing the voltage level at the node N1. The inventors of the present disclosure have found that this leakage affects the Vgs of the driving transistor Td (the voltage difference between the gate and the source of the driving transistor Td), resulting in impaired contrast and flickering of the display panel. As an example to illustrate this problem, if the source of the first reset transistor Tr1 has a voltage level of -3V and the drain of the first reset transistor Tr1 has a voltage level of 0V to 6V (the same as the voltage level of Gtd in the light emitting phase V), the voltage difference between the source of the first reset transistor Tr1 and the drain of the first reset transistor Tr1 is in the range of 3V to 9V, resulting in charge leakage at the gate of the driving transistor Td.

[0069] The inventors of the present disclosure have found that, unexpectedly and surprisingly, by making the first reset signal line SLr1 and the second reset signal line SLr2 independent of each other in the pixel driving circuit, the leakage problem can be avoided. In some embodiments, the timing of operating the pixel driving circuit also includes a voltage holding phase IV between the data writing phase III and the light emitting phase V. In the voltage holding phase IV, the control signal is maintained in the same corresponding state as the control signal in the second sub-phase IIIb, except that the voltage holding signal Vvm is provided to the first reset signal line SLr1. As an example for illustrative purposes, the source of the first reset transistor Tr1 has a voltage level of 3V, and the drain of the first reset transistor Tr1 has a voltage level of 0V to 6V (the same as the voltage level of Gtd in the light emitting phase V), and the voltage difference between the source of the first reset transistor Tr1 and the drain of the first reset transistor Tr1 is now reduced to -3V to 3V, thereby significantly preventing the charge leakage at the gate of the driving transistor Td, especially in low-frequency displays.

[0070] Table 1 shows the unexpected and surprising reduction of voltage leakage in the pixel driving circuit ("present PDC") according to the present disclosure compared to the reference pixel driving circuit ("reference PDC") in which the first reset transistor and the second reset transistor share the same reset signal or the same reset signal line. In one example, a constant first initialization voltage (e.g., at a level of -3V) is provided to the first reset signal line in the reference pixel driving circuit at all stages of the timing operation; and the first reset signal line in the pixel driving circuit according to the present disclosure is provided with a first initialization voltage (e.g., at a level of -3V) at the initial stage, the reset stage, and the data writing stage; and a voltage holding voltage (e.g., at a level of 3V) is provided at the voltage holding stage and the light emitting stage.

[0071] Table 1. Reduction of voltage leakage in the pixel driving circuit according to the present disclosure compared with the reference pixel driving circuit.

[0072]

[0073] In Table 1, V Data Represents the voltage level of the data voltage signal, V Anode represents the voltage level measured at the anode of the light emitting element, and Gtd represents the voltage level measured at the node N1 connecting the gate of the driving transistor and the second capacitor electrode, V leakage represents the measured value of the voltage leakage between the drain and source of the first reset transistor. As shown in Table 1, the voltage leakage of the pixel driving circuit can be reduced by up to 92.58% (V Data =4.2V). Optionally, the voltage leakage can be reduced by at least 40% (V Data =6.6V).

[0074] Therefore, in some embodiments, the first reset transistor Tr1 is configured to be turned on in the reset phase II to allow the first initialization voltage signal Vint1 provided by the first reset signal line SLr1 to be written into the second capacitor electrode Ce2; the first reset transistor Tr1 is configured to be turned off, and the first reset signal line SLr1 is configured to provide a voltage holding signal Vvm to the source of the first reset transistor Tr1 in the voltage holding phase IV. The voltage holding signal Vvm is different from the first initialization voltage signal Vint1. Optionally, the voltage holding signal Vvm is closer to the voltage level Gtd in the light emitting phase V than the first initialization voltage signal Vint1. Optionally, the first voltage difference between the voltage holding signal Vvm and the voltage level Gtd in the light emitting phase V is less than the second voltage difference between the first initialization voltage signal Vint1 in the data writing phase III and the voltage level Gtd in the light emitting phase V. Optionally, the first voltage difference is at least 20% smaller than the second voltage difference, for example at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 100%.

[0075] Similarly, in some embodiments, the voltage holding signal Vvm is different from the second initialization voltage signal Vint2. Optionally, the voltage holding signal Vvm is closer to the voltage level Gtd in the light emitting stage V than the second initialization voltage signal Vint2. Optionally, a first voltage difference between the voltage holding signal Vvm and the voltage level Gtd in the light emitting stage V is less than a third voltage difference between the second initialization voltage signal Vint2 in the data writing stage III and the voltage level Gtd in the light emitting stage V. Optionally, the first voltage difference is at least 20% smaller than the third voltage difference, for example, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% or at least 100%.

[0076] Optionally, the first initialization voltage signal Vint1 and the second initialization voltage signal Vint2 are substantially the same. As used herein, the term "substantially the same" means that the difference between the two values ​​does not exceed 10% of a base value (e.g., one of the two values), such as no more than 8%, no more than 6%, no more than 4%, no more than 2%, no more than 1%, no more than 0.5%, no more than 0.1%, no more than 0.05%, and no more than 0.01% of the base value.

[0077] The first reset signal line SLr1 and the second reset signal line SLr2 are independent of each other. Optionally, the second reset signal line SLr2 is provided with a second initialization voltage signal Vint2, which is constant in all stages of operation (including initial stage I, reset stage II, data writing stage III, voltage holding stage IV and light emitting stage V). Optionally, the first reset signal line SLr1 is provided with a first initialization voltage signal Vint1 in the initial stage I, reset stage II and data writing stage III; and is provided with a voltage holding signal Vvm in the voltage holding stage IV and the light emitting stage V. Optionally, the second reset signal lines respectively connected to the plurality of pixel drive circuits in the plurality of sub-pixels in the display panel are connected to a common power supply.

[0078] Figure 5 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure. Figure 6 is a timing diagram for operating a display panel having a pixel driving circuit according to some embodiments of the present disclosure. Figure 5 and Figure 6In some embodiments, the pixel driving circuit further comprises a dual signal switch sub-circuit SCDss, which is connected to the first reset signal line SLr1. The dual signal switch sub-circuit SCdss is configured to generate a first initialization voltage signal Vint1 in the reset phase II, and to generate a voltage holding signal Vvm in the voltage holding phase IV. Optionally, the dual signal switch sub-circuit SCdss is configured to generate a first initialization voltage signal Vint1 in the initial phase I, the reset phase II, and the data writing phase III; and to generate a voltage holding signal Vvm in the voltage holding phase IV and the light emitting phase V.

[0079] In some embodiments, the dual signal switch sub-circuit SCdss includes a first control transistor Tc1 and a second control transistor Tc2. Optionally, the first control transistor Tc1 includes a gate connected to the first control signal line SLc1, a source connected to the first switch signal line SLs1 configured to provide a voltage hold signal Vvm, and a drain connected to the first reset signal line SLr1. Optionally, the second control transistor Tc2 includes a gate connected to the second control signal line SLc2, a source connected to the second switch signal line SLs2 configured to provide a first initialization voltage signal Vint1, and a drain connected to the first reset signal line SLr1. In the reset phase II and the data writing phase III, the first control transistor Tc1 is configured to be turned off, and the second control transistor Tc2 is configured to be turned on. Optionally, in the initial phase I, the reset phase II and the data writing phase III, the first control transistor Tc1 is configured to be turned off, and the second control transistor Tc2 is configured to be turned on. In the voltage holding stage IV, the first control transistor Tc1 is configured to be turned on, and the second control transistor Tc2 is configured to be turned off. Optionally, in the voltage holding stage IV and the light emitting stage V, the first control transistor Tc1 is configured to be turned on, and the second control transistor Tc2 is configured to be turned off.

[0080] See also Figure 5 and Figure 6In at least one of the initial stage I, the reset stage II, and the data writing stage III, the first off control signal Voff1 is provided to the gate of the first control transistor Tc1 through the first control signal line SLc1 to turn off the first control transistor Tc1 of the dual signal switch sub-circuit SCdss. The first initialization voltage signal Vint1 is provided to the source of the second control transistor Tc1 through the second switch signal line SLs2. The second on control signal Von2 is provided to the gate of the second control transistor Tc2 through the second control signal line SLc2 to turn on the second control transistor Tc2 of the dual signal switch sub-circuit SCdss, thereby allowing the first initialization voltage signal Vint1 to be transmitted from the source of the second control transistor Tc2 to the drain of the second control transistor Tc2, and then to the first reset signal line SLr1 connected to the drain of the second control transistor Tc2. The first reset signal line SLr1 is configured to provide the first initialization voltage signal Vint1 to the first reset transistor Tr1 in at least one of the initial stage I, the reset stage II, and the data writing stage III.

[0081] In at least one of the voltage holding phase IV and the light emitting phase V, the second turn-off control signal Voff2 is provided to the gate of the second control transistor Tc2 through the second control signal line SLc2 to turn off the second control transistor Tc2 of the dual signal switch sub-circuit SCdss. The voltage holding signal Vvm is provided to the source of the first control transistor Tc1 through the first switch signal line SLs1. The first turn-on control signal Von1 is provided to the gate of the first control transistor Tc1 through the first control signal line SLc1 to turn on the first control transistor Tc1 of the dual signal switch sub-circuit SCdss, thereby allowing the voltage holding signal Vvm to be transmitted from the source of the first control transistor Tc1 to the drain of the first control transistor Tc1, and then to the first reset signal line SLr1 connected to the drain of the first control transistor Tc1. The first reset signal line SLr1 is configured to provide the voltage holding signal Vvm to the first reset transistor Tr1 in at least one of the voltage holding phase IV and the light emitting phase V. The timing of other control signals (reset control signal line rst, gate line GL, light emission control signal line em, voltage level Gtd, first reset signal line SLr1 and second reset signal line SLr2) is similar to Figure 4 The timing described in the relevant text is very similar.

[0082] Figure 7 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure. Figure 8 is a timing diagram for operating a display panel having a pixel driving circuit according to some embodiments of the present disclosure. Figure 7 and Figure 8In some embodiments, the pixel driving circuit further includes a reverse switch subcircuit SCis connected to the dual signal switch subcircuit SCdss. In at least one of the initial stage I, the reset stage II, and the data writing stage III, the reverse switch subcircuit SCis is configured to generate a first off control signal Voff1, which reaches the gate of the first control transistor Tc1 through the first control signal line SLc1 to turn off the first control transistor Tc1 of the dual signal switch subcircuit SCdss, and generate a second on control signal Von2, which reaches the gate of the second control transistor Tc2 through the second control signal line SLc2 to turn on the second control transistor Tc2 of the dual signal switch subcircuit SCdss. In at least one of the voltage holding stage IV and the light emitting stage V, the reverse switching sub-circuit SCis is configured to generate a first turn-on control signal Von1, which reaches the gate of the first control transistor Tc1 through the first control signal line SLc1 to turn on the first control transistor Tc1 of the dual-signal switching sub-circuit SCdss, and to generate a second turn-off control signal Voff2, which reaches the gate of the second control transistor Tc2 through the second control signal line SLc2 to turn off the second control transistor Tc2 of the dual-signal switching sub-circuit SCdss.

[0083] In some embodiments, the reverse switch subcircuit SCis includes a third control transistor Tc3 and a fourth control transistor Tc4. Optionally, the third control transistor Tc3 includes a gate connected to the first control signal line SLc1, a source connected to the first voltage signal line SLv1 configured to provide a first voltage signal (e.g., a high voltage signal), and a drain connected to the second control signal line SLc2. Optionally, the fourth control transistor Tc4 includes a gate connected to the third control signal line SLc3, a source connected to the second voltage signal line SLv2 configured to provide a second voltage signal (e.g., a low voltage signal), and a drain connected to the second control signal line SLc2.

[0084] The first control signal line SLc1 is connected to both the gate of the third control transistor Tc3 and the gate of the first control transistor Tc1. The second control signal line SLc2 is connected to the drains of the third control transistor Tc3 and the fourth control transistor Tc4, and the gate of the second control transistor Tc2.

[0085] In the reset phase II and the data writing phase III, the third control transistor Tc3 is configured to be turned off, and the fourth control transistor Tc4 is configured to be turned on. Optionally, in the initial phase I, the reset phase II and the data writing phase III, the third control transistor Tc3 is configured to be turned off, and the fourth control transistor Tc4 is configured to be turned on. In the voltage holding phase IV, the third control transistor Tc3 is configured to be turned on, and the fourth control transistor Tc4 is configured to be turned off. Optionally, in the voltage holding phase IV and the light emitting phase V, the third control transistor Tc3 is configured to be turned on, and the fourth control transistor Tc4 is configured to be turned off.

[0086] Reference Figure 7 and Figure 8 In at least one of the initial stage I, the reset stage II, and the data writing stage III, the first turn-off control signal Voff1 is provided to the gate of the third control transistor Tc3 of the reverse switch sub-circuit SCis through the first control signal line SLc1 to turn off the third control transistor Tc3 of the reverse switch sub-circuit SCis connected to the dual signal switch sub-circuit SCdss, and the first turn-off control signal Voff1 is simultaneously provided to the gate of the first control transistor Tc1 to turn off the first control transistor Tc1. A second voltage signal (e.g., a low voltage signal) is provided to the source of the fourth control transistor Tc4 of the reverse switch sub-circuit SCis through the second voltage signal line SLv2. The third turn-on control signal Von3 is provided to the gate of the fourth control transistor Tc4 of the reverse switch sub-circuit SCis through the third control signal line SLc3 to turn on the fourth control transistor Tc4 of the reverse switch sub-circuit SCis, thereby allowing the second voltage signal to be transmitted from the source of the fourth control transistor Tc4 to the drain of the fourth control transistor Tc4, and then to the second control signal line SLc2 connected to the gate of the second control transistor Tc2. The second voltage signal (e.g., a low voltage signal) is used as the second turn-on control signal Von2 to turn on the second control transistor Tc2 in at least one of the initial stage I, the reset stage II, and the data writing stage III.

[0087] In at least one of the voltage holding phase IV and the light emitting phase V, the third turn-off control signal Voff3 is provided to the gate of the fourth control transistor Tc4 of the reverse switch sub-circuit SCis through the third control signal line SLc3 to turn off the fourth control transistor Tc4. The first voltage signal (e.g., a high voltage signal) is provided to the source of the third control transistor Tc3 of the reverse switch sub-circuit SCis connected to the dual signal switch sub-circuit SCdss through the first voltage signal line SLv1. The first turn-on control signal Von1 is provided to the gate of the third control transistor Tc3 through the first control signal line SLc1 to turn on the third control transistor Tc3, thereby allowing the first voltage signal (e.g., a high voltage signal) to be transmitted from the source of the third control transistor Tc3 to the drain of the third control transistor Tc3, and then to the second control signal line SLc2 connected to the gate of the second control transistor Tc2. The first voltage signal (e.g., a high voltage signal) is used as the second turn-off control signal Voff2 to turn off the second control transistor Tc2 in at least one of the voltage holding phase IV and the light emitting phase V. The timing of other control signals (reset control signal line rst, gate line GL, light emission control signal line em, voltage level Gtd, first reset signal line SLr1, second reset signal line SLr2, first control signal line SLc1 and second control signal line SLc2) is the same as Figure 4 and Figure 6 and the timing described in the relevant text is basically similar.

[0088] Reference Figure 8 , the third conduction control signal Von3 has different voltage levels in the initial stage I and the reset stage II. The voltage level of the third conduction control signal Von3 in the reset stage II is lower than the voltage level of the third conduction control signal Von3 in the initial stage I.

[0089] In another aspect, the present disclosure also provides a display device including the pixel driving circuit described herein, a first control array upper gate circuit connected to a third control signal line, and a second control array upper gate circuit connected to the first control signal line. Fig. 9 is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure. Fig.10 is a schematic diagram showing the structure of a display device in some embodiments of the present disclosure. Fig.11 is an image of a layout of a peripheral area of ​​a display device in some embodiments of the present disclosure. Figures 9 to 11In some embodiments, the display device displays an image in a plurality of sub-pixels row by row. Therefore, each row of pixel driving circuits for driving each row of sub-pixels is connected to a dual signal switch sub-circuit SCdss and a reverse switch sub-circuit SCis. In order to scan the first reset signal line in a row-by-row manner, the display device includes an additional array upper gate unit, such as a first control array upper gate circuit RST_GOA connected to the third control signal line SLc3 and a second control array upper gate circuit EMS_GOA connected to the first control signal line SLc1. The display device also includes a gate scanning array upper gate circuit Gate_GOA connected to multiple rows of gate lines and an emitting scanning array upper gate circuit EM_GOA connected to multiple rows of emitting control signal lines.

[0090] Fig.11 An example is shown in which the second control array upper gate circuit EMS_GOA, the first control array upper gate circuit RST_GOA, the reverse switch subcircuit SCis, the dual signal switch subcircuit SCdss, the light emitting scan array upper gate circuit EM_GOA and the gate scan array upper gate circuit Gate_GOA are arranged sequentially. Various alternative arrangements can be implemented in which the order of the various circuits can be changed.

[0091] The first control array upper gate circuit RST_GOA is configured to generate a signal for the third control signal line SLc3 in each row of the plurality of rows of pixel driving circuits. Figure 8 and Fig.10 , the third conduction control signal Von3 has different voltage levels in the initial stage I and the reset stage II. The voltage level of the third conduction control signal Von3 in the reset stage II is lower than the voltage level of the third conduction control signal Von3 in the initial stage I. In the initial stage I, the voltage level of the third conduction control signal Von3 is (VGL-Vth), where Vth is the threshold voltage of the driving transistor Td, and VGL is the second voltage signal provided to the second voltage signal line SLv2. In the reset stage II, due to the boost function of the gate circuit RST_GOA on the first control array, the third conduction control signal Von3 is further reduced to a voltage level (2VGL-VGH-Vth), where Vth is the threshold voltage of the driving transistor Td, VGH is the first voltage signal provided to the first voltage signal line SLv1, and VGL is the second voltage signal provided to the second voltage signal line SLv2. Therefore, in the reset stage II, the third conduction control signal Von3 is much lower than the voltage level of VGL, which helps the fourth control transistor Tc4 to be fully turned on.

[0092] In some embodiments, the display device includes a plurality of rows of pixel driving circuits. The pixel driving circuits described herein are pixel driving circuits in each row of the plurality of rows of pixel driving circuits. Optionally, each row of the plurality of rows of pixel driving circuits is connected to a dual-signal switch subcircuit and a reverse switch subcircuit. Optionally, for each row of the plurality of rows of pixel driving circuits, the dual-signal switch subcircuit is configured to generate a first initialization voltage signal in a reset phase and to generate a voltage hold signal in a voltage hold phase.

[0093] Fig.12 is a circuit diagram showing the structure of a multi-row pixel driving circuit according to some embodiments of the present disclosure. Fig.13 is a timing diagram for operating a display panel having a pixel driving circuit according to some embodiments of the present disclosure. Fig.12 and Fig.13 , showing a row Rn and a next adjacent row R(n+1) of a multi-row pixel driving circuit. Each row of the multi-row pixel driving circuit (e.g., the corresponding row Rn and the next adjacent row R(n+1)) is connected to a set of reverse switch sub-circuits SCi and dual-signal switch sub-circuits SCdss for receiving a first initialization voltage signal in a reset phase and receiving a voltage holding signal in a voltage holding phase. Each row of the multi-row pixel driving circuit (e.g., the corresponding row Rn and the next adjacent row R(n+1)) is connected to a single first control array upper gate circuit in the first control array upper gate circuit RST_GOA, which provides a third turn-off control signal Voff3 and a third turn-on control signal Von3. However, multiple rows of pixel driving circuits (e.g., the corresponding row Rn and the next adjacent row R(n+1)) are commonly connected to a single second control array upper gate circuit in the second control array upper gate circuit EMS_GOA, which provides the first turn-on control signal Von1 and the first turn-off control signal Voff1 to the reverse switch sub-circuit SCis and the dual signal switch sub-circuit SCdss in the multiple rows of pixel driving circuits (e.g., the corresponding row Rn and the next adjacent row R(n+1)).

[0094] In some embodiments, each of the light emitting scanning array upper gate circuit EM_GOA and the second control array upper gate circuit EMS_GOA, the gate scanning array upper gate circuit Gate_GOA and the first control array upper gate circuit RST_GOA includes a plurality of cascaded shift registers.

[0095] Fig.14 is a circuit diagram of a light emitting control shift register. In some examples of the present disclosure, Fig.14 The light emitting control shift registers shown represent the various shift registers in the gate circuit EM_GOA on the light emitting scanning array, or the various shift registers in the gate circuit EMS_GOA on the second control array. Fig.15 is Fig.14 The timing diagram of the signals in the case of the light emission control shift register operation is shown below. Fig.14 and Fig.15 Briefly describe the operation process of the light emission control shift register.

[0096] like Fig.14 As shown, the light emitting control shift register 100 includes ten transistors (a first transistor T1, a second transistor T2, ..., a tenth transistor T10) and three capacitors (a first capacitor C1, a second capacitor C2, and a third capacitor C3). For example, in the case where a plurality of light emitting control shift registers are cascaded, the first electrode of the first transistor T1 in the first-stage light emitting control shift register 100 is configured to be connected to the first trigger signal line ESTV1 to receive the first trigger signal ESTV1, and the first electrode of the first transistor T1 in each of the other stages of the light emitting control shift register 100 is connected to the previous-stage light emitting control shift register 100 to receive the first output signal EM output by the previous-stage light emitting control shift register 100.

[0097] In addition, Fig.14 and Fig.15 In the figure, CK represents the first clock signal terminal, ECK represents the first clock signal line and the first clock signal, and the first clock signal terminal CK is connected to the first clock signal line ECK to receive the first clock signal; CB represents the second clock signal terminal, ECB represents the second clock signal line and the second clock signal, and the second clock signal terminal CB is connected to the second clock signal line ECB to receive the second clock signal. For example, the first clock signal ECK and the second clock signal ECB can use a pulse signal with a duty cycle greater than 50%; VGH1 represents the first power line and the first power supply voltage provided by the first power line. For example, the first power supply voltage is a DC high level voltage, VGL1 represents the third power line and the second power supply voltage provided by the third power line, for example, the second power supply voltage is a DC low level voltage, and the first power supply voltage is greater than the second power supply voltage; N1, N2, N3 and N4 represent the first node, the second node, the third node and the fourth node, respectively.

[0098] like Fig.14As shown, the gate of the first transistor T1 is connected to the first clock signal terminal CK (i.e., the first clock signal line ECK) to receive the first clock signal, the first electrode of the first transistor T1 is connected to the input terminal IN, and the second electrode of the first transistor T1 is connected to the first node N1. For example, in the case where the light emitting control shift register is a first-stage shift register, the input terminal IN is connected to the first trigger signal line ESTV1 to receive the first trigger signal, and in the case where the light emitting control shift register is a shift register other than the first-stage shift register, the input terminal IN of the light emitting control shift register is connected to the output terminal OUT of the previous-stage light emitting control shift register of the light emitting control shift register.

[0099] A gate of the second transistor T2 is connected to the first node N1 , a first electrode of the second transistor T2 is connected to the first clock signal line ECK to receive the first clock signal, and a second electrode of the second transistor T2 is connected to the second node N2 .

[0100] A gate of the third transistor T3 is connected to the first clock signal line ECK to receive the first clock signal, a first electrode of the third transistor T3 is connected to the third power line VGL1 to receive the second power voltage, and a second electrode of the third transistor T3 is connected to the second node N2.

[0101] A gate of the fourth transistor T4 is connected to the second clock signal terminal CB (ie, the second clock signal line ECB) to receive the second clock signal, a first electrode of the fourth transistor T4 is connected to the first node N1, and a second electrode of the fourth transistor T4 is connected to the first electrode of the fifth transistor T5.

[0102] A gate electrode of the fifth transistor T5 is connected to the second node N2 , and a second electrode of the fifth transistor T5 is connected to the first power line VGH to receive the first power voltage.

[0103] A gate electrode of the sixth transistor T6 is connected to the second node N2 , a first electrode of the sixth transistor T6 is connected to the second clock signal line ECB to receive the second clock signal, and a second electrode of the sixth transistor T6 is connected to the third node N3 .

[0104] A first end of the first capacitor C1 is connected to the second node N2 , and a second end of the first capacitor C1 is connected to the third node N3 .

[0105] A gate of the seventh transistor T7 is connected to the second clock signal line ECB to receive the second clock signal, a first electrode of the seventh transistor T7 is connected to the third node N3, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0106] A gate of the eighth transistor T8 is connected to the first node N1 , a first electrode of the eighth transistor T8 is connected to the first power line VGH1 to receive the first power voltage, and a second electrode of the eighth transistor T8 is connected to the fourth node N4 .

[0107] A gate of the ninth transistor T9 is connected to the fourth node N4 , a first electrode of the ninth transistor T9 is connected to the first power line VGH1 to receive the first power voltage, and a second electrode of the ninth transistor T9 is connected to the output terminal OUT.

[0108] A first end of the third capacitor C3 is connected to the fourth node N4 , and a second end of the third capacitor C3 is connected to the first power line VGH1 to receive the first power voltage.

[0109] A gate of the tenth transistor T10 is connected to the first node N1 , a first electrode of the tenth transistor T10 is connected to the third power line VGL1 to receive the second power voltage, and a second electrode of the tenth transistor T10 is connected to the output terminal OUT.

[0110] A first end of the second capacitor C2 is connected to the second clock signal line ECB to receive the second clock signal, and a second end of the second capacitor C2 is connected to the first node N1.

[0111] Fig.14 The transistors in the light emitting control shift register 100 shown are all described by taking P-type transistors as examples, that is, when the gate of each transistor is connected to a low level, each transistor is turned on, and when the gate of each transistor is connected to a high level, each transistor is turned off. In this case, the first electrode can be a source electrode, and the second electrode can be a drain electrode.

[0112] Embodiments of the present disclosure include but are not limited to Fig.14 The configuration shown, for example, Fig.14 The transistors in the light emitting control shift register 100 shown may also be N-type transistors, or may be P-type transistors and N-type transistors, as long as the port polarities of the selected type of transistors are connected correspondingly to the port polarities of the corresponding transistors in the embodiments of the present disclosure.

[0113] As described above, in some examples of the present disclosure, Fig.14The light emitting control shift register shown represents each shift register in the gate circuit EM_GOA on the light emitting scanning array, or each shift register in the gate circuit EMS_GOA on the second control array. In some embodiments, the size of the ninth transistor T9 in the gate circuit EM_GOA on the light emitting scanning array is larger than the size of the ninth transistor T9 in the gate circuit EMS_GOA on the second control array. Optionally, the ratio of the size of the ninth transistor T9 in the gate circuit EM_GOA on the light emitting scanning array to the size of the ninth transistor T9 in the gate circuit EMS_GOA on the second control array is in the range of 2:1 to 3:1. Optionally, the ratio of the channel length of the ninth transistor T9 in the gate circuit EM_GOA on the light emitting scanning array to the channel length of the ninth transistor T9 in the gate circuit EMS_GOA on the second control array is in the range of 2:1 to 3:1. Optionally, the ratio of the channel width of the ninth transistor T9 in the gate circuit EM_GOA on the light emitting scanning array to the channel width of the ninth transistor T9 in the gate circuit EMS_GOA on the second control array is in the range of 2:1 to 3:1.

[0114] In some embodiments, the size of the tenth transistor T10 in the light emitting scanning array upper gate circuit EM_GOA is greater than the size of the tenth transistor T10 in the second control array upper gate circuit EMS_GOA. Optionally, the ratio of the size of the tenth transistor T10 in the light emitting scanning array upper gate circuit EM_GOA to the size of the tenth transistor T10 in the second control array upper gate circuit EMS_GOA is in the range of 2:1 to 3:1. Optionally, the ratio of the channel length of the tenth transistor T10 in the light emitting scanning array upper gate circuit EM_GOA to the channel length of the tenth transistor T10 in the second control array upper gate circuit EMS_GOA is in the range of 2:1 to 3:1. Optionally, the ratio of the channel width of the tenth transistor T10 in the light emitting scanning array upper gate circuit EM_GOA to the channel width of the tenth transistor T10 in the second control array upper gate circuit EMS_GOA is in the range of 2:1 to 3:1.

[0115] Fig.16 It is a schematic diagram of the circuit structure of a shift register unit of a display substrate provided in some embodiments of the present disclosure. Fig.17 is Fig.16 The timing diagram of the signal in the case of the light emitting control shift register operation shown in FIG. Fig.16 The shift register shown represents a corresponding shift register in a gate-on-array circuit Gate_GOA, or represents a corresponding shift register in a first control array gate circuit RST_GOA.

[0116] For example, Fig.16 As shown, the shift register unit 100 includes an input control circuit 110, an input circuit 120, an output circuit 130 and an output terminal GOUT.

[0117] For example, the first signal line group of the display substrate includes a first clock signal line CK and a second clock signal line CB, the first clock signal line CK is configured to provide a first clock signal, and the second clock signal line CB is configured to provide a second clock signal. The plurality of power lines include a first power line VGL and a second power line VGH, the first power line VGL is configured to provide a first power signal, and the second power line VGH is configured to provide a second power signal.

[0118] For example, the input control circuit 110 is configured to input a first power supply signal to the output circuit 130 in response to a first clock signal.

[0119] For example, Fig.16 As shown, the input control circuit 110 is electrically connected to the first power line VGL, the first clock signal line CK, and the second node N2, respectively. The first power line VGL is configured to provide a first power signal, the first clock signal line CK is configured to provide a first clock signal, and the second node N2 is electrically connected to the output circuit 130. The input control circuit 110 is configured to write the first power signal on the first power line VGL to the second node N2 under the control of the first clock signal on the first clock signal line CK. That is, under the control of the first clock signal, when the input control circuit 110 is turned on, the first power signal on the first power line VGL can be transmitted to the output circuit 130.

[0120] For example, the input control circuit 110 includes a first transistor T1, and the control terminal of the input control circuit 110 includes a gate of the first transistor T1. The gate of the first transistor T1 is electrically connected to the first clock signal line CK to receive the first clock signal, a first electrode of the first transistor T1 is electrically connected to the first power line VGL to receive the first power signal, and a second electrode of the first transistor T1 is electrically connected to the second node N2.

[0121] For example, the input circuit 120 is configured to input an input signal to the output circuit 130 in response to a first clock signal.

[0122] For example, Fig.16As shown, the input circuit 120 is electrically connected to the input signal line STV, the first clock signal line CK, and the third node N3, respectively. The input signal line STV is configured to provide an input signal, the first clock signal line CK is configured to provide a first clock signal, and the third node N3 is electrically connected to the output circuit 130. The input circuit 120 is configured to write the input signal on the input signal line STV to the third node N3 under the control of the first clock signal on the first clock signal line CK. That is, under the control of the first clock signal, when the input circuit 120 is turned on, the input signal on the input signal line STV can be transmitted to the output circuit 130.

[0123] For example, the input circuit 120 includes a second transistor T2, and the control terminal of the input circuit 120 includes a gate of the second transistor T2. The gate of the second transistor T2 is electrically connected to the first clock signal line CK to receive the first clock signal, a first electrode of the second transistor T2 is electrically connected to the input signal line STV to receive the input signal, and a second electrode of the second transistor T2 is electrically connected to the third node N3.

[0124] Note that Fig.16 In the example shown, the gate of the first transistor T1 and the gate of the second transistor T2 are both electrically connected to the first clock signal line CK, but the embodiments of the present disclosure are not limited thereto. In some examples, the gate of the first transistor T1 and the gate of the second transistor T2 can also be electrically connected to two different signal lines.

[0125] For example, the output circuit 130 is configured to output the second clock signal or the second power signal to the output terminal GOUT under the control of the input signal and the first power signal.

[0126] For example, Fig.16As shown, the output circuit 130 is electrically connected to the second node N2, the third node N3, the output terminal GOUT, the first power line VGL, the second power line VGH, the first clock signal line CK and the second clock signal line CB, respectively. The first power line VGL is configured to provide a first power signal, the second power line VGH is configured to provide a second power signal, and the second clock signal line CB is configured to provide a second clock signal. Under the control of the input signal written to the third node N3 and the first power signal written to the second node N2, the output circuit 130 outputs the second clock signal on the second clock signal line CB or the second power signal on the second power line VGH to the output terminal GOUT. That is, under the control of the input signal and the first power signal, when the output circuit 130 allows the second clock signal line CB to be electrically connected to the output terminal GOUT, the second clock signal can be output to the output terminal GOUT as an output signal. Alternatively, when the output circuit 130 allows the second power line VGH to be electrically connected to the output terminal GOUT, the second power signal can be output to the output terminal GOUT as an output signal.

[0127] For example, in a gate drive circuit including Fig.16 In the case of multiple cascaded shift register units 100 shown, the output terminal GOUT can be electrically connected to the corresponding gate line to control multiple rows of pixel units in the pixel array on the display substrate 10 to be turned on sequentially, that is, the output signal of the output terminal GOUT can be used as a switching state voltage signal for controlling each pixel unit of the display substrate 10.

[0128] For example, the output circuit 130 includes an output subcircuit, a first output control subcircuit, and a second output control subcircuit.

[0129] For example, Fig.16 As shown, the output subcircuit is electrically connected to the second clock signal line CB, the output terminal GOUT and the first node N1 respectively. The output subcircuit is configured to output the second clock signal on the second clock signal line CB as an output signal to the output terminal GOUT under the control of the level of the first node N1.

[0130] For example, the output subcircuit includes an eighth transistor T8, a gate of the eighth transistor T8 is electrically connected to the first node N1, a first electrode of the eighth transistor T8 is electrically connected to the second clock signal line CB to receive the second clock signal, and a second electrode of the eighth transistor T8 is electrically connected to the output terminal GOUT.

[0131] For example, the first output control subcircuit is electrically connected to the second power line VGH, the output terminal GOUT and the second node N2 respectively. The first output control subcircuit is configured to output the second power signal on the second power line VGH as an output signal to the output terminal GOUT under the control of the level of the second node N2.

[0132] For example, the first output control subcircuit includes a third transistor T3, a gate of the third transistor T3 is electrically connected to the second node N2, a first electrode of the third transistor T3 is electrically connected to the second power line VGH to receive a second power signal, and a second electrode of the third transistor T3 is electrically connected to the output terminal GOUT.

[0133] For example, the second output control subcircuit is electrically connected to the first node N1, the second node N2, the third node N3, the first clock signal line CK, the second clock signal line CB, the first power line VGL, and the second power line VGH, respectively. The second output control subcircuit is configured to control the level of the first node N1 and the level of the second node N2. For example, when the level of the first node N1 can control the output subcircuit to be turned on, the output subcircuit can write the second clock signal as the output signal to the output terminal GOUT; and when the level of the second node N2 can control the first output control subcircuit to be turned on, the first output control subcircuit can write the second power signal as the output signal to the output terminal GOUT.

[0134] For example, the second output control subcircuit includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0135] For example, a gate of the fourth transistor T4 is electrically connected to the second node N2, a first electrode of the fourth transistor T4 is electrically connected to the second power line VGH to receive the second power signal, and a second electrode of the fourth transistor T4 is electrically connected to a first electrode of the fifth transistor T5.

[0136] For example, a gate electrode of the fifth transistor T5 is electrically connected to the second clock signal line CB to receive the second clock signal, and a second electrode of the fifth transistor T5 is electrically connected to the third node N3.

[0137] For example, a gate of the sixth transistor T6 is electrically connected to the first power line VGL to receive a first power signal, a first electrode of the sixth transistor T6 is electrically connected to the third node N3, and a second electrode of the sixth transistor T6 is electrically connected to the first node N1.

[0138] For example, a gate of the seventh transistor T7 is electrically connected to the third node N3, a first electrode of the seventh transistor T7 is electrically connected to the first clock signal line CK to receive the first clock signal, and a second electrode of the seventh transistor T7 is electrically connected to the second node N2.

[0139] For example, Fig.16As shown, the output circuit 130 further includes a first storage subcircuit for maintaining the level at the second node N2. For example, the first storage subcircuit includes a first capacitor C1, a first electrode of the first capacitor C1 is electrically connected to the second node N2, and a second electrode of the first capacitor C1 is electrically connected to the second power line VGH and the first electrode of the third transistor T3.

[0140] For example, Fig.16 As shown, the output circuit 130 further includes a second storage subcircuit, and the second storage subcircuit is used to maintain the level at the first node N1. For example, the second storage subcircuit includes a second capacitor C2, a first electrode of the second capacitor C2 is electrically connected to the first node N1, and a second electrode of the second capacitor C2 is electrically connected to the output terminal GOUT and the second electrode of the eighth transistor T8.

[0141] For example, both the first power signal and the second power signal can be DC voltage signals. For example, the first power signal is a low level signal (e.g., 0V, -5V or other voltages), and the second power signal is a high level signal (e.g., 5V, 10V or other voltages). It should be noted that the low level signal and the high level signal are relative, and the low level signal is less than the high level signal. In different embodiments, the value of the high level signal can be different, and the value of the low level signal can also be different.

[0142] Notice, Fig.16 The input control circuit 110, the input circuit 120 and the output circuit 130 shown are only examples of the embodiments of the present disclosure, and the shift register unit of the display substrate provided by the embodiments of the present disclosure includes but is not limited to Fig.16 The situation shown.

[0143] Note that all transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors or other switching elements with the same characteristics. The source and drain of the transistor used here may be symmetrical in structure, and therefore, the source and drain of the transistor may be structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two electrodes other than the gate of the transistor, one of the two electrodes is described as a first electrode, and the other of the two electrodes is described as a second electrode, so that the first electrode and the second electrode of all or part of the transistors in the embodiments of the present disclosure can be interchanged as needed. For example, the first electrode of the transistor described in the embodiments of the present disclosure may be a source, and the second electrode of the transistor described in the embodiments of the present disclosure may be a drain. Alternatively, the first electrode of the transistor may be a drain, and the second electrode of the transistor may be a source. In addition, according to the characteristics, transistors may be divided into N-type transistors and P-type transistors. When the transistor is a P-type transistor, the on-voltage is a low-level voltage (e.g., 0V, -5V or other values), and the off-voltage is a high-level voltage (e.g., 5V, 10V or other values); when the transistor is an N-type transistor, the on-voltage is a high-level voltage (e.g., 5V, 10V or other values), and the off-voltage is a low-level voltage (e.g., 0V, -5V or other values).

[0144] For example, in Fig.16 In the embodiments of the present disclosure described in , all transistors are P-type transistors.

[0145] For example, in Fig.16 In the embodiment of the present disclosure shown, the channel of the transistor may correspond to, for example, a channel region between a source region and a drain region of an active layer of the transistor, the distance between the source region and the drain region is the length of the channel of the transistor, and the extension direction of the channel of the transistor is the direction from the first electrode to the second electrode of the transistor. The extension direction of the channel of at least one selected from the group consisting of the first transistor T1 to the eighth transistor T8 is parallel to the extension direction of the clock signal line (for example, the first clock signal line CK and the second clock signal line CB), so that the width of the position occupied by the gate drive circuit of the shift register unit including multiple cascades in the display substrate is reduced, thereby optimizing the layout structure of the display substrate, reducing the frame size of the display device including the display substrate, and realizing a narrow frame design.

[0146] As described above, in some examples of the present disclosure, Fig.16The shift registers shown represent the individual shift registers in the gate circuit Gate_GOA on the gate scan array, or the individual shift registers in the gate circuit RST_GOA on the first control array. In some embodiments, the size of the third transistor T3 in the gate circuit Gate_GOA on the gate scan array is larger than the size of the third transistor T3 in the gate circuit RST_GOA on the first control array. Optionally, the ratio of the size of the third transistor T3 in the gate circuit Gate_GOA on the gate scan array to the size of the third transistor T3 in the gate circuit RST_GOA on the first control array is in the range of 2:1 to 3:1. Optionally, the ratio of the channel length of the third transistor T3 in the gate circuit Gate_GOA on the gate scan array to the channel length of the third transistor T3 in the gate circuit RST_GOA on the first control array is in the range of 2:1 to 3:1. Optionally, a ratio of a channel width of the third transistor T3 in the gate circuit Gate_GOA on the gate scan array to a channel width of the third transistor T3 in the gate circuit RST_GOA on the first control array is in a range of 2:1 to 3:1.

[0147] Optionally, the ratio of the size of the eighth transistor T8 in the gate circuit Gate_GOA on the gate scan array to the size of the eighth transistor T8 in the gate circuit RST_GOA on the first control array is in the range of 2:1 to 3:1. Optionally, the ratio of the channel length of the eighth transistor T8 in the gate circuit Gate_GOA on the gate scan array to the channel length of the eighth transistor T8 in the gate circuit RST_GOA on the first control array is in the range of 2:1 to 3:1. Optionally, the ratio of the channel width of the eighth transistor T8 in the gate circuit Gate_GOA on the gate scan array to the channel width of the eighth transistor T8 in the gate circuit RST_GOA on the first control array is in the range of 2:1 to 3:1.

[0148] In some embodiments, the display device further includes a data driver integrated circuit. Optionally, the data driver integrated circuit is configured to provide a data voltage signal to a plurality of sub-pixels in each frame image before displaying each frame image in the plurality of frames of images; and to designate the calculated value as the value of the voltage holding signal. Optionally, the calculated value is calculated by a function based on the data voltage signals of the plurality of sub-pixels in each frame image. Optionally, the function includes an average algorithm, and the calculated value is equal to the sum of the threshold voltage of the driving transistor and the average value of the data voltage signals of the plurality of sub-pixels. Optionally, the average algorithm is selected from the group consisting of a root mean square value algorithm, an arithmetic average algorithm, a geometric average algorithm, and a weighted average algorithm. Optionally, the function is based on a data signal compensation model f(Vdata(1), Vdata(2), ..., Vdata(N)); Vdata(1), Vdata(2), ..., Vdata(N) represent the data voltage signals of the plurality of sub-pixels.

[0149] In another aspect, the present disclosure provides an array substrate. Figures 11 to 17 In some embodiments, the array substrate includes a first control array gate circuit RST_GOA, which includes a plurality of cascaded first shift registers; a second control array gate circuit EMS_GOA, which includes a plurality of cascaded second shift registers; and a plurality of rows of dual-signal switch sub-circuits and reverse switch sub-circuits, each row including a dual-signal switch sub-circuit SCdss and a reverse switch sub-circuit SCis.

[0150] In some embodiments, the dual-signal switch sub-circuit SCdss in each row is connected to the first reset signal line SLr1; and the reverse switch sub-circuit SCis in each row is connected to the dual-signal switch sub-circuit SCdss. Optionally, the dual-signal switch sub-circuit SCdss is configured to generate a first initialization voltage signal Vint1 in the reset phase, and to generate a voltage holding signal Vvm in the voltage holding phase. Optionally, in the reset phase, the reverse switch sub-circuit SCis is configured to generate a first turn-off control signal to the gate of the first control transistor Tc1 through the first control signal line SLc1 to turn off the first control transistor Tc1 of the dual-signal switch sub-circuit SCdss, and to generate a second turn-on control signal Von2 to the gate of the second control transistor Tc2 through the second control signal line SLc2 to turn on the second control transistor Tc2 of the dual-signal switch sub-circuit SCdss. Optionally, in the voltage holding stage, the reverse switch sub-circuit SCis is configured to generate a first turn-on control signal Von1 to the gate of the first control transistor Tc1 through the first control signal line SLc1 to turn on the first control transistor Tc1 of the dual-signal switch sub-circuit SCdss, and to generate a second turn-off control signal Voff2 to the gate of the second control transistor Tc2 through the second control signal line SLc2 to turn off the second control transistor Tc2 of the dual-signal switch sub-circuit SCdss.

[0151] In some embodiments, multiple rows of dual-signal switch subcircuits and reverse switch subcircuits are respectively connected to multiple first shift registers of the first control array upper gate circuit RST_GOA. Optionally, the number of the multiple rows is the same as the number of the multiple first shift registers. Optionally, each of the multiple first shift registers is configured to provide a third turn-off control signal Voff3 and a third turn-on control signal Von3 to the reverse switch subcircuit SCis in each of the multiple rows.

[0152] In some embodiments, the plurality of rows of dual-signal switch subcircuits and the reverse switch subcircuits are commonly connected to a single second shift register of the second control array upper gate circuit EMS_GOA. Optionally, the single second shift register is configured to provide the reverse switch subcircuits and the dual-signal switch subcircuits in the plurality of rows of dual-signal switch subcircuits and the reverse switch subcircuits with a first turn-on control signal Von1 and a first turn-off control signal Voff1.

[0153] In some embodiments, the array substrate further includes a gate circuit Gate_GOA on a gate scanning array, which includes a plurality of cascaded third shift registers, which are configured to generate a plurality of gate drive signals; and a gate circuit EM_GOA on a light emitting scanning array, which includes a plurality of cascaded fourth shift registers configured to generate a plurality of light emitting control signals. Optionally, each first shift register in the plurality of cascaded first shift registers and each third shift register in the plurality of cascaded third shift registers have the same circuit structure. Optionally, each second shift register in the plurality of cascaded second shift registers and each fourth shift register in the plurality of cascaded fourth shift registers have the same circuit structure. Optionally, the ratio of the size of the output transistors in each first shift register in the plurality of cascaded first shift registers and each third shift register in the plurality of cascaded third shift registers is in the range of 1:3 to 1:2. Optionally, a ratio of sizes of output transistors in each of the plurality of cascaded second shift registers and each of the plurality of cascaded fourth shift registers is in the range of 1:3 to 1:2.

[0154] In some embodiments, the array substrate further comprises a plurality of rows of pixel driving circuits, which are electrically connected to the plurality of rows of dual signal switch subcircuits and the reverse switch subcircuits, respectively. Optionally, the plurality of rows of pixel driving circuits are located in the display area AA of the array substrate. Optionally, the first control array upper gate circuit RST_GOA, the second control array upper gate circuit EMS_GOA, the gate scanning array upper gate circuit Gate_GOA, the light emitting scanning array upper gate circuit EM_GOA, and the plurality of rows of dual signal switch subcircuits and the reverse switch subcircuits are located in the peripheral area of ​​the array substrate. Optionally, the light emitting scanning array upper gate circuit EM_GOA is located on the side of the gate scanning array upper gate circuit Gate_GOA away from the display area AA. Optionally, a column of dual signal switch subcircuits in the plurality of rows of dual signal switch subcircuits and the reverse switch subcircuits is located on the side of the light emitting scanning array upper gate circuit EM_GOA away from the gate scanning array upper gate circuit Gate_GOA. Optionally, a column of reverse switch subcircuits in the plurality of rows of dual signal switch subcircuits and the reverse switch subcircuits is located on the side of the column of dual signal switch subcircuits away from the light emitting scanning array upper gate circuit EM_GOA. Optionally, the first control array upper gate circuit RST_GOA is located on a side of the column reverse switch subcircuit away from the column dual signal switch subcircuit. Optionally, the second control array upper gate circuit EMS_GOA is located on a side of the first control array upper gate circuit RST_GOA away from the column reverse switch subcircuit.

[0155] As used herein, the term "display area" refers to the area of ​​the array substrate in the display panel where the image is actually displayed. Optionally, the display area may include a sub-pixel area and an inter-sub-pixel area. The sub-pixel area refers to the light-emitting area of ​​the sub-pixel, for example, the area corresponding to the pixel electrode in the liquid crystal display, or the area corresponding to the light-emitting layer in the organic light-emitting diode display panel. The inter-sub-pixel area refers to the area between adjacent sub-pixel areas, for example, the area corresponding to the black matrix in the liquid crystal display, or the area corresponding to the pixel defining layer in the organic light-emitting diode display panel. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-sub-pixel area is the area between two adjacent sub-pixel areas in two adjacent pixels. As used herein, the term "peripheral area" refers to the area of ​​the array substrate in the display panel, in which various circuits and wires are provided to transmit signals to the display substrate. In order to increase the transparency of the display device, the opaque or non-transparent components (e.g., batteries, printed circuit boards, metal frames) of the display device can be arranged in the peripheral area instead of in the display area.

[0156] On the other hand, the present disclosure provides a pixel driving method. In some embodiments, the pixel driving method includes, in a reset phase, turning on a first reset transistor to allow a first initialization voltage signal to be written to a second capacitor electrode of a storage capacitor; in a data writing phase, turning on a data writing subcircuit to allow a voltage of a data voltage signal and a threshold voltage of a driving transistor to be written to the second capacitor electrode; in a voltage holding phase, turning off the first reset transistor, and providing a voltage holding signal from a first reset signal line to a source of the first reset transistor; and in a light emitting phase, when the voltage of the second capacitor electrode is greater than the threshold voltage of the driving transistor, turning on the light emitting control subcircuit to control a voltage power supply signal of a voltage power supply line to be written to the driving transistor, and the driving transistor generates a driving current to drive the light emitting element to emit light. The voltage holding signal is different from the first initialization voltage signal. Optionally, the pixel driving method further includes providing a turn-off reset control signal to the gate of the first reset transistor through a reset control signal line to turn off the first reset transistor in at least one of the initial phase, the data writing phase, the voltage holding phase, and the light emitting phase. Optionally, the pixel driving method further includes, in the reset phase, providing a conduction reset control signal to the gate of the first reset transistor via a reset control signal line to allow the first initialization voltage signal from the first reset signal line to be written into the second capacitor electrode of the storage capacitor.

[0157] In some embodiments, the pixel driving method further comprises, during the reset phase, turning on the second reset transistor to allow the second initialization voltage signal to enter the anode of the light emitting element during the reset phase. The voltage holding signal is different from the second initialization voltage signal.

[0158] In some embodiments, the pixel driving method further comprises using a dual signal switch subcircuit connected to the first reset signal line to generate the first initialization voltage signal in the reset phase and to generate the voltage holding signal in the voltage holding phase.

[0159] In some embodiments, generating the first initialization voltage signal during the reset phase includes: providing a first turn-off control signal to the gate of the first control transistor of the dual-signal switch sub-circuit through a first control signal line to turn off the first control transistor; providing the first initialization voltage signal to the source of the second control transistor through a second switch signal line; and providing a second turn-on control signal to the gate of the second control transistor of the dual-signal switch sub-circuit through a second control signal line to turn on the second control transistor, thereby allowing the first initialization voltage signal to be transmitted from the source of the second control transistor to the drain of the second control transistor, and then to the first reset signal line connected to the drain of the second control transistor.

[0160] In some embodiments, the pixel driving method also includes, in a reset phase, providing the first turn-off control signal to the gate of the third control transistor of the reverse switch subcircuit through the first control signal line to turn off the third control transistor of the reverse switch subcircuit connected to the dual-signal switch subcircuit, and simultaneously providing the first turn-off control signal to the gate of the first control transistor to turn off the first control transistor; providing the second voltage signal to the source of the fourth control transistor of the reverse switch subcircuit through the second voltage signal line; and providing the third turn-on control signal to the gate of the fourth control transistor of the reverse switch subcircuit through the third control signal line to turn on the fourth control transistor of the reverse switch subcircuit, thereby allowing the second voltage signal to be transmitted from the source of the fourth control transistor to the drain of the fourth control transistor, and then to the second control signal line connected to the gate of the second control transistor, and the second voltage signal is used as the second turn-on control signal to turn on the second control transistor in the reset phase.

[0161] In some embodiments, generating the voltage holding signal in the voltage holding stage includes: providing the voltage holding signal to the source of the first control transistor through the first switch signal line; providing a first turn-on control signal to the gate of the first control transistor of the dual-signal switch sub-circuit through the first control signal line to turn on the first control transistor, thereby allowing the voltage holding signal to be transmitted from the source of the first control transistor to the drain of the first control transistor, and then to the first reset signal line connected to the drain of the first control transistor; and providing a second turn-off control signal to the gate of the second control transistor of the dual-signal switch sub-circuit through the second control signal line to turn off the second control transistor.

[0162] In some embodiments, the pixel driving method also includes, during the voltage holding stage, providing a first voltage signal to the source of a third control transistor of a reverse switch subcircuit connected to the dual-signal switch subcircuit through a first voltage signal line; providing the first turn-on control signal to the gate of the third control transistor through the first control signal line to turn on the third control transistor, thereby allowing the first voltage signal to be transmitted from the source of the third control transistor to the drain of the third control transistor, and then to the second control signal line connected to the gate of the second control transistor, the first voltage signal being used as the second turn-off control signal to turn off the second control transistor during the voltage holding stage; and providing the third turn-off control signal to the gate of a fourth control transistor of the reverse switch subcircuit through the third control signal line to turn off the fourth control transistor.

[0163] In some embodiments, the pixel driving method further includes generating the first initialization voltage signal during the data writing phase using the dual signal switch sub-circuit connected to the first reset signal line.

[0164] In some embodiments, the pixel driving method further includes generating the first initialization voltage signal in an initial stage using the dual-signal switch subcircuit connected to the first reset signal line.

[0165] In some embodiments, the pixel driving method further includes, before displaying each frame of the multiple frames of images, obtaining data voltage signals of multiple sub-pixels of the display panel in each frame of the image; and specifying the calculated value as the value of the voltage holding signal. Optionally, the calculated value is calculated by a function based on the data voltage signals of the multiple sub-pixels in each frame of the image. Optionally, the function includes an averaging algorithm. Optionally, the calculated value is equal to the sum of the threshold voltage of the driving transistor and the average value of the data voltage signals of the multiple sub-pixels. As used herein, the term "average value" includes all known calculation methods that result in the average value formed thereby. Examples of averaging algorithms include, but are not limited to, root mean square value algorithms, arithmetic mean algorithms, geometric mean algorithms, and weighted average algorithms. Optionally, the averaging algorithm is selected from the group consisting of root mean square value algorithms, arithmetic mean algorithms, geometric mean algorithms, and weighted average algorithms. Optionally, the function is based on a data signal compensation model f(Vdata(1), Vdata(2), ..., Vdata(N)); wherein Vdata(1), Vdata(2), ..., Vdata(N) represent the data voltage signals of the multiple sub-pixels.

[0166] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. A pixel driving circuit, comprising: a storage capacitor comprising a first capacitor electrode and a second capacitor electrode, the first capacitor electrode being connected to a voltage supply line; a driving transistor configured to generate a driving current for driving the light emitting element to emit light when the voltage of the second capacitor electrode is greater than a threshold voltage of the driving transistor, wherein a gate of the driving transistor is connected to the second capacitor electrode; a data writing subcircuit connected to the data line and to the second capacitor electrode, the data writing subcircuit being configured to write the voltage of the data voltage signal and the threshold voltage of the driving transistor to the second capacitor electrode during a data writing phase; a light emitting control subcircuit connected to the driving transistor, wherein the light emitting control subcircuit is configured to control the voltage power supply signal of the voltage power supply line to be written into the driving transistor in a light emitting phase to generate a driving signal; as well as a first reset transistor having a gate connected to a reset control signal line, a source connected to a first reset signal line, and a drain connected to a gate of the drive transistor and the second capacitor electrode; a dual signal switch subcircuit connected to the first reset signal line; a reverse switch subcircuit connected to the dual signal switch subcircuit; wherein the first reset transistor is configured to be turned on during a reset phase to allow a first initialization voltage signal provided by the first reset signal line to be written into the second capacitor electrode; In the voltage holding phase, the first reset transistor is configured to be turned off, and the first reset signal line is configured to provide a voltage holding signal to the source of the first reset transistor; The voltage holding signal is different from the first initialization voltage signal; a first voltage difference between the voltage holding signal and a voltage level of the gate of the driving transistor in the light emitting stage is smaller than a second voltage difference between the first initialization voltage signal and a voltage level of the gate of the driving transistor in the light emitting stage; The dual-signal switch subcircuit is configured to generate the first initialization voltage signal in the reset phase and to generate the voltage holding signal in the voltage holding phase; In the reset phase, the reverse switch subcircuit is configured to generate a first turn-off control signal, which reaches the gate of the first control transistor of the dual-signal switch subcircuit through the first control signal line to turn off the first control transistor, and generate a second turn-on control signal, which reaches the gate of the second control transistor of the dual-signal switch subcircuit through the second control signal line to turn on the second control transistor; In the voltage holding stage, the reverse switch subcircuit is configured to generate a first on-control signal, which reaches the gate of the first control transistor of the dual-signal switch subcircuit through the first control signal line to turn on the first control transistor, and generate a second off-control signal, which reaches the gate of the second control transistor of the dual-signal switch subcircuit through the second control signal line to turn off the second control transistor; The dual signal switch subcircuit comprises: a first control transistor having a gate connected to a first control signal line, a source connected to a first switch signal line configured to provide the voltage hold signal, and a drain connected to the first reset signal line; a second control transistor having a gate connected to a second control signal line, a source connected to a second switch signal line configured to provide the first initialization voltage signal, and a drain connected to the first reset signal line; Wherein, in the reset phase and the data writing phase, the first control transistor is configured to be turned off, and the second control transistor is configured to be turned on; In the voltage holding phase, the first control transistor is configured to be turned on, and the second control transistor is configured to be turned off; The reverse switch subcircuit comprises: a third control transistor having a gate connected to the first control signal line, a source connected to a first voltage signal line configured to provide a first voltage signal, and a drain connected to the second control signal line; and a fourth control transistor having a gate connected to the third control signal line, a source connected to a second voltage signal line configured to provide a second voltage signal, and a drain connected to the second control signal line; Wherein, in the reset phase and the data writing phase, the third control transistor is configured to be turned off, and the fourth control transistor is configured to be turned on; In the voltage holding phase, the third control transistor is configured to be turned on, and the fourth control transistor is configured to be turned off.

2. The pixel driving circuit according to claim 1, further comprising a second reset transistor, the second reset transistor having a gate connected to the reset control signal line, a source connected to the second reset signal line, and a drain connected to the light emitting control subcircuit and the anode of the light emitting element, the second reset transistor being configured to write a second initialization voltage signal to the anode of the light emitting element during the reset phase; in, The first reset signal line and the second reset signal line are independent of each other; and The voltage maintaining signal is different from the second initializing voltage signal.

3. The pixel driving circuit according to claim 1 or 2, wherein: The data writing subcircuit includes a first transistor and a second transistor; The first transistor includes a gate connected to the gate line, a source connected to the data line, and a drain connected to the source of the driving transistor; as well as The second transistor includes a gate connected to the gate line, a source connected to the second capacitor electrode of the storage capacitor and the gate of the driving transistor, and a drain connected to the drain of the driving transistor.

4. The pixel driving circuit according to claim 1 or 2, wherein: The light emitting control subcircuit comprises a third transistor and a fourth transistor; The third transistor includes a gate connected to the light emission control signal line, a source connected to the voltage supply line, and a drain connected to the source of the driving transistor and the drain of the first transistor; as well as The fourth transistor includes a gate connected to the light emission control signal line, a source connected to a drain of the driving transistor and a drain of the second transistor, and a drain connected to an anode of the light emitting element.

5. The pixel driving circuit according to claim 1 or 2, wherein: The first voltage difference is at least 20% smaller than the second voltage difference.

6. An array substrate, comprising: A first control array upper gate circuit includes a plurality of cascaded first shift registers; A second control array upper gate circuit, which includes a plurality of cascaded second shift registers; as well as A plurality of rows of dual-signal switch subcircuits and reverse switch subcircuits, each row including a dual-signal switch subcircuit and a reverse switch subcircuit; wherein the dual-signal switch sub-circuit in each row is connected to a first reset signal line; and The reverse switch subcircuits in each row are connected to the dual signal switch subcircuits; The dual-signal switch subcircuit is configured to generate a first initialization voltage signal in a reset phase and to generate a voltage holding signal in a voltage holding phase; In the reset phase, the reverse switch subcircuit is configured to generate a first turn-off control signal, which reaches the gate of the first control transistor of the dual-signal switch subcircuit through the first control signal line to turn off the first control transistor, and generate a second turn-on control signal, which reaches the gate of the second control transistor of the dual-signal switch subcircuit through the second control signal line to turn on the second control transistor; and In the voltage holding stage, the reverse switch subcircuit is configured to generate a first on-control signal, which reaches the gate of the first control transistor of the dual-signal switch subcircuit through the first control signal line to turn on the first control transistor, and generate a second off-control signal, which reaches the gate of the second control transistor of the dual-signal switch subcircuit through the second control signal line to turn off the second control transistor; wherein the plurality of rows of dual-signal switch subcircuits and reverse switch subcircuits are respectively connected to a plurality of first shift registers of the gate circuit on the first control array, the number of the plurality of rows is the same as the number of the plurality of first shift registers, and each of the plurality of first shift registers is configured to provide a third turn-off control signal and a third turn-on control signal to the reverse switch subcircuit in each of the plurality of rows; and The multiple rows of dual-signal switch sub-circuits and reverse switch sub-circuits are commonly connected to a single second shift register of the gate circuit on the second control array, and the single second shift register is configured to provide the first on-control signal and the first off-control signal to the reverse switch sub-circuit and the dual-signal switch sub-circuit in the multiple rows of dual-signal switch sub-circuits and reverse switch sub-circuits.

7. The array substrate according to claim 6, further comprising: a gate circuit on a gate scanning array, comprising a plurality of cascaded third shift registers, the plurality of cascaded third shift registers being configured to generate a plurality of gate driving signals; as well as a gate circuit on the light emitting scanning array, comprising a plurality of cascaded fourth shift registers configured to generate a plurality of light emitting control signals; Wherein, each first shift register in the plurality of cascaded first shift registers and each third shift register in the plurality of cascaded third shift registers have the same circuit structure; Each second shift register in the plurality of cascaded second shift registers and each fourth shift register in the plurality of cascaded fourth shift registers have the same circuit structure; a ratio of sizes of output transistors in each of the plurality of cascaded first shift registers and each of the plurality of cascaded third shift registers, respectively, in a range of 1:3 to 1:2; and A ratio of sizes of output transistors in each of the plurality of cascaded second shift registers and each of the plurality of cascaded fourth shift registers, respectively, is in a range of 1:3 to 1:

2.

8. The array substrate according to claim 7, further comprising a plurality of rows of pixel driving circuits, which are electrically connected to the plurality of rows of dual-signal switch subcircuits and reverse switch subcircuits respectively; in, The multiple rows of pixel driving circuits are located in the display area of ​​the array substrate; The first control array upper gate circuit, the second control array upper gate circuit, the gate scanning array upper gate circuit, the light emitting scanning array upper gate circuit, and the multiple rows of dual signal switch subcircuits and reverse switch subcircuits are located in the peripheral area of ​​the array substrate; The gate circuit on the light emitting scanning array is located on a side of the gate circuit on the gate scanning array away from the display area; A column of dual-signal switch subcircuits respectively from the plurality of rows of dual-signal switch subcircuits and the reverse switch subcircuits is located on a side of the gate circuit on the light-emitting scanning array away from the gate circuit on the gate scanning array; A column of reverse switch subcircuits from the plurality of rows of dual-signal switch subcircuits and reverse switch subcircuits is located on a side of the column of dual-signal switch subcircuits away from the gate circuit on the light-emitting scanning array; The gate circuit on the first control array is located on a side of the column of reverse switch sub-circuits away from the column of dual-signal switch sub-circuits; and The second control array upper gate circuit is located on a side of the first control array upper gate circuit away from the column reverse switch sub-circuit.

9. A display device, comprising a pixel driving circuit according to any one of claims 1 to 5, a first control array upper gate circuit connected to the third control signal line, and a second control array upper gate circuit connected to the first control signal line; The display device comprises: a plurality of rows of pixel driving circuits; The pixel driving circuit is in each row of the plurality of rows of pixel driving circuits; Each row of the plurality of rows of pixel driving circuits is connected to the dual signal switch subcircuit and the reverse switch subcircuit; and The dual-signal switch subcircuit is configured to generate the first initialization voltage signal in the reset phase and generate the voltage holding signal in the voltage holding phase for each row of the plurality of rows of pixel driving circuits.

10. The display device according to claim 9, further comprising a data drive integrated circuit; in, The data driving integrated circuit is configured as follows: Before displaying each frame of the plurality of frames of images, providing a data voltage signal to the plurality of sub-pixels in each frame of the images; and assigning a calculated value as a value of the voltage hold signal; The calculated value is calculated by a function based on the data voltage signals of the plurality of sub-pixels in each frame image.

11. The display device according to claim 10, wherein: The function includes an averaging algorithm; and The calculated value is equal to a sum of a threshold voltage of the driving transistor and an average value of the data voltage signals of the plurality of sub-pixels.

12. The display device according to claim 11, wherein: The averaging algorithm is selected from the group consisting of a root mean square algorithm, an arithmetic mean algorithm, a geometric mean algorithm and a weighted mean algorithm.

13. The display device according to claim 12, wherein: The function is based on a data signal compensation model f(Vdata(1), Vdata(2), ..., Vdata(N)); and Vdata(1), Vdata(2), . . . , Vdata(N) represent the data voltage signals of the plurality of sub-pixels.

14. A pixel driving method, comprising: In the reset phase, turning on the first reset transistor to allow the first initialization voltage signal to be written into the second capacitor electrode of the storage capacitor; In the data writing phase, turning on the data writing sub-circuit to allow the voltage of the data voltage signal and the threshold voltage of the driving transistor to be written into the second capacitor electrode; In the voltage holding phase, the first reset transistor is turned off, and a voltage holding signal from the first reset signal line is provided to the source of the first reset transistor; as well as In the light emitting stage, the light emitting control subcircuit is turned on to write the voltage power supply signal of the control voltage power supply line into the driving transistor, so that when the voltage of the second capacitor electrode is greater than the threshold voltage of the driving transistor, the driving transistor generates a driving current to drive the light emitting element to emit light; Using a dual signal switch subcircuit connected to the first reset signal line, generating the first initialization voltage signal in the reset phase and generating the voltage holding signal in the voltage holding phase; Generating the first initialization voltage signal in the reset phase includes: Providing a first turn-off control signal to the gate of the first control transistor of the dual-signal switch subcircuit through a first control signal line to turn off the first control transistor; Providing the first initialization voltage signal to the source of the second control transistor through a second switch signal line; providing a second turn-on control signal to the gate of the second control transistor of the dual-signal switch sub-circuit through a second control signal line to turn on the second control transistor, thereby allowing the first initialization voltage signal to be transmitted from the source of the second control transistor to the drain of the second control transistor, and then to the first reset signal line connected to the drain of the second control transistor; In the reset stage, it also includes: providing the first turn-off control signal to the gate of a third control transistor of a reverse switch subcircuit connected to the dual-signal switch subcircuit through the first control signal line to turn off the third control transistor of the reverse switch subcircuit, and simultaneously providing the first turn-off control signal to the gate of the first control transistor to turn off the first control transistor; providing a second voltage signal to a source of a fourth control transistor of the reverse switch subcircuit through a second voltage signal line; providing a third conduction control signal to the gate of the fourth control transistor of the reverse switch subcircuit through a third control signal line to turn on the fourth control transistor of the reverse switch subcircuit, thereby allowing the second voltage signal to be transmitted from the source of the fourth control transistor to the drain of the fourth control transistor and then to the second control signal line connected to the gate of the second control transistor, the second voltage signal being used as the second conduction control signal to turn on the second control transistor in the reset stage; In which, the voltage holding signal is different from the first initialization voltage signal; the first voltage difference between the voltage holding signal and the voltage level of the gate of the driving transistor in the light-emitting stage is less than the second voltage difference between the first initialization voltage signal and the voltage level of the gate of the driving transistor in the light-emitting stage.

15. The pixel driving method according to claim 14, further comprising turning on a second reset transistor in the reset phase to write a second initialization voltage signal into the anode of the light emitting element in the reset phase; in, The voltage maintaining signal is different from the second initializing voltage signal.

16. The pixel driving method according to claim 14, wherein generating the voltage holding signal in the voltage holding stage comprises: providing the voltage holding signal to the source of the first control transistor through the first switch signal line; providing a first turn-on control signal to a gate of a first control transistor of the dual-signal switch sub-circuit through a first control signal line to turn on the first control transistor, thereby allowing the voltage holding signal to be transferred from a source of the first control transistor to a drain of the first control transistor, and further to the first reset signal line connected to the drain of the first control transistor; as well as A second turn-off control signal is provided to the gate of the second control transistor of the dual-signal switch sub-circuit through a second control signal line to turn off the second control transistor.

17. The pixel driving method according to claim 16, further comprising: In the voltage holding stage, providing a first voltage signal to a source of a third control transistor connected to a reverse switch subcircuit of the dual signal switch subcircuit through a first voltage signal line; providing the first on-control signal to the gate of the third control transistor through the first control signal line to turn on the third control transistor, thereby allowing the first voltage signal to be transmitted from the source of the third control transistor to the drain of the third control transistor, and then to the second control signal line connected to the gate of the second control transistor, the first voltage signal being used as the second off-control signal for turning off the second control transistor in the voltage holding stage; as well as A third turn-off control signal is provided to the gate of the fourth control transistor of the reverse switch sub-circuit through a third control signal line to turn off the fourth control transistor. 18 . The pixel driving method according to claim 14 , further comprising generating the first initialization voltage signal in the data writing phase using the dual signal switch subcircuit connected to the first reset signal line.

19. The pixel driving method according to any one of claims 14 to 17, further comprising generating the first initialization voltage signal in an initial stage using the dual-signal switch sub-circuit connected to the first reset signal line.

20. The pixel driving method according to any one of claims 14 to 17, further comprising: Before displaying each frame of the plurality of frames of images, obtaining data voltage signals of a plurality of sub-pixels of the display panel in each frame of the image; as well as assigning a calculated value as a value of the voltage hold signal; The calculated value is calculated by a function based on the data voltage signals of the plurality of sub-pixels in each frame image.

21. The pixel driving method according to claim 20, wherein: The function includes an averaging algorithm; and The calculated value is equal to a sum of a threshold voltage of the driving transistor and an average value of the data voltage signals of the plurality of sub-pixels.

22. The pixel driving method according to claim 21, wherein: The averaging algorithm is selected from the group consisting of a root mean square algorithm, an arithmetic mean algorithm, a geometric mean algorithm and a weighted mean algorithm.

23. The pixel driving method according to claim 22, wherein: The function is based on a data signal compensation model f(Vdata(1), Vdata(2), ..., Vdata(N)); and Vdata(1), Vdata(2), . . . , Vdata(N) represent the data voltage signals of the plurality of sub-pixels.

Images