Semiconductor memory devices and memory systems

Abstract

The semiconductor memory device of the present invention includes a first memory section storing: a first unique identifier, which is inherently assigned; and a first chip address, which has fewer bits than the first unique identifier and can be identified from other semiconductor memory devices.

Description

Technical Field

[0001] The embodiments relate to a semiconductor memory device and a memory system. Background Technology

[0002] NAND flash memory is known as a semiconductor storage device.

[0003] Background Technology Documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 4791924

[0006] Patent Document 2: US Patent No. 9773527

[0007] Patent Document 3: Japanese Patent No. 4080843 Summary of the Invention

[0008] [The problem the invention aims to solve]

[0009] To provide a high-quality semiconductor memory device.

[0010] [Technical means to solve the problem]

[0011] The semiconductor memory device of the embodiment includes a first storage section, which stores: a first unique number, which is inherently assigned; and a first chip address, which has fewer bits than the first unique number and can be identified from other semiconductor memory devices. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an example of the configuration of the storage system in the first embodiment.

[0013] Figure 2 This is a block diagram illustrating an example of the configuration of the package in the first embodiment.

[0014] Figure 3 This is a block diagram illustrating an example of the relationship between the memory chips included in the package of the first embodiment.

[0015] Figure 4 This is a block diagram illustrating an example of the configuration of the memory chip in the first embodiment.

[0016] Figure 5 This is an example of a circuit diagram illustrating the configuration of one block of the memory cell array of the memory chip in the first embodiment.

[0017] Figure 6 It is a flowchart illustrating the manufacturing method and usage method of the storage system.

[0018] Figure 7 It is a simplified diagram showing the appearance of the chip and batch.

[0019] Figure 8 It is a diagram showing the relationship between the chip and the XY coordinates.

[0020] Figure 9 It is a diagram representing a memory chip and the sequence of instructions input to the memory chip.

[0021] Figure 10 It is a diagram representing a memory chip and the sequence of instructions input to the memory chip.

[0022] Figure 11 It is a diagram representing the package and the sequence of instructions input to the package.

[0023] Figure 12 It is a diagram representing a memory chip and the sequence of instructions input to the memory chip.

[0024] Figure 13 It is a diagram representing a memory chip and the sequence of instructions input to the memory chip.

[0025] Figure 14 It is a diagram representing a memory chip and the sequence of instructions input to the memory chip.

[0026] Figure 15 This is a diagram illustrating an example of the structure of the package for a comparative example.

[0027] Figure 16 This is a diagram showing an example of the structure of the package in the first embodiment.

[0028] Figure 17 This is a block diagram illustrating an example of the relationship between the memory chips contained in the package of a comparative example.

[0029] Figure 18 This is a block diagram illustrating an example of the relationship between the memory chips contained in the package of a comparative example.

[0030] Figure 19 This is a block diagram illustrating an example of the configuration of the storage system in the second embodiment.

[0031] Figure 20 It is a flowchart illustrating the manufacturing method and usage method of the storage system.

[0032] Figure 21 It is a diagram representing the package, the sequence of instructions input to the package, and the signal WEn.

[0033] Figure 22 It is a diagram representing a memory chip and the sequence of instructions input to the memory chip.

[0034] Figure 23 This is a block diagram illustrating an example of the configuration of the storage system in the third embodiment.

[0035] Figure 24 It is a flowchart illustrating the manufacturing method and usage method of the storage system.

[0036] Figure 25 This is a block diagram illustrating an example of the configuration of the memory chip in the fourth embodiment.

[0037] Figure 26 This is a diagram representing the action (POR) of the comparative example.

[0038] Figure 27 This is a diagram illustrating the operation (POR) of the fourth embodiment.

[0039] Figure 28 This is a block diagram illustrating an example of the configuration of the memory chip in the fifth embodiment.

[0040] Figure 29 It is a flowchart illustrating the manufacturing method and usage method of the storage system.

[0041] Figure 30 It is a flowchart illustrating the manufacturing method and usage method of the storage system.

[0042] Figure 31 This is a block diagram illustrating an example of the structure of the package in the sixth embodiment.

[0043] Figure 32 This is a block diagram illustrating an example of the relationship between the memory chips contained in a package of a variation.

[0044] Figure 33 It is a flowchart illustrating the manufacturing method and usage method of the storage system. Detailed Implementation

[0045] Hereinafter, embodiments will be described with reference to the drawings. Each embodiment illustrates an apparatus and method for embodying the technical concept of the invention. The drawings are schematic or conceptual, and the dimensions and proportions of each drawing may not be the same as actual figures. The technical concept of the present invention is not specific to the shape, structure, arrangement, etc. of the constituent elements.

[0046] Furthermore, in the following description, constituent elements having substantially the same function and structure are marked with the same symbols. The numbers following the text of a constituent reference symbol are used for reference by reference symbols containing the same text, and to distinguish elements with the same structure from each other. When elements represented by reference symbols containing the same text do not need to be distinguished from each other, the elements are each referenced by reference symbols containing only text.

[0047] <1> First Embodiment

[0048] <1-1> Composition

[0049] First, the configuration of the storage system in the first embodiment will be described.

[0050] <1-1-1> Overall Structure of the Storage System

[0051] Regarding the configuration example of the storage system in the first embodiment, using Figure 1 Please provide an explanation. Figure 1 This is a block diagram illustrating an example of the configuration of a storage system according to an implementation method. Storage system 1 is connected to host device 2 (which may be referred to as a host or external device) via a host bus, functioning as an external storage device for host device 2. Host device 2 may be, for example, an information processing device such as a personal computer, a mobile phone, a camera device, a portable terminal such as a tablet computer or smartphone, a gaming device, or an in-vehicle terminal such as a car navigation system. Storage system 1 stores data from host device 2 and reads data from host device 2.

[0052] like Figure 1 As shown, the storage system 1 includes a controller 20 and a storage device (which may be described as a storage unit or storage device) 10. The controller 20 receives commands from the host device 2 and controls the storage device 10 based on the received commands. Specifically, the controller 20 writes data instructed to be written from the host device 2 to the storage device 10, reads data read from the host device 2 from the storage device 10, and sends it to the host device 2. The controller 20 is connected to the storage device 10 via a NAND bus. The storage device 10 has multiple storage cells and non-volatilely stores data. Furthermore, the storage device 10 is a non-volatile data storage device. The storage device 10, for example, includes multiple packages (which may be described as semiconductor storage devices) 11 (in... Figure 1 The image shows four 11 (11(0), 11(1), 11(2) and 11(3))) non-volatile semiconductor memories.

[0053] Alternatively, the storage system 1 can be a memory card that integrates the controller 20 and the storage device 10 into a single package, or it can be an SSD (Solid State Drive).

[0054] Furthermore, the number of packages 11 provided by the storage device 10 is not limited to four, and any number of packages 11 may be provided.

[0055] <1-1-2> Regarding the composition of the controller

[0056] Next, using Figure 1 The controller 20 of the storage system 1 described in the embodiment will be explained. The controller 20 includes: a main interface circuit 21, a processor (CPU: Central Processing Unit) 22, a built-in memory (RAM: Random Access Memory) 23, a buffer memory 24, an ECC (Error Check and Correction) circuit 25, and a NAND interface circuit 26.

[0057] The main interface circuit 21 is connected to the host device 2 and manages communication with the host device 2. The main interface circuit 21 can be a UFS interface according to the UFS (Universal Flash Storage) specification, a SAS interface according to the SAS (Serial Attached SCSI) specification, or an interface according to other specifications, or even the communication cable itself. The main interface circuit 21, for example, transmits commands and data received from the host device 2 to the processor 22 and the buffer memory 24, respectively.

[0058] Processor 22 controls the overall operation of controller 20. For example, in response to a read command received from host device 2, processor 22 issues a read command to storage device 10 based on NAND interface circuit 26. The same applies to write and erase operations. Furthermore, processor 22 has the function of performing various operations on the read data from storage device 10. When storage system 1 receives power, processor 22 controls the overall operation of controller 20 by reading firmware (control program) stored in ROM (not shown) to buffer memory 24 or internal memory 23 and performing specific processing. Here, processor 22 is also referred to as the core or processor core. Additionally, the control of the overall operation of controller 20 can be implemented through specific hardware, rather than through processor 22 executing firmware.

[0059] Built-in memory 23, such as DRAM (Dynamic RAM) or other semiconductor memory, is used as the operating area of ​​processor 22. Built-in memory 23 stores firmware and various management tables used to manage storage device 10.

[0060] The buffer memory 24 temporarily stores data received by the controller 20 from the storage device 10 and the host device 2. More specifically, the buffer memory 24 is composed of general-purpose memory such as SRAM (Static RAM) or DRAM. In addition, the buffer memory 24 may be installed inside the controller 20 or installed independently outside the controller 20.

[0061] ECC circuit 25 performs error detection and error correction. More specifically, during data writing, an ECC symbol is generated for each of a certain number of data groups based on the data received from host device 2. Furthermore, during data reading, the ECC symbol is decoded, and errors are detected. Moreover, when an error is detected, its bit position is identified, and the error is corrected.

[0062] NAND interface circuit 26 is connected to storage device 10 via NAND bus and manages communication with storage device 10. NAND interface circuit 26 sends instructions (CMD), addresses (ADD), and write data (DATA) to storage device 10 according to the instructions of processor 22. Additionally, NAND interface circuit 26 receives read data (DATA) from storage device 10.

[0063] <1-1-3> Composition of the package

[0064] Next, regarding a configuration example of the package 11 in the embodiment, using... Figure 2 Please provide an explanation. Figure 2 This is a block diagram illustrating an example of the configuration of the package 11 in an embodiment. Figure 2 For simplicity, we will extract one package 11 for explanation.

[0065] like Figure 2 As shown, the package 11 includes multiple memory chips (or simply referred to as chips) 100 (in Figure 2 The display shows eight 100s (100(0) to 100(7)). Each of the memory chips 100 can operate independently of each other; for example, there is a NAND flash memory chip. In a NAND flash memory chip, generally, data is written and read in units called pages, and data is erased in units called blocks. In addition, the number of memory chips 100 included in the package 11 is not limited to eight, and any number of memory chips 100 can be included.

[0066] Each of the 100 memory chips is connected to the NAND bus.

[0067] The NAND bus transmits and receives signals CEn, CLE, ALE, WEn, REn, WPn, RBn, and DQ<7:0> via individual signal lines according to the NAND interface. Signal CEn is used to enable memory chip 100. Signal CLE informs memory chip 100 that signals DQ<7:0> flowing through memory chip 100 during the period when signal CLE is at a "H" level are instructions. Signal ALE informs memory chip 100 that signals DQ<7:0> flowing through memory chip 100 during the period when signal ALE is at a "H" level are addresses. Signal WEn indicates that signals DQ<7:0> flowing through memory chip 100 during the period when signal WEn is at a "L" level (L < H) will be captured into memory chip 100. Signal REn indicates that signals DQ<7:0> will be output to memory chip 100. Signal WPn instructs memory chip 100 to disable data writing and erasure. Signal RBn indicates whether memory chip 100 is in a ready state (accepting commands from external sources) or a busy state (not accepting commands from external sources). Signal DQ<7:0> is, for example, an 8-bit signal. Signal DQ<7:0> represents the data transmitted and received between memory chip 100 and controller 20, including instructions (CMD), addresses (ADD), and data (DATA). Data (DATA) includes written data and read data.

[0068] Additionally, for the memory chip 100, voltages VCC and VSS are supplied externally as reference voltages. Voltage VCC is, for example, the power supply voltage used to drive the memory chip 100, and voltage VSS is, for example, the ground voltage, which is lower than voltage VCC.

[0069] <1-1-4> Relationship between various memory chips

[0070] Next, regarding the relationship between the memory chips 100 included in the package 11 of the first embodiment, using... Figure 3 Please provide an explanation. Figure 3 This is a block diagram illustrating an example of the relationship between the memory chips 100 included in the package 11 of an embodiment. Figure 3 For simplicity, the illustrations of the encapsulating resin contained in the package 11 and the substrate for stacking each memory chip 100 are omitted.

[0071] like Figure 3 As shown, the plurality of memory chips 100 contained in the package 11 are stacked in a stepped, inclined manner above a substrate (not shown). Furthermore, the plurality of memory chips 100 are positioned with multiple pads (on the end of each memory chip 100) at their respective ends. Figure 3 For simplicity, the example shows a configuration with 10 pads exposed.

[0072] Each pad disposed on the memory chip 100 receives signals or reference voltages related to the NAND bus used to operate the memory chip 100, or transmits signals to the controller 20. That is, the number of pads corresponding to the number of signals transmitted and received between the controller 20 and the memory chip 100, and the number of voltages received by the memory chip 100, are configured accordingly. The pads are, for example, electrode terminals. Among the multiple memory chips 100, pads receiving the same signal or voltage are electrically connected via bonding leads BWI. Each bonding lead BWI is, for example, an external wiring containing gold (Au), which functions as a transmission path for power supply voltages and signals between the memory chip 100 and the corresponding pads. Each bonding lead BWI is fixed by an encapsulating resin (not shown) and is insulated from the connection points with the memory chip 100 and the corresponding pads.

[0073] like Figure 3 As shown, the pads of a certain memory chip 100 are connected to the pads of other chips with common functions via bonding leads (BWI). That is, the pads with the same function in the plurality of memory chips 100 contained in the package 11 are connected in a common manner. In other words, the same signal is input to the plurality of memory chips 100 contained in the package 11.

[0074] Specifically, the pads for receiving signals CEn of memory chip 100(0) and CEn of memory chip 100(1) are connected via bonding leads BWI. Similarly, the pads for receiving signals CEn of memory chip 100(1) and CEn of memory chip 100(2) are connected via bonding leads BWI. Additionally, the pads for receiving signals CEn of memory chip 100(2) and CEn of memory chip 100(3) are connected via bonding leads BWI. The pads for receiving signals CEn of memory chip 100(3) and CEn of memory chip 100(4) are connected via bonding leads BWI. The pads for receiving signals CEn of memory chip 100(4) and CEn of memory chip 100(5) are connected via bonding leads BWI. The pads for receiving signals CEn of memory chip 100(5) and memory chip 100(6) are connected via bonding leads BWI. The pads for receiving signals CEn of memory chip 100(6) and memory chip 100(7) are connected via bonding leads BWI. That is, the pads for receiving signals CEn of memory chips 100(0) to (7) are connected in series via bonding leads BWI.

[0075] The same applies to pads related to other signals or voltages.

[0076] <1-1-5> Composition of Memory Chips

[0077] Next, an example of the configuration of the memory chip 100 in the first embodiment will be described. Figure 4 This is a block diagram showing an example of the configuration of the memory chip 100 in the first embodiment.

[0078] like Figure 4 As shown, the memory chip 100 includes: a core circuit 110, a peripheral circuit 120, an input / output pad group 130 (0), a logic control pad group 130 (1), and a power supply pad group 130 (2).

[0079] The peripheral circuit 120 includes: input / output circuit 102, logic control circuit 103, buffer 104, sequencer 105, voltage generation circuit 106, and driver group 107.

[0080] The core circuit 110 includes a memory cell array 101, a row decoder 108, and a sensing amplifier module 109.

[0081] The memory cell array 101 has multiple blocks BLK (BLK(0), BLK(1), ...). Each block BLK contains multiple non-volatile memory cell transistors (not shown) associated with word lines and bit lines. A block BLK serves as an erasure unit for data, for example. Data within the same block BLK is erased in batches. Each block BLK has multiple string units SU (SU(0), SU(1), ...). Furthermore, the number of blocks in the memory cell array 101 and the number of string units within a single block BLK can be set to any number.

[0082] The input / output circuit 102 and the controller 20 transmit and receive signals DQ<7:0>. The input / output circuit 102 transmits the instruction (CMD) within the signal DQ<7:0> to the instruction buffer 1041 within the buffer 104. Additionally, the input / output circuit 102 transmits the address (ADD) within the signal DQ<7:0> to the address buffer 1042 within the buffer 104. The input / output circuit 102 and the sense amplifier module 109 transmit and receive write and read data.

[0083] The logic control circuit 103 receives signals CEn, CLE, ALE, WEn, REn, and WPn from the controller 20. Additionally, the logic control circuit 103 transmits signal RBn to the controller 20 and notifies the external system of the state of the memory chip 100.

[0084] The register 104 includes: instruction register 1041, address register 1042, status register 1043, unique number register 1044, unique number matching determination unit 1021 and chip address matching determination unit 1022.

[0085] Instruction buffer 1041 receives and stores instructions (CMD) from input / output circuit 102. Instruction buffer 1041 then transmits the instructions (CMD) to sequencer 105.

[0086] Address buffer 1042 receives and stores addresses (ADD) from input / output circuit 102. Address buffer 1042 transmits addresses (ADD) to row decoder 108 and sense amplifier module 109.

[0087] Additionally, address register 1042 stores the chip address CAD read from memory cell array 101. Address register 1042 sends the chip address CAD to chip address consistency determination unit 1022 based on a request from an external source (e.g., controller 20).

[0088] The state buffer 1043 receives and stores various state information from the sequencer 105. The state buffer 1043 sends various state information to the outside via the input / output circuit 102 based on requests from the outside (e.g., controller 20).

[0089] The unique number matching determination unit 1021 determines whether the unique number (which may be described as a solid-state identification number, inherent number, identification number, manufacturing number, etc.) stored in the unique number cache 1044 in the cache 104 matches or does not match the unique number received from an external source (e.g., controller 20). Furthermore, the unique number matching determination unit 1021 is configured to notify the external source of the determination result. The unique number matching determination unit 1021 is, for example, a circuit. The unique number can be any number as long as it is a number that can uniquely (inherently) identify the memory chip 100. Specific examples regarding unique numbers will be described later.

[0090] The chip address consistency determination unit 1022 determines whether the chip address CADD stored in the address register 1042 within the register 104 is consistent with or inconsistent with the chip address CADD received from an external source (e.g., the controller 20). Furthermore, the chip address consistency determination unit 1022 is configured to notify the external source of the determination result. Specifically, when the input / output circuit 102 receives a status instruction after receiving an instruction to select the memory chip 100, the chip address consistency determination unit 1022 notifies the controller 20 of the determination result. The chip address consistency determination unit 1022 is, for example, a logic circuit. More specifically, the chip address consistency determination unit 1022 is, for example, a logic circuit including: an XNOR circuit that performs an XNOR operation on each bit of the chip address CADD stored in the address register 1042 and the chip address CADD received from an external source, and an AND circuit that performs an AND operation on the result output from the XNOR circuit. The chip address CADD is the address used to identify the memory chip 100. Specifically, it receives an instruction set containing the chip address CADD, and executes the instruction set if the chip address CADD matches. Furthermore, the number of bits in the chip address CADD is less than the number of bits in the unique identifier. Also, the chip address CADD is different from the signal CEn.

[0091] Unique number cache 1044 stores unique numbers read from storage cell array 101. Unique number cache 1044 sends unique numbers to unique number consistency determination unit 1021 based on requests from external sources (e.g., controller 20).

[0092] The sequencer 105 receives instructions (CMD) and controls the entire memory chip 100 according to the sequence of the received instructions (CMD).

[0093] The voltage generation circuit 106 generates the voltage required for data writing, reading, and erasing operations based on instructions from the sequencer 105. The voltage generation circuit 106 supplies the generated voltage to the driver assembly 107.

[0094] The driver group 107 includes multiple drivers that supply various voltages from the voltage generation circuit 106 to the memory cell array 101, the row decoder 108, and the sense amplifier module 109 based on the address from the register 104.

[0095] The row decoder 108 receives the row address from the address (ADD) in the register 104 and selects a block BLK based on, for example, the block address within the row address. Furthermore, voltages from the driver group 107 are transmitted to the selected block BLK via the row decoder 108.

[0096] When reading data, the sensing amplifier module 109 senses the read data read from the memory cell transistor towards the bit line and transmits the sensed read data to the input / output circuit 102. When writing data, the sensing amplifier module 109 transmits the write data written via the bit line to the memory cell transistor. Additionally, the sensing amplifier module 109 receives the row address from the address (ADD) in the register 104 and outputs column data based on the row address.

[0097] Input / output pad group 130(0) transmits the signal DQ<7:0> received from controller 20 to input / output circuit 102. In addition, input / output pad group 130(0) transmits the signal DQ<7:0> sent from input / output circuit 102 to the outside of memory chip 100.

[0098] The logic control pad group 130(1) transmits the signals CEn, CLE, ALE, WEn, REn, and WPn received from the controller 20 to the logic control circuit 103. In addition, the logic control pad group 130(1) transmits the signal RBn sent from the logic control circuit 103 to the outside of the memory chip 100.

[0099] The power supply pad group 130(2) transmits the externally supplied voltages VCC and VSS to the memory surface PB. More specifically, the power supply pad group 130(2) includes pads PAD_VCC and PAD_VSS. Pads PAD_VCC and PAD_VSS supply voltages VCC and VSS to the memory chip 100, respectively.

[0100] <1-1-6> Composition of a memory cell array

[0101] Next, using Figure 5 The configuration of the memory cell array of the memory chip in the embodiment will be described. Figure 5 This is an example of a circuit diagram illustrating the configuration of one block of a memory cell array of a memory chip used to illustrate an implementation method.

[0102] like Figure 5 As shown, block BLK contains, for example, four string units SU(0) to SU(3). Each string unit SU contains multiple NAND strings NS.

[0103] Multiple NAND strings NS are associated with bit lines BL(0) to BL(m) (where m is an integer greater than or equal to 1). Each NAND string NS contains, for example, memory cell transistors MT(0) to MT(7) and selection transistors ST(1) and ST(2).

[0104] The storage cell transistor MT contains a control gate and a charge storage layer, and stores data non-volatilely. The selection transistors ST(1) and ST(2) are used to select the string cell SU for various operations.

[0105] In each NAND string NS, the drain of the select transistor ST(1) is connected to the associated bit line BL. Memory cell transistors MT(0) to MT(7) are connected in parallel between the source of the select transistor ST(1) and the drain of the select transistor ST(2).

[0106] In the same block BLK, the gates of the selection transistors ST(1) contained in each of the string units SU(0) to SU(3) are all connected to the selection gate lines SGD(0) to SGD(3). The control gates of each of the memory unit transistors MT(0) to MT(7) are all connected to the word lines WL(0) to WL(7). The gate of the selection transistor ST(2) is all connected to the selection gate line SGS.

[0107] Each bit line BL(0) to BL(m) is assigned a different column address. Each bit line BL is connected to the selection transistor ST(1) of the corresponding NAND string NS across multiple blocks BLK. Word lines WL(0) to WL(7) are each set in each block BLK. The source line SL is shared, for example, across multiple blocks BLK.

[0108] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is called, for example, a cell CU. For example, the storage capacity of a cell CU containing memory cell transistors MT that each store 1 bit of data is defined as "1 page of data". A cell CU can have a storage capacity of 2 pages or more, depending on the number of bits of data stored by the memory cell transistors MT.

[0109] Furthermore, the configuration of the memory chip 100 described above is ultimately just one example and is not limited thereto. For example, the number of memory cell transistors MT and selection transistors ST(1) and ST(2) contained in each NAND string NS can be set to any number. The number of string units SU contained in each block BLK can be designed to be any number. The configuration and number of transistors set as dummy transistors can be designed to be any configuration and number.

[0110] <1-2> Manufacturing method and usage method

[0111] Then, following Figure 6 The flowchart shown illustrates the manufacturing method and usage method of storage system 1.

[0112] Figure 6 This is a flowchart illustrating the manufacturing method of storage system 1 and the usage method of storage system 1.

[0113] [S1001]

[0114] use Figure 7 The following explanation will focus on step S1001. Figure 7 It is a simplified diagram showing the appearance of the chip and batch.

[0115] In step S1001, a chip (silicon chip) 200 is prepared. Specifically, a generally disk-shaped chip 200 is produced by thinly cutting a single-crystal silicon ingot. The diameter of the chip 200 is, for example, approximately 200 mm, 300 mm, or 450 mm. Multiple memory chips 100 are formed on the chip 200 as described below. Multiple chips 200 are processed in batches during the formation of the memory chips 100. The unit processed in the batch is referred to, for example, as a "batch". Figure 7 As shown, a batch contains multiple chips 200. Additionally, each chip 200 is assigned a wafer number for identification during the formation of the memory chip 100. Furthermore, each batch is assigned a batch ID for identification during the formation of the memory chip 100.

[0116] [S1002]

[0117] use Figure 8 The following explanation will focus on step S1002. Figure 8 This is a diagram showing the relationship between chip 200 and the XY coordinates.

[0118] A unique number is generated in step S1002. For example... Figure 8 As shown, a memory chip forming region 300 is prepared in chip 200 for the formation of memory chip 100 in subsequent steps. Multiple memory chip forming regions 300 are prepared on chip 200. The memory chip forming regions 300 are assigned X and Y coordinates using the XY coordinate system (also collectively referred to as XY coordinates).

[0119] As described above, a batch ID is assigned to each batch, and a wafer number is assigned to each chip 200. Therefore, each memory chip forming area 300 can be identified using the batch ID, wafer number, and XY coordinates. Thus, for example, a unique number can be generated based on the batch ID, wafer number, and XY coordinates. Furthermore, the unique number is stored, for example, in a database DB. Additionally, the unique number can be any number as long as it is a number that can identify each memory chip forming area 300. Furthermore, at the time of step S1002, memory chip 100 has not yet been formed, but memory chip 100 is formed in the memory chip forming area 300 according to the method described below. That is, the unique number is a number that can identify each memory chip 100.

[0120] [S1003]

[0121] In step S1003, a circuit is formed on the chip 200. Specifically, the chip 200 is processed in various ways to form a circuit that becomes the memory chip 100 in the memory chip forming region 300.

[0122] [S1004]

[0123] Chip testing is performed in step S1004. Specifically, as chip testing, before cutting the memory chip 100 from the chip 200, a needle (probe) made of conductive material is placed against the bonding pad and connected to a tester to perform various tests.

[0124] [S1005]

[0125] In step S1005, the unique number is read out. Specifically, the test device (not shown) that performs the test on the memory chip 100 reads the unique number corresponding to the memory chip 100 being tested from the database DB.

[0126] [S1006]

[0127] use Figure 9 The following explanation will focus on step S1006. Figure 9 This is a diagram representing the memory chip 100 and the sequence of instructions input to the memory chip 100.

[0128] In step S1006, a unique number is written to the memory chip 100. Specifically, the testing device (not shown) issues a sequence of instructions to write the unique number assigned to the memory chip 100 in step S1002 to the memory chip 100. The instruction sequence includes, for example, instructions (CMD), addresses (ADD), and data (DATA). Moreover, the instruction sequence is supplied to the memory chip 100 as a signal DQ<7:0>.

[0129] like Figure 9 As shown, in step S1006, the memory chip 100 receives a sequence of instructions for writing a unique number as a signal DQ<7:0> from the test device. As an example of the instruction sequence, the memory chip 100 first receives the instruction CMD_AA, followed by an address spanning multiple cycles (e.g., 5 cycles). Furthermore, the memory chip 100 receives data (DATA) and the instruction CMD_BB. The instruction CMD_AA in the instruction sequence for writing a unique number signifies writing a unique number. The address (ADD) in the instruction sequence for writing a unique number represents the address used to write the unique number. The data (DATA) in the instruction sequence for writing a unique number represents the unique number. The instruction CMD_BB in the instruction sequence for writing a unique number instructs the execution of writing the unique number. Furthermore, the above example of the instruction sequence for writing a unique number is just one example, and various modifications can be made.

[0130] If the input / output circuit 102 receives a sequence of instructions for writing a unique number, the signal RBn is set from "ready" to "busy" via the logic control circuit 103.

[0131] Then, while the signal RBn is "busy", the memory chip 100 writes the unique number into the memory cell array 101. Specifically, the memory cell array 101 contains a block BLK(x) (x is any integer) that functions as a ROM fuse area for storing setting information of the memory chip 100. The address (ADD) contained in the instruction sequence for writing the unique number is the address of the memory cell transistor MT in the specified block BLK(x) that stores the unique number. Then, the sequencer 105 stores the unique number in the block BLK(x) based on the address (ADD) contained in the instruction sequence for writing the unique number.

[0132] In addition, steps S1005 and S1006 can be incorporated into step S1004.

[0133] [S1007]

[0134] In step S1007, the chip 200 is cut. Specifically, the chip 200 is fixed, and each memory chip 100 is physically cut apart using a blade.

[0135] [S1008]

[0136] In step S1008, the memory chip 100 is bonded. Specifically, the memory chip 100 manufacturing apparatus (not shown) picks up the memory chip 100 that was cut in step S1007. Furthermore, as... Figure 3As shown, multiple memory chips 100 are stacked with exposed pads. Then, bonding leads are connected to the exposed pads of each memory chip 100. In this way, the multiple memory chips 100 are connected.

[0137] [S1009]

[0138] Encapsulation is performed in step S1009. Specifically, a manufacturing apparatus (not shown) for the memory chip 100 seals the plurality of memory chips 100 that were bonded in step S1008 with resin. This produces a package 11. The package 11 is then encapsulated in the memory system 1.

[0139] [S1010]

[0140] In step S1010, a final test is performed. Specifically, a testing device (not shown) verifies the operation of the storage system 1. At this time, a visual inspection of the storage system 1 and an inspection of the solder balls can be performed.

[0141] [S1011]

[0142] use Figure 10 The following explanation will focus on step S1011. Figure 10 This is a diagram representing the memory chip 100 and the sequence of instructions input to the memory chip 100.

[0143] In step S1011, the unique number is read from the unique number cache 1044 within the memory chip 100. Specifically, the test device (not shown) issues a sequence of instructions to the memory chip 100 to read the unique number of block BLK(x) stored in the memory cell array 101 in step S1006 from the unique number cache 1044.

[0144] like Figure 10 As shown, in step S1011, the memory chip 100 receives a sequence of instructions for reading a unique number as a signal DQ<7:0> from the test device. As an example of the instruction sequence, the memory chip 100 first receives the instruction CMD_CC, followed by an address sequence spanning multiple cycles (e.g., 5 cycles). The instruction CMD_CC in the instruction sequence for reading a unique number signifies reading the unique number. The address (ADD) of the instruction sequence for reading a unique number represents the address of the memory cell transistor MT that stores the unique number. Furthermore, the above example of an instruction sequence for reading a unique number is just one example and various modifications are possible.

[0145] If the input / output circuit 102 receives a sequence of instructions for reading a unique number, the signal RBn is set from "ready" to "busy" via the logic control circuit 103.

[0146] Then, while the signal RBn is "busy", the memory chip 100 reads the unique number from the memory cell array 101. Specifically, the sequencer 105 reads the unique number from block BLK(x) based on the address (ADD) contained in the instruction sequence used to read the unique number. The read unique number is then stored in the unique number cache 1044.

[0147] [S1012]

[0148] In step S1012, a unique number is read out. Specifically, the test apparatus (not shown) that performs the test on the memory chip 100 reads the unique number corresponding to the memory chip 100 being tested from the database DB.

[0149] [S1013]

[0150] use Figure 11 The following explanation will focus on step S1013. Figure 11 This is a diagram representing the package 11 and the sequence of instructions input to the package 11.

[0151] In step S1013, an instruction to specify an address is issued to package 11 based on a unique number. Specifically, the test device (not shown) issues a sequence of instructions to write the chip address CADD, determined based on the unique number assigned to memory chip 100 in step S1002, into memory chip 100.

[0152] like Figure 11 As shown, the test device (not shown) issues a command to package 11 at a specified address based on a unique number.

[0153] like Figure 11 As shown, the pads with the same function in the plurality of memory chips 100 contained in the package 11 are connected in a common manner. Therefore, the same instruction sequence is input to the plurality of memory chips 100 contained in the package 11 at approximately the same timing. Figure 11 In the case of an example, the instruction sequence for writing the chip address is input to each memory chip 100.

[0154] like Figure 11 As shown, as an example of an instruction sequence, each memory chip 100 first receives the instruction CMD_DD, followed by an address over multiple cycles (e.g., 10 cycles). Then, each memory chip 100 receives the instruction CMD_EE, and receives an address (e.g., one cycle). The instruction CMD_DD in the instruction sequence used to write the chip address signifies writing the chip address. The address (ADD) following the instruction CMD_DD indicates a unique identifier. The instruction CMD_EE in the instruction sequence used to write the chip address signifies that the subsequent address is the chip address. The address (ADD) following the instruction CMD_EE indicates the chip address.

[0155] As described above, one set of instruction sequences is an instruction sequence associated with one memory chip 100. That is, in step S1013, the testing device issues a set of instruction sequences corresponding to the number of memory chips 100 contained in the package 11. Figure 11 In the example, since the package 11 contains 8 memory chips 100, the test device issues 8 sets of instruction sequences.

[0156] For example, the case where the unique number of memory chip 100(0) is 500 and the unique number of memory chip 100(1) is 1000 will be explained.

[0157] Memory chips 100(0) and 100(1) do not store chip addresses until they receive a sequence of instructions for writing chip addresses. However, as Figure 11 As shown, the test device receives the instruction sequence with chip address CADD0 when the unique number is 500, and receives the instruction sequence with chip address CADD1 when the unique number is 1000.

[0158] [S1014]

[0159] use Figure 12 The following explanation will focus on step S1014. Figure 12 This is a diagram representing the memory chip 100 and the sequence of instructions input to the memory chip 100.

[0160] In step S1014, a chip address is written to the memory chip 100. Specifically, when the memory chip 100 receives the instruction sequence issued in step S1013, it determines whether the unique numbers are consistent or inconsistent.

[0161] Specifically, the unique number consistency determination unit 1021 obtains a unique number from the unique number register 1044 and determines whether it matches or does not match the unique number contained in the instruction sequence. If the unique number obtained from the unique number register 1044 matches the unique number obtained from the unique number register 1044, the signal RBn is set to a busy state. Then, the unique number consistency determination unit 1021 notifies the sequencer 105 of the intention and stores the chip address contained in the instruction sequence with the same address in the chip address CADD of the block BLK(x) which functions as, for example, a ROM fuse.

[0162] If a unique number is obtained from the unique number register 1044 and is inconsistent with the unique number obtained from the unique number register 1044, the chip address contained in the instruction sequence that is the same as the inconsistent address is ignored.

[0163] In addition, steps S1011 to S1014 can be incorporated into step S1010.

[0164] [S1015]

[0165] In step S1015, the storage system 1 is shipped to, for example, a customer.

[0166] [S1016]

[0167] use Figure 13 The following explanation will focus on step S1016. Figure 13 This is a diagram representing the memory chip 100 and the sequence of instructions input to the memory chip 100.

[0168] In step S1016, a POR (power on read or power on reset) is performed. For example, when the controller 20 starts the memory chip 100 (power on), it issues the command CMD_FF, and the memory chip 100 performs a POR. A POR is to read the parameter settings for various actions from the block BLK(x), which functions as a ROM fuse.

[0169] Specifically, if the sequencer 105 receives the instruction CMD_FF during the startup of the memory chip 100, it sets the signal RBn to a busy state. Then, the sequencer 105 reads the parameter settings for various actions from block BLK(x). Specifically, it powers on POR to read the chip address from block BLK(x) and stores it in the chip address buffer 104.

[0170] [S1017]

[0171] use Figure 14 The following explanation will focus on step S1017. Figure 14 This is a diagram representing the memory chip 100 and the sequence of instructions input to the memory chip 100.

[0172] In step S1017, the user performs a normal action (e.g., a read operation) on the package 11. Specifically, the controller 20 issues a sequence of instructions to the package 11 regarding the read operation.

[0173] like Figure 14 As shown, in step S1006, the memory chip 100 receives a sequence of instructions for data reading from the test device as a signal DQ<7:0>. As an example of the instruction sequence, the memory chip 100 first receives the instruction CMD_JJ, followed by an address spanning multiple cycles (e.g., 5 cycles). Then, the memory chip 100 receives the instruction CMD_KK.

[0174] The instruction CMD_JJ, used in the instruction sequence for reading data, signifies the read operation. The address following CMD_JJ contains the address of the location from which data is read and the chip address CADD. The instruction CMD_KK is the instruction used to perform the read operation.

[0175] When the chip address consistency determination unit 1022 receives the chip address CADD, it determines whether the chip address CADD stored in the address buffer 1042 is consistent or inconsistent.

[0176] If the chip address consistency determination unit 1022 determines that the chip address CADD is consistent, it executes an instruction sequence containing the chip address CADD.

[0177] If the chip address consistency determination unit 1022 determines that the chip address CADD is inconsistent, it will not execute the instruction sequence containing the chip address CADD.

[0178] <1-3> Effects

[0179] According to the above-described embodiment, before assembling the memory chip 100 into the package 11, a unique number is stored in the memory chip 100. This unique number is a number that can specifically identify the memory chip 100. Furthermore, in the package 11 that connects multiple memory chips 100 in a common manner, the chip address CADD is stored in the memory chip 100 based on the unique number.

[0180] Therefore, when multiple memory chips 100 that are commonly connected are present in the package 11, each memory chip 100 can be individually specified using the chip address CADD.

[0181] The effects of this implementation method are explained here.

[0182] To illustrate the effects of this embodiment, a configuration example of the package 11 in the comparative example is used. Figure 15 Please provide an explanation. Figure 15 This is a diagram illustrating an example of the configuration of the package 11 in the comparative example. Figure 15 For simplicity, two packages, 11(0) and 11(1), are extracted for explanation.

[0183] like Figure 15As shown, each of the two packages 11(0) and 11(1) has eight memory chips 100. Furthermore, chip addresses CADD (0-7) are assigned to the eight memory chips 100 contained in package 11(0). Similarly, chip addresses CADD (0-7) are assigned to the eight memory chips 100 contained in package 11(1). Thus, in the comparative example, the memory chips 100 contained in package 11(0) and the memory chips 100 contained in package 11(1) are assigned the same chip addresses CADD. However, different signals CEn are input to the two packages 11(0) and 11(1). Specifically, signal CEn(0) is input to package 11(0), and signal CEn(1) is input to package 11(1). Therefore, in the case of selecting chip address CADD(0), for example, the memory chip 100(0) corresponding to the chip address CADD(0) of either package 11(0) or 11(1) can be selected by selecting signal CEn(0) or CEn(1). However, in the case of the comparative example, a different signal CEn must be prepared for each package 11. In this case, the number of signal lines may increase accordingly with the number of packages 11.

[0184] On the other hand, in this embodiment, the chip address CADD can be freely assigned regardless of the package 11.

[0185] Here, regarding the configuration example of the package 11 in this embodiment, using... Figure 16 Please provide an explanation. Figure 16 This diagram illustrates an example of the configuration of the package 11 in this embodiment. Figure 16 For simplicity, two packages, 11(0) and 11(1), are extracted for explanation.

[0186] like Figure 16 As shown, each of the two packages 11(0) and 11(1) has eight memory chips 100. Furthermore, chip addresses CADD(0) to (7) are assigned to the eight memory chips 100 contained in package 11(0). Additionally, chip addresses CADD(8) to (15) are assigned to the eight memory chips 100 contained in package 11(1). Thus, in this embodiment, chip addresses CADD can be freely assigned regardless of the package 11.

[0187] Since the memory chips 100 contained in the two packages 11(0) and 11(1) are assigned different chip addresses CADD, unlike the comparative example, the signal CEn can be shared in the two packages 11(0) and 11(1). As a result, the increase in the number of signal lines related to the signal CEn can be suppressed.

[0188] Furthermore, another effect of this embodiment will be explained.

[0189] As described above, the package 11 contains multiple memory chips 100. Furthermore, among the multiple memory chips 100, pads for receiving (or transmitting / receiving) the same signal are commonly connected via bonding leads. Therefore, it is not necessary to distinguish between the multiple memory chips 100 contained in the package 11. If the individual memory chips are not distinguished, when the package 11 receives a certain instruction set, all the memory chips 100 contained in the package 11 will perform the same operation. In this case, although the package 11 contains multiple memory chips 100, it becomes the same state as containing a single memory chip 100. Therefore, at least a chip address (CADD) must be assigned to each memory chip 100.

[0190] use Figure 17 The relationship between the memory chips 100 contained in the package 11 of the comparative example will be explained. Figure 17 This is a block diagram illustrating an example of the relationship between the memory chips 100 contained in the package 11 of the comparative example. For example... Figure 17 As shown, consider providing multiple pads (CADDs) for chip address CADDs in, for example, each memory chip 100. More specifically, the multiple pads (CADDs) for chip address CADDs are provided at the ends of the memory chip 100 in the same manner as other pads. Figure 17 As shown, for example, there are three pads (CADDs) for the chip address CADD. Furthermore, by changing whether or not the voltage VCC is input to the three pads (CADDs), 3 bits of information can be generated. In the comparative example, the 3 bits of information are the chip address CADD. This can be achieved by changing the connection of the bonding leads associated with the voltage VCC for each memory chip 100.

[0191] However, in this case, an area is needed for the pad (CADD) used to set the chip address CADD. As a result, the area of ​​the memory chip 100 may increase.

[0192] In the above-described embodiments, since there is no need for a chip address CADD pad (CADD), the increase in the area of ​​the memory chip 100 can be suppressed.

[0193] In addition, such as Figure 17 As shown, this embodiment can also be applied to a memory chip 100 that has multiple pads (CADDs) for chip address CADD.

[0194] In addition, such as Figure 18 As shown, this can be a case where the pad (CADD) used for the chip address CADD is not connected to the bonding leads.

[0195] In the process of incorporating the technology of this embodiment into the memory chip 100, it is possible to manufacture, for example... Figure 17 and Figure 18 The product shown. In this case, the above-described implementation method can also be applied.

[0196] <2> Second Implementation Method

[0197] Next, the second embodiment will be described. In the second embodiment, an example of assigning a chip address based on a controller-specific unique number will be described. Furthermore, descriptions of parts identical to those in the embodiment described above will be omitted. Additionally, the second embodiment can be combined with the first embodiment.

[0198] <2-1> Regarding the composition of the controller

[0199] use Figure 19 The controller 20 of the storage system 1 in the second embodiment will be described. Figure 19 This is a block diagram illustrating an example of the configuration of the storage system according to the second embodiment. The controller 20 includes: a main interface circuit 21, a processor (CPU: Central Processing Unit) 22, built-in memory (RAM: Random Access Memory) 23, a buffer memory 24, an ECC (Error Check and Correction) circuit 25, a NAND interface circuit 26, and a chip address allocation circuit 27.

[0200] The chip address allocation circuit 27 includes a chip address determination circuit 271. The chip address determination circuit 271 determines the chip address CADD allocated to the memory chip 100. Furthermore, it supplies the chip address CADD to the memory chip 100.

[0201] <2-2> Manufacturing method and usage method

[0202] The first embodiment described above can be applied to situations where the testing device can determine which memory chip 100 stores which unique number. However, in the actual manufacture of the memory system 1, the manufacturer manages multiple memory chips 100. Therefore, it may be difficult to determine which memory chip 100 stores which unique number. In such cases, the unique number of the memory chip 100 can be appropriately determined by employing the method described later.

[0203] Follow Figure 20 The flowchart shown illustrates the manufacturing method and usage method of storage system 1.

[0204] Figure 20This is a flowchart illustrating the manufacturing method of storage system 1 and the usage method of storage system 1.

[0205] [S2001]

[0206] Step S2001 is the same as steps S1001 to S1011 described in the first embodiment.

[0207] [S2012]~

[2014]

[0208] Steps S2012 to S2014 are actions taken by the manufacturer of the envisioned storage system 1 at the point in step S2012 when they are unable to establish a unique association with the storage chip 100.

[0209] use Figure 21 and Figure 22 The following explanation will focus on steps S2012 to S2014. Figure 21 This is a diagram representing package 11, the sequence of instructions input to package 11, and signal WEn. Figure 22 This is a diagram representing the memory chip 100 and the sequence of instructions input to the memory chip 100.

[0210] In step S2012, an instruction is issued to determine the unique number of each memory chip 100. Specifically, the controller 20 issues a sequence of instructions to the package 11 to determine the unique number assigned to the memory chip 100 in step S1002.

[0211] like Figure 21 As shown, as an example of an instruction sequence, the chip address determination circuit 271 sends the instruction CMD_LL to each memory chip 100, and then causes a specific signal (e.g., signal WEN) to undergo a dual-state transition multiple times (e.g., 1002 times). Then, after causing the specific signal to undergo a specific number of dual-state transitions, the chip address determination circuit 271 sends the instruction CMD_MM to each memory chip 100.

[0212] The instruction CMD_LL, used to determine a unique identifier, signifies the start of the unique identifier retrieval. The number of bi-state thixotropic transitions of a specific signal (e.g., signal WEn) represents the unique identifier. The instruction CMD_MM, used to determine a unique identifier, signifies the end of the unique identifier retrieval.

[0213] In step S2013, the memory chip 100 determines whether the instruction sequence matches its own unique number. If the memory chip 100 determines that it has received its own unique number (step S2013, Yes), it sets the signal RBn from "ready" to "busy" (step S2014). Thus, the chip address determination circuit 271 can determine the unique number of the memory chip 100.

[0214] exist Figure 21 For example, memory chip 100(0) stores a unique number 500, and memory chip 100(1) stores a unique number 1000. In this case, memory chip 100(0) sets signal RBn from "ready" to "busy" when signal WEN is double-state-triggered 500 times. Similarly, memory chip 100(1) sets signal RBn from "ready" to "busy" when signal WEN is double-state-triggered 1000 times. Therefore, chip address determination circuit 271 can determine which memory chip 100 in package 11 has a unique number 500 and which has a unique number 1000. Furthermore, the wiring for signal RBn is shared by memory chips 100(0) and 100(1). Therefore, chip address determination circuit 271 cannot determine which memory chip 100 has a unique number 500 and which has a unique number 1000.

[0215] use Figure 22 The explanation will focus on a memory chip 100. Figure 22 Extract from the middle Figure 21 The memory chip 100(0).

[0216] like Figure 22 As shown, if the memory chip 100 receives the instruction sequence of step S2012, it uses, for example, a unique number consistency determination unit 1021 to count the number of times the dual-state transition of the signal WEN is performed. Then, it determines whether the number of dual-state transitions of the signal WEN is consistent with the unique number stored in the unique number buffer 1044. Moreover, if the unique number consistency determination unit 1021 determines that the number of dual-state transitions of the signal WEN is consistent with the unique number stored in the unique number buffer 1044, it uses the logic control circuit 103 to set the signal RBn from "ready" to "busy".

[0217] [S2015]

[0218] When the signal RBn becomes "busy", the chip address determination circuit 271 stores a unique number based on the timing of the "busy" transition of the signal RBn and the number of times the signal WEn undergoes a two-state transition. Then, after step S2014, a chip address CAD is assigned to each unique number. The chip address CAD can be assigned in any way. For example, the chip address CAD can be assigned in ascending order of the unique numbers.

[0219] [S2016]

[0220] Step S2016 is the same as steps S1013 to S1017 described in the first embodiment.

[0221] <2-3> Effects

[0222] According to the above implementation method, a unique number can be appropriately read from a package containing multiple memory chips that are interconnected with each other.

[0223] In the manufacturing method of storage system 1, when writing the unique number to storage chip 100 (S1006), storage chip 100 is not separated from chip 200. Therefore, the unique number of storage chip 100 can be determined. However, when storage chip 100 is separated from chip 200 and assembled into package 11, it is difficult to determine which storage chip 100 has which unique number. Therefore, by applying the above-described implementation method, the unique number of storage chip 100 can be appropriately determined.

[0224] Furthermore, when reading the unique number from the package 11 alone, or from all the memory chips 100 contained in the package 11, there is a signal conflict from all the memory chips 100 in the signal DQ, making it impossible to read the unique number properly.

[0225] However, by applying the above-described implementation method, a unique number can be appropriately determined.

[0226] <3> Third Implementation Method

[0227] Next, the third embodiment will be described. In the third embodiment, an example will be described where the controller uses a binary search method to assign a unique chip address. Furthermore, descriptions of parts identical to those in the embodiments described above will be omitted. Additionally, the third embodiment can be combined with the first and second embodiments.

[0228] <3-1> Regarding the composition of the controller

[0229] use Figure 23 The controller 20 of the storage system 1 in the third embodiment will be described. Figure 23 This is a block diagram illustrating an example of the configuration of the storage system in the third embodiment.

[0230] The chip address allocation circuit 27 includes a chip address determination circuit 271 and a binary search circuit 272. The binary search circuit 272 is a circuit that uses binary search to determine the unique number of the memory chip 100.

[0231] <3-2> Manufacturing method and usage method

[0232] The second implementation described above requires the specific signal to undergo a dual-state transition the number of times equal to the maximum value of the unique identifier. For example, if the maximum unique identifier is the 100,000th, the specific signal must undergo a dual-state transition 100,000 times. There are cases where the larger the unique identifier, the more time is required to determine it.

[0233] However, in this embodiment, the time required to determine the unique number can be shortened.

[0234] Follow Figure 24 The flowchart shown illustrates the manufacturing method and usage method of storage system 1.

[0235] Figure 24 This is a flowchart illustrating the manufacturing method of storage system 1 and the usage method of storage system 1.

[0236] [S2001]

[0237] Step S2001 is the same as steps S1001 to S1011 described in the first embodiment.

[0238] [S3012]

[0239] The binary search circuit 272 uses a binary search method to determine the unique identifier of each memory chip 100. Specifically, the binary search circuit 272 calculates the first intermediate value, which is the midpoint between the minimum and maximum values ​​that constitute a unique identifier, and distinguishes memory chips 100 with unique identifiers less than the first intermediate value and memory chips 100 with unique identifiers greater than the first intermediate value. Next, the binary search circuit 272 calculates the second intermediate value, which is the midpoint between the minimum and the first intermediate value that constitutes a unique identifier, and distinguishes memory chips 100 with unique identifiers less than the second intermediate value and memory chips 100 with unique identifiers greater than the second intermediate value. In this way, the unique identifier of each memory chip 100 can be determined using a numerical analytical binary search method.

[0240] Furthermore, the intermediate values ​​used in the binary search method can be represented using data contained in the instruction sequence. Moreover, if each memory chip 100 has the same unique number, it can be represented using the signal RBn in the same way as in the second embodiment.

[0241] In this way, the binary search circuit 272 determines the unique number of the memory chip 100.

[0242] [S2013]~

[2016]

[0243] The steps S2013 to S2016 are the same as those described in the second embodiment.

[0244] <3-3> Effects

[0245] According to the above implementation method, the unique number of the memory chip 100 can be determined more quickly than in the second implementation method.

[0246] <4> Fourth Implementation Method

[0247] Next, the fourth embodiment will be described. In the fourth embodiment, the case where the memory chip 100 includes a delay circuit will be described. Furthermore, descriptions of parts that are the same as in the embodiments described above will be omitted. Additionally, the fourth embodiment can be combined with the first to third embodiments.

[0248] <4-1> About the composition of memory chips

[0249] Next, using Figure 25 Hereinafter, an example of the configuration of the memory chip 100 in the fourth embodiment will be described. Figure 25 This is a block diagram illustrating an example of the configuration of the memory chip 100 in the fourth embodiment.

[0250] like Figure 25 As shown, the peripheral circuit 120 includes: an input / output circuit 102, a logic control circuit 103, a buffer 104, a sequencer 105, a voltage generation circuit 106, a driver group 107, and a delay circuit 140.

[0251] The delay circuit 140 is a circuit that delays the execution timing of instructions in accordance with the chip address CADD.

[0252] <4-2> Actions

[0253] use Figure 26 and Figure 27 The operation of the fourth embodiment will be explained. Figure 26 This is a diagram representing the action (POR) of the comparative example. In Figure 26 For simplicity, the actions of the four memory chips 100 are displayed. Figure 27 This is a diagram illustrating the operation (POR) of the fourth embodiment. Figure 27 For simplicity, the actions of the four memory chips 100 are displayed.

[0254] like Figure 26 As shown, if package 11 receives the instruction CMD_FF during POR, the memory chips 100(0) to (3) contained in package 11 will simultaneously perform POR. In this case, the power consumption of memory system 1 may increase. From the viewpoint of power consumption of memory system 1, it is more ideal to suppress the number of memory chips 100 operating simultaneously.

[0255] like Figure 27As shown, in this embodiment, if each memory chip 100 receives the instruction CMD_FF in the POR operation, it only reads the chip address CADD in the POR operation. Furthermore, the delay circuit 140 included in each memory chip 100 determines the chip address CADD that has been read into the address buffer 1042. Then, the delay circuit 140, with timing corresponding to the chip address CADD, causes the sequencer 105 to perform operations other than reading the chip address CADD in the POR operation.

[0256] <4-3> Effects

[0257] like Figure 27 As shown, for example, assume that memory chip 100(0) is chip address CADD(0), memory chip 100(1) is chip address CADD(1), memory chip 100(2) is chip address CADD(2), and memory chip 100(3) is chip address CADD(3). Furthermore, the delay circuit 140 is configured to operate, for example, in a sequence (times T2 to T5) of chip addresses CADD(0) to (3). In this case, as... Figure 27 As shown, the timing of actions other than reading the chip address CADD in the POR operation varies depending on the memory chip 100. Therefore, the increase in power consumption of the memory system 1 can be suppressed.

[0258] <5> Fifth Implementation Method

[0259] Next, the fifth embodiment will be described. In the fifth embodiment, the case where the memory chip 100 includes a circuit for generating a unique serial number will be described. Furthermore, descriptions of parts identical to those in the embodiments described above will be omitted. Additionally, the fifth embodiment can be combined with the first to fourth embodiments.

[0260] <5-1> About the composition of memory chips

[0261] Next, an example of the configuration of the memory chip 100 in the fifth embodiment will be described. Figure 28 This is a block diagram illustrating an example of the configuration of the memory chip 100 in the fifth embodiment.

[0262] like Figure 28 As shown, the input / output circuit 102 includes a unique number generation circuit 1023. The unique number generation circuit 1023 can obtain a unique number from the memory chip 100. The unique number generation circuit 1023 is, for example, a random number generation circuit. Furthermore, even if, for example, the power supply to the memory chip 100 is restarted, the random number generation circuit must generate the same random number.

[0263] <5-2> Manufacturing method and usage method

[0264] The first to fourth embodiments described above determine a unique serial number externally to the memory chip 100. However, according to this embodiment, the memory chip 100 itself can generate a unique serial number. Therefore, the operation of generating a unique serial number in the manufacturing method of the memory system 1 described above can be skipped.

[0265] Follow Figure 29 The flowchart shown illustrates the manufacturing method and usage method of storage system 1.

[0266] Figure 29 This is a flowchart illustrating the manufacturing method of storage system 1 and the usage method of storage system 1.

[0267] [S1001], [S1003], [S1004], [S1007]~[S1010]

[0268] The steps S1001, S1003, S1004, S1007 to S1010 described in the first embodiment are the same.

[0269] [S4011]

[0270] The unique number generation circuit 1023 generates a unique number before the unique number is determined externally (e.g., by the controller 20). For example, if the unique number generation circuit 1023 receives the instruction CMD_LL as described in the second embodiment, it generates a unique number. Then, the unique number consistency determination unit 1021 uses the unique number generated by the unique number generation circuit 1023 to determine whether it is consistent with or inconsistent with the unique number received from the outside.

[0271] [S4012]

[0272] The steps S2012 to S2016 are the same as those described in the second embodiment.

[0273] <5-3> Variation Example

[0274] The fifth embodiment can also be combined with the third embodiment.

[0275] Specifically, the unique number determination can be performed using the binary search circuit 272 described in the third embodiment.

[0276] In this case, the manufacturing method and usage method of storage system 1 are as follows: Figure 30 The process is shown below.

[0277] [S1001], [S1003], [S1004], [S1007]~[S1010]

[0278] The steps S1001, S1003, S1004, S1007 to S1010 described in the first embodiment are the same.

[0279] [S4011]

[0280] The same as step S4011 described in embodiment 5.

[0281] [S4013]

[0282] The steps S3012, S2013 to S2016 are the same as those described in the third embodiment.

[0283] <6> 6th Implementation Method

[0284] Next, the sixth embodiment will be described. In the sixth embodiment, the configuration is described in a way that allows visual identification of which memory chip 100 is operating. Furthermore, descriptions of parts identical to those in the embodiments described above will be omitted. Additionally, the sixth embodiment can be combined with embodiments 1 through 5.

[0285] <6-1> Composition of the package

[0286] Regarding the configuration example of the package 11 in the sixth embodiment, using Figure 31 Please provide an explanation. Figure 31 This is a block diagram illustrating an example of the configuration of the package 11 in the sixth embodiment. Figure 31 For simplicity, we will extract one package 11 for explanation.

[0287] like Figure 31 As shown, the plurality of memory chips 100 contained in the package 11 are stacked in a stepped, inclined manner above a substrate (not shown). Furthermore, the plurality of memory chips 100 are separated by multiple pads disposed at the ends of each memory chip 100. Figure 31 For simplicity, the illustration shows 10 pads and the light-emitting part 1000 is exposed.

[0288] A light-emitting part 1000 is disposed in each memory chip 100. The light-emitting part 1000 may be, for example, an LED (Light Emitting Diode) or a paint whose color changes according to temperature. When the light-emitting part 1000 is an LED, the interior of the memory chip 100 is controlled to emit light during read, write, or erase operations. Alternatively, when the light-emitting part 1000 is a paint whose color changes according to temperature, the color of the paint changes as the temperature inside the memory chip 100 rises during read, write, or erase operations, allowing the naked eye to determine whether the memory chip 100 is in operation.

[0289] <6-2> Effects

[0290] As described above, the memory chips 100 contained in the package 11 are all interconnected, making it difficult to determine the chip address (CADD) of each memory chip 100 based on its appearance. Therefore, during inspections of the package 11, it can be difficult to determine which memory chip 100 is active. Therefore, by providing a light-emitting unit 1000, it is possible to visually determine which memory chip 100 is active. As a result, the time and labor required for inspecting the package 11 can be greatly reduced.

[0291] <7> Others

[0292] In addition, Figure 3 The example shown illustrates an instance where the signals CEn of all memory chips 100 within package 11 are commonly connected via bonding leads, but is not limited to this. It is permissible to commonly connect the signals CEn of a portion of the memory chips 100 within package 11, and to independently commonly connect the signals CEn of another portion of the memory chips 100 within package 11. For example, as... Figure 32 As shown, in the case of stacking 8 memory chips 100, the signals CEn of the four lower memory chips 100 (0) to (3) can be connected together and supplied with signal CEn0, and the signals CEn of the four upper memory chips 100 (4) to (7) can be connected together and supplied with signal CEn1, which is independent of signal CEn0.

[0293] For example, if the number of memory chips 100 connected to a signal CEn increases, the effective current when signal CEn is enabled may increase, or it may restrict the operation of multiple chips (the operation that causes multiple memory chips 100 to operate in parallel).

[0294] On the other hand, if the number of memory chips 100 connected to one signal CEn is increased, it may be possible to reduce the switching of the customer's signal CEn, thereby suppressing the increase in manufacturing costs.

[0295] like Figure 32 As shown, if the signal CEn is segmented within the package 11, the customer can also short-circuit the signal CEn either outside or within the package 11. In this case, the increase in effective current when the signal CEn is enabled can be suppressed, the constraint of multi-chip operation can be eliminated, and the switching of the signal CEn can be reduced.

[0296] Even if the memory chips 100 are structurally contained within the same package 11, if the signals CEn are independent, the groups that share the common signal CEn can be considered as imaginarily (electrically or functionally) independent packages 11. The "package" in each of the above embodiments not only shows a group of memory chips that are structurally integrally stacked as described above, but also shows a group of memory chips that are functionally (electrically) integrally connected by sharing the signal CEn.

[0297] Moreover, such as Figure 33 Generally, it can also be based on the customer and executed with Figure 6 The process described herein is the same as that described above, and thus, the chip address CADD can also be reassigned by the customer.

[0298] [S5001]

[0299] conduct Figure 6 Steps S1001 to S1016 as described herein.

[0300] [S5002]

[0301] Customers must be aware of the unique serial number. As an example of implementation, this can be achieved by writing the unique serial number of all memory chips 100 in the package 11 into the first memory chip 100 (e.g., memory chip 100(0)) during the final test (S1010).

[0302] In step S5002, the controller 20 issues a sequence of instructions to the memory chip 100 to read the unique number of the block BLK(x) stored in the memory cell array 101 in step S1006 toward the unique number cache 1044.

[0303] Then, the controller 20 reads the unique number corresponding to the memory chip 100 being tested from the first memory chip 100.

[0304] [S5003]

[0305] In step S5003, the controller 20 issues a sequence of instructions to write the chip address CADD, which is determined based on the unique number assigned to the memory chip 100 in step S1002, into the address register 1042.

[0306] [S5004]

[0307] In step S5004, the chip address is written to the address buffer 1042. Specifically, when the storage chip 100 receives the instruction sequence issued in step S5003, it determines whether the unique numbers are consistent or inconsistent. If the unique numbers are consistent, the unique number consistency determination unit 1021 stores the chip address contained in the instruction sequence with the same consistent address in the address buffer 1042.

[0308] [S5005]

[0309] In step S5005, the controller 20 issues a sequence of instructions to write the chip address CADD, which is determined based on the unique number assigned to the memory chip 100 in step S1002, into the ROM fuse.

[0310] [S5006]

[0311] In step S5006, the chip address is written to the ROM fuse. Specifically, when the memory chip 100 receives the instruction sequence issued in step S5005, it determines whether the unique numbers are consistent or inconsistent. If the unique numbers are consistent, the unique number consistency determination unit 1021 stores the chip address contained in the instruction sequence with the same consistent address in the ROM fuse.

[0312] Alternatively, steps S5005 and S5006 can be omitted.

[0313] [S1017]

[0314] conduct Figure 6 Step S1017 as described herein.

[0315] Alternatively, as described above, the customer can arbitrarily assign the chip address CADD after shipment.

[0316] The embodiments of the present invention have been described above, but the present invention is not limited to the above embodiments, and various changes can be made within the scope of its intent. Furthermore, the inventions described above include various stages, and various inventions can be extracted by appropriately combining the disclosed constituent elements. For example, even if several constituent elements are removed from the disclosed constituent elements, as long as a specific effect is obtained, it can still be extracted as an invention.

Claims

1. A semiconductor memory device comprising a first memory section, wherein the first memory section stores: The first unique number is inherently assigned; The first chip address has fewer bits than the first unique number and can be identified by other semiconductor memory devices; The first determination unit receives a first instruction set containing a second unique number from an external source. If it determines that the second unique number matches the first unique number stored in the first memory, it writes the second chip address contained in the first instruction set as the first chip address into the first memory. The second determination unit, upon receiving a second instruction set containing the address of the third chip from an external source... If it is determined that the address of the third chip is consistent with the address of the first chip stored in the first storage unit, Execute the instructions contained in the second instruction set.

2. The semiconductor memory device of claim 1, wherein it is enabled by receiving a first signal from an external source.

3. A storage system comprising: The first package includes a first memory chip and a second memory chip; The controller controls the first package; and The bus electrically connects the controller and the first package; and The first memory chip and the second memory chip each have a pad group for receiving signals or voltages from the bus, and the pad groups of the first memory chip and the second memory chip are interconnected. The first memory chip and the second memory chip respectively store: a first unique number, which is inherently assigned; and a first chip address, which has fewer bits than the first unique number and can be identified from other memory chips; The controller: For the first memory chip and the second memory chip, Supply the first instruction set containing the second unique number; and The first memory chip and the second memory chip, If the second unique number is determined to be the same as the first unique number... The address of the second chip contained in the first instruction set is stored as the address of the first chip; The controller: For the first memory chip and the second memory chip, Supply the second instruction set containing the address of the third chip; and The first memory chip and the second memory chip, If it is determined that the address of the third chip is the same as the address of the first chip, Execute the instructions contained in the second instruction set.

4. The storage system according to claim 3, wherein the first storage chip and the second storage chip, The timing of the action is controlled based on the address of the first chip.

5. The storage system according to claim 3, further comprising a second package having a third storage chip and a fourth storage chip; and The third and fourth memory chips each have pads for receiving signals or voltages from the bus, and the pads of the first to fourth memory chips are interconnected. The third and fourth memory chips respectively store: a first unique number, which is inherently assigned; And the first chip address, which has fewer bits than the first unique number, can be identified by other memory chips.

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