Socket design for memory devices

Abstract

This application relates to a socket design for a memory device. A die may include one or more memory arrays, each containing any number of word lines and any number of bit lines. The word lines and bit lines may be oriented in different directions, and memory cells may be located at the intersection of the word lines and bit lines. The socket couples the word lines and bit lines to an associated driver, and the socket may be positioned such that memory cells farther from a corresponding word line socket are closer to a corresponding bit line socket, and vice versa. For example, the sockets may be arranged in parallel rows or regions, and may not be orthogonal to the corresponding word lines and bit lines.

Description

[0001] Cross-reference

[0002] This patent application is a national phase application of International Patent Application No. PCT / US20 / 58805, filed November 4, 2020, entitled “Socket Design for a Memory Device”, filed by Majumdar et al., which claims priority to U.S. Patent Application No. 16 / 685,349, filed November 15, 2019, entitled “Socket Design for a Memory Device”, each of which has been assigned to its assignee and the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to socket designs for memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, typically represented by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write or program states into the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and so on. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for extended periods, even in the absence of an external power supply. Volatile memory devices (e.g., DRAM) can lose their stored state when disconnected from an external power supply.

[0006] Improving memory devices typically includes increasing memory cell density, increasing read / write speed, increasing reliability, increasing data retention, reducing power consumption, reducing stress on memory cells or other components of the memory device, or reducing manufacturing costs, as well as other metrics. Summary of the Invention

[0007] Describe a device. In some instances, the device may include: a set of first access lines for a memory array extending in a first direction; a set of second access lines for the memory array extending in a second direction; a set of first sockets, each coupled to a corresponding first access line of the set and to a corresponding first driver of a set of first drivers, the set of first sockets being arranged in a first row; and a set of second sockets, each coupled to a corresponding second access line of the set and to a corresponding second driver of a set of second drivers, the set of second sockets being arranged in a second row parallel to the first row.

[0008] Describe a device. In some instances, the device may include: a set of first access lines for a memory array extending in a first direction; a set of second access lines for the memory array extending in a second direction; a set of first sockets, each coupled to a corresponding first access line of the set and to a corresponding first driver of a set of first drivers, the set of first sockets being arranged in a first row skewed relative to the first direction; and a set of second sockets, each coupled to a corresponding second access line of the set and to a corresponding second driver of a set of second drivers, the set of second sockets being arranged in a second row skewed relative to the second direction.

[0009] Describe a device. In some instances, the device may include: a set of word lines for a group of memory cells, wherein each word line of the group extends in a first direction; a set of bit lines for the group of memory cells, wherein each bit line of the group extends in a second direction; a row of word line sockets, wherein each word line socket of the row is coupled to a corresponding word line of the group and a corresponding word line driver of a set of word line drivers; and a row of bit line sockets, wherein each bit line socket of the row is coupled to a corresponding bit line of the group and a corresponding bit line driver of a set of bit line drivers, and wherein the row of bit line sockets is parallel to the row of word line sockets.

[0010] Describe a device. In some instances, the device may include: word lines for a memory cell array, wherein each word line is oriented in a first direction; bit lines for the memory cell array, wherein each bit line is oriented in a second direction orthogonal to the first direction; vias oriented in a third direction orthogonal to the first and second directions, wherein the vias are coupled to a circuit system located below the memory cell array; rows of word line sockets, wherein the word line sockets couple the word lines to a first subset of the vias, and wherein the rows of word line sockets are oriented in a fourth direction different from the first, second, and third directions; and rows of bit line sockets, wherein the bit line sockets couple the bit lines to a second subset of the vias, and wherein the rows of bit line sockets are oriented in a fifth direction different from the first, second, and third directions.

[0011] Describe a method. In some instances, the method may include: receiving an access command for a memory cell coupled to a first access line and a second access line; routing current through the memory cell, the first access line, a first socket coupled to the first access line, the second access line, and a second socket coupled to the second access line based on the access command, wherein the first socket is included in a first socket row and the second socket is included in a second socket row parallel to the first socket row; and reading or writing the memory cell based on the current. Attached Figure Description

[0012] Figure 1 This describes an example memory device that supports socket design for memory devices, based on examples disclosed herein.

[0013] Figure 2 This describes an example of a memory array that supports socket design for memory devices, based on examples disclosed herein.

[0014] Figures 3A to 3C This section describes an example of a socket design for a crosspoint memory, based on examples disclosed herein.

[0015] Figure 4A and 4B This document describes examples of die layouts for socket designs of memory devices, based on examples disclosed herein.

[0016] Figure 5 This describes an example of a socket area that supports socket design for memory devices, based on examples disclosed herein.

[0017] Figure 6The flowchart illustrates a method for designing sockets for memory devices, based on examples disclosed herein. Detailed Implementation

[0018] In some cases, according to aspects of this disclosure, a memory device (e.g., a cross-point memory device) may be configured to access memory cells and sense logical states stored in said memory cells. Access may occur as part of a read operation, a write operation, or a combination thereof. Memory cells in a memory array may be arranged in columns and rows, wherein each row of memory cells corresponds to the same word line (e.g., coupled thereto), and each column of memory cells corresponds to the same bit line (e.g., coupled thereto). The bit lines and word lines of the memory device may not be parallel to each other (e.g., orthogonal), and each memory cell in the memory array may be located at the intersection of the word line and the bit line.

[0019] In some memory architectures, accessing a memory cell during a read or write operation may involve applying a non-zero voltage across the memory cell to read (e.g., sense) the logic state stored through the memory cell. Therefore, accessing a memory cell may involve selecting bit lines and word lines by applying corresponding voltages to bit lines and word lines coupled to the memory cell. Bit lines and word lines (either or both may be referred to as access lines) may be coupled to corresponding sockets, which in turn may be coupled to corresponding drivers configured to apply current and voltage to the word lines and bit lines as part of an access operation. For example, each socket may be coupled to a via, and the via may be coupled to a driver for the socket and an associated bit line or word line. Vias may extend in directions different from the bit lines and word lines (e.g., vias may extend through a layer or deck of the memory device, which for clarity may be referred to as a vertical direction, while bit lines and word lines may extend horizontally within the corresponding layer or deck of the memory device). In some instances, sockets may be arranged in rows, and an area of ​​the memory device containing one or more rows of sockets may be referred to as a socket area. Generally, a socket area can be defined as (e.g., of a memory die) an area where access lines terminate at vias (e.g., coupled thereto) to and from which signals are carried.

[0020] The memory device can be configured to apply a voltage V across the memory cells. cell As part of the access operation. For example, voltage V cell This can represent a threshold voltage used to sense logic states stored in memory cells. The memory device can be configured with a driver to apply a current I and a voltage V. source The word lines and bit lines coupled to the memory cells are selected based on voltage V. cell and the resistor R associated with the word line WL and the resistance R associated with the bit line BL Determine or otherwise configure voltage Vsource For example, the voltage V can be determined. source Make Among them, compared to R WL and R BL The resistance of vias or other interconnect structures between the source and memory cells can be considered negligible. Furthermore, the resistance associated with word lines and bit lines can vary depending on the respective lengths of the word lines and bit lines. Specifically, the resistance R... WL and resistance R BL It can be defined as and L WL L represents the length of the word line from the word line socket to the memory cell. BL The word line represents the length of the bit line from the bit line socket to the memory cell, and ρ represents the resistivity of the word line and the bit line (i.e., resistance per unit length). In some instances, the word line and the bit line may have the same resistivity (e.g., when the word line and the bit line are made of the same material). In some other instances, the word line and the bit line may be made of different materials, or may have different cross-sectional areas (e.g., different widths and / or thicknesses) or other variations, and each word line and bit line may have a different resistivity ρ.

[0021] Memory cells can be based on the corresponding resistor R WL and resistance R BL The associated electrical distance (ED) is also considered. The ED associated with a memory cell can be expressed, for example, as the sum of a first number of lines and spaces between the memory cell and the word line socket, and a second number of lines and spaces between the memory cell and the bit line socket. For instance, a memory cell located 1,000 lines (and spaces between the lines) from the word line socket and 500 lines from the bit line socket can have an associated ED of 1500, which can be expressed as 1.5 K ED. Therefore, a first memory cell physically located near both the word line socket and the bit line socket (which can be referred to as a near-distance memory cell) can have a smaller ED compared to a second memory cell physically located further away from both the word line socket and the bit line socket (which can be referred to as a far-distance memory cell).

[0022] Variations in electrical discharge current (ED) associated with memory cells in a memory array can negatively impact memory device performance and design optimization. For example, accessing distant memory cells may require relatively large drive currents, which can affect driver design or other design considerations, as well as power consumption and other performance aspects. This is attributed to the charge accumulated in the associated parasitic capacitances and the corresponding R... WL and R BL The relatively low value allows access to nearby memory cells to be made when the memory cell is activated (e.g., in V). cellWhen the cell's threshold voltage is reached, a large discharge current (e.g., current spike) is generated, which can increase wear on near-field memory cells unless reduced drive current or other mitigation techniques are applied to the near-field memory cells.

[0023] Some memory devices may attempt to improve memory cell location by (e.g., by increasing the driver current for distant memory cells and decreasing the driver current for nearby memory cells, for example by adjusting V) source Adjusting driver operation to compensate for changes in the electrical current (ED) across memory cells can be achieved, but the use of this algorithm or scheme can introduce operational complexity or latency (e.g., to execute the algorithm and adjust the driver based on the algorithm). Furthermore, some such techniques may rely on mapping a memory cell address table to an associated ED or drive current, which may occupy memory that could otherwise be used to store other data.

[0024] As described herein, it is beneficial to reduce variations in the edge parameters (ED) of memory cells across memory devices and thereby improve the performance and efficiency of memory devices through structural features. For example, bit line socket rows and word line socket rows (and thus associated socket areas) may be skewed (tilted) relative to word lines or bit lines, such that the socket rows extend in a direction skewed (i.e., non-orthogonal) relative to word lines or bit lines. In some cases, bit line socket rows and word line socket rows may be parallel to each other.

[0025] In some instances, such as when the resistivity ρ is the same for both word lines and bit lines, the socket row can extend in a direction inclined at 45° relative to the directions of both word lines and bit lines. In some instances, such as when the resistivity ρ of the word lines is the same... W The resistivity ρ of the bit line B At this time, the socket row can extend in a direction tilted at an angle relative to the bit line (and at an additional angle relative to the word line), where the angle is based on the resistivity ρ of the word line. W and the resistivity ρ of the bit line B For example, a reference angle θ can be defined relative to the direction of the bit line and according to the equation... A reference angle θ is determined, but those skilled in the art will understand that a similar reference angle may alternatively be defined relative to the direction of the word line.

[0026] Originally in reference Figure 1 and 2 The features of this disclosure are described in the background content describing the memory system and memory die. Next, as referenced... Figure 3A , 3B Features of this disclosure are described in the context of socket designs, die layouts, and socket area descriptions in 3C, 4A, 4B, and 5. (See references to...) Figure 6The flowcharts describing the socket design for the memory device further illustrate and describe these and other features of this disclosure with reference to the flowcharts.

[0027] Figure 1 This document describes an example memory device 100, which supports socket design for memory devices based on examples disclosed herein. The memory device 100 may also be referred to as an electronic memory device. Figure 1 This is an illustrative representation of the various components and features of the memory device 100. Therefore, it should be understood that the components and features of the memory device 100 are shown to illustrate functional interrelationships, and not necessarily their actual physical locations within the memory device 100. Figure 1 In an illustrative example, memory device 100 includes a three-dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 programmable to store different states. In some instances, each memory cell 105 is programmable to store one of two states represented as logic 0 and logic 1. In some instances, memory cells 105 can be configured to store one of more than two logic states. Although the values ​​are indicated by numeric indicators... Figure 1 Some elements are shown, but other corresponding elements are not labeled, but they are the same or will be understood as similar, in an effort to increase the visibility and clarity of the features depicted.

[0028] 3D memory array 102 may comprise two or more two-dimensional (2D) memory arrays formed on top of each other. Compared to 2D arrays, this increases the number of memory cells that can be placed or generated on a single die or substrate, which in turn reduces manufacturing costs or increases the performance of the memory device, or both. Memory array 102 may comprise two levels of memory cells 105 and thus can be considered a 3D memory array; however, the number of levels is not limited to two and may be one or more in some cases. Each level may be aligned or positioned such that memory cells 105 can be aligned (completely, overlapping, or approximately) with each other across each level, thereby forming a memory cell stack 145. In some cases, the memory cell stack 145 may comprise a plurality of memory cells 105 laid on top of each other while sharing access lines. In some cases, the memory cells 105 may be configured to each store one data bit.

[0029] In some instances, memory cell 105 may be a self-selecting memory cell, a phase-change memory (PCM) cell, and / or another type of resistive or threshold-based memory cell. Self-selecting memory cell 105 may include one or more components of a material (e.g., a chalcogenide material) that each acts as a storage element and a cell selector (selection) element, thereby eliminating the need for a separate cell selector circuitry (a selector circuitry that does not contribute to storage). This element may be referred to as a storage and selector assembly (or element), or a self-selecting memory assembly (or element). In contrast, other types of memory cells (e.g., dynamic random access memory (DRAM) or PCM cells) may each include a separate (dedicated) cell selector element (e.g., a three-terminal selector element (e.g., a transistor)) that contributes to the selection or non-selection of the memory cell but does not contribute to the storage of any logic state.

[0030] Memory array 102 may include multiple word lines 110 (e.g., row lines) labeled WL_1 to WL_M for each stack and multiple bit lines 115 (e.g., column lines) labeled BL_1 to BL_N, where M and N depend on the array size. In some instances, each row of memory cells 105 is connected to a word line 110, and each column of memory cells 105 is connected to a bit line 115. In some cases, word lines 110 and bit lines 115 may be collectively referred to as access lines because they allow access to memory cells 105. In some instances, bit lines 115 may also be referred to as digital lines 115. References to access lines, word lines, and bit lines or the like are interchangeable without loss of understanding or operation. Activating or selecting a word line 110 or bit line 115 may involve applying a voltage to the corresponding line. Word lines 110 and bit lines 115 may be made of conductive materials, such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), metal alloys, carbon, conductive doped semiconductors or other conductive materials, alloys, compounds or the like.

[0031] Word lines 110 and bit lines 115 may be substantially perpendicular (i.e., orthogonal) to each other or otherwise intersect to create an array of memory cells. For example... Figure 1As shown, two memory cells 105 in the memory cell stack 145 can share a common conductive line (e.g., bit line 115). That is, bit line 115 can electronically communicate with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. Other configurations are possible; for example, a third layer can share access lines 110 and 115 with the lower layer. Generally, a memory cell 105 can be located at the intersection of two conductive lines (e.g., word line 110 and bit line 115). This intersection point can be referred to as the address of the memory cell 105. The target memory cell 105 can be the memory cell 105 located at the intersection of the energized word line 110 and bit line 115; that is, word line 110 and bit line 115 can be energized to read or write to the memory cell 105 at its intersection point. Other memory cells 105 that communicate electronically with the same word line 110 or bit line 115 (e.g., connected to the same word line 110 or bit line 115) may be referred to as unmarked memory cells 105.

[0032] Electrodes may be coupled to memory cell 105 and word line 110 or bit line 115. The term electrode may refer to an electrical conductor and, in some cases, may serve as an electrical contact to memory cell 105. Electrodes may include traces, wires, conductive lines, conductive layers, or the like that providing a conductive path between elements or components of memory device 100. In some instances, memory cell 105 may include a plurality of self-select or other memory components (e.g., select components and storage components) separated from each other by electrodes and from access lines 110, 115. As previously described, for self-select memory cell 105, a single component (e.g., a segment or layer of chalcogenide material within memory cell 105) may serve as a storage element (e.g., to store the state of memory cell 105 or contribute to the storage of the state of memory cell 105) and as a selector element (e.g., to select memory cell 105 or contribute to the selection of memory cell 105).

[0033] The electrodes within the memory cell stack 145 may each have the same material (e.g., carbon) or may have various (different) materials. In some cases, the electrodes may be made of a material different from that of the access lines. In some instances, the electrodes may shield the word lines 110 and 115 with materials contained in the self-select or other memory components (e.g., chalcogenide materials) to prevent chemical interactions between the materials and the word lines 110, 115, or another memory component.

[0034] Operations (e.g., reads and writes) can be performed on memory cell 105 by activating or selecting the corresponding word line 110 and bit line 115. Access to memory cell 105 can be controlled by row decoder 120 and column decoder 130. For example, row decoder 120 may receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. This process may be referred to as decoding a row or word line address. Similarly, column decoder 130 may receive a column address from memory controller 140 and activate the appropriate bit line 115. This process may be referred to as decoding a column or bit line address. For example, row decoder 120 and / or column decoder 130 may be instances of decoders implemented using decoder circuitry. In some cases, row decoder 120 and / or column decoder 130 may include charge pump circuitry configured to increase the voltage applied to word line 110 or bit line 115 (respectively).

[0035] When accessing memory cell 105 (e.g., in cooperation with memory controller 140, row decoder 120, and / or column decoder 130) to determine the logic state stored in memory cell 105, the memory cell 105 can be read (e.g., sensed) by sensing component 125. Sensing component 125 can provide an output signal indicating (e.g., at least in part based on) the logic state stored in memory cell 105 to one or more components (e.g., to column decoder 130, input / output component 135, memory controller 140). In some instances, the detected logic state can be provided to a host device (e.g., a device using memory device 100 for data storage, a processor coupled to memory device 100 in an embedded application), where this signaling can be provided directly from input / output component 135 or via memory controller 140.

[0036] Sensing component 125 may include various transistors or amplifiers to detect and amplify signal differences (this may be referred to as latching). The detected logic state of the memory unit 105 can then be output as output 135 via column decoder 130. In some cases, sensing component 125 may be part of column decoder 130 or row decoder 120. Alternatively, sensing component 125 may be connected to or in electronic communication with column decoder 130 or row decoder 120. Those skilled in the art will appreciate that sensing components can be associated with column decoders or row decoders without losing their functional purpose.

[0037] In some memory architectures, accessing memory cell 105 can degrade or corrupt the logic state stored through one or more memory cells 105, and a rewrite or refresh operation can be performed to transfer the original logic state back to memory cell 105. In architectures, for example, that include a material portion for logic storage, sensing operations can cause changes in the atomic configuration or distribution of memory cells 105, thereby altering the resistance or threshold characteristics of memory cells 105. Therefore, in some instances, the logic state stored in memory cell 105 can be rewritten after an access operation.

[0038] In some instances, reading memory cell 105 may be non-destructive. That is, after reading memory cell 105, it may not be necessary to rewrite the logic state of memory cell 105. For example, in an architecture that includes a material portion for logic storage, sensing memory cell 105 may not corrupt the logic state, and therefore, memory cell 105 may not need to be rewritten after access. However, in some instances, refreshing the logic state of memory cell 105 may or may not be necessary in the absence of or presence of other access operations. For example, the logic state stored by memory cell 105 may be refreshed periodically by applying appropriate write or refresh pulses or bias voltages to maintain the stored logic state. Refreshing memory cell 105 can reduce or eliminate read interference errors or logic state corruption.

[0039] Although illustrated on the side of memory array 102 for clarity, row decoder 120 and column decoder 130 may, in some cases, be located below memory array 102. Each decoder 120, 130 may include or be coupled to one or more drivers configured to drive access lines 110, 115 to a desired voltage (e.g., to access one or more associated memory cells 105). In some cases, the drivers may be distributed across a region below memory array 102. Vias may extend through one or more layers or stacks of memory device 100 to couple drivers to their corresponding access lines 110, 115. For example, if access lines 110, 115 are considered to extend in a horizontal direction (e.g., the x-direction or y-direction), then vias may extend in a vertical (z-direction). In some cases, one or more layers between the driver and the access line may contain metal wiring, which may be referred to as interconnect layers or collectively as interconnect layers, wherein the driver may be coupled to a corresponding line in the interconnect layer and vias may extend between the interconnect layer and the layer containing the access line 115.

[0040] Word lines 110 may be coupled to row decoder 120 via one or more rows of word line sockets (not shown), and bit lines 115 may be coupled to column decoder 130 via one or more rows of bit line sockets (not shown). For example, each socket may be coupled to a corresponding via or other interconnect structure, thereby coupling the corresponding access lines 110, 115 to the corresponding decoders 120, 130 (e.g., to a driver contained in or coupled to the corresponding decoders 120, 130). As described herein, word line sockets and bit line sockets may be positioned such that the same access point (ED) is associated with each memory cell 105 in memory array 102, or otherwise reduce ED variation. This can be achieved by tilting the rows of bit line sockets and word line sockets such that the socket rows extend in a direction skewed (i.e., non-orthogonal) relative to word lines 110 or bit lines 115. In some cases, bit line socket rows may be parallel to word line socket rows.

[0041] Since each memory cell 105 has the same or similar associated ED, the memory device 100 can be subjected to the same or similar voltage V. source And thus the same or similar drive current I (e.g., via memory controller 140) achieves the same or similar voltage drop V across any memory cell 105 in memory array 102. cell This allows the memory device to provide sufficient drive current while avoiding excessive current discharge across memory cells 105 attributable to parasitic capacitances of word lines 110 or bit lines 115. This improves performance and increases the lifetime of memory cells 105, regardless of their physical location in the memory array 102. Furthermore, the memory device 100 can operate without dynamically changing the voltage V of different memory cells 105 at different physical locations. source And current I, which can reduce signaling add-ons or other complexities and latency associated with access operations, and can support various design optimizations.

[0042] Figure 2 This document describes an example of a 3D memory array 200 supporting socket design for memory devices, as disclosed herein. The memory array 200 may be used as a reference. Figure 1 An example of a portion of the described memory array 102. Memory array 200 may include a first memory cell array or stack 205-a positioned above substrate 204 and a second memory cell array or stack 205-b located on top of the first array or stack 205-a. Although the example of memory array 200 includes two stacks 205-a, 205-b, it should be understood that one stack (e.g., a 2D memory array) or two or more stacks are also possible.

[0043] Memory array 200 may also include word lines 210-a and 210-b and bit lines 215-a, which may be as shown in the reference. Figure 1 Examples of word line 210 and bit line 215 are described. Word line 210 may be coupled to one or more word line socket rows (not shown), and bit line 215 may be coupled to one or more bit line socket rows (not shown). Although one memory element 220 per memory cell is shown for clarity, memory cells of the first stack 205-a and the second stack 205-b may each contain one or more memory elements 220 (e.g., elements containing memory material configurable to store information), which may or may not be self-selected memory elements. Although the numerical indicators indicate that the elements contained in... Figure 2 Some elements are shown, but other corresponding elements are not labeled, but they are the same or will be understood as similar, in an effort to increase the visibility and clarity of the features depicted.

[0044] The memory cell of the first stack 205-a may include a first electrode 225-a, a memory element 220-a, and a second electrode 225-b. Additionally, the memory cell of the second stack 205-b may include a first electrode 225-c, a memory element 220-b, and a second electrode 225-d. In some embodiments, the memory cells of the first stack 205-a and the second stack 205-b may have a common conductive line such that corresponding memory cells of each stack 205-a and 205-b can share a bit line 215 or a word line 210, as referenced. Figure 1 Description. For example, the first electrode 225-c of the second stack 205-b and the second electrode 225-b of the first stack 205-a can be coupled to bit line 215-a, such that bit line 215-a is shared by vertically adjacent memory cells.

[0045] In some instances, memory element 220 may comprise, for example, a chalcogenide material or other alloy comprising selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some instances, a chalcogenide material primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some instances, the SAG alloy may also comprise silicon (Si), and this chalcogenide material may be referred to as a SiSAG alloy. In some other instances, the SAG alloy may also contain indium (In), and this chalcogenide material may be referred to as an InSAG alloy in some cases. In some instances, the chalcogenide may comprise additional elements, each in atomic or molecular form, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F).

[0046] In some cases, memory element 220 may be included in a PCM cell and may vary between a crystalline and an amorphous state. A crystalline memory element 220 may have atoms arranged in a periodic structure, which can result in relatively low resistance (e.g., in a set state). In contrast, an amorphous memory element 220 may not have a periodic atomic structure or may have a relatively small periodic atomic structure, which can result in relatively high resistance (e.g., in a reset state). The difference in resistance between the amorphous and crystalline states of memory element 220 can be significant; for example, a material in an amorphous state may have a resistance one or more orders of magnitude greater than that of a material in its crystalline state. In some cases, the amorphous state may have an associated threshold voltage and current may not flow until it exceeds Vth. In other cases, memory element 220 may be partially amorphous and partially crystalline, and the resistance may have a value between the resistance of a fully crystalline or fully amorphous memory element 220. Therefore, memory element 220 can be used for applications other than binary logic applications, i.e., the number of possible states stored in the material can be more than two.

[0047] By applying a voltage across memory element 220 and thus allowing current to flow through it to heat it above its melting temperature, and then removing the voltage and current according to various timing parameters configured to place memory element 220 in a desired state (e.g., amorphous or crystalline), memory element 220 can switch from amorphous to crystalline and vice versa, and thus the state can be written to the memory cell containing memory element 220. The heating and quenching of memory element 220 can be accomplished by controlling the current flowing through it, which in turn can be accomplished by controlling the voltage difference between the corresponding word line 210 and the corresponding bit line 215.

[0048] In some cases, the memory element 220 included in the self-selection memory cell may be operable so that it does not undergo a phase transition during normal operation of the memory cell (e.g., due to the composition of the memory (e.g., chalcogenide) material, and / or due to the operating voltage and current configured to maintain the memory element 220 in a single phase (e.g., an amorphous or glassy phase). For example, the memory element 220 may contain a chemical element (e.g., arsenic) that inhibits the crystallization of the chalcogenide material and thus remains in an amorphous state. Here, some or all of the aforementioned sets of logic states supported by the memory cell (e.g., including the memory element 220 and electrode 225) may be associated with the amorphous state of the memory element 220 (e.g., stored by the memory element 220 when it is in an amorphous state). For example, both logic state '0' and logic state '1' may be associated with the amorphous state of the memory element 220 (e.g., stored by the memory element 220 when it is in an amorphous state). In some cases, the memory element 220 may be configured to store logic states corresponding to information bits.

[0049] During a programming (writing) operation of a memory cell (e.g., including electrode 225-a, memory element 220-a, and electrode 225-b), the polarity used for programming (writing) or whether memory element 220 is programmed to an amorphous or crystalline state can affect (determine, set, program) a specific column or characteristic of memory element 220 (e.g., the threshold voltage of memory element 220). The difference in the threshold voltage of memory element 220 depending on the logic state stored by memory element 220 (e.g., the difference between the threshold voltage when memory element 220 stores logic state '0' and logic state '1') can correspond to the read window of memory element 220.

[0050] In some cases, the architecture of memory array 200 may be referred to as a cross-point architecture, where memory cells are formed at the topological cross-points between word lines and bit lines, such as... Figure 2 The explanation is as follows. Compared to at least some other memory architectures, this crossover architecture can provide relatively high-density data storage at a lower production cost. For example, the crossover architecture can have memory cells with a smaller area and therefore increased memory cell density compared to other architectures.

[0051] The memory array 200 can be configured to support socket designs for memory devices, which implement the desired edge (ED) of each memory cell in the memory array 200 (e.g., 3K, 4K, etc.). For example, each word line 210 and bit line 215 can be connected to a corresponding socket ( Figure 2(Not shown in the diagram) coupling, and word line sockets and bit line sockets can be positioned such that the ED associated with each memory cell in memory array 200 is the same or similar. This can be achieved, for example, by arranging bit line socket rows and word line socket rows such that the socket rows extend in a direction skewed (i.e., non-orthogonal) relative to word line 210 or bit line 215. In some cases, bit line socket rows can be parallel to word line socket rows.

[0052] Figure 3A , 3B The 3C specification describes an example of a socket design 300 for a crosspoint memory, as disclosed herein. In some cases, socket design 300 may be incorporated into references... Figure 1 The memory array 102 described or as referenced Figure 2 The memory array 200 described herein. The socket design 300 may also include memory cells 305, word lines 310, and bit lines 315, which may be as shown in the reference. Figure 1 Examples of memory cell 105, word line 110, and bit line 115 described.

[0053] Each row of memory cells 305 may be coupled to a corresponding word line 310, and each column of memory cells 305 may be coupled to a corresponding bit line 315. Word lines 310 may extend in a first direction corresponding to the x-direction. Bit lines 315 may extend in a second direction corresponding to the y-direction orthogonal to the x-direction. Each word line 310 may be coupled to a word line socket in word line socket area 320, and each bit line 315 may be coupled to a bit line socket in bit line socket area 325. Word line sockets may be coupled to the end (but not, for example, the midpoint) of the corresponding word line 310, and bit line sockets may be coupled to the end (but not, for example, the midpoint) of the corresponding bit line 315.

[0054] The word line sockets in word line socket area 320 can be organized into rows, said rows being parallel to the longer edge of word line socket area 320. Similarly, the bit line sockets in bit line socket area 325 can be organized into rows, said rows being parallel to the longer edge of bit line socket area 325. Each socket area 320, 325 may contain any number of socket rows. Figure 3A As shown, the longer edge of bit line socket area 325 may be parallel to the longer edge of word line socket area 320, and the bit line socket row may be parallel to the word line socket row. In addition, the bit line socket row and the word line socket row may be skewed (i.e., not orthogonal) and not parallel to word line 310 and bit line 315.

[0055] The word line socket in word line socket area 320 can couple word line 310 to a via extending below the plane of word line 310 and bit line 315. That is, the via can extend upward in a third direction corresponding to the z direction orthogonal to the x and y directions. Similarly, the bit line socket in bit line socket area 325 can couple bit line 315 to a via extending below the plane of word line 310 and bit line 315. The via can couple to circuitry (e.g., word line driver or bit line driver) located below the plane of word line 310 and bit line 315.

[0056] like Figure 3A The description states that word lines 310-a to 310-d can each couple to a word line socket in one of word line socket areas 320-a and 320-b, and can extend in the x-direction away from word line socket areas 320-a and 320-b and toward bit line socket areas 325-a and 325-b. Word lines 310-a to 310-d can terminate before reaching bit line socket areas 325-a and 325-b. Similarly, bit lines 315-a to 315-d can each couple to a bit line socket in one of bit line socket areas 325-a and 325-b, and can extend in the y-direction away from bit line socket areas 325-a and 325-b and toward word line socket areas 320-c and 320-d. Bit lines 315-a to 315-d can terminate before reaching word line socket areas 320-c and 320-d.

[0057] Memory cells 305-a to 305-j may be located at the intersection of word line 310 and bit line 315. For example, memory cell 305-a may be located at the intersection of word line 310-d and bit line 315-a. Based on socket design 300-a, each memory cell 305 (e.g., each of memory cells 305-a to 305-j) may have the same or similar associated ED (e.g., combined R). WL and R BL In the first example, memory cell 305-a is located via a word line socket relatively close to word line 310-d in word line socket area 320-b and relatively far from bit line 315-a in bit line socket area 325-a. Therefore, the corresponding word line resistance R of memory cell 305-a... WL,305-a It can be small, and corresponds to the bit line resistance R. BL,305-a It can be large. In the second example, memory cell 305-d can be located via a word line socket relatively far from word line 310-d in word line socket area 320-b and relatively close to bit line 315-d in bit line socket area 325-b. Therefore, the corresponding word line resistance R of memory cell 305-d is... WL,305-d It can be large, and corresponds to the bit line resistance R. BL,305-dIt can be small. However, in both instances, the sum of the word line resistance and the bit line resistance can be the same, such as... Or similar. That is, the ED of memory cell 305-a may be the same as or similar to the ED of memory cell 305-d. By extension, the ED of each of memory cells 305-a to 305-j may be the same as or similar.

[0058] exist Figure 3B In the socket design 300-b described herein, word line 310-e may extend in the x-direction away from word line socket area 320-e and toward bit line socket area 325-c. Word line 310-e may terminate before reaching bit line socket area 325-c. Similarly, bit line 315-e may extend in the y-direction away from bit line socket area 325-c and toward word line socket area 320-e, and bit line 315-e may terminate before reaching word line socket area 320-e. Memory cell 305-k may be located at the intersection of word line 310-e and bit line 315-e.

[0059] exist Figure 3B In some examples, word lines 310-e and bit lines 315-e may have the same resistivity ρ. In some examples, word lines 310-e and bit lines 315-e may be made of the same material. In some other examples, word lines 310-e and bit lines 315-e may be made of different materials, and the memory device may be manufactured or processed (e.g., to give word lines 310 and 315 different cross-sectional areas, such as different thicknesses) so that word lines 310-e and bit lines 315-e have the same resistivity ρ. Both word line socket area 320-e and bit line socket area 325-c may be tilted at an angle 330-a (which may be 45°) relative to the x-direction.

[0060] Based on the socket design 300-b, each memory cell 305 (e.g., memory cell 305-k) can have the same associated ED. That is, the sum of the word line resistance and the bit line resistance R WL + R BL This can be the same for each memory cell 305. For example, memory cell 305-k can be located along bit line 315-e at a distance 335-a from the bit line socket in bit line socket area 325-c. The distance 335-a can be referred to as L. BL Furthermore, memory cell 305-k can be positioned along word line 310-e at a distance 335-b from the word line socket in word line socket area 320-e. Distance 335-b may be referred to as L. WL Since the word lines 310 and bit lines 315 in the socket design 300-b have the same resistivity ρ, the sum of the corresponding word line distance and the corresponding bit line distance for each memory cell 305 in the socket design 300-b can be the same (L).WL + L BL That is, the increase or decrease in distance 335-a from the corresponding bit line socket to the memory cell 305 can be compensated by the decrease or increase in distance 335-b from the corresponding word line socket to the memory cell 305 so that each memory cell 305 has the same associated ED.

[0061] exist Figure 3C In the socket design 300-c described herein, word line 310-f may extend in the x-direction away from word line socket area 320-f and toward bit line socket area 325-d. Word line 310-f may terminate before reaching bit line socket area 325-d and has a length B. Similarly, bit line 315-f may extend in the y-direction away from bit line socket area 325-d and toward word line socket area 320-f. Bit line 315-f may terminate before reaching word line socket area 320-f and has a length H. Memory cell 305-1 may be located at the intersection of word line 310-f and bit line 315-f. Memory cell 305-1 may be located along bit line 315-f at a distance 335-d from the bit line socket in bit line socket area 325-d. Distance 335-d may also be referred to as h. Furthermore, memory cell 305-k can be positioned along word line 310-f at a distance 335-c from the word line socket in word line socket area 320-f. Distance 335-c can also be referred to as b.

[0062] exist Figure 3C In this example, word line 310-f and bit line 315-f can have different resistivities. For instance, word line 310-f can have a resistivity ρ W Furthermore, bit line 315-f can have resistivity ρ B In some instances, word lines 310-f and bit lines 315-f may be made of different materials. In other instances, word lines 310-f and bit lines 315-f may be made of the same material, and the memory device may be manufactured or processed (e.g., to give word lines 310 and 315 different cross-sectional areas, such as different thicknesses) such that word lines 310-f and bit lines 315-f have corresponding resistivity ρ. W and ρ B The letter socket area 320-f and the bit socket area 325-d can be tilted at an angle 330-b (which may not be 45°) relative to the x-direction. Angle 330-b can also be referred to as θ, where... Furthermore, the angle θ can be expressed as... .

[0063] Based on the socket design 300-c, each memory cell 305 (e.g., memory cell 305-1) can have the same associated ED. That is, the sum of the word line resistance and the bit line resistance R WL + RBL For each memory cell 305, the distances may be the same or similar. To make this sum the same or similar for each memory cell 305, the memory cell 305 at the farthest distance H from the bit line socket area 325-d and the memory cell 305 at the farthest distance B from the word line socket area 325-f may have the same or similar distances; for example... This equation can be rewritten as ,in .

[0064] For memory cell 305-1, the total R WL + R BL It can be expressed as Through substitution, this sum can also be expressed as After rearrangement, this sum can become , and Same. The second term can be equal to 0, and the first term can be rewritten as B·ρ after the permutation. W Resistance B·ρ W It can be a constant value independent of h and b, which means that the resistance B·ρ W (or equivalent resistance H·ρ) B Each memory cell 305 in the socket design 300-c may be identical. Therefore, each memory cell 305 in the socket design 300-c may have the same or similar ED.

[0065] In each of the socket designs 300, since each memory cell 305 has the same or similar associated ED, the memory device can, for example, be subjected to the same voltage V. source And the same current I to achieve the same voltage drop V across any memory cell 305. cell This allows the memory device to avoid large current discharges across nearby memory cells 305 attributable to parasitic capacitances of word lines 310 or bit lines 315 and sufficient drive current for distant memory cells 305. This improves performance and increases the lifetime of memory cells 305, regardless of their physical location in the memory array. Furthermore, the memory device does not need to determine the appropriate voltage V for different memory cells 305 at different physical locations. source And an appropriate current I, which can reduce the associated delays of signaling add-ons and access operations, as well as other advantages.

[0066] Figure 4A and 4B This describes an example of a memory die 400 supporting a socket design for a memory device, as disclosed herein. The memory die 400 may include one or more memory arrays 405, each of which may be referenced. Figure 1 ,2 Or an example of a memory array described in 3A to 3C.

[0067] Figure 4A An example of memory array 405-a is illustrated. Memory array 405-a may include word line socket rows 410 and bit line socket rows 415. Each word line socket in each word line socket row 410 may be coupled to a word line, which may be as shown in the reference. Figure 1 An example of word line 110 is described. Similarly, each line socket in each line socket row 415 may be coupled to a bit line, which may be as described in the reference. Figure 1 An instance of bit line 115 is described.

[0068] like Figure 4A The description states that word lines can extend from word line sockets in row 410, and bit lines can extend from bit line sockets in row 415. A word line extending from a word line socket in row 410-a may terminate before reaching bit line socket 415-a. Similarly, a bit line extending from a bit line socket in row 415-b may terminate before reaching word line socket 410-b.

[0069] Word lines may be orthogonal to bit lines. Word line socket row 410 may be parallel to bit line socket row 415. Word line socket row 410 and bit line socket row 415 may be skewed relative to word lines and bit lines (i.e., not orthogonal or parallel). Furthermore, word line socket row 410 and bit line socket row 415 may be parallel to the edge of memory array 405-a.

[0070] like Figure 4A The description states that multiple bit line socket rows 415 (e.g., bit line socket rows 415-a and 415-b) can be positioned between consecutive word line socket rows 410-a and 410-b. Bit line socket rows 415-a and 415-b can be considered as contained within a single bit line socket area, and word line socket rows 410-a and 410-b can be considered as contained within dissimilar word line socket areas, and therefore bit and word line areas can alternate, even if multiple rows of a given socket type are located between rows of another socket type.

[0071] In some instances, such as in multi-layer stack configurations, two or more rows of receptacles of a given type can be located within a receptacle area, where the receptacle area can be viewed as a 3D space encompassing stacked 2D regions within different layers containing the receptacles. For example, within a single receptacle area, rows of receptacles and vias coupled to access lines for one stack can be located between rows of receptacles and vias coupled to access lines for another stack.

[0072] Figure 4BThis describes an example layout for memory die 400. Memory die 400 may include multiple memory arrays 405-b, 405-c, and 405-d. Each memory array 405 may include, as shown in the reference... Figure 4A The word lines, bit lines, bit line socket rows 415, and word line socket rows 410 are described or otherwise as described herein, wherein socket rows 410, 415 may be grouped and / or contained in corresponding socket areas. The word line socket rows 410 and bit line socket rows 415 of the memory array 405 may be parallel to a first edge of the memory die 400. Furthermore, the word line socket rows 410 and bit line socket rows 415 of the memory array 405 may be perpendicular (orthogonal) to a second edge of the memory die 400. The word lines and bit lines may be skewed (i.e., neither orthogonal nor parallel) relative to the word line socket rows 410 and bit line socket rows 415 and at least two (in some cases all) edges of the memory die 400.

[0073] The memory die 400 may also include a peripheral region 420 located between memory arrays 405 (e.g., between socket areas associated with adjacent memory arrays 405). Additional circuitry for operating the memory devices (e.g., a power bus) may be located beneath the peripheral region 420.

[0074] Figure 5 This describes an example of a socket area 500 supporting a socket design for a memory device, as disclosed herein. The socket area 500 may include sockets 510 of a first stack of memory devices, wherein each socket 510 may be coupled to an access line 505 of the first stack, the access line 505 being a reference... Figure 1 Examples of word lines 110 or bit lines 115 are described. Socket region 500 may also include sockets 520 of a second stack of memory devices, each socket 520 being coupled to access lines 515 of the second stack. The second stack may be located above or below the first stack. Socket region 500 may also include vias (e.g., through-silicon vias (TSVs)) 525 that can pass through multiple stacks and potentially through the die containing socket region 500. Access lines 505 and 515 may extend in a first direction, which may be either the x-direction or the y-direction.

[0075] Each socket 510, 520 can couple access lines 505, 515 to vias extending in the z-direction from a first stack or a second stack. The vias can couple to circuitry (e.g., power buses, memory controllers, etc.) that can be located beneath the stack of the memory device. Because the vias can extend across the entire stack of the memory device, one or more rows of sockets 520 for one stack can be positioned between one or more rows of sockets 510 for another stack. Furthermore, the spacing between sockets 510, 520 relative to adjacent access lines 505, 515 can be wide, and therefore the sockets 510 can be staggered in the first direction to allow for a greater density of access lines 505, 515 in each first stack. Interleaved sockets 510, 520 may include parallel rows 530 of sockets 510, 520, wherein access lines 505, 515 coupled to sockets 510, 520 in one row 530 are separated by access lines 505, 515 coupled to sockets 510, 520 in one or more other rows 530.

[0076] Figure 5 Includes sockets 510 and 520 for the first and second stacks, respectively. Socket area 500 may further include additional sockets (not shown) for any number of additional stacks. As more sockets for additional stacks are added to socket area 500, socket area 500 may become wider to ensure that through-holes for stacking are separated (isolated) from each other.

[0077] Figure 6 The flowchart illustrates one or more methods 600 supporting socket design for a memory device, based on examples disclosed herein. The operation of method 600 can be implemented using a memory device or its components as described herein. For example, it can be implemented using... (See reference...) Figure 1 The described memory device performs the operation of method 600. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform instances of the described function.

[0078] At 605, the memory device may receive access commands for memory cells coupled to the first access line and the second access line. Operation 605 may be performed according to the methods described herein.

[0079] In 610, the memory device can route current through a memory cell, a first access line, a first socket coupled to the first access line, a second access line, and a second socket coupled to the second access line, based on an access command, wherein the first socket is included in a first socket row and the second socket is included in a second socket row parallel to the first row. Operation of 610 can be performed according to the methods described herein.

[0080] In 615, the memory device can read from or write to memory cells based on current. Operation of 615 can be performed according to the methods described herein.

[0081] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving an access command for a memory cell coupled to a first access line and a second access line; routing current through the memory cell, the first access line, a first socket coupled to the first access line, the second access line, and a second socket coupled to the second access line, based on the access command, wherein the first socket is included in a first socket row and the second socket is included in a second socket row parallel to the first row; and reading or writing the memory cell based on the current.

[0082] In some instances of the method 600 and apparatus described herein, the first socket row may not be orthogonal to the first access line, and the second socket row may not be orthogonal to the second access line.

[0083] In some instances of the method 600 and apparatus described herein, the first socket row may not be orthogonal to the second access line, and the second socket row may not be orthogonal to the first access line.

[0084] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more methods can be combined.

[0085] Describe an apparatus. The apparatus may include: a set of first access lines for a memory array extending in a first direction; a set of second access lines for the memory array extending in a second direction; a set of first sockets, each coupled to a corresponding first access line of the set and to a corresponding first driver of a set of first drivers, the set of first sockets being arranged in a first row; and a set of second sockets, each coupled to a corresponding second access line of the set and to a corresponding second driver of a set of second drivers, the set of second sockets being arranged in a second row parallel to the first row.

[0086] In some instances, both the first and second rows extend upwards in a third direction, and neither the first nor the second direction may be parallel to the third direction.

[0087] In some instances, the first and second directions may not be orthogonal to the third direction.

[0088] In some instances, the first and second directions may form a 45-degree angle with respect to the third direction.

[0089] In some instances, the first access line and the second access line of the group each contain the same material.

[0090] Some examples may further include one of the first and second directions forming an acute angle with respect to the third direction, and the other of the first and second directions forming an obtuse angle with respect to the third direction.

[0091] In some instances, the first access lines of the group each contain a first material, and the second access lines of the group each contain a second material.

[0092] In some instances, the first access lines of the group may each have a first resistivity, and the second access lines of the group may each have a second resistivity.

[0093] Some examples of the device may include a set of through-holes, wherein a first socket and a second socket of the set may be coupled to a corresponding first driver or a corresponding second driver through the respective through-holes of the set, and wherein the through-holes of the set extend in a fourth direction that may be orthogonal to the first, second and third directions.

[0094] In some instances, the group first access line, the group second access line, the group first socket, and the group second socket may be contained in a bare die having a first edge and a second edge, and both the first row and the second row extend upward on a third party that may be parallel to the first edge or the second edge.

[0095] In some instances, the first direction may not be parallel to the first edge and the second edge, and the second direction may not be parallel to the first edge and the second edge.

[0096] Some examples of the device may include: a second set of first access lines, each extending in a first direction; a second set of first sockets, each coupled to a corresponding first access line of the second set and to a corresponding first driver of the second set of first drivers, the second set of first sockets being arranged in a third row, wherein there is a gap between the first row and the third row; and a power distribution circuit system located below the gap.

[0097] In some instances, each first socket of the group may be coupled to the end of a corresponding first access line of the group, and each second socket of the group may be coupled to the end of a corresponding second access line of the group.

[0098] In some instances, the first direction may be orthogonal to the second direction.

[0099] In some instances, each first access line of the group comprises a word line, and each second access line of the group comprises a bit line.

[0100] Describe an apparatus. The apparatus may include: a set of first access lines for a memory array extending in a first direction; a set of second access lines for the memory array extending in a second direction; a set of first sockets, each coupled to a corresponding first access line of the set and to a corresponding first driver of a set of first drivers, the set of first sockets being arranged in a first row skewed relative to the first direction; and a set of second sockets, each coupled to a corresponding second access line of the set and to a corresponding second driver of a set of second drivers, the set of second sockets being arranged in a second row skewed relative to the second direction.

[0101] In some instances, the first and second rows may not be parallel to the first and second directions.

[0102] In some instances, the first line may be parallel to the second line.

[0103] In some instances, the group first access line, the group second access line, the group first socket, and the group second socket may be contained in a bare die having a first edge and a second edge, and both the first direction and the second direction may not be parallel to the first edge.

[0104] In some instances, both the first and second directions may not be parallel to the second edge.

[0105] In some instances, the first and second rows may be parallel to the first edge.

[0106] Some instances of the device may include a set of through-holes, each extending in a fourth direction, wherein each through-hole of the set couples a corresponding socket of the first socket or the second socket of the set to a corresponding driver of the first driver or the second driver of the set, and wherein the fourth direction may be orthogonal to the first direction, the second direction and the third direction.

[0107] Describe an apparatus. The apparatus may include: a set of word lines for a group of memory cells, wherein each word line of the group extends in a first direction; a set of bit lines for the group of memory cells, wherein each bit line of the group extends in a second direction; a row of word line sockets, wherein each word line socket of the row is coupled to a corresponding word line of the group and a corresponding word line driver of a set of word line drivers; and a row of bit line sockets, wherein each bit line socket of the row is coupled to a corresponding bit line of the group and a corresponding bit line driver of a set of bit line drivers, and wherein the row of bit line sockets is parallel to the row of word line sockets.

[0108] Some examples of the device may include: a second set of word lines for a second set of memory cells, wherein each word line of the second set extends in a first direction; a second set of bit lines for the second set of memory cells, wherein each bit line of the second set extends in a second direction; a second row of word line sockets, wherein each word line socket of the second row is coupled to a corresponding word line of the second set and a corresponding word line driver of the second set of word line drivers; a second row of bit line sockets, wherein each bit line socket of the second row is coupled to a corresponding bit line of the set and a corresponding bit line driver of the second set of bit line drivers, wherein the word line socket row and the second word line socket row may be located between the bit line socket row and the second bit line socket row.

[0109] In some instances, the second word line socket row and the second bit line socket row may be parallel to the word line socket row and the bit line socket row.

[0110] In some instances, the second word line socket row and the second bit line socket row may not be orthogonal to the first and second directions.

[0111] In some instances, each word line socket in the row may be coupled to the end of the corresponding word line of the group furthest from the bit line socket row, and each word line socket in the second row may be coupled to the end of the corresponding word line of the second group furthest from the second bit line socket row.

[0112] In some instances, the second word line socket row and the second bit line socket row may not be orthogonal to the first and second directions.

[0113] In some instances, the word line socket row and the bit line socket row may not be orthogonal to the first and second directions.

[0114] Describe an apparatus. The apparatus may include: word lines for a memory cell array, wherein each word line is oriented in a first direction; bit lines for the memory cell array, wherein each bit line is oriented in a second direction orthogonal to the first direction; vias oriented in a third direction orthogonal to the first and second directions, wherein the vias are coupled to a circuit system located below the memory cell array; rows of word line sockets, wherein the word line sockets couple the word lines to a first subset of the vias, and wherein the rows of word line sockets are oriented in a fourth direction different from the first, second, and third directions; and rows of bit line sockets, wherein the bit line sockets couple the bit lines to a second subset of the vias, and wherein the rows of bit line sockets are oriented in a fifth direction different from the first, second, and third directions.

[0115] In some instances, the fourth direction may be parallel to the fifth direction.

[0116] In some instances, the fourth direction may not be orthogonal to the first direction, and the fifth direction may not be orthogonal to the second direction.

[0117] The information and signals described herein can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced herein can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0118] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at approximately zero volts (0 V) but is not directly coupled to ground. Therefore, the voltage of a virtual ground may fluctuate temporarily and return to approximately 0 V in a steady state. Various electronic circuit components can be used to implement a virtual ground, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "via virtual ground" means connected to approximately 0 V.

[0119] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports signal flow between them. Components are considered electronically connected (or conductively contacted, connected, or coupled) to each other if any conductive path exists between them that can readily support signal flow between them. At any given time, the conductive path between electronically connected (or conductively contacted, connected, or coupled) components can be open or closed, depending on the operation of a device containing connected components. The conductive path between connected components can be a direct conductive path between components or an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some cases, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0120] The term "coupling" refers to the condition that changes from an open-circuit relationship between components that was previously unable to transmit signals between components via conductive paths to a closed-circuit relationship that allows signals to be transmitted between components via conductive paths. When a component (such as a controller) couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0121] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated from each other when the switch is open. When a controller isolates two components, the controller affects changes that prevent signals from flowing between the components using previously permitted conductive paths.

[0122] As used herein, the term "layer" refers to a layer or sheet of geometry. Each layer may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer may be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. Layers may contain different elements, components, and / or materials. In some cases, a layer may consist of two or more sublayers. In some figures, two dimensions of a three-dimensional layer are depicted for illustrative purposes.

[0123] As used in this article, the term “generally” means that the modified characteristic (e.g., a verb or adjective modified by the term “generally”) does not need to be absolute, but is close enough to achieve the advantage of the characteristic.

[0124] As used herein, the term "electrode" can refer to an electrical conductor and, in some cases, can serve as an electrical contact to a memory cell or other component of the memory array. Electrodes can comprise traces, wires, conductive lines, conductive layers, or the like that providing a conductive path between elements or components of the memory array.

[0125] The devices discussed herein (including memory arrays) can be formed on a semiconductor substrate (e.g., silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc.). In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species (including, but not limited to, phosphorus, boron, or arsenic). Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0126] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "turned off" or "deactivated."

[0127] The descriptions and accompanying drawings presented herein are exemplary configurations and do not represent all instances that can be implemented or are within the scope of the claims. The term "example" as used herein means "serving as an example, illustration, or illustration" and is not "preferred" or "superior to other examples." Specific details are included to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0128] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type can be distinguished by adding a dash after the reference label and a second label to differentiate similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, without regard to the second reference label.

[0129] The various illustrative blocks and modules described herein can be implemented or executed using general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of arithmetic devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0130] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions may also be physically located in various locations, including portions distributed such that the functions are implemented in different physical locations. Furthermore, as used herein, the word "or" included in the claims, as in a list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of..."), indicates a list of inclusions such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as a reference to a conditionally closed set. For example, without departing from the scope of this disclosure, an instance step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0131] Computer-readable media includes both non-transitory computer storage media and communication media containing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is suitably referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, radio, and microwave is included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. The above combination also includes computer-readable media.

[0132] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: a set of first access lines for a memory array, extending in a first direction; a set of second access lines for the memory array, extending in a second direction; a set of first sockets each coupled with a respective first access line of the set and with a respective first driver of a set of first drivers, the set of first sockets arranged in a first row; a set of second sockets each coupled with a respective second access line of the set and with a respective second driver of a set of second drivers, the set of second sockets arranged in a second row parallel to the first row; a second set of first access lines each extending in the first direction; a second set of first sockets each coupled with a respective first access line of the second set of first access lines and with a respective first driver of a second set of first drivers, the second set of first sockets arranged in a third row, wherein there is a gap between the first row and the third row; and power distribution circuitry below the gap.

2. The memory device of claim 1, wherein: the first row and the second row both extend in a third direction; and the first direction and the second direction are both non-parallel to the third direction.

3. The memory device of claim 2, wherein the first direction and the second direction are both non-orthogonal to the third direction.

4. The memory device of claim 2, wherein the first direction and the second direction are at a forty-five degree angle with respect to the third direction.

5. The memory device of claim 4, wherein the first access lines of the set and the second access lines of the set each comprise a same material.

6. The memory device of claim 2, wherein: one of the first direction and the second direction is at an acute angle with respect to the third direction; and the other of the first direction and the second direction is at an obtuse angle with respect to the third direction.

7. The memory device of claim 6, wherein: the first access lines of the set each comprise a first material; and the second access lines of the set each comprise a second material.

8. The memory device of claim 6, wherein: the first access lines of the set each have a first resistivity; and the second access lines of the set each have a second resistivity.

9. The memory device of claim 2, wherein the set of first drivers and the set of second drivers are below the memory array, the device further comprising: a plurality of vias, wherein each socket of the set of first sockets and each socket of the set of second sockets is each coupled with the respective first driver or with the respective second driver through a respective via of the plurality of vias, and wherein the vias of the plurality of vias each extend in a fourth direction orthogonal to the first direction, the second direction, and the third direction.

10. The memory device of claim 1, wherein: the set of first access lines, the set of second access lines, the set of first sockets, and the set of second sockets are included in a die having a first edge and a second edge; and the first edge and the second edge are parallel to each other. The first and second rows both extend in a third direction parallel to the first or second edge.

11. The memory device of claim 10, wherein: The first direction is non-parallel to the first and second edges; and The second direction is non-parallel to the first and second edges.

12. The memory device of claim 1, wherein: Each first socket of the set is coupled to an end of the respective first access line of the set; and Each second socket of the set is coupled to an end of the respective second access line of the set.

13. The memory device of claim 1, wherein the first direction is orthogonal to the second direction.

14. The memory device of claim 1, wherein: Each first access line of the set comprises a word line; and Each second access line of the set comprises a bit line.

15. A memory device comprising: a set of first access lines for a memory array, extending in a first direction; a set of second access lines for the memory array, extending in a second direction; a set of first sockets each coupled with a respective first access line of the set and with a respective first driver of a set of first drivers, the set of first sockets arranged in a first row skewed relative to the first direction; and a set of second sockets each coupled with a respective second access line of the set and with a respective second driver of a set of second drivers, the set of second sockets arranged in a second row skewed relative to the second direction, wherein the set of first access lines, the set of second access lines, the set of first sockets, and the set of second sockets are included in a die having a first edge and a second edge; and wherein both the first direction and the second direction are non-parallel to the first edge.

16. The memory device of claim 15, wherein the first and second rows are non-parallel to the first and second directions.

17. The memory device of claim 15, wherein the first row is parallel to the second row.

18. The memory device of claim 15, wherein both the first direction and the second direction are non-parallel to the second edge.

19. The memory device of claim 18, wherein the first and second rows are parallel to the first edge.

20. The memory device of claim 15, wherein the set of first drivers and the set of second drivers are under the set of the first sockets and the set of second sockets, the device further comprising: a plurality of vias each extending in a fourth direction, wherein each via of the plurality of vias couples a respective socket of the set of first sockets or the set of second sockets with a respective driver of the set of first drivers or the set of second drivers, and wherein the fourth direction is orthogonal to the first, second, and third directions.

21. A memory device comprising: a first set of word lines for a first set of memory cells, wherein each word line of the first set extends in a first direction; a second set of word lines for a second set of memory cells, wherein each word line of the second set extends in a second direction; a second set of word lines for a second set of memory cells, wherein each word line of the second set extends in the first direction; a first set of bit lines for the first set of memory cells, wherein each bit line of the first set extends in a second direction; a second set of bit lines for the second set of memory cells, wherein each bit line of the second set extends in the second direction; a first word line socket row, wherein each word line socket of the first word line socket row is coupled with a corresponding word line of the first set and a corresponding word line driver of a first set of word line drivers; a second word line socket row, wherein each word line socket of the second word line socket row is coupled with a corresponding word line of the second set and a corresponding word line driver of a second set of word line drivers; a first bit line socket row, wherein each bit line socket of the first bit line socket row is coupled with a corresponding bit line of the first set and a corresponding bit line driver of a first set of bit line drivers, and wherein the first bit line socket row is parallel to the first word line socket row; and a second bit line socket row, wherein each bit line socket of the second bit line socket row is coupled with a corresponding bit line of the second set of bit lines and a corresponding bit line driver of a second set of bit line drivers, and wherein the first word line socket row and the second word line socket row are between the first bit line socket row and the second bit line socket row.

22. The memory device of claim 21, wherein: the second word line socket row and the second bit line socket row are parallel to the first word line socket row and the first bit line socket row.

23. The memory device of claim 21, wherein: the second word line socket row and the second bit line socket row are not orthogonal to the first direction and the second direction.

24. The memory device of claim 21, wherein: each word line socket of the first word line socket row is coupled with an end of the corresponding word line of the first set of word lines that is farthest from the first bit line socket row; and each word line socket of the second word line socket row is coupled with an end of the corresponding word line of the second set of word lines that is farthest from the second bit line socket row.

25. The memory device of claim 21, wherein: the second word line socket row and the second bit line socket row are not orthogonal to the first direction and the second direction.

26. The memory device of claim 21, wherein: the first word line socket row and the first bit line socket row are not orthogonal to the first direction and the second direction.

27. A memory device, comprising: word lines for an array of memory cells, wherein the word lines are each oriented in a first direction; bit lines for the array of memory cells, wherein the bit lines are each oriented in a second direction that is orthogonal to the first direction; a via oriented in a third direction that is orthogonal to the first direction and the second direction, wherein the via is coupled with circuitry located below the array of memory cells; a word line plug row, wherein the word line plugs couple the word line with a first subset of the vias, and wherein the word line plug row is oriented in a fourth direction different from the first direction, different from the second direction, and different from the third direction; and a bit line plug row, wherein the bit line plugs couple the bit line with a second subset of the vias, and wherein the bit line plug row is oriented in a fifth direction different from the first direction, different from the second direction, and different from the third direction, wherein the word line, the bit line, the word line plug row, and the bit line plug row are included in a die having a first edge and a second edge; and wherein both the first direction and the second direction are non-parallel to the first edge.

28. The memory device of claim 27, wherein the fourth direction is parallel to the fifth direction.

29. The memory device of claim 27, wherein: the fourth direction is non-orthogonal to the first direction; and the fifth direction is non-orthogonal to the second direction.

30. A method for operating a memory device, comprising: receiving an access command for a memory cell coupled with a first access line and a second access line, wherein the first access line extends in a first direction and the second access line extends in a second direction; routing a first current through the memory cell, the first access line, a first plug coupled with the first access line, the second access line, and a second plug coupled with the second access line based at least in part on the access command, wherein: the first plug is included in a first plug row; and the second plug is included in a second plug row parallel to the first plug row; receiving a second access command for a second memory cell coupled with a third access line, the third access line extending in the first direction; routing a second current through the second memory cell, the third access line, and a third plug coupled with the third access line based at least in part on the second access command, wherein the third plug is included in a third plug row, and wherein there is a gap between the first plug row and the third plug row, and wherein power distribution circuitry is located below the gap; and reading or writing the memory cell based at least in part on the first current, the second current, or both.

31. The method of claim 30, wherein: the first plug row is non-orthogonal to the first access line; and the second plug row is non-orthogonal to the second access line.

32. The method of claim 31, wherein: the first plug row is non-orthogonal to the second access line; and the second plug row is non-orthogonal to the first access line.

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