Bonded three-dimensional memory devices and methods of manufacturing the same by replacing a carrier substrate with a source layer

Abstract

The present disclosure provides a three-dimensional memory device including an alternating stack of insulating layers and electrically conductive layers located above a carrier substrate. Memory stack structures vertically extend through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. A straight-through via structure vertically extends through a portion of dielectric material adjacent to the alternating stack. A memory die can be bonded to a logic die that includes peripheral circuitry to support operation of memory cells within the memory die. Distal end portions of each of the vertical semiconductor channels are physically exposed by removal of the carrier substrate. A source layer is formed directly on the distal end portion of each of the vertical semiconductor channels. Backside bond pads or bond wires are formed to electrically connect to the straight-through via structure.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Non-Provisional Application No. 16 / 829,591 and U.S. Non-Provisional Application No. 16 / 829,667, both filed on March 25, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to the field of semiconductor devices, and more specifically to bonded three-dimensional memory devices and methods of manufacturing them by replacing the carrier substrate with a source layer and contact structures. Background Technology

[0004] Three-dimensional semiconductor devices, including three-dimensional vertical NAND strings with one bit per cell, are disclosed in T. Endoh et al.’s article, “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. Supporting circuitry for performing write, read, and erase operations on memory cells within the vertical NAND string is typically provided by complementary metal-oxide-semiconductor (CMOS) devices formed on the same substrate as the three-dimensional memory device. Summary of the Invention

[0005] According to one aspect of this disclosure, a semiconductor structure is provided, the semiconductor structure including a memory die bonded to a logic die. The memory die includes: an alternating stack of insulating and conductive layers; a memory stack structure extending through the alternating stack, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; a dielectric portion contacting a sidewall of the alternating stack; and a source layer comprising a first conductive material and electrically connected to an end portion of the vertical semiconductor channel remote from the interface between the logic die and the memory die.

[0006] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming a memory die on a carrier substrate, wherein the memory die includes: a memory stack structure extending vertically through alternating stacks of insulating and conductive layers; a dielectric portion contacting sidewalls of the alternating stacks; and a via structure extending vertically through the dielectric portion, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; physically exposing a distal end of each vertical semiconductor channel and a distal end of the via structure after removing the carrier substrate; directly forming a source layer comprising a first conductive material on the semiconductor material at the distal end of each vertical semiconductor channel; and directly forming a connection pad comprising a second conductive material different from the first conductive material on the via structure and the dielectric portion, wherein the connection pad is electrically isolated from the source layer.

[0007] According to another aspect of this disclosure, a semiconductor structure is provided, the semiconductor structure including a memory die bonded to a logic die. The memory die includes: an alternating stack of insulating and conductive layers; a memory stack structure extending through the alternating stack, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; a dielectric portion contacting a sidewall of the alternating stack; a source layer comprising a first portion of conductive material and electrically connected to an end portion of the vertical semiconductor channel remote from the interface between the logic die and the memory die; a through-hole structure having a vertical extent greater than the vertical thickness of the alternating stack and extending vertically through the dielectric portion; and a connection pad comprising a second portion of the conductive material, contacting a distal surface of the through-hole structure and electrically isolated from the source layer.

[0008] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming a memory die on a carrier substrate, wherein the memory die includes: a memory stack structure extending vertically through alternating stacks of insulating and conductive layers; a dielectric portion contacting sidewalls of the alternating stacks; and a through-hole structure extending vertically through the dielectric portion, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; and physically exposing the memory die after removing the carrier substrate. The method includes: depositing a conductive material on the material at the distal end of each vertical semiconductor channel and the distal end of the via structure; simultaneously depositing a conductive material on the material at the distal end of each vertical semiconductor channel and on the distal end of the via structure; and patterning the conductive material into multiple portions, wherein a source layer comprising a first portion of the conductive material is formed on the distal end of each vertical semiconductor channel, and a connection pad comprising a second portion of the conductive material is formed on the via structure and electrically isolated from the source layer.

[0009] According to one aspect of this disclosure, a semiconductor structure is provided, the semiconductor structure including a memory die bonded to a logic die. The memory die includes: an alternating stack of insulating and conductive layers; a memory stack structure extending through the alternating stack, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; a dielectric portion contacting a sidewall of the alternating stack; a source layer electrically connected to an end portion of the vertical semiconductor channel remote from the interface between the logic die and the memory die; a through-hole structure having a vertical extent greater than the vertical thickness of the alternating stack and extending vertically through the dielectric portion; and a back-side bonding pad located above the dielectric portion, electrically connected to the through-hole structure, and electrically isolated from the source layer.

[0010] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising: forming a memory die on a carrier substrate, wherein the memory die includes: a memory stack structure extending vertically through alternating stacks of insulating and conductive layers; a dielectric portion contacting sidewalls of the alternating stacks; and a via structure extending vertically through the dielectric portion, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; physically exposing a distal end of each vertical semiconductor channel and a distal end of the via structure after removing the carrier substrate; forming a source layer on the distal end of each vertical semiconductor channel; and forming a back-side bonding pad above the dielectric portion, the back-side bonding pad being electrically connected to the via structure and electrically isolated from the source layer.

[0011] According to one aspect of this disclosure, a three-dimensional memory device includes: alternating stacks of insulating and conductive layers; memory stack structures extending through the alternating stacks, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; a drain region located at a first end of a corresponding vertical semiconductor channel; and a source layer having a first surface and a second surface, wherein the first surface is located at the second end of each vertical semiconductor channel. The first end of each vertical semiconductor channel is closer to a logic die than the second end of each vertical semiconductor channel. A semiconductor wafer is not located above the second surface of the source layer.

[0012] According to another aspect of this disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming an alternating stack of insulating layers and spacer material layers over a carrier substrate, wherein the spacer material layers are formed as conductive layers or subsequently replaced by conductive layers; forming a memory stack structure through the alternating stacks, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; physically exposing the distal end of each vertical semiconductor channel by removing the carrier substrate; and directly forming a source layer on the distal end of each vertical semiconductor channel. Attached Figure Description

[0013] Figure 1 This is a schematic vertical cross-sectional view of an exemplary structure including a carrier substrate according to a first embodiment of the present disclosure.

[0014] Figure 2 This is a schematic vertical cross-sectional view of an exemplary structure following the alternating stacking of insulating and sacrificial material layers according to a first embodiment of the present disclosure.

[0015] Figure 3 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of a stepped surface and a stepped dielectric material portion, according to a first embodiment of the present disclosure.

[0016] Figure 4A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the memory opening and the support opening, according to a first embodiment of the present disclosure.

[0017] Figure 4B yes Figure 4A A top view of an exemplary structure. Vertical plane A-A' is... Figure 4A The plane of the cross section.

[0018] Figures 5A to 5F This is a schematic vertical cross-sectional view of the memory openings located within an exemplary structure during the formation of a memory stack structure, optional dielectric core, and drain region, according to a first embodiment of the present disclosure.

[0019] Figure 6 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of a memory stack structure and a support pillar structure, according to a first embodiment of the present disclosure.

[0020] Figure 7A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the back side groove, according to a first embodiment of the present disclosure.

[0021] Figure 7B yes Figure 7A A partial perspective top view of an exemplary structure. Vertical plane AA′ is... Figure 7A A schematic vertical cross-sectional view of the plane.

[0022] Figure 8 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the back recess according to a first embodiment of the present disclosure.

[0023] Figure 9 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of a conductive layer, according to a first embodiment of the present disclosure.

[0024] Figure 10A This is a schematic vertical cross-sectional view of an exemplary structure after the deposited conductive material has been removed from the back trench according to a first embodiment of the present disclosure.

[0025] Figure 10B yes Figure 10A A partial perspective top view of an exemplary structure. Vertical plane AA′ is... Figure 10A A schematic vertical cross-sectional view of the plane.

[0026] Figure 11 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of an insulating wall structure, according to a first embodiment of the present disclosure.

[0027] Figure 12A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the contact via structure according to a first embodiment of the present disclosure.

[0028] Figure 12B yes Figure 12A A top view of an exemplary structure. Vertical plane AA′ is... Figure 12A A schematic vertical cross-sectional view of the plane.

[0029] Figure 13A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of a first via-level metal interconnect structure and a first line-level metal interconnect structure, according to a first embodiment of the present disclosure.

[0030] Figure 13B yes Figure 13A A partial perspective top view of an exemplary structure. Vertical plane AA′ is... Figure 13A A schematic vertical cross-sectional view of the plane.

[0031] Figure 14 This is a schematic vertical cross-sectional view of an exemplary structure of a first semiconductor die formed after the formation of an additional metal interconnect structure, according to a first embodiment of the present disclosure.

[0032] Figure 15 This is a schematic vertical cross-sectional view of a second semiconductor die according to a first embodiment of the present disclosure.

[0033] Figure 16 This is a schematic vertical cross-sectional view of the bonding assembly of a first semiconductor die and a second semiconductor die according to a first embodiment of the present disclosure.

[0034] Figure 17 This is a schematic vertical cross-sectional view of the bonding assembly after the distal portion of the carrier substrate has been removed, according to a first embodiment of the present disclosure.

[0035] Figure 18 This is a schematic vertical cross-sectional view of the bonding assembly after the proximal portion of the carrier substrate has been removed, according to a first embodiment of the present disclosure.

[0036] Figures 19A to 19CThis is a sequential vertical cross-sectional view of a first configuration of a memory opening-filling structure during various processing steps up to the deposition of a layer of doped semiconductor material, according to a first embodiment of the present disclosure.

[0037] Figure 20 This is a vertical cross-sectional view of a bonding assembly after the deposition of a layer of doped semiconductor material, according to a first embodiment of the present disclosure.

[0038] Figure 21 This is a vertical cross-sectional view of a bonding assembly after the doped semiconductor material layer has been patterned into a source layer and after various bonding pads have been formed and bonding lines have been attached, according to a first embodiment of the present disclosure.

[0039] Figures 22A to 22C This is a sequential vertical cross-sectional view of a second configuration of a memory opening filling structure during various processing steps up to the deposition of a layer of doped semiconductor material, according to an embodiment of this disclosure.

[0040] Figures 23A to 23O This is a sequential vertical cross-sectional view of a first alternative configuration of the bonding assembly during various processing steps up to the formation of the back-side bonding pad, according to a second embodiment of this disclosure.

[0041] Figure 23P and Figure 23Q It shows Figure 230 Other embodiments of the first alternative configuration of the joining components.

[0042] Figures 24A to 24I This is a sequential vertical cross-sectional view of a second alternative configuration of the bonding assembly during various processing steps up to the formation of the back-side bonding pad, according to a third embodiment of this disclosure.

[0043] Figure 24J It shows Figure 24I Another embodiment of the second alternative configuration of the coupling component.

[0044] Figures 25A to 25G This is a sequential vertical cross-sectional view of a third alternative configuration of the bonding assembly during various processing steps up to the formation of the back-side bonding pad, according to a fourth embodiment of this disclosure.

[0045] Figures 26A to 26G This is a sequential vertical cross-sectional view of a fourth alternative configuration of the bonding assembly during various processing steps up to the formation of the back-side bonding pad, according to a fifth embodiment of this disclosure.

[0046] Figure 26H It shows Figure 26G Another embodiment of the fourth alternative configuration of the coupling component. Detailed Implementation

[0047] As described above, embodiments of this disclosure relate to three-dimensional memory devices and methods for forming a bonded three-dimensional memory device by replacing the carrier substrate with a source layer and contact structures, various aspects of which are described below. Embodiments of this disclosure can be used to form various structures, including multi-level memory structures, non-limiting examples of which include semiconductor devices, such as three-dimensional monolithic memory array devices comprising multiple NAND memory strings. Embodiments of this disclosure can be used to form bonded assemblies of multiple semiconductor dies comprising memory dies. Support circuitry (also referred to as peripheral circuitry or drive circuitry) for performing write, read, and erase operations on memory cells in a vertical NAND string can be implemented in a CMOS device formed on the same substrate as the three-dimensional memory device. In such devices, a design and manufacturing consideration is that the degradation of the CMOS device caused by thermal cycling and hydrogen diffusion during the fabrication of the three-dimensional memory device severely constrains the performance of the support circuitry. Various embodiments include methods for providing high-performance support circuitry for three-dimensional memory devices. Various embodiments include methods for providing a source layer in a three-dimensional memory device that are easier to implement than conventional methods.

[0048] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The same reference numerals denote the same or similar elements. Unless otherwise stated, elements having the same reference numerals are assumed to have the same composition. Unless otherwise specified, “contact” between elements means direct contact between elements providing a shared edge or surface. As used herein, a first element positioned “on” a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first and second elements, the first element is positioned “directly” on the second element. As used herein, a “prototype” structure or “in-process” structure refers to a transient structure in which the shape or composition of at least one of its components is subsequently modified. As used herein, if there is a conductive path between a first electronic component and a second electronic component, the first electronic component is electrically connected to the second electronic component.

[0049] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a extent smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of uniform or non-uniform continuous structure whose thickness is less than that of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0050] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed over a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" refers to the fact that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167 entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate may be thinned or removed from the memory level prior to bonding, but since the memory levels are initially formed over separate substrates, such a memory is not a true monolithic three-dimensional memory array. Three-dimensional memory devices according to various embodiments of this disclosure include monolithic three-dimensional NAND string memory devices and can be fabricated using the various embodiments described herein.

[0051] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips"), which are attached therein, for example, by flip-chip bonding or another chip-to-chip bonding method. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands simultaneously as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. When the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. Each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming.

[0052] See Figure 1 This illustration shows an exemplary structure according to a first embodiment of the present disclosure, which can be used, for example, to fabricate a device structure comprising a vertical NAND memory device. The exemplary structure includes a carrier substrate 9 and a semiconductor material layer 10 located on the top surface of the carrier substrate 9. In one embodiment, the carrier substrate 9 and the semiconductor material layer 10 may be provided as a commercially available single-crystal semiconductor wafer. The surface portion of the single-crystal semiconductor wafer may include the semiconductor material layer 10, and the body portion of the single-crystal semiconductor wafer may include the carrier substrate 9, which is subsequently removed, for example, by back-side grinding. The interface 7 between the carrier substrate 9 and the semiconductor material layer 10 may be located at a depth corresponding to a target stop plane of the back-side grinding process. Alternatively, the semiconductor material layer 10 may include a single-crystal or polycrystalline semiconductor material layer disposed on the carrier substrate 9, the carrier substrate comprising a material different from the material of the semiconductor material layer 10. In this case, the carrier substrate 9 may include an insulating material (such as sapphire or silicon oxide), a conductive material, or a semiconductor material different from the material of the semiconductor material layer 10. The thickness of the carrier substrate 9 may be sufficient to mechanically support the semiconductor material layer 10 and the structure subsequently formed thereon. For example, the substrate 9 may have a thickness ranging from 60 micrometers to 1,000 micrometers. The thickness of the semiconductor material layer 10 may range from 100 nm to 5,000 nm, but smaller and larger thicknesses may also be used. The semiconductor material layer 10 includes at least one elemental semiconductor material (e.g., a single-crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0053] As used in this article, "semiconductor material" refers to a material with a conductivity of 1.0 × 10⁻⁶ m / s. -6 S / cm up to 1.0×10 5 Materials with electrical conductivity in the range of S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the absence of electrical dopants of 1.0 × 10⁻⁶ S / cm. -6 S / cm up to 1.0×10 5 Materials with conductivity in the range of S / cm are produced, and materials with conductivity from 1.0 S / cm to 1.0 × 10⁻⁶ S / cm can be produced with appropriate doping agents. 5 Doped materials with electrical conductivity in the range of S / cm. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band of the band structure, or an n-type dopant that adds electrons to the conduction band of the band structure. As used herein, “conductive material” refers to a material with conductivity greater than 1.0 × 10⁻⁶ S / cm. 5 Materials with a conductivity of S / cm. As used herein, "insulating material" or "dielectric material" refers to a material with a conductivity of less than 1.0 × 10⁻⁶ S / cm. -6 Materials with an electrical conductivity of S / cm. As used herein, "heavily doped semiconductor material" refers to a material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0 × 10⁻⁶ S / cm) when formed into a crystalline material or converted into a crystalline material by an annealing process (e.g., starting from an initial amorphous state). 5 Semiconductor materials with a conductivity of S / cm. "Doped semiconductor materials" can be heavily doped semiconductor materials, or can include those exhibiting a conductivity of 1.0 × 10⁻⁶ S / cm. -6 S / cm up to 1.0×10 5 Semiconductor materials with electrical dopant concentrations (i.e., p-type and / or n-type dopant) in the range of S / cm. "Intrinsic semiconductor material" refers to a semiconductor material undoped with electrical dopants. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. Doped semiconductor materials can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material comprising at least one metallic element. All conductivity measurements were performed under standard conditions.

[0054] refer to Figure 2An alternating stack of multiple first material layers (which may be insulating layer 32) and second material layers (which may be sacrificial material layer 42) is formed above the top surface of the semiconductor material layer 10. As used herein, a “material layer” means a layer comprising material throughout its entirety. As used herein, an alternating stack of multiple first elements and second elements means a structure in which instances of first elements and instances of second elements alternate. Each instance of a first element that is not an end element of an alternating stack of elements is adjacent to two instances of a second element on both sides, and each instance of a second element that is not an end element of an alternating stack of elements is adjacent to two instances of a first element at both ends. The first elements may have the same thickness therebetween or may have different thicknesses. The second elements may have the same thickness therebetween or may have different thicknesses. The alternating stack of multiple first material layers and second material layers may begin with an instance of a first material layer or an instance of a second material layer, and may end with an instance of a first material layer or an instance of a second material layer. In one embodiment, instances of first elements and instances of second elements may form cells that are periodically repeated within the alternating stack of elements.

[0055] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer may be a sacrificial material layer. In this case, the stack may include alternating plurality of insulating layers 32 and sacrificial material layers 42, and constitute a prototype stack including alternating layers of insulating layers 32 and sacrificial material layers 42.

[0056] Alternating stacks are referred to herein as alternating stacks (32, 42). In one embodiment, the alternating stacks (32, 42) may include an insulating layer 32 made of a first material and a sacrificial material layer 42 made of a second material, wherein the second material is different from the material of the insulating layer 32. The first material of the insulating layer 32 may be at least one insulating material. Thus, each insulating layer 32 may be an insulating material layer. Insulating materials that may be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., alumina, hafnium oxide, etc.) and their silicates, commonly referred to as high dielectric constant (high k) dielectric oxides, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide.

[0057] The second material of the sacrificial material layer 42 is a sacrificial material that can be selectively removed from the first material of the insulating layer 32. As used herein, the removal of the first material is "selective" for the second material if the removal process removes the first material at a rate at least twice that of the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0058] The sacrificial material layer 42 may comprise an insulating material, a semiconductor material, or a conductive material. A second material of the sacrificial material layer 42 may subsequently be replaced with a conductive electrode, which may serve as a control gate electrode for, for example, a vertical NAND device. Non-limiting examples of the second material include silicon nitride, amorphous semiconductor materials (such as amorphous silicon), and polycrystalline semiconductor materials (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer comprising silicon nitride or a semiconductor material, the semiconductor material comprising at least one of silicon and germanium.

[0059] In one embodiment, the insulating layer 32 may comprise silicon oxide, and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The first material of the insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. A second material may be used to form the sacrificial material layer 42, such as through CVD or atomic layer deposition (ALD).

[0060] The sacrificial material layer 42 can be appropriately patterned so that conductive material portions subsequently formed by replacing the sacrificial material layer 42 can be used as conductive electrodes, such as the control gate electrode of a subsequently formed monolithic three-dimensional NAND string memory device. The sacrificial material layer 42 may include strip-shaped portions extending substantially parallel to the main surface of the substrate (such as surface 7).

[0061] The thickness of the insulating layer 32 and the sacrificial material layer 42 can range from 20 nm to 50 nm, but smaller and larger thicknesses can be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the pairs of insulating layers 32 and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42 can range from 2 to 1,024, and is typically in the range of 8 to 256, but more repetitions can also be used. The top gate electrode and the bottom gate electrode in the stack can be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a substantially uniform thickness within each respective sacrificial material layer 42.

[0062] While this disclosure describes an embodiment in which the spacer material layer is subsequently replaced by the conductive layer as a sacrificial material layer 42, in other embodiments, the sacrificial material layer is formed as a conductive layer. In such embodiments, the step of replacing the spacer material layer with a conductive layer can be omitted.

[0063] Optionally, an insulating cap layer 70 may be formed over the alternating stacks (32, 42). The insulating cap layer 70 comprises a dielectric material different from that of the sacrificial material layer 42. In one embodiment, the insulating cap layer 70 may comprise a dielectric material that can be used for the insulating layer 32 as described above. The insulating cap layer 70 may have a greater thickness than each insulating layer 32. The insulating cap layer 70 may be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer 70 may be a silicon oxide layer.

[0064] An exemplary structure may include: at least one memory array region 100 in which a three-dimensional array of memory elements will subsequently be formed; at least one staircase region 300 in which a stepped surface of alternating stacks (32, 42) will subsequently be formed; and an interconnect region 200 in which interconnect via structures extending through the alternating stacks (32, 42) will subsequently be formed.

[0065] See Figure 3 A stepped surface is formed in the staircase area 300, which is referred to herein as the platform area. As used herein, a “stepped surface” means a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within this volume by removing portions of alternately stacked (32, 42) from the volume through the formation of the stepped surface. A “stepped cavity” refers to a cavity having a stepped surface.

[0066] A platform region is formed in the staircase region 300, which is located between the memory array region 100 and the interconnect region 200. This peripheral device region contains the at least one semiconductor device for peripheral circuitry. The stepped cavity can have various stepped surfaces, such that the horizontal cross-sectional shape of the stepped cavity gradually changes according to the vertical distance from the top surface of the semiconductor material layer 10. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. This set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the cavity depth by one or more levels, and the second type of etching process laterally extending the area to be vertically etched in subsequent first type of etching processes. As used herein, a “level” comprising alternating plurality of structures is defined as the relative position of a pair of first and second material layers within the structure.

[0067] Each sacrificial material layer 42 within the alternating stacks (32, 42), except for the topmost sacrificial material layer 42, extends laterally further than any overlying sacrificial material layer 42 within the alternating stacks (32, 42) in the plateau region. The plateau region comprises stepped surfaces of the alternating stacks (32, 42) that extend continuously from the bottom layer within the alternating stacks (32, 42) to the top layer within the alternating stacks (32, 42).

[0068] Each vertical step of the stepped surface can have one or more pairs of insulating layers 32 and sacrificial material layers at its height. In one embodiment, each vertical step can have a single pair of insulating layers 32 and sacrificial material layers 42 at its height. In another embodiment, multiple “columns” of steps can be formed along a first horizontal direction hd1, such that each vertical step has multiple pairs of insulating layers 32 and sacrificial material layers 42 at its height, and the number of columns can be at least the number of such multiple pairs. Each column of stairs can be vertically offset from each other such that each of the sacrificial material layers 42 has a physically exposed top surface in the corresponding column of stairs. In an exemplary example, two columns of stairs are formed for each block of the memory stack structure to be subsequently formed, such that one column of stairs provides a physically exposed top surface for odd-numbered sacrificial material layers 42 (e.g., counted from the bottom) and the other column of stairs provides a physically exposed top surface for even-numbered sacrificial material layers (e.g., counted from the bottom). A configuration of three, four, or more columns of stairs with a corresponding set of vertical offsets between the physically exposed surfaces of the sacrificial material layers 42 can also be used. Each sacrificial material layer 42 has a greater lateral extent in at least one direction than any covering sacrificial material layer 42, such that each physically exposed surface of any sacrificial material layer 42 has no overhangs. In one embodiment, the vertical steps within each column of stairs may be arranged along a first horizontal direction hd1, and the columns of stairs may be arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1 may be perpendicular to the boundary between the memory array region 100 and the stair region 300.

[0069] A stepped dielectric portion 65 (i.e., an insulating filler portion) can be formed therein by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed, for example, from the top surface of the insulating cap layer 70 by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric portion 65. As used herein, a “stepped” element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases with the vertical distance from the substrate on which the top surface of the element is located. If silicon oxide is used for the stepped dielectric portion 65, the silicon oxide of the stepped dielectric portion 65 may be doped with or may not be doped with dopants such as B, P, and / or F. In one embodiment, the stepped dielectric portion 65 has a gradually increasing lateral extent with increasing vertical distance from the carrier substrate 9.

[0070] Optionally, the drain selection level isolation structure 72 can be formed from a subset of an insulating cap layer 70 and a sacrificial material layer 42 positioned at the drain selection level. The drain selection level isolation structure 72 can be formed, for example, by forming a drain selection level isolation trench and filling the trench with a dielectric material such as silicon oxide. Excess dielectric material can be removed from above the top surface of the insulating cap layer 70.

[0071] refer to Figure 4A and Figure 4B A photolithographic material stack (not shown), including at least a photoresist layer, can be formed over an insulating cap layer 70 and a stepped dielectric portion 65, and can be photolithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the stair region 300. The pattern in the photolithographic material stack can be transferred through the insulating cap layer 70 or the stepped dielectric portion 65 by at least one anisotropic etching using the patterned photolithographic material stack as an etch mask, and through alternating stacks (32, 42). A portion of the alternating stacks (32, 42) below the openings in the patterned photolithographic material stack is etched to form a memory opening 49 and a support opening 19. As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, are subsequently formed. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory opening 49 extends through the integral formation of the alternating stacks (32, 42) in the insulating cap layer 70 and the memory array region 100. The support opening 19 extends through the stepped dielectric material portion 65 and the portion of the alternating stacks (32, 42) located below the stepped surface in the stair region 300.

[0072] Memory opening 49 extends through the entirety of the alternating stack (32, 42). Support opening 19 extends through a subset of layers within the alternating stack (32, 42). The chemical properties of the anisotropic etching process used to etch the material through the alternating stack (32, 42) can be alternately selected to optimize the etching of the first and second materials in the alternating stack (32, 42). The anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of memory opening 49 and support opening 19 can be substantially vertical or can be tapered. The patterned lithographic material stack can then be removed, for example, by ashing.

[0073] The memory opening 49 and the support opening 19 can extend from the top surface of the alternating stack (32, 42) to at least a horizontal plane including the topmost surface of the semiconductor material layer 10. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening 19, over-etching of the semiconductor material layer 10 may optionally be performed. Over-etching may be performed before or after the removal of the photolithography material stack. In other words, the recessed surface of the semiconductor material layer 10 may be vertically offset from the unrecessed top surface of the semiconductor material layer 10 by a recess depth. The recess depth may be in the range of, for example, 1 nm to 50 nm, but smaller and larger depths may also be used. Over-etching is optional and may be omitted. If over-etching is not performed, the bottom surfaces of the memory opening 49 and the support opening 19 may be coplanar with the topmost surface of the semiconductor material layer 10.

[0074] Each of the memory opening 49 and the support opening 19 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 may be formed in the memory array region 100. A two-dimensional array of support openings 19 may be formed in the staircase region 300.

[0075] Figures 5A to 5F The structural change in memory opening 49 is shown, which is Figure 4A and Figure 4B One of the memory openings 49 in the exemplary structure. The same structural variation occurs simultaneously in each of the other memory openings 49 and each support opening 19.

[0076] refer to Figure 5A , showed Figure 4A and Figure 4B The memory opening 49 in the exemplary device structure extends through the insulating cap layer 70, the alternating stacks (32, 42), and optionally into the upper portion of the semiconductor material layer 10. In this processing step, each support opening 19 may extend through a subset of the stepped dielectric material portion 65, the alternating stacks (32, 42), and optionally through the upper portion of the semiconductor material layer 10. The recess depth of the bottom surface of each memory opening relative to the top surface of the semiconductor material layer 10 may range from 0 nm to 30 nm, but larger recess depths may also be used. Optionally, the sacrificial material layer 42 may be partially laterally recessed, for example, by isotropic etching to form a lateral recess (not shown).

[0077] refer to Figure 5B A stack of layers, including a barrier dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel layer 60L, can be sequentially deposited in the memory opening 49.

[0078] The barrier dielectric layer 52 may comprise a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the barrier dielectric layer may comprise a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metallic element and at least oxygen. Subsequently, the dielectric metal oxide layer may serve as a dielectric material portion that blocks the leakage of stored charge to the control gate electrode. In one embodiment, the barrier dielectric layer 52 comprises aluminum oxide. In one embodiment, the barrier dielectric layer 52 may comprise multiple dielectric metal oxide layers with different material compositions. Alternatively or otherwise, the barrier dielectric layer 52 may comprise a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. In one embodiment, the barrier dielectric layer 52 may comprise silicon oxide. The thickness of the barrier dielectric layer 52 may range from 3 nm to 20 nm, but smaller and larger thicknesses may also be used. Alternatively, the barrier dielectric layer 52 may be omitted, and the back-side barrier dielectric layer may be formed after a back-side recess is formed on the surface of the memory film to be subsequently formed.

[0079] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge-trapping material comprising a dielectric charge-trapping material (e.g., silicon nitride). Alternatively, the charge storage layer 54 may comprise a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material), which may be patterned into multiple electrically insulating portions (e.g., floating gates) for example by forming a sacrificial material layer 42 within a lateral recess. In one embodiment, the charge storage layer 54 comprises a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically overlapping sidewalls, and the charge storage layer 54 may be formed as a single continuous layer.

[0080] In another embodiment, the sacrificial material layer 42 may be laterally recessed relative to the sidewalls of the insulating layer 32, and a combination of deposition and anisotropic etching processes may be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. While this disclosure is described using embodiments in which the charge storage layer 54 is a single continuous layer, embodiments in which the charge storage layer 54 is replaced by a plurality of vertically spaced memory material portions (which may be charge-trapping material portions or electrically isolated conductive material portions) are explicitly contemplated herein.

[0081] The charge storage layer 54 can be formed as a single charge storage layer with uniform composition, or it can include a stack of multiple charge storage layers. The thickness of the charge storage layer 54 can be in the range of 2 nm to 20 nm, but smaller and larger thicknesses can also be used.

[0082] The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under appropriate electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer, depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may range from 2 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0083] The optional semiconductor channel layer 60L comprises a semiconductor material, such as at least one elemental semiconductor material, at least one group III-V compound semiconductor material, at least one group II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer 60L comprises amorphous silicon or polycrystalline silicon. The semiconductor channel layer 60L can be formed by conformal deposition methods such as low-pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer 60L can range from 2 nm to 10 nm, but smaller and larger thicknesses can also be used. Memory cavities 49′ exist within the volume of the unfilled deposited material layers (52, 54, 56, 60L) of each memory opening 49.

[0084] refer to Figure 5C If the memory cavity 49' in each memory opening is not completely filled by the semiconductor channel layer 60L, a dielectric core layer 62L can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' in each memory opening. The dielectric core layer 62L comprises a dielectric material such as silicon oxide or organosilicon glass. The dielectric core layer 62L can be deposited by conformal deposition methods such as low-pressure chemical vapor deposition (LPCVD) or by self-planarization deposition processes such as spin coating.

[0085] refer to Figure 5D The dielectric core layer 62L can be selectively recessed relative to the material of the semiconductor channel layer 60L, for example, by recess etching. The material of the dielectric core layer 62L is vertically recessed below a horizontal plane including the top surface of the insulating cap layer 70. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62.

[0086] refer to Figure 5E The horizontal portions of the semiconductor channel layer 60L, tunneling dielectric layer 56, charge storage layer 54, and barrier dielectric layer 52 can be removed from above the top surface of the insulating cap layer 70 using a planarization process. A series of recessed etching processes can be used, which may include at least one anisotropic etching step and / or at least one isotropic etching step. Each remaining portion of the semiconductor channel layer 60L may be integrally positioned within the memory opening 49 or entirely positioned within the support opening 19.

[0087] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60. Current can flow through each vertical semiconductor channel 60 when the vertical NAND device including the vertical semiconductor channel 60 is turned on. Within each memory opening 49, a tunneling dielectric layer 56 is surrounded by a charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent barrier dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 collectively constitutes a memory film 50, which can store charge for a macroscopic retention time. In some embodiments, the barrier dielectric layer 52 may be absent in the memory film 50 at this step, and the barrier dielectric layer may be formed subsequently after the formation of the backside recess. As used herein, macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours. Each combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55.

[0088] refer to Figure 5F The drain region 63 can be formed by depositing doped semiconductor material in each recessed region above the dielectric core 62. The drain region 63 can have a second conductivity type of doping opposite to the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the drain region 63 can be 5.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3 Within the range, but smaller and larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon. Excess portions of the deposited semiconductor material can be removed from the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP) or recess etching, to form the drain region 63.

[0089] Each memory stack structure 55 is a combination of a semiconductor channel, a tunneling dielectric layer, a plurality of memory elements including a portion of a charge storage layer 54, and an optional barrier dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening-filled structure 58. Each combination of the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 constitutes a support pillar structure.

[0090] refer to Figure 6 This illustrates an exemplary structure after a memory opening filling structure 58 and a support pillar structure 20 are formed within the memory opening 49 and support opening 19, respectively. It is possible to... Figure 4A and Figure 4B An instance of a memory opening filling structure 58 is formed within each memory opening 49 of the structure. It can be... Figure 4A and Figure 4B An example of a support pillar structure 20 is formed within each support opening 19 of the structure. The support pillar structure 20 is formed through a region below the stepped surface of the alternating stack (32, 42) and a region above the stepped surface of the stepped dielectric material portion 65. Each support pillar structure 20 includes: a semiconductor material portion (i.e., a vertical semiconductor channel 60 of the support pillar structure 20) having the same composition as the vertical semiconductor channel 60 of the memory opening-fill structure 58; and a dielectric layer stack (i.e., a memory film 50 of the support pillar structure 20) comprising the same set of dielectric material layers as each memory film 50 of the memory opening-fill structure 58. Although this disclosure is described using the illustrated configuration for a memory stack structure, the methods of this disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60.

[0091] refer to Figure 7A and Figure 7B The contact-level dielectric layer 73 can be formed over the alternating stacks (32, 42) of the insulating layer 32 and the sacrificial material layer 42, and over the memory stack structure 55 and the support pillar structure 20. The contact-level dielectric layer 73 comprises a dielectric material different from that of the sacrificial material layer 42. For example, the contact-level dielectric layer 73 may comprise silicon oxide. The contact-level dielectric layer 73 can have a thickness ranging from 50 nm to 500 nm, but smaller and larger thicknesses are also possible.

[0092] A photoresist layer (not shown) may be applied to the contact-level dielectric layer 73 and photolithographically patterned to form openings in regions between clusters of the memory stack structure 55. The pattern in the photoresist layer may be transmitted through the contact-level dielectric layer 73, the alternating stacks (32, 42), and / or the stepped dielectric material portions 65 using anisotropic etching to form a back trench 79 that extends vertically from the top surface of the contact-level dielectric layer 73 to the top surface of the substrate semiconductor material layer 10 and laterally through the memory array region 100 and the stair region 300.

[0093] In one embodiment, the back-side trenches 79 may extend laterally along a first horizontal direction hd1 and may be laterally spaced from each other along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. Memory stack structures 55 may be arranged in rows extending along the first horizontal direction hd1. Drain select hierarchical isolation structures 72 may extend laterally along the first horizontal direction hd1. Each back-side trench 79 may have a uniform width that remains constant along the longitudinal direction (i.e., along the first horizontal direction hd1). Each drain select hierarchical isolation structure 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1, which does not change with translation along the first horizontal direction hd1. Multi-row memory stack structures 55 may be located between adjacent pairs of back-side trenches 79 and drain select hierarchical isolation structures 72, or between adjacent pairs of drain select hierarchical isolation structures 72. In one embodiment, the back-side trenches 79 may include source contact openings, where source contact via structures may subsequently be formed. The photoresist layer can be removed, for example, by ashing.

[0094] refer to Figure 8 An etchant can be introduced into the back-side trench 79, for example, using an etching process. This etchant selectively etches the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32. A back-side recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The second material of the sacrificial material layer 42 can be selectively removed from the first material of the insulating layer 32, the material of the stepped dielectric portion 65, the semiconductor material of the semiconductor material layer 10, and the outermost material of the memory film 50. In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, and the materials of the insulating layer 32 and the stepped dielectric portion 65 may be selected from silicon oxide and dielectric metal oxide.

[0095] The etching process that selectively removes the second material from the outermost layer of the first material and memory film 50 can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process that introduces the etchant in a vapor phase into the back-side trench 79. For example, if the sacrificial material layer 42 comprises silicon nitride, the etching process can be a wet etching process that immerses the exemplary structure in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride against silicon oxide, silicon, and various other materials used in the art. When the back-side recess 43 is present within the volume previously occupied by the sacrificial material layer 42, the support pillar structure 20, the stepped dielectric material portion 65, and the memory stack structure 55 provide structural support.

[0096] Each back-side recess 43 may be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each back-side recess 43 may be greater than the height of the back-side recess 43. Multiple back-side recesses 43 may be formed in a volume of a second material from which the sacrificial material layer 42 is removed. The memory openings forming the memory stack structure 55 are referred to herein as front openings or front cavities, in contrast to the back-side recesses 43. In one embodiment, the memory array region 100 includes a single three-dimensional NAND string array having multiple device levels disposed above the substrate semiconductor material layer 10. In this case, each back-side recess 43 may define space for receiving a corresponding word line of the single three-dimensional NAND string array.

[0097] Each of the plurality of back-side recesses 43 may extend substantially parallel to the top surface of the substrate semiconductor material layer 10. The back-side recesses 43 may be defined perpendicularly by the top surface of the lower insulating layer 32 and the bottom surface of the covering insulating layer 32. In one embodiment, each back-side recess 43 may always have a uniform height.

[0098] refer to Figure 9 Optionally, a back-side barrier dielectric layer 44 may be formed. The back-side barrier dielectric layer 44 (if present) comprises a dielectric material serving as a control gate dielectric for a control gate subsequently formed in the back-side recess 43. The back-side barrier dielectric layer 44 is optional if a barrier dielectric layer 52 is present in each memory opening. The back-side barrier dielectric layer 44 is present even if the barrier dielectric layer 52 is omitted.

[0099] A back-side barrier dielectric layer 44 can be formed in the back-side recess 43 and on the sidewalls of the back-side trench 79. The back-side barrier dielectric layer 44 can be formed directly on the horizontal surface of the insulating layer 32 within the back-side recess 43 and on the sidewalls of the memory stack structure 55. In one embodiment, the back-side barrier dielectric layer 44 can be formed using a conformal deposition process such as atomic layer deposition (ALD). The back-side barrier dielectric layer 44 can be substantially composed of aluminum oxide. The thickness of the back-side barrier dielectric layer 44 can range from 1 nm to 15 nm, such as 2 nm to 6 nm, but smaller and larger thicknesses are also possible.

[0100] At least one metallic material may be deposited in a plurality of back-side recesses 43, on the sidewalls of at least one back-side trench 79, and above the top surface of the contact-level dielectric layer 73. The at least one metallic material may include conductive metal nitride materials (such as TiN, TaN, or WN) and metal-filled materials (such as W, Co, Ru, Ti, and / or Ta). Each metallic material may be deposited using a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof.

[0101] Multiple conductive layers 46 may be formed in multiple back-side recesses 43, and a continuous metal material layer 46L may be formed on the sidewalls of each back-side trench 79 and above the contact-level dielectric layer 73. Each conductive layer 46 includes a portion of a metal barrier layer and a portion of a metal filler layer located between a pair of vertically adjacent dielectric material layers, such as a pair of insulating layers 32. The continuous metal material layer 46L includes a continuous portion of the metal barrier layer and a continuous portion of the metal filler layer located in the back-side trench 79 or above the contact-level dielectric layer 73.

[0102] Each sacrificial material layer 42 can be replaced by a conductive layer 46. A back cavity 79' exists in the portion of each back trench 79 that is not filled with a back barrier dielectric layer 44 and a continuous metallic material layer 46L.

[0103] refer to Figure 10A and Figure 10B The deposited metallic material of the continuous conductive material layer 46L is etched back from the sidewalls of each back trench 79 and from above the contact-level dielectric layer 73, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metallic material in the back recess 43 constitutes the conductive layer 46. Each conductive layer 46 may be a conductive line structure. Therefore, the sacrificial material layer 42 is replaced by the conductive layer 46.

[0104] Each conductive layer 46 can serve as a combination of multiple control gate electrodes located at the same level and word lines electrically interconnected (i.e., electrically connected) to the multiple control gate electrodes located at the same level. The multiple control gate electrodes within each conductive layer 46 are control gate electrodes for vertical memory devices including the memory stack structure 55. In other words, each conductive layer 46 can serve as a word line serving as a common control gate electrode for multiple vertical memory devices.

[0105] In one embodiment, the removal of the continuous conductive material layer 46L may be selective for the material of the back-side barrier dielectric layer 44. In this case, a horizontal portion of the back-side barrier dielectric layer 44 may be present at the bottom of each back-side trench 79. In another embodiment, the removal of the continuous conductive material layer 46L may be non-selective for the material of the back-side barrier dielectric layer 44, or the back-side barrier dielectric layer 44 may be omitted. A back-side cavity 79′ is present within each back-side trench 79.

[0106] refer to Figure 11 Dielectric wall structures 76 can be formed within each back-side cavity 79' by depositing at least one dielectric material in the remaining unfilled volume of the back-side trench 79 (i.e., back-side cavity 79'). The at least one dielectric material may include silicon oxide, silicon nitride, dielectric metal oxide, organosilicon glass, or combinations thereof. In one embodiment, the insulating material layer may include silicon oxide. The at least one dielectric material may be deposited, for example, by low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). Optionally, a contact-level dielectric layer 73 may be used as a stop layer to planarize the at least one dielectric material. If a chemical mechanical planarization (CMP) process is used, the contact-level dielectric layer 73 may be used as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the back-side trench 79 constitutes a dielectric wall structure 76. The dielectric wall structure 76 may be formed between alternating stacks (32, 46) of each adjacent pair of insulating and conductive layers.

[0107] refer to Figure 12A and Figure 12B Additional contact via structures (88, 86, 8P) may be formed through the contact-level dielectric layer 73 and optionally through the stepped dielectric portion 65. For example, a drain contact via structure 88 may be formed through the contact-level dielectric layer 73 on each drain region 63. A word line contact via structure 86 may be formed on the conductive layer 46 through the contact-level dielectric layer 73 and through the stepped dielectric portion 65. A through-hole structure 8P may be formed to the semiconductor material layer 10 through the stepped dielectric portion 65.

[0108] See Figure 13A and Figure 13BA via-level dielectric layer 80 is formed above the contact-level dielectric layer 73. Various contact via structures (198, 196, 194) can be formed through the via-level dielectric layer 80. For example, a bit line connection via structure 198 can be formed on the drain contact via structure 88, a word line connection via structure 196 can be formed on the word line contact via structure 86, and a peripheral extension via structure 194 can be formed on the through via structure 8P.

[0109] A first-line level dielectric layer 90 is deposited above the via level dielectric layer 80. Various metal line structures (98, 96, 94) are formed in the first-line level dielectric layer 90. The metal line structures (98, 96, 94) are referred to herein as first-line level metal interconnect structures. The various metal line structures (98, 96, 94) include bit lines 98 electrically connected to corresponding plurality of drain contact via structures 88 (e.g., via bit lines connecting via structures 198), word line connection metal interconnects 98 electrically connected to a corresponding one of word line contact via structures 86 (e.g., via bit lines connecting via structures 198), and peripheral metal interconnects 94 electrically connected to a corresponding one of through via structures 8P (e.g., via peripheral extension via structures 194).

[0110] Bit line 98 is electrically connected to the upper end of a corresponding subset of vertical semiconductor channels 60 in the memory stack structure 55 in the memory array region 100. In one embodiment, the memory stack structure 55 is arranged as a row extending along a first horizontal direction hd1, and bit line 98 extends laterally along a second horizontal direction hd2.

[0111] refer to Figure 14 Through the Figure 13A and Figure 13BThe exemplary structure performs additional processing steps to provide a memory die 1000. Specifically, an additional metal interconnect structure 168 is formed, including an additional interconnect level dielectric layer 160. In an exemplary example, the additional interconnect level dielectric layer 160 may include a via level dielectric layer 110, a second line level dielectric layer 120, a second via level dielectric layer 130, and a metal pad structure level dielectric layer 140. The metal interconnect structure 168 may include: a first metal via structure 108 included in the first via level dielectric layer 110; a second metal line structure 118 included in the second line level dielectric layer 120; a second metal via structure 128 included in the second via level dielectric layer 130; and a first bonding structure 178 (such as a metal pad structure) included in the metal pad structure level dielectric layer 140. While this disclosure has been described using examples in which the additional interconnect-level dielectric layer 160 includes a first via-level dielectric layer 110, a second line-level dielectric layer 120, a second via-level dielectric layer 130, and a metal pad structure-level dielectric layer 140, embodiments in which the additional interconnect-level dielectric layer 160 includes different numbers and / or different combinations of dielectric material layers are explicitly contemplated herein. The memory die 1000 includes a three-dimensional array of memory elements. Electrical connection paths may be provided by each combination of a first bonding structure 178 and a set of metal interconnect structures {(194, 94, 108, 118, 128), (196, 96, 108, 118, 128), or (198, 98, 108, 118, 128)}.

[0112] refer to Figure 15A second semiconductor die may be provided, which may be a logic die 700 comprising various semiconductor devices 710. Semiconductor device 710 includes peripheral circuitry for operating a three-dimensional memory array in memory die 1000. This peripheral circuitry may include: word line drivers for driving conductive layers 46 within memory die 1000; bit line drivers for driving bit lines 98 within memory die 1000; word line decoder circuitry for decoding addresses of conductive layers 46; bit line decoder circuitry for decoding addresses of bit lines 98; sense amplifier circuitry for sensing the state of memory elements within a memory stack structure 55 in memory die 1000; power supply / distribution circuitry for supplying power to memory die 1000; data buffers and / or latches and / or any other semiconductor circuitry that may be used to operate the array of memory stack structures 55 in memory die 1000. Logic die 700 may include a logic die substrate 708, which may be a semiconductor substrate. The substrate may include a substrate semiconductor layer 709. The substrate semiconductor layer 709 may be a semiconductor wafer or a semiconductor material layer, and may include at least one elemental semiconductor material (e.g., a single-crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art.

[0113] A shallow trench isolation structure 720 may be formed in the upper portion of the substrate semiconductor layer 709 to provide electrical isolation for semiconductor devices in a sense amplifier circuit. Various semiconductor devices 710 may include field-effect transistors (FETs) comprising corresponding transistor active regions 742 (i.e., source and drain regions), a channel 746, and a gate structure 750. The FETs may be arranged in a CMOS configuration. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. For example, semiconductor device 710 may include a word line driver for electrically biasing word lines of a memory die 1000, the word line driver including a conductive layer 46.

[0114] A dielectric material layer is formed over the semiconductor device 710, and this dielectric material layer is referred to herein as the logic-side dielectric layer 760. Optionally, a dielectric pad 762 (such as a silicon nitride pad) may be formed to apply mechanical stress to various field-effect transistors and / or prevent hydrogen or impurities from diffusing from the logic-side dielectric layer 760 into the semiconductor device 710. A logic-side metal interconnect structure 780 is included within the logic-side dielectric layer 760. The logic-side metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes of corresponding source and drain nodes of contact devices or gate electrode contacts), interconnect-level metal line structures 784, interconnect-level metal via structures 786, and second bonding structures 788 (such as metal pad structures) that may be configured to serve as bonding pads.

[0115] The logic die 700 may include a back-side insulating layer 714 located on the back-side surface of the logic die substrate 708. Laterally insulating through-substrate via structures (711, 712) may be formed through the logic die substrate 708 to provide electrical contact with various input and output nodes of peripheral circuitry. Each laterally insulating through-substrate via structure (711, 712) includes a through-substrate conductive via structure 712 and a tubular insulating liner 711 laterally surrounding the through-substrate conductive via structure 712. Back-side bonding pads 716 may be formed on surface portions of the laterally insulating through-substrate via structures (711, 712). Generally, a semiconductor die is provided comprising a semiconductor device 710 located on a semiconductor substrate (such as a substrate semiconductor layer 709). A second bonding structure 788 covers and is electrically connected to the semiconductor device 710, and the laterally insulating through-substrate via structures (711, 712) may extend through the semiconductor substrate.

[0116] refer to Figure 16 The memory die 1000 and logic die 700 are positioned such that the second bonding structure 788 of the logic die 700 faces the first bonding structure 178 of the memory die 1000. In one embodiment, the memory die 1000 and logic die 700 may be designed such that the pattern of the second bonding structure 788 of the logic die 700 is a mirror image of the pattern of the first bonding structure 178 of the memory die 1000. The memory die 1000 and logic die 700 may be bonded to each other by a metal-to-metal bond. Alternatively, an array of solder material portions may be used to bond the memory die 1000 and logic die 700 by an array of solder material portions (such as solder balls).

[0117] In the case of metal-to-metal bonding, the face-to-face contacts of the first bonding structure 178 of the memory die 1000 and the second bonding structure 788 of the logic die 700 can be in direct contact with each other and can be subjected to elevated temperatures to induce material diffusion across the interface between adjacent pairs of metal pad structures (178, 788). This interdiffusion of metallic material can induce bonding between each adjacent pair of metal pad structures (178, 788). Furthermore, the logic-side dielectric layer 760 and the interconnect-level dielectric layer 160 can include dielectric materials (such as silicate glass) that can be bonded to each other. In this case, the physically exposed surfaces of the logic-side dielectric layer 760 and the interconnect-level dielectric layer 160 can be in direct contact with each other and can be subjected to thermal annealing to provide additional bonding.

[0118] When using an array of solder material portions to provide bonding between memory die 1000 and logic die 700, solder material portions (such as solder balls) can be applied to each of the first bonding structures 178 of memory die 1000, and / or to each of the second bonding structures 788 of logic die 700. Memory die 1000 and logic die 700 can be bonded to each other by reflowing the solder material portions through the array of solder material portions, with each solder material portion contacted by a corresponding pair of the first bonding structures 178 of memory die 1000 and the second bonding structures 788 of logic die 700.

[0119] Generally, the logic die 700 can be bonded to the memory die 1000. The memory die 1000 includes an array of memory stack structures 55, and the logic die 700 includes complementary metal-oxide-semiconductor (CMOS) circuitry, which includes peripheral circuitry electrically coupled to nodes of the array of memory stack structures 55 via subsets of metal interconnect structures 168 included within the memory die 1000. The memory die 1000 includes a semiconductor material layer 10 and is attached to a carrier substrate 9.

[0120] refer to Figure 17The carrier substrate 9 can be removed from above the semiconductor material layer 10. For example, if the carrier substrate 9 comprises a body portion of a semiconductor wafer, a back-side grinding process can be performed to remove the carrier substrate 9. If the carrier substrate 9 comprises a material different from the semiconductor material layer 10, a suitable separation method can be used to separate the carrier substrate 9 from the semiconductor material layer 10. In one embodiment, the carrier substrate 9 can be attached to the semiconductor material layer 10 by a sacrificial separation material layer, which is isotropically etched (e.g., using a wet etching process) to cause separation of the carrier substrate 9 from the semiconductor material layer 10. In one embodiment, the sacrificial separation material layer may comprise silicon nitride, and the removal of the sacrificial separation material layer can be performed by a wet etching process using thermal phosphoric acid. When the carrier substrate 9 is removed, the back-side surface of the semiconductor material layer 10 can be physically exposed.

[0121] refer to Figure 18 and Figure 19A The semiconductor material layer 10 can be removed. In one embodiment, the removal of the semiconductor material layer 10 can be performed by chemical mechanical planarization (CMP) using the farthest insulating layer in the insulating layer 32 and the stepped dielectric material portion 65 as a stop structure. When the semiconductor material layer 10 is removed, the farthest end of each vertical semiconductor channel in the vertical semiconductor channel 60 is physically exposed. When the semiconductor material layer 10 is removed, the farthest insulating layer in the insulating layer 32 within the alternating stack (32, 46) (i.e., in Figure 2 In the processing steps, the flat surface of the bottom insulating layer 32, which is directly formed on the semiconductor material layer 10, is physically exposed. When the semiconductor material layer 10 is removed, the flat surface of the stepped dielectric material portion 65 is physically exposed. During the CMP process, the portion of the memory stack structure 55 that protrudes through the horizontal plane HP, which includes the flat surface of the farthest insulating layer in the insulating layer 32, is removed.

[0122] refer to Figure 19BThe physically exposed surface of the dielectric core 62 can be selectively vertically recessed for the semiconductor material of the vertical semiconductor channel 60. An isotropic etching process can be performed that selectively etches the material of the dielectric core 62 for the semiconductor material of the vertical semiconductor channel 60 to cause the dielectric core 62 to be vertically recessed. For example, wet etching using diluted hydrofluoric acid can be used to selectively cause the distal flat surface of the dielectric core 62 to be vertically recessed for the annular distal surface of the vertical semiconductor channel 60, the distal flat surface of the dielectric core being located within a horizontal plane HP including the annular distal surface of the vertical semiconductor channel 60. The vertical recess of the dielectric core 62 increases the area of ​​the physically exposed surface of the vertical semiconductor channel 60, thereby reducing the contact resistance between the vertical semiconductor channel 60 and the source layer subsequently formed thereon. In one embodiment, the dielectric core 62 may comprise a dielectric material having a greater etch rate than the dielectric material of the insulating layer 32. For example, the dielectric core 62 may comprise borosilicate glass, borosilicate glass, or organosilicon glass, and the insulating layer 32 may comprise dense, undoped silicate glass. In one embodiment, the physically exposed surface of the insulating layer 32 (which is furthest from the interface between the memory die 1000 and the logic die 700 and closest to the subsequently formed source layer) may incidentally be recessed during the recessing of the physically exposed flat surface of the dielectric core 62. The distal surface of the through-hole structure 8P may be physically exposed.

[0123] refer to Figure 19C and Figure 20 The doped semiconductor material layer 18L can be directly deposited on the physically exposed surface of the vertical semiconductor channel 60, the physically exposed surface of one of the insulating layers 32, and the physically exposed flat surface of the stepped dielectric material portion 65. The doped semiconductor material layer 18L may include a conductive semiconductor material (i.e., a heavily doped semiconductor material) doped with a second conductivity type (i.e., the opposite of the first conductivity type). Therefore, the doped semiconductor material layer 18L may include a conductivity greater than 1.0 × 10⁻⁶. 5 The doped semiconductor material has a conductivity of S / cm. The thickness of the doped semiconductor material layer 18L can range from 100 nm to 1,000 nm, but smaller and larger thicknesses are also possible. The vertically projecting portion 18P of the doped semiconductor material layer 18L projectes vertically across a horizontal plane including the annular top surface of the vertical semiconductor channel 60 toward a corresponding dielectric core in the dielectric core 62 and contacts that corresponding dielectric core in the dielectric core 62.

[0124] refer to Figure 21The doped semiconductor material layer 18L can be patterned into a source layer 18, for example, using a combination of photolithography and etching processes. The photolithographically patterned photoresist layer can cover only the portion of the doped semiconductor material layer 18L located within the memory array region. An etching process can be used to remove the portion of the doped semiconductor material layer 18L not covered by the patterned photoresist layer. The photoresist layer can be removed, for example, by ashing. The source layer 18 is formed directly on the distal end of each vertical semiconductor channel 60 within the memory aperture filling structure 58 and does not contact any vertical semiconductor channel 60 within the support pillar structure 20. The lateral extent of the source layer 18 can be limited within the memory region 100. The source layer 18 includes a shape greater than 1.0 × 10⁻⁶. 5 A doped semiconductor material with a conductivity of S / cm. Optionally, a dielectric passivation layer (not shown) may be formed over alternating stacks (32, 46), a stepped dielectric material portion 65, and a source layer 18.

[0125] Various bonding pads (14, 16) may be formed on the source layer 18 and the via structure 8P. The bonding pads (14, 16) may include at least one source bonding pad 14 formed directly on the back side of the source layer 18, and a back bonding pad 16 formed directly on the distal surface of the via structure 8P. Bond lines 15 may be bonded to a corresponding one of the bonding pads (14, 16). Back bonding lines 715 may be bonded to each back bonding pad 716.

[0126] Figures 22A to 22C An alternative configuration for the memory opening-filling structure during the formation of source layer 18 is shown, which can be used instead of Figures 19A to 19C , Figure 20 and Figure 21 The processing steps.

[0127] refer to Figure 22AThe semiconductor material layer 10 can be removed by a recess etching process, which may include a wet etching process or a dry etching process. In this case, the removal of the semiconductor material layer 10 may be selective in terms of the materials of the insulating layer 32, the stepped dielectric portion 65, and the memory film 50. For example, a wet etching process using KOH or NaOH may be used to remove the semiconductor material layer 10. The distal flat surface of the alternatingly stacked (32, 46) insulating layer 32, the flat distal surface of the stepped dielectric portion 65, and the distal outer surface of the memory film 50 may be physically exposed when the semiconductor material layer 10 is removed. During the removal of the semiconductor material layer 10, the memory film 50 may be used as an etch-blocking material portion. In one embodiment, the vertical semiconductor channel 60 may be covered by a cap portion of the memory film 50 on the distal side of the bonding assembly, above the physically exposed surface of the distal insulating layer in the insulating layer 32. The memory film 50 may be substantially intact or may be partially damaged, for example, by thinning of the outer layers (such as the blocking dielectric layer 52 and / or the charge storage layer 54).

[0128] refer to Figure 22B A series of isotropic etching processes can be performed to remove physically exposed portions of the memory film 50. The surface of the distal portion of each vertical semiconductor channel 60 can be physically exposed after a series of isotropic etching processes. The outer sidewall of each vertical semiconductor channel 60 can project vertically outward from a horizontal plane including the physically exposed surface of the insulating layer 32.

[0129] refer to Figure 22C Executable Figure 19C , Figure 20 and Figure 21 The processing steps are to form a source layer 18, which contacts the outer wall of the vertical semiconductor channel within the memory opening filling structure 58.

[0130] Referring to all the accompanying drawings and various embodiments of this disclosure, a three-dimensional memory device is provided, comprising a memory die 1000 bonded to a logic die 700. The memory die 1000 includes: alternating stacks of insulating layers 32 and conductive layers 46; memory stack structures 55 extending through the alternating stacks (32, 46), wherein each memory stack structure 55 includes a corresponding vertical semiconductor channel 60 and a corresponding memory film 50; a drain region 63 located at a first end (e.g., a proximal end) of a corresponding vertical semiconductor channel 60; and a source layer 18 having a first surface (e.g., facing...). Figure 21The vertical semiconductor channel 60 and logic die 700 are shown with a bottom surface and a second surface (e.g., a top surface) opposite the first surface. The first surface is located at the second end (e.g., the distal end) of each vertical semiconductor channel 60. The first end (e.g., the proximal end) of each vertical semiconductor channel 60 is closer to the logic die 700 than the second end (e.g., the distal end) of each vertical semiconductor channel 60. The semiconductor wafer 9 (such as a silicon wafer) is not located on the second surface of the source layer 18 (e.g., the bottom surface). Figure 21 Above the top surface of the source layer 18. In other words, there is no carrier substrate 9 (e.g., silicon wafer or any other type of substrate) on which the vertical semiconductor channel 60 was originally grown.

[0131] In one embodiment, the source layer 18 and the drain region 63 comprise respective doped semiconductor materials having a doped semiconductor material having a density greater than 1.0 × 10⁻⁶. 5 The conductivity is S / cm and it is doped with the same type of conductivity (such as a second type of conductivity, e.g., n-type).

[0132] In one embodiment, the first surface of the source layer 18 contacts the flat surface of the nearest insulating layer (i.e., the farthest insulating layer 32 from the interface between the memory die 1000 and the logic die 700) in the alternating stack (32, 46).

[0133] In one embodiment, the alternating stack (32, 46) includes a stepped surface that extends continuously from the nearest insulating layer in the insulating layer 32 within the alternating stack to the farthest insulating layer in the insulating layer 32, which is the insulating layer farthest from the source layer 18 among all the insulating layers in the alternating stack (32, 46); and the memory die 1000 includes a stepped dielectric portion 65 that contacts the stepped surface and has a progressively increasing lateral extent LE (e.g., ...) that increases with a vertical distance VD from a horizontal plane HP comprising the interface between the source layer 18 and the nearest insulating layer in the insulating layer 32. Figure 21 (As shown).

[0134] In one embodiment, the memory die 1000 includes a support pillar structure 20 that extends vertically through regions of alternating stacks (32, 46) located below or above a stepped surface and regions of stepped dielectric material portions 65 located above or below a stepped surface; and each support pillar structure 20 includes: a first semiconductor material portion having the same composition as the vertical semiconductor channel 60 (of the memory opening-fill structure 58) (i.e., the vertical semiconductor channel 60 within the support pillar structure 20); a second semiconductor material portion having the same composition as the drain region 63 (of the memory opening-fill structure 58) (i.e., the drain region 63 within the support pillar structure 20); and a dielectric layer stack containing the same set of dielectric material layers as each memory film 50 (of the memory opening-fill structure 58) (i.e., the memory film 50 within the support pillar structure 20).

[0135] In one embodiment, each of the memory stack structure 55 and the support pillar structure 20 includes a corresponding horizontal surface that lies entirely within a horizontal plane including the horizontal interface between the source layer 18 and the vertical semiconductor channel 60; and the memory stack structure and the support pillar structure do not extend through the horizontal plane including the horizontal interface between the source layer and the vertical semiconductor channel 60.

[0136] In one embodiment, the source layer 18 does not contact any of the support pillar structures in the support pillar structure 20; and the source layer 18 includes a vertical protrusion 18P that protrudes through a horizontal plane including the horizontal interface between the source layer 18 and the vertical semiconductor channel 60, and contacts the sidewall of the vertical semiconductor channel 60.

[0137] In one embodiment, the three-dimensional memory device includes: a bonding pad 14 that contacts a second surface of a source layer 18; a through-hole structure 8P extending vertically through a stepped dielectric material portion 65; and an additional bonding pad 16 that contacts a corresponding through-hole structure in the through-hole structure 8P.

[0138] In one embodiment, the horizontal surface of the stepped dielectric material portion 65 lies in a horizontal plane within the interface between the nearest side insulating layer of the source layer 18 and the insulating layer 32, and the additional bonding pad 16 contacts a corresponding annular portion of the horizontal surface of the stepped dielectric material portion 65; and the bonding pad 14 that contacts the source layer 18 is vertically offset from the thickness of the source layer 18 from the additional bonding pad.

[0139] In one embodiment, the three-dimensional memory device includes: a bonding line 15 bonded to a bonding pad 14 of a contact source layer 18; and an additional bonding line 15 bonded to a corresponding additional bonding pad in an additional bonding pad 16.

[0140] In one embodiment, the memory die 1000 includes a first bonding structure 178 that is farther from a horizontal plane including the interface between the source layer 18 and the vertical semiconductor channel 60 than the drain region 63 is from the horizontal plane; the logic die 700 includes a second bonding structure 788; and the second bonding structure 788 is bonded to the first bonding structure 178.

[0141] In one embodiment, memory die 1000 includes a two-dimensional array of vertical NAND strings forming a three-dimensional array of memory elements; and logic die 700 includes peripheral circuitry supporting the operation of the three-dimensional array of memory elements.

[0142] In one embodiment, the three-dimensional memory device includes: laterally insulating through-substrate via structures (711, 712) that extend vertically through the substrate 709 of a logic die 700 and are electrically connected to a corresponding node of a peripheral circuit semiconductor device 710 located on the logic die 700; and a back-side bonding pad 716 that contacts a corresponding laterally insulating through-substrate via structure (711, 712) and is vertically spaced from the semiconductor device 710 by the substrate 709 of the logic die 700.

[0143] The source layer 18 according to various embodiments of the present disclosure provides electrical contact with each distal end of the vertical semiconductor channel 60 without any substitution of material through the narrow trench. Furthermore, the source layer 18 may contact the inner or outer sidewall of the distal end of the vertical semiconductor channel 60, thereby providing low contact resistance between the vertical semiconductor channel 60 and the source layer 18. Therefore, reduced process complexity and enhanced electrical contact between the vertical semiconductor channel 60 and the source layer 18 can be achieved through the methods and structures of various embodiments of the present disclosure.

[0144] Figures 23A to 23O This is a sequential vertical cross-sectional view of a first alternative configuration of the bonding assembly (700, 1000) during various processing steps up to the formation of the back-side bonding pad 16, according to a second embodiment of the present disclosure.

[0145] refer to Figure 23A A portion of the joining assembly (700, 1000) corresponds to Figure 18 The processing steps are shown in the diagram. Figure 23AThe first alternative configuration (700, 1000) of the joining assembly shown can be based on Figure 18 The bonding components (700, 1000) modify the memory die 1000 to derive this. Specifically, the memory die 1000 can be modified to add a vertical stack of sacrificial silicon oxide pads 102 and sacrificial silicon nitride pads 104 between the alternating stacks of semiconductor material layer 10 and insulating layer 32 and conductive layer 46. Specifically, the sacrificial silicon oxide pads 102 can be formed directly on... Figure 1 The semiconductor material layer 10 is on the top surface of the semiconductor material layer 10, and the sacrificial silicon nitride pad 104 can be formed directly on the top surface of the sacrificial silicon oxide pad 102. Figure 2 The alternating stacking of insulating layer 32 and sacrificial material layer 42 shown can be formed on the top surface of sacrificial silicon nitride pad 104. The thickness of sacrificial silicon oxide pad 102 can be in the range of 3 nm to 60 nm, such as in the range of 6 nm to 30 nm. The thickness of sacrificial silicon nitride pad 104 can be in the range of 3 nm to 60 nm, such as in the range of 6 nm to 30 nm. Although this disclosure has been described with an embodiment in which sacrificial silicon oxide pad 102 and sacrificial silicon nitride pad 104 are present, embodiments in which sacrificial silicon oxide pad 102 and / or sacrificial silicon nitride pad 104 are expressly contemplated.

[0146] Generally, the memory die 1000 includes a carrier substrate 9. The carrier substrate 9 may be a commercially available semiconductor substrate (such as a silicon wafer) providing a semiconductor material layer 10. When the carrier substrate 9 is a semiconductor substrate, the semiconductor material layer 10 may be formed on the carrier substrate 9, or may be an upper portion of the carrier substrate 9. The memory die 1000 includes: a memory stack structure 55 extending vertically through alternating stacks of insulating layer 32 and conductive layer 46; a dielectric material portion 65 contacting the sidewalls (32, 46) of the alternating stacks; and a through-hole structure 8P extending vertically through the dielectric material portion 65. Each memory stack structure in the memory stack structure 55 includes a corresponding vertical semiconductor channel 60 and a corresponding memory film 50. In one embodiment, the through-hole structure 8P may have a vertical range greater than the vertical thickness of the alternating stacks (32, 46) and may extend vertically through the dielectric material portion 65. The memory die 1000 may include a first bonding structure 178 electrically connected to the memory stack structure 55 and the conductive layer 46.

[0147] A logic die 700 is provided, which includes a semiconductor device 710 and a second bonding structure 788. The second bonding structure 788 is electrically connected to the semiconductor device 710. In one embodiment, the semiconductor device 710 in the logic die 700 includes peripheral circuitry configured to operate memory elements in a memory stack structure 55 and drive a conductive layer 46. When a carrier substrate 9 is attached to a memory die 1000, the logic die 700 can be attached to the memory die 1000 by bonding the second bonding structure 788 to a first bonding structure 178. A semiconductor structure (i.e., a bonding assembly) is provided, which includes a memory die 1000 bonded to the logic die 700. After the logic die 700 is attached to the memory die 1000, the carrier substrate 9 can be decoupled from the memory die 1000.

[0148] Subsequently, the semiconductor material layer 10 can be selectively removed from the sacrificial silicon oxide pad 102. For example, in the case where the semiconductor material layer 10 contains silicon, a wet etching process can be used to selectively remove the semiconductor material layer 10 from the sacrificial silicon oxide pad 102, employing a KOH solution, a thermally heated trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) solution, and / or a tetramethylammonium hydroxide (TMAH) solution. Therefore, it is possible to provide... Figure 23A The structure is shown in the figure. In this case, the semiconductor material layer 10 can be selectively removed from the dielectric material of the memory film 50. Therefore, the portion of the memory film 50 embedded in the semiconductor material layer 10 before the semiconductor material layer 10 is removed will not be removed by the etching process that removes the semiconductor material layer.

[0149] In some embodiments, the end portions of the dielectric wall structure 76 may be embedded in the semiconductor material layer 10 before the semiconductor material layer 10 is removed. The etching process for removing the semiconductor material layer 10 may be selective for the dielectric wall structure 76.

[0150] The via structure 8P may include a pad-connected via structure 8P1 for providing electrical connection to subsequently formed bonding pads. Additionally, the via structure 8P may include a source-connected via structure 8P2 for providing electrical connection to subsequently formed buried source layers. Each of the pad-connected via structure 8P1 and the source-connected via structure 8P2 may include a metal barrier layer 82 and a conductive via-fill material portion 84. The metal barrier layer contains a conductive metal barrier material (such as TiN, TaN, and / or WN, or a combination of TiN and titanium layers), and the conductive via-fill material portion contains a conductive via-fill material (such as W, Cu, Mo, Ru, Co, and / or heavily doped semiconductor materials). After removing the carrier substrate 9 and the semiconductor material layer 10, the distal end of each via structure 8P may be physically exposed. As used herein, the end of the structure near the interface between memory die 1000 and logic die 700 is referred to as the proximal end, and the end of the structure far from the interface between memory die 1000 and logic die 700 is referred to as the distal end.

[0151] refer to Figure 23B The sacrificial silicon oxide pad 102 can be removed by performing isotropic etching using diluted hydrofluoric acid. In the case where the outermost layer of each memory film 50 includes a barrier dielectric layer 52 containing silicon oxide, the portion of each barrier dielectric layer 52 protruding from the physically exposed surface of the sacrificial silicon nitride pad 104 can be etched in parallel during the removal of the sacrificial silicon oxide pad 102.

[0152] refer to Figure 23C The sacrificial silicon nitride pad 104 can be removed by performing isotropic etching using thermal phosphoric acid. In cases where the charge storage layer 54 of each memory film 50 contains silicon nitride, portions of each charge storage layer 54 protruding from the physically exposed surface of the insulating layer 32 (farthest from the bonding interface between the memory die 1000 and the logic die 700) can be etched in parallel during the removal of the sacrificial silicon nitride pad 104. Subsequently, an additional selective etching process (e.g., chemical dry etching, or "CDE") can be performed to isotropically etch the physically exposed portions of the tunneling dielectric layer 56. Thus, the physically exposed portions of the memory film 50 are removed, and the outer sidewalls of the vertical semiconductor channels 60 are physically exposed. The distal ends of each vertical semiconductor channel 60 are physically exposed.

[0153] After the distal surface of the vertical semiconductor channel 60 is physically exposed, the distal surface of the memory film 50 may lie in a horizontal plane within the horizontal plane of the physically exposed horizontal surface of the distal insulating layer 32, which comprises alternating stacks of insulating layer 32 and conductive layer 46, or may be recessed relative to the physically exposed horizontal surface of the distal insulating layer 32 of the alternating stacks (32, 46) toward the bonding interface between the memory die 1000 and the logic die 700. The recess depth may be in the range of 0 nm to 60 nm, such as in the range of 0 nm to 30 nm.

[0154] refer to Figure 23D A dopant of a second conductivity type can be optionally implanted into the physically exposed portion of the vertical semiconductor channel 60 by performing an ion implantation process (represented by "I / I"). The physically exposed region of the distal portion of each vertical semiconductor channel 60 can be converted into a doped semiconductor region with dopant of the second conductivity type, referred to herein as source cap region 606. A pn ​​junction can be formed at each interface between the source cap region 606 and the adjacent vertical semiconductor channel 60.

[0155] refer to Figure 23E A first conductive material can be deposited on the physically exposed surface of the memory die 1000 on its distal side (i.e., the back side). For example, a sequentially doped semiconductor material layer 218L can be deposited on the physically exposed surfaces of the source cap region 606, the pad-to-through-hole structure 8P1, and the source-to-through-hole structure 8P2. The sequentially doped semiconductor material layer 218L can have a second conductivity type of doping, i.e., the same conductivity type as the source cap region 606. In one embodiment, the sequentially doped semiconductor material layer 218L may comprise doped polysilicon with an atomic concentration of 1.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3 The dopant can be of a second conductivity type within the range, but smaller and larger dopant concentrations are also possible. The thickness of the continuously doped semiconductor material layer 218L above the flat surface of the dielectric material portion 65 can be in the range of 50 nm to 600 nm, such as in the range of 100 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0156] In one embodiment, a continuously doped semiconductor material layer 218L can be formed by depositing an amorphous silicon dioxide layer. The amorphous silicon dioxide layer can be doped in situ during deposition, or it can be undoped at the time of deposition, and then doped by ion implantation after deposition. After deposition, the amorphous silicon dioxide layer is converted into a polycrystalline silicon layer by crystallization using any suitable crystallization annealing process, such as laser annealing, flash annealing, annealing in a sufficiently long gas environment, spike annealing, etc. In another embodiment, a continuously doped semiconductor material layer 218L can be formed by depositing a polycrystalline silicon layer. The polycrystalline silicon layer can be doped in situ during deposition, or it can be undoped at the time of deposition, and then doped by ion implantation after deposition. If the continuously doped semiconductor material layer 218L is doped by ion implantation, the implanted ions can be activated by any suitable dopant activation annealing process, such as laser annealing, flash annealing, annealing in a sufficiently long gas environment, spike annealing, etc.

[0157] refer to Figure 23F A photoresist layer (not shown) may be applied over a continuously doped semiconductor material layer 218L and may be photolithographically patterned to cover multiple discrete regions. In one embodiment, the photoresist layer may continuously cover the corresponding source connection via structures configured to electrically bias a vertical semiconductor channel 60 within a set of memory aperture fill structures 58 and source connection via structures 8P2. In one embodiment, the photoresist layer does not cover the pad connection via structure 8P1 or the dielectric wall structure 76.

[0158] A photoresist layer can be used as an etching mask layer to perform the etching process. The etching process may include anisotropic etching or isotropic etching. The etching process etches the unmasked portions of the continuously doped semiconductor material layer 218L. The patterned portions of the continuously doped semiconductor material layer 218L include at least one doped semiconductor material layer 218. Each doped semiconductor material layer 218 acts as a source layer that electrically connects a corresponding set of source cap regions 606 to a corresponding source connection via structure 8P2. Alternatively, in the absence of an etching mask layer, the etching process may be performed in a manner that is not explicitly masked. Figure 23D In the absence of a source cap region 606, each doped semiconductor material layer 218 acts as a source layer electrically connecting a corresponding set of distal end portions of the vertical semiconductor channel 60 to a corresponding source connection via structure 8P2. Generally, the source layer including the doped semiconductor material layer 218 can be formed by depositing doped semiconductor material on the distal end of each vertical semiconductor channel 60 and by patterning the doped semiconductor material.

[0159] Generally, when implanting a dopant of the second conductivity type, a source layer (such as a doped semiconductor material layer 218), which contains a first conductive material, is formed directly on the semiconductor material at the distal end of each vertical semiconductor channel 60. This source layer may include a source cap region 606. The first conductive material can be patterned to form a first conductive material layer, such as the doped semiconductor material layer 218, which contacts the semiconductor material at the distal end of each vertical semiconductor channel 60. The vertical semiconductor channel 60 may contain semiconductor material doped with a first conductivity type, and the first conductive material may contain doped semiconductor material doped with a second conductivity type opposite to the first conductivity type.

[0160] In one embodiment, the interface between the semiconductor material of the vertical semiconductor channel 60 and the source layer (including the doped semiconductor material layer 218) protrudes from the horizontal plane including the horizontal interface between the source layer and the alternating stack (32, 46) in a vertical direction pointing away from the interface between the logic die 700 and the memory die 1000. For example, the interface between the source cap region 606 and the source layer (including the doped semiconductor material layer 218) may be farther from the bonding interface between the logic die 700 and the memory die 1000 than the horizontal plane including the horizontal interface between the source layer and the alternating stack (32, 46).

[0161] The source layer (including the doped semiconductor material layer 218) is electrically connected to the end portion of the vertical semiconductor channel 60 away from the interface between the logic die 700 and the memory die 1000. If the source cap region 606 is omitted, the source layer (including the doped semiconductor material layer 218) contacts the end portion of the vertical semiconductor channel 60 away from the interface between the logic die 700 and the memory die 1000. If the source cap region 606 is present, the source layer (including the doped semiconductor material layer 218) is electrically connected through the source cap region 606 to the end portion of the vertical semiconductor channel 60 away from the interface between the logic die 700 and the memory die 1000.

[0162] In one embodiment, the distal surface of the memory film 50 lies in a horizontal plane including the horizontal interface between the source layer (including the doped semiconductor material layer 218) and the alternating stacks of the insulating layer 32 and the conductive layer 46, or the distal surface of the memory film is closer to the interface between the logic die 700 and the memory die 1000 than the interface between the source layer and the alternating stacks (32, 46) is closer to the interface between the logic die 700 and the memory die 1000.

[0163] refer to Figure 23GA back-side isolation dielectric layer 230 may be formed over the first conductive material layer (i.e., the source layer including the doped semiconductor material layer 218) and over the via structure 8P (which includes pads connecting the via structure 8P1). For example, the back-side isolation dielectric layer 230 may be formed on the distal surface of the doped semiconductor material layer 218 and on the flat distal surface of the dielectric material portion 65. In one embodiment, the back-side isolation dielectric layer 230 may comprise a dielectric material, such as undoped silicate glass (e.g., silicon oxide) or doped silicate glass, and may have a thickness in the range of 100 nm to 2,000 nm, such as in the range of 200 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0164] refer to Figure 23H A photoresist layer 237 can be applied above the distal surface of the back-side isolation dielectric layer 230 and can be photolithographically patterned to form discrete opening patterns in the region covering the pad-connected via structure 8P1. In one embodiment, the pad-connected via structure 8P1 can be arranged as a periodic array of pad-connected via structures 8P1. The openings in the photoresist layer can cover a corresponding subset of the pad-connected via structures 8P1, which is subsequently connected to the same bonding pad. In other words, multiple pad-connected via structures 8P1 can be used to provide a conductive path to the bonding pad. Alternatively, a single pad-connected via structure 8P1 can be used to provide a conductive path to the bonding pad.

[0165] refer to Figure 23I An etching process can be performed to remove unmasked portions of the back-side isolation dielectric layer 230. Anisotropic or isotropic etching processes can be performed. The etching process can be selective for the material of the pad-connected via structure 8P1. Openings can be formed through the back-side isolation dielectric layer 230, and the distal surface of each pad-connected via structure 8P1 is physically exposed. The distal portion of the pad-connected via structure 8P1 protrudes from the horizontally physically exposed surface of the dielectric material portion 65.

[0166] refer to Figure 23JThe second conductive material can be deposited on the distal surface of the pad-connected through-hole structure 8P1 through an opening in the back-side isolation dielectric layer 230. In one embodiment, the second conductive material may comprise at least one metallic material. In this case, the at least one metallic material can be deposited over the back-side isolation dielectric layer 230 and enter through the opening in the back-side isolation dielectric layer 230. The at least one metallic material may comprise, for example, a pad blocking liner layer 342L and a continuous metallic material layer 344L, the pad blocking liner layer comprising a metal nitride material such as TiN, TaN, and / or WN, and the continuous metallic material layer comprising a metal pad material such as copper, aluminum, or alloys thereof. The thickness of the pad blocking liner layer 342L may be in the range of 10 nm to 100 nm, and the thickness of the continuous metallic material layer 344L may be in the range of 300 nm to 3,000 nm, but smaller and larger thicknesses are also possible.

[0167] refer to Figure 23K The second conductive material can be patterned by combining photolithography patterning and etching processes. For example, a photoresist layer 247 can be applied over a continuous metal material layer 344L and can be photolithographically patterned to cover each region of an opening in the back-side isolation dielectric layer 230. The photoresist layer 247 can be patterned into discrete photoresist material portions that cover the regions of corresponding openings in the openings through the back-side isolation dielectric layer 230.

[0168] refer to Figure 23L An etching process can be performed to transfer a pattern of the photoresist layer 247 through the continuous metal material layer 344L and the pad block liner layer 342L. The etching process can include anisotropic etching processes (such as reactive ion etching) or isotropic etching processes (such as wet etching). The etching process removes unmasked portions of the continuous metal material layer 344L and the pad block liner layer 342L. In one embodiment, a first portion (which may contain metallic material) of the second conductive material covering the source layer (including the doped semiconductor material layer 218) can be removed without removing a second portion of the second conductive material over the pad-connected via structure 8P1.

[0169] Each remaining portion of the second conductive material contact pad connection through-hole structure 8P1 includes a connection pad 340. Each connection pad 340 may include a remaining second portion of the second conductive material (which may contain a metallic material). For example, after an etching process, each set of consecutive remaining material portions from the continuous metallic material layer 344L and the pad block pad layer 342L includes a connection pad 340. Each connection pad 340 may include a pad block pad 342 (which is a patterned portion of the pad block pad layer 342L) and a pad metal portion 344 (which is a patterned portion of the continuous metallic material layer 344L). The pad metal portion 344 includes at least one metallic material portion, such as copper, aluminum, or a copper-aluminum alloy portion.

[0170] Generally, the connection pad 340, which contains a second conductive material different from the first conductive material of the source layer (including the doped semiconductor material layer 218), can be directly formed on the pad connecting the through-hole structure 8P1 and the dielectric material portion 65. The connection pad 340 is electrically isolated from the source layer (including the doped semiconductor material layer 218).

[0171] Each connection pad 340 may be formed on the distal end of a corresponding through-hole structure 8P, such as a corresponding pad-connected through-hole structure 8P1. The distal portion of each pad-connected through-hole structure 8P1 protrudes from a horizontal plane including the horizontal interface between the connection pad 340 and the dielectric material portion 65 in a vertical direction pointing away from the interface between the logic die 700 and the memory die 1000, and contacts the recessed surface of the connection pad 340. Each pad-connected through-hole structure 8P1 includes a metal barrier layer 82 and a metal filler portion 84. The metal barrier layer comprises a metal nitride material, and the metal filler portion is embedded in the metal barrier layer 82, does not contact the connection pad 340, and is spaced apart from the connection pad 340 by a cap portion of the metal barrier layer 82, which is contained within the distal portion of the pad-connected through-hole structure 8P1.

[0172] refer to Figure 23M A back-side passivation dielectric layer 250 can be formed over the back-side isolation dielectric layer 230 and the connection pads 340. The back-side passivation dielectric layer 250 contains a dielectric material that can passivate the back side of the memory die 1000, i.e., a dielectric material that can act as a diffusion barrier layer to block the diffusion of moisture and impurities. In one embodiment, the back-side passivation dielectric layer 250 may comprise a silicon nitride or silicon oxide and silicon nitride bilayer structure deposited by plasma-enhanced chemical vapor deposition (PECVD). The thickness of the back-side passivation dielectric layer 250 can range from 100 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0173] Reference Figure 23NA back-side polymer dielectric layer 260 may be formed over a back-side passivation dielectric layer 250. Generally, the back-side polymer dielectric layer 260 may be a dielectric polymer layer. For example, the back-side polymer dielectric layer 260 may be formed by spin-coating and curing a photosensitive polyimide. The photosensitive polyimide may be exposed and developed by photolithography to form an opening over the region of the connection pad 340. An anisotropic etching process using the back-side polymer dielectric layer 260 as an etching mask may be performed to etch the unmasked portion through the back-side passivation dielectric layer 250. The connection pad 340 may be used as an etch stop structure. A terminal via (TV) cavity 269 may be formed through the back-side polymer dielectric layer 260 and the back-side passivation dielectric layer 250. Additional terminal via cavities (not shown) may be formed to physically expose a source layer (such as a doped semiconductor material layer 218).

[0174] refer to Figure 230 Optional bonding pads 16 are formed in a TV cavity 269 between bonding line 15 and connecting pad 340. Bonding pads can be formed by depositing a metal pad material such as TiN, TaN, and / or WN in the terminal via cavity 269 and subsequently depositing at least one bonding pad material in the TV cavity 269. The at least one bonding pad material may comprise, for example, a pad metal such as copper or aluminum, and an under-bump metallization (UBM) material stack to facilitate subsequent attachment of solder material thereon. For example, the at least one bonding pad material may comprise a vertical stack of copper portions and under-bump metallization (UBM) stack portions, or a vertical stack of aluminum portions and UBM stack portions. An exemplary UBM stack portion may comprise, from bottom to top, a Ti / Cu layer, a nickel layer, and a Cu layer. The at least one bonding pad material and metal pad material may then be patterned, for example, by applying and patterning a photoresist layer over it, and by transferring a pattern in the photoresist layer through the at least one bonding pad material and the metal pad material. Various bonding pads 16 can be formed directly on corresponding bonding pads in bonding pads 340. Additional bonding pads can be formed directly on the distal surface of the source layer (such as the doped semiconductor material layer 218), such as... Figure 21 At least one source bonding pad 14 is shown. Bonding lines 15 can be bonded to corresponding bonding pads in bonding pads (14, 16), such as... Figure 21 As shown in the diagram. Backside bonding line 715 can be bonded to each backside bonding pad 716.

[0175] Generally, at least one back-side dielectric layer (230, 250, 260) may be formed over the source layer (such as the doped semiconductor material layer 218). Each back-side bonding pad 16 may be formed above the distal surface of at least one back-side dielectric layer (230, 250, 260). Each back-side bonding pad 16 may include a via portion extending through at least one back-side dielectric layer (230, 250, 260). At least one back-side dielectric layer (230, 250, 260) may include a back-side polymer dielectric layer 260 that contacts a metal portion of the bonding pad 340 and extends over the source layer (such as the doped semiconductor material layer 218). In one embodiment, at least one back-side dielectric layer (230, 250, 260) may comprise a stack of silicon oxide layers (such as back-side isolation dielectric layer 230), silicon nitride layers (such as back-side passivation dielectric layer 250), and dielectric polymer layers (such as back-side polymer dielectric layer 260). At least a subset of the back-side bonding pads 16 may be formed across at least one back-side dielectric layer (230, 250, 260) on the distal surface of the respective bonding pad 340.

[0176] At least one back-side bonding pad 16 may be electrically connected to the via structure 8P and may be electrically isolated from the source layer (such as the doped semiconductor material layer 218). At least one back-side bonding pad 16 may be formed over the dielectric material portion 65 and may have a region overlapping with the dielectric material portion 65 in a plan view. Each bonding pad 340 may contact the distal surface of the corresponding via structure 8P (such as the corresponding pad connecting to the via structure 8P1) and may contact the proximal surface of the corresponding back-side bonding pad 16.

[0177] The source layer (including a doped semiconductor material layer 218) contains a first conductive material and is electrically connected to the end portion of the vertical semiconductor channel 60 remote from the interface between the logic die 700 and the memory die 1000. Through-hole structures (such as pad-connected through-hole structures 8P1) have a vertical range greater than the vertical thickness of the alternating stacks (32, 46) and extend vertically through the dielectric material portion 65. The connecting pad 340 contains a second conductive material different from the first conductive material, contacts the distal surface of the through-hole structure, and is electrically isolated from the source layer.

[0178] In one embodiment, the vertical semiconductor channel 60 includes a semiconductor material doped with a first conductivity type, and the source layer (including the doped semiconductor material layer 218) includes a doped semiconductor material doped with a second conductivity type opposite to the first conductivity type. In one embodiment, a source cap region 606 including a portion of the doped semiconductor material with the second conductivity type may be directly located on a corresponding end portion of the vertical semiconductor channel in the vertical semiconductor channel 60. The source layer contacts each source cap region in the source cap region 606.

[0179] In one embodiment, the second conductive material may comprise a metallic material. In one embodiment, the connection pad 340 may include a pad blocking pad 342 and a pad metal portion 344, the pad blocking pad comprising a metallic blocking material and contacting the distal horizontal surface of the dielectric material portion 65, the pad metal portion comprising a metallic material and contacting the pad blocking pad 342. In one embodiment, a through-hole structure (such as a pad-connected through-hole structure 8P1) includes a metallic blocking layer 82 and a metallic filler portion 84, the metallic blocking layer contacting the sidewalls of the pad blocking pad 342 and the dielectric material portion 65, the metallic filler portion being spaced apart from the connection pad 340 and the dielectric portion 65 by the metallic blocking layer 82. In one embodiment, a distal portion of the metallic blocking layer 82 protrudes from and enters the connection pad 340 from the horizontal interface between the dielectric material portion 65 and the connection pad 340, and is laterally surrounded by the connection pad 340. The back-side bonding pad 16 can be located above the dielectric material portion 65, can contact the distal surface of the bonding pad 340, and can be electrically isolated from the source layer (including the doped semiconductor material layer 218).

[0180] refer to Figure 23P This illustrates another embodiment of the first alternative configuration of the joining assembly, which can be adapted to... Figure 230 The bonding assembly is derived by omitting the ion implantation process that forms the source cap region 606. In this case, the doped semiconductor material layer 218 directly contacts the end portion of the vertical semiconductor channel 60. The doped semiconductor material layer 218 serves as the source layer for the common source of all vertical NAND strings including the vertical semiconductor channel 60.

[0181] refer to Figure 23Q This illustrates another embodiment of the first alternative configuration of the joining assembly, which can be adapted to... Figure 230 The bonding assembly is derived by omitting the bonding pad 16. In this embodiment, bonding lines 15 are deposited into the TV cavity 269 to directly and physically contact the bonding pad 340.

[0182] Figures 24A to 24IThis is a sequential vertical cross-sectional view of a second alternative configuration of the bonding assembly (700, 1000) during various processing steps up to the formation of the back-side bonding pad 16, according to a third embodiment of this disclosure.

[0183] refer to Figure 24A The second alternative configuration of the coupling components (700, 1000) can be with Figure 23G The first alternative configuration of the joining components (700, 1000) shown is the same.

[0184] refer to Figure 24B A photoresist layer 237 can be applied above the distal surface of the back-side isolation dielectric layer 230 and can be photolithographically patterned to remove the photoresist material from above the region of the doped semiconductor material layer 218 and from above the region surrounding the pad-connected via structure 8P1. The patterned portion of the photoresist layer 237 can cover portions of the back-side isolation dielectric layer 230 located around or between the doped semiconductor material layer 218, but not the region where the connection pads will subsequently form. In one embodiment, the pad-connected via structures 8P1 can be arranged as a periodic array of pad-connected via structures 8P1. In this case, openings in the photoresist layer can cover a corresponding subset of the pad-connected via structures 8P1, which is subsequently connected to the same bonding pad. In other words, multiple pad-connected via structures 8P1 can be used to provide conductive paths to the bonding pads. Alternatively, a single pad can be connected to a through-hole structure 8P1 to provide a conductive path to the bonding pad.

[0185] refer to Figure 24C An etching process can be performed to remove unmasked portions of the back-side isolation dielectric layer 230. An anisotropic or isotropic etching process can be performed. The etching process can be selective for the material of the pad-connected via structure 8P1. Openings are formed through the back-side isolation dielectric layer 230, physically exposing the distal surface of each pad-connected via structure 8P1. After the back-side isolation dielectric layer 230 is patterned, the distal surface (i.e., the back surface) of the first material layer (such as the doped semiconductor material layer 218) can be physically exposed.

[0186] The distal portion of the pad-connected via structure 8P1 protrudes from the horizontally physically exposed surface of the dielectric material portion 65. The remaining portion of the back-side isolation dielectric layer 230 covers the gap between portions of the doped semiconductor material layer 218. The combination of the doped semiconductor material layer 218 and the back-side isolation dielectric layer 230 covers the entire back surface of the memory die 1000, including the area where the pad-connected via structure 8P1 is located, and not just the area where the connection pads will subsequently form.

[0187] refer to Figure 24D A second conductive material (such as at least one metallic material) can be deposited over the back-side isolation dielectric layer 230 and enter through an opening in the back-side isolation dielectric layer 230. The second conductive material may include, for example, a metal barrier pad layer 442L and a continuous metal material layer 444L. The metal barrier pad layer comprises a metal nitride material such as TiN, TaN, and / or WN or a Ti / TiN bilayer structure, and the continuous metal material layer comprises a metallic material such as copper, aluminum, or alloys thereof. The thickness of the metal barrier pad layer 442L can range from 10 nm to 100 nm, and the thickness of the continuous metal material layer 444L can range from 300 nm to 3,000 nm, but smaller and larger thicknesses are also possible. The metal barrier pad layer 442L can be deposited directly on the distal surface of the doped semiconductor material layer 218 and directly on the protruding surface of the metal barrier layer 82 of the through-hole structure 8P1 connected to the pad.

[0188] refer to Figure 24E A photoresist layer 247 can be applied over a continuous metal material layer 444L and can be photolithographically patterned to cover each region of the opening in the back-side isolation dielectric layer 230. Thus, the patterned photoresist layer 247 covers regions of the doped semiconductor material layer 218, regions of the pad-connected via structure 8P1, and regions of the metal barrier pad layer 442L contacting the dielectric material portion 65 around the pad-connected via structure 8P1. The patterned portion of the photoresist layer 247 includes discrete photoresist material portions that cover the corresponding regions that will subsequently form the corresponding connection pads.

[0189] refer to Figure 24F An etching process can be performed to transfer a pattern of photoresist layer 247 through continuous metal material layer 444L and metal barrier pad layer 442L. The etching process may include anisotropic etching processes (such as reactive ion etching) and / or isotropic etching processes (such as wet etching). The etching process removes unmasked portions of continuous metal material layer 444L and metal barrier pad layer 442L. A second conductive material, which may include the at least one metal material, can be patterned to provide a first portion of the at least one metal material covering the source layer (including doped semiconductor material layer 218) and a second portion of the at least one metal material located above the pad-connected through-hole structure 8P1. This portion of the at least one metal material can be incorporated into the source layer.

[0190] Following the etching process, each set of continuous remaining material portions from the continuous metal material layer 444L and the metal barrier pad layer 442L covers and electrically connects to at least one set of pad-connected through-hole structures 8P1, including connection pads 340. Each connection pad 340 may include a pad barrier pad 342 (which is a patterned portion of the pad barrier pad layer 442L) and a pad metal portion 344 (which is a patterned portion of the continuous metal material layer 444L). The pad metal portion 344 includes at least one portion of a metal material, such as copper, aluminum, or an alloy thereof.

[0191] Following the etching process, each set of consecutive remaining material portions from the continuous metal material layer 444L and the metal barrier pad layer 442L covers and is electrically connected to the doped semiconductor material layer 218, including the metal source layer 440. Each metal source layer 440 may include a source barrier pad 442 (which is a patterned portion of the metal barrier pad layer 442L) and a metal material layer 444 (which is a patterned portion of the continuous metal material layer 444L). The metal material layer 444 includes at least one metal material portion, such as copper, aluminum, or an alloy thereof.

[0192] Each connection pad 340 may be formed on the distal end of a corresponding through-hole structure 8P, such as a corresponding pad-connected through-hole structure 8P1. The distal portion of each pad-connected through-hole structure 8P1 protrudes from a horizontal plane including the horizontal interface between the connection pad 340 and the dielectric material portion 65 in a vertical direction pointing away from the interface between the logic die 700 and the memory die 1000, and contacts the recessed surface of the connection pad 340. Each pad-connected through-hole structure 8P1 includes a metal barrier layer 82 and a metal filler portion 84. The metal barrier layer comprises a metal nitride material, and the metal filler portion is embedded in the metal barrier layer 82, does not contact the connection pad 340, and is spaced apart from the connection pad 340 by a cap portion of the metal barrier layer 82, which is contained within the distal portion of the pad-connected through-hole structure 8P1.

[0193] refer to Figure 24G A back-side passivation dielectric layer 250 can be formed over the back-side isolation dielectric layer 230, the bonding pads 340, and the metal source layer 440. The back-side passivation dielectric layer 250 contains a dielectric material that can passivate the back side of the memory die 1000, i.e., a dielectric material that can act as a diffusion barrier layer to block the diffusion of moisture and impurities. In one embodiment, the back-side passivation dielectric layer 250 may comprise a silicon nitride or silicon oxide / silicon nitride bilayer structure deposited by plasma-enhanced chemical vapor deposition (PECVD). The thickness of the back-side passivation dielectric layer 250 can range from 100 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0194] Reference Figure 24H A back-side polymer dielectric layer 260 may be formed over a back-side passivation dielectric layer 250. Generally, the back-side polymer dielectric layer 260 may be a dielectric polymer layer. For example, the back-side polymer dielectric layer 260 may be formed by spin-coating and curing a photosensitive polyimide. The photosensitive polyimide may be exposed and developed by photolithography to form an opening over the region of the connection pad 340. An anisotropic etching process using the back-side polymer dielectric layer 260 as an etching mask may be performed to etch the unmasked portion through the back-side passivation dielectric layer 250. The connection pad 340 may be used as an etch stop structure. A terminal via (TV) cavity 269 may be formed through the back-side polymer dielectric layer 260 and the back-side passivation dielectric layer 250. Additional terminal via cavities (not shown) may be formed to physically expose a source layer (such as a metal source layer 440).

[0195] refer to Figure 24I A metal pad material such as TiN, TaN, and / or WN can be deposited in the end via cavity 269, and at least one bonding pad material can subsequently be deposited. This at least one bonding pad material may comprise, for example, a pad metal such as copper, aluminum, or an alloy thereof, and an under-bump metallization (UBM) material stack to facilitate subsequent attachment of solder material thereon. For example, the at least one bonding pad material may comprise a vertical stack of copper portions and under-bump metallization (UBM) stack portions, or a vertical stack of aluminum portions and UBM stack portions. An exemplary UBM stack portion may comprise, from bottom to top, a Ti / Cu layer, a nickel layer, and a Cu layer.

[0196] The at least one bonding pad material and metal pad material can then be patterned, for example, by applying and patterning a photoresist layer over it, and by transferring the pattern in the photoresist layer through the at least one bonding pad material and metal pad material. Various bonding pads 16 can be formed directly on corresponding bonding pads in the bonding pads 340. Additional bonding pads can be formed directly on the distal surface of the source layer (such as the doped semiconductor material layer 218), such as... Figure 21 At least one source bonding pad 14 is shown. Bonding lines 15 can be bonded to corresponding bonding pads in bonding pads (14, 16), such as... Figure 21 As shown in the diagram. Backside bonding lines 715 can be bonded to each backside bonding pad 716. Alternatively, the bonding pads 16 can be omitted, and bonding lines 15 can be deposited into the TV cavity 269 to directly and physically contact the bonding pads 340, similar to... Figure 23Q The configuration shown.

[0197] Generally, at least one back-side dielectric layer (230, 250, 260) may be formed over the source layer (such as the doped semiconductor material layer 218 and the metal source layer 240). Each back-side bonding pad 16 may be formed above the distal surface of the at least one back-side dielectric layer (230, 250, 260). Each back-side bonding pad 16 may include a via portion extending through the at least one back-side dielectric layer (230, 250, 260). The at least one back-side dielectric layer (230, 250, 260) may include a back-side polymer dielectric layer 260 that contacts the metal portion of the bonding pad 340 and extends over the source layer (such as the doped semiconductor material layer 218). In one embodiment, at least one back-side dielectric layer (230, 250, 260) may comprise a stack of silicon oxide layers (such as back-side isolation dielectric layer 230), silicon nitride layers (such as back-side passivation dielectric layer 250), and dielectric polymer layers (such as back-side polymer dielectric layer 260). At least a subset of the back-side bonding pads 16 may be formed across at least one back-side dielectric layer (230, 250, 260) on the distal surface of the respective bonding pad 340.

[0198] At least one back-side bonding pad 16 may be electrically connected to the via structure 8P and may be electrically isolated from the source layer (such as the doped semiconductor material layer 218). At least one back-side bonding pad 16 may be formed over the dielectric material portion 65 and may have a region overlapping with the dielectric material portion 65 in a plan view. Each bonding pad 340 may contact the distal surface of the corresponding via structure 8P (such as the corresponding pad connecting to the via structure 8P1) and may contact the proximal surface of the corresponding back-side bonding pad 16.

[0199] In one embodiment, the source layers (218, 440) may include a first conductive material (including a doped semiconductor material layer 218) and may be electrically connected to an end portion of the vertical semiconductor channel 60 remote from the interface between the logic die 700 and the memory die 1000. Through-hole structures (such as pad-connected through-hole structure 8P1) may have a vertical range greater than the vertical thickness of the alternating stacks (32, 46) and may extend vertically through the dielectric material portion 65. The source layers (218, 440) may also include a metallic source layer 440 comprising a second conductive material, which may comprise at least one metallic material. The second conductive material is different from the first conductive material. Connecting pads 340 may comprise the second conductive material and may contact the distal surface of the through-hole structure (such as pad-connected through-hole structure 8P1) and may be electrically isolated from the source layers (218, 440).

[0200] In one embodiment, the vertical semiconductor channel 60 includes a doped semiconductor material having a first conductivity type, and the source layer (including the doped semiconductor material layer 218) includes a doped semiconductor material having a second conductivity type opposite to the first conductivity type. In one embodiment, a source cap region 606 including a portion of the doped semiconductor material having the second conductivity type may be directly located on a corresponding end portion of the vertical semiconductor channel in the vertical semiconductor channel 60. The source layers (218, 440) contact each source cap region in the source cap regions 606.

[0201] In one embodiment, the second conductive material may comprise a metallic material. In one embodiment, the connection pad 340 may include a pad blocking pad 342 and a pad metal portion 344, the pad blocking pad comprising a metallic blocking material and contacting the distal horizontal surface of the dielectric material portion 65, the pad metal portion comprising a metallic material and contacting the pad blocking pad 342. In one embodiment, a through-hole structure (such as a pad-connected through-hole structure 8P1) includes a metallic blocking layer 82 and a metallic filler portion 84, the metallic blocking layer contacting the sidewalls of the pad blocking pad 342 and the dielectric material portion 65, the metallic filler portion being spaced apart from the connection pad 340 and the dielectric portion 65 by the metallic blocking layer 82. In one embodiment, a distal portion of the metallic blocking layer 82 protrudes from and enters the connection pad 340 from the horizontal interface between the dielectric material portion 65 and the connection pad 340, and is laterally surrounded by the connection pad 340. The back-side bonding pad 16 can be located above the dielectric material portion 65, can contact the distal surface of the bonding pad 340, and can be electrically isolated from the source layer (including the doped semiconductor material layer 218).

[0202] refer to Figure 24J This illustrates another embodiment of a second alternative configuration of the coupling assembly, which can be adapted to... Figure 24I The bonding assembly is derived by omitting the ion implantation process that forms the source cap region 606. In this case, the doped semiconductor material layer 218 directly contacts the end portion of the vertical semiconductor channel 60. The doped semiconductor material layer 218 is part of the source layer that serves as the common source for all vertical NAND strings including the vertical semiconductor channel 60.

[0203] Figures 25A to 25G This is a sequential vertical cross-sectional view of a third alternative configuration of the bonding assembly (700, 1000) during various processing steps up to the formation of the back-side bonding pad 16, according to a fourth embodiment of this disclosure.

[0204] refer to Figure 25A The second alternative configuration of the coupling components (700, 1000) can be with Figure 23CThe first alternative configuration of the bonding assembly at the processing step is the same. The distal end of each vertical semiconductor channel 60 and the distal end of each through-hole structure 8P are physically exposed.

[0205] refer to Figure 25B At least one conductive material can be deposited simultaneously on the material at the distal end of each vertical semiconductor channel 60 and at the distal end of each through-hole structure 8P. For example, the at least one conductive material comprises a layer stack including a metal barrier liner layer 242L and a continuous metal material layer 244L. In this case, the metal barrier liner layer 242L and the continuous metal material layer 244L can be deposited over the physically exposed surfaces of the vertical semiconductor channel 60 and the through-hole structure 8P. The metal barrier liner layer 242L comprises a metal barrier material, such as TiN, TaN, and / or WN or a Ti / TiN bilayer structure. The metal barrier liner layer 242L can be deposited by physical vapor deposition or chemical vapor deposition and can have a thickness in the range of 3 nm to 60 nm, such as in the range of 6 nm to 30 nm, but smaller and larger thicknesses are also possible. The continuous metallic layer 244L comprises elemental metals or intermetallic alloys, such as Al, Cu, W, Mo, Ru, Co, and / or alloys thereof. The continuous metallic layer 244L can be deposited by physical vapor deposition and / or by electroplating, and can have a thickness in the range of 200 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0206] refer to Figure 25C The at least one conductive material can be patterned into multiple discrete portions. For example, a photoresist layer (not shown) can be applied over a continuous metal material layer 244L and can be photolithographically patterned to cover multiple discrete regions. In one embodiment, the patterned portion of the photoresist layer can continuously cover corresponding source connection via structures configured to electrically bias a vertical semiconductor channel 60 within a set of memory opening-fill structures 58 and source connection via structures 8P2. In one embodiment, the patterned photoresist layer includes discrete photoresist material portions that cover a corresponding subset of the pad connection via structures 8P1.

[0207] A photoresist layer can be used as an etching mask layer to perform the etching process. The etching process may include anisotropic etching or isotropic etching. A source layer containing a first portion of the at least one conductive material is formed on the distal end of each vertical semiconductor channel 60. A connection pad 340 containing a second portion of the at least one conductive material is formed on a through-hole structure (such as a pad-connected through-hole structure 8P1). The connection pad 340 is electrically isolated from the source layer.

[0208] Specifically, the etching process etches the unmasked portions of the continuous metal material layer 244L and the metal barrier pad layer 242L. The patterned portion of the continuous metal material layer 244L includes at least one metal material layer 244 and a pad metal portion 344. The metal material layer covers a corresponding set of memory aperture filling structures 58 and extends continuously over at least one source connection via structure 8P2. The pad metal portion covers at least one pad connection via structure 8P1. The patterned portion of the metal barrier pad layer 242L includes at least one source barrier pad 242 and a pad barrier pad 342. The at least one source barrier pad contacts a corresponding set of memory aperture filling structures 58 and at least one source connection via structure 8P2, and the pad barrier pad contacts at least one pad connection via structure 8P1. Each continuous combination of the metal material layer 244 and the source barrier pad 242 constitutes a metal source layer 240. Each consecutive combination of pad metal portion 344 and pad blocking pad 342 constitutes a connection pad 340. The metal source layer 240 acts as the source layer for electrically connecting a corresponding set of vertical semiconductor channels 60 to at least one source connection through-hole structure 8P2.

[0209] Generally, a source layer including a metal source layer 240 can be formed by depositing at least one metal material on the distal end of each vertical semiconductor channel 60 and by patterning the at least one metal material. In one embodiment, the interface between the semiconductor material of the vertical semiconductor channel 60 and the source layer (including the metal source layer 240) protrudes from a horizontal plane including the horizontal interface between the source layer and the alternating stack (32, 46) in a vertical direction pointing away from the interface between the logic die 700 and the memory die 1000. For example, the interface between the vertical semiconductor channel 60 and the source layer (including the metal source layer 240) may be farther from the bonding interface between the logic die 700 and the memory die 1000 than the horizontal plane including the horizontal interface between the source layer and the alternating stack (32, 46).

[0210] The source layer (including the metal source layer 240) is electrically connected to and contacts the end portion of the vertical semiconductor channel 60 remote from the interface between the logic die 700 and the memory die 1000. In one embodiment, the distal surface of the memory film 50 lies in a horizontal plane including the horizontal interface between the source layer (including the metal source layer 240) and the alternating stacks of insulating layer 32 and conductive layer 46, or the distal surface of the memory film is closer to the interface between the logic die 700 and the memory die 1000 than the interface between the source layer and the alternating stacks (32, 46) is closer to the interface between the logic die 700 and the memory die 1000.

[0211] refer to Figure 25D A back-side isolation dielectric layer 230 may be formed on the distal surface of the metal source layer 240, on the distal surface of each bonding pad 340, and on the flat distal surface of the dielectric material portion 65. In one embodiment, the back-side isolation dielectric layer 230 may comprise a dielectric material, such as undoped or doped silicate glass, and may have a thickness in the range of 100 nm to 2,000 nm, such as in the range of 200 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0212] Reference Figure 25E A back-side passivation dielectric layer 250 can be formed above the back-side isolation dielectric layer 230. The back-side passivation dielectric layer 250 contains a dielectric material that can passivate the back side of the memory die 1000, i.e., a dielectric material that can act as a diffusion barrier layer to block the diffusion of moisture and impurities. In one embodiment, the back-side passivation dielectric layer 250 may comprise a silicon nitride or silicon oxide / silicon nitride bilayer structure deposited by plasma-enhanced chemical vapor deposition (PECVD). The thickness of the back-side passivation dielectric layer 250 can range from 100 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0213] Reference Figure 25FA back-side polymer dielectric layer 260 can be formed above a back-side passivation dielectric layer 250. Generally, the back-side polymer dielectric layer 260 can be a dielectric polymer layer. For example, the back-side polymer dielectric layer 260 can be formed by spin-coating and curing a photosensitive polyimide. The photosensitive polyimide can be exposed and developed by photolithography to form an opening above the area of ​​the connection pad 340. An anisotropic etching process using the back-side polymer dielectric layer 260 as an etching mask can be performed to etch unmasked portions through the back-side passivation dielectric layer 250 and the back-side isolation dielectric layer 230. The connection pad 340 can be used as an etch stop structure. A terminal via (TV) cavity 269 can be formed through the back-side polymer dielectric layer 260 and the back-side passivation dielectric layer 250. Additional terminal via cavities (not shown) can be formed to physically expose source layers (such as a metal source layer 240).

[0214] refer to Figure 25G A metal pad material such as TiN, TaN, and / or WN can be deposited in the end via cavity 269, and at least one bonding pad material can subsequently be deposited. This at least one bonding pad material may comprise, for example, a pad metal such as copper, aluminum, or an alloy thereof, and an under-bump metallization (UBM) material stack to facilitate subsequent attachment of solder material thereon. For example, the at least one bonding pad material may comprise a vertical stack of copper portions and under-bump metallization (UBM) stack portions, or a vertical stack of aluminum portions and UBM stack portions. An exemplary UBM stack portion may comprise, from bottom to top, a Ti / Cu layer, a nickel layer, and a Cu layer.

[0215] The at least one bonding pad material and metal pad material can then be patterned, for example, by applying and patterning a photoresist layer over it, and by transferring the pattern in the photoresist layer through the at least one bonding pad material and metal pad material. Various bonding pads 16 can be formed directly on corresponding bonding pads in the bonding pads 340. Additional bonding pads, such as those on the distal surface of the source layer (e.g., the metal source layer 240), can be formed directly on the distal surface of the source layer. Figure 21 At least one source bonding pad 14 is shown. Bonding lines 15 can be bonded to corresponding bonding pads in bonding pads (14, 16), such as... Figure 21 As shown in the diagram. Backside bonding lines 715 can be bonded to each backside bonding pad 716. Alternatively, the bonding pads 16 can be omitted, and bonding lines 15 can be deposited into the TV cavity 269 to directly and physically contact the bonding pads 340, similar to... Figure 23Q The configuration shown.

[0216] Generally, at least one back-side dielectric layer (230, 250, 260) may be formed over a source layer (such as a metal source layer 240). Each back-side bonding pad 16 may be formed above the distal surface of at least one back-side dielectric layer (230, 250, 260). Each back-side bonding pad 16 may include a via portion extending through at least one back-side dielectric layer (230, 250, 260). At least one back-side dielectric layer (230, 250, 260) may include a back-side polymer dielectric layer 260 that contacts a metal portion of the bonding pad 340 and extends over the source layer (such as a metal source layer 240). In one embodiment, at least one back-side dielectric layer (230, 250, 260) may comprise a stack of silicon oxide layers (such as back-side isolation dielectric layer 230), silicon nitride layers (such as back-side passivation dielectric layer 250), and dielectric polymer layers (such as back-side polymer dielectric layer 260). At least a subset of the back-side bonding pads 16 may be formed across at least one back-side dielectric layer (230, 250, 260) on the distal surface of the respective bonding pad 340.

[0217] At least one back-side bonding pad 16 may be electrically connected to the via structure 8P and may be electrically isolated from the source layer (such as the metal source layer 240). At least one back-side bonding pad 16 may be formed over the dielectric material portion 65 and may have regional overlap with the dielectric material portion 65 in a plan view. Each bonding pad 340 may contact the distal surface of the corresponding via structure 8P (such as the corresponding pad connecting to the via structure 8P1) and may contact the proximal surface of the corresponding back-side bonding pad 16.

[0218] In one embodiment, the source layer (including metal source layer 240) comprises a first portion of conductive material and is electrically connected to the end portion of the vertical semiconductor channel 60 remote from the interface between the logic die 700 and the memory die 1000. Through-hole structures (such as pad-connected through-hole structure 8P1) have a vertical extent greater than the vertical thickness of the alternating stacks (32, 46) and extend vertically through the dielectric material portion 65. Connecting pads comprise a second portion of conductive material, contact the distal surface of the through-hole structure (such as pad-connected through-hole structure 8P1), and are electrically isolated from the source layer (including metal source layer 240).

[0219] In one embodiment, the conductive material comprises a metallic material. In one embodiment, a source layer (including a metal source layer 240) contacts the distal horizontal surface of an alternating stack (32, 46), and a connection pad 340 contacts the distal horizontal surface of a dielectric material portion 65. In one embodiment, the source layer (including the metal source layer 240) comprises a stack of source barrier pads 242 and a metallic material layer 244, the source barrier pad contacting the distal horizontal surface of the alternating stack (32, 46), the metallic material layer comprising a first portion of metallic material and covering the source barrier pad 242. The connection pad 340 comprises a stack of pad barrier pads 342 and a pad metallic portion 344, the pad barrier pad contacting the distal horizontal surface of the dielectric material portion 65, the pad metallic portion comprising a second portion of metallic material. In one embodiment, the source barrier pads 242 and 342 have the same material composition and the same thickness.

[0220] Figures 26A to 26G This is a sequential vertical cross-sectional view of a fourth alternative configuration of the bonding assembly during various processing steps up to the formation of the back-side bonding pad, according to a fifth embodiment of this disclosure.

[0221] refer to Figure 26A The fourth alternative configuration of the coupling components (700, 1000) can be combined with... Figure 23E The first alternative configuration of the bonding components (700, 1000) shown is the same. In this case, a dopant of the second conductivity type may optionally be implanted into the material at the distal end of each vertical semiconductor channel 60 to form a source cap region 606 with dopant of the second conductivity type. Generally, conductive material can be deposited directly on the material at the distal end of each vertical semiconductor channel (which may include the source cap region 606 in the case of forming the source cap region 606, or may include the end portion of the vertical semiconductor channel 60) and directly on the distal end of the through-hole structure 8P. In this case, the vertical semiconductor channel 60 contains semiconductor material with dopant of the first conductivity type, and the conductive material contains a continuous doped semiconductor material layer 218L with dopant of the second conductivity type opposite to the first conductivity type.

[0222] refer to Figure 26BAt least one metal material can be deposited on the distal surface of the continuously doped semiconductor material layer 218L. For example, a layer stack including a metal barrier pad layer 442L and a continuous metal material layer 444L can be deposited directly on the distal surface of the continuously doped semiconductor material layer 219L. The at least one metal material may include, for example, the metal barrier pad layer 442L and the continuous metal material layer 444L, the metal barrier pad layer comprising a metal nitride material such as TiN, TaN and / or WN or a Ti / TiN bilayer structure, and the continuous metal material layer comprising a metal material such as copper, aluminum or alloys thereof. The thickness of the metal barrier pad layer 442L can be in the range of 10 nm to 100 nm, and the thickness of the continuous metal material layer 444L can be in the range of 300 nm to 3,000 nm, but smaller and larger thicknesses are also possible. The metal barrier pad layer 442L does not directly contact the pad connection to the through-hole structure 8P1 or the source cap region 606 (or the vertical semiconductor channel 60).

[0223] refer to Figure 26C A photoresist layer (not shown) may be applied over a continuous metal material layer 444L and may be photolithographically patterned to form openings in areas other than the memory aperture fill structure 58, the source interconnect via structure 8P2, and the pad interconnect via structure 8P1. The patterned portion of the photoresist layer includes a continuous photoresist material portion extending over the areas of the memory aperture fill structure 58 and the source interconnect via structure 8P2, and a discrete photoresist material portion covering a corresponding set of at least one pad interconnect via structure 8P1.

[0224] An etching process can be performed to pass through the pattern in the stacked transfer photoresist layer of the continuous metal material layer 444L, the metal barrier pad layer 442L, and the continuous doped semiconductor material layer 218L. The etching process may include anisotropic etching processes (such as reactive ion etching processes) or isotropic etching processes (such as wet etching processes). The etching process removes unmasked portions of the continuous metal material layer 444L, the metal barrier pad layer 442L, and the continuous doped semiconductor material layer 218L.

[0225] Generally, the same etching mask can be used to pattern the stack of metal barrier pad layer 442L and continuous metal material layer 444L, and the conductive material of the underlying continuous doped semiconductor material layer 218L. Source layers (218, 440) are formed, comprising a first remaining portion of the stack (442L, 444L) and a first remaining portion of the continuous doped semiconductor material layer 218L. Connector pads (238, 640) are formed, comprising a second remaining portion of the stack (442L, 444L) and a second remaining portion of the continuous doped semiconductor material layer 218L. Generally, the stack (442L, 444L) and the continuous doped semiconductor material layer 218L can be patterned into multiple discrete portions. Source layers (218, 440) can be formed on the distal end of each vertical semiconductor channel in the vertical semiconductor channel 60. Connecting pads (238, 640) can be formed on via structures (such as pad-connected via structure 8P1) and can be electrically isolated from the source layer (218, 440).

[0226] Specifically, a patterned portion of the continuous doped semiconductor material layer 218L, which is contacted and / or electrically connected to the distal end of the vertical semiconductor channel 60 and the source connection via structure 8P2, includes the doped semiconductor material layer 218, which is a semiconductor source layer. After the etching process, each set of continuous remaining material portions from the continuous metal material layer 444L and the metal barrier pad layer 442L covers and is electrically connected to the doped semiconductor material layer 218, including the metal source layer 440. Each metal source layer 440 may include a source barrier pad 442 (which is a patterned portion of the metal barrier pad layer 442L) and a metal material layer 444 (which is a patterned portion of the continuous metal material layer 444L). The metal material layer 444 includes at least one metal material portion, such as copper, aluminum, or an alloy thereof. The stack of the doped semiconductor material layer 218 and the metal source layer 440 constitutes the source layer (218, 440).

[0227] Each patterned portion of the continuously doped semiconductor material layer 218L contacts a corresponding set of at least one pad-connected via structure 8P1, including a semiconductor connection pad 238. Following the etching process, each set of continuous remaining material portions from the continuous metal material layer 444L and the metal barrier pad layer 442L covers and is electrically connected via the corresponding set of at least one pad-connected via structure 8P1, including a metal connection pad 640, through the corresponding semiconductor connection pad 238. Each metal connection pad 640 may include a pad barrier pad 642 (which is a patterned portion of the metal barrier pad layer 442L) and a pad metal portion 644 (which is a patterned portion of the continuous metal material layer 444L). The pad metal portion 644 includes at least one metal material portion, such as copper, aluminum, or an alloy thereof. Each vertical stack of the semiconductor connection pads 238 and the metal connection pads 640 constitutes a composite connection pad (238, 640). In one embodiment, the sidewall of each semiconductor connection pad 238 may vertically overlap with the sidewall of the overlying metal connection pad 640.

[0228] Each composite connection pad (238, 640) is a connection pad formed on the distal end of a corresponding through-hole structure 8P, such as a corresponding pad-connected through-hole structure 8P1. The distal portion of each pad-connected through-hole structure 8P1 protrudes from a horizontal plane including the horizontal interface between the connection pad 640 and the dielectric material portion 65 in a vertical direction pointing away from the interface between the logic die 700 and the memory die 1000, and contacts the recessed surface of the composite connection pad (238, 640). Each pad-connected through-hole structure 8P1 includes a metal barrier layer 82 and a metal filler portion 84. The metal barrier layer contains a metal nitride material. The metal filler portion is embedded in the metal barrier layer 82, does not contact the composite connection pads (238, 640), and is spaced apart from the composite connection pads (238, 640) by a cap portion of the metal barrier layer 82, which is contained within the distal portion of the pad-connected through-hole structure 8P1.

[0229] refer to Figure 26D A back-side isolation dielectric layer 230 may be formed on the distal surface of the metal source layer, on the distal surface of the composite connection pads (238, 640), and on the physically exposed distal surface of the dielectric material portion 65. In one embodiment, the back-side isolation dielectric layer 230 may comprise a dielectric material, such as undoped or doped silicate glass, and may have a thickness in the range of 100 nm to 2,000 nm, such as in the range of 200 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0230] Reference Figure 26EA back-side passivation dielectric layer 250 can be formed above the back-side isolation dielectric layer 230. The back-side passivation dielectric layer 250 contains a dielectric material that can passivate the back side of the memory die 1000, i.e., a dielectric material that can act as a diffusion barrier layer to block the diffusion of moisture and impurities. In one embodiment, the back-side passivation dielectric layer 250 may comprise a silicon nitride or silicon oxide / silicon nitride bilayer structure deposited by plasma-enhanced chemical vapor deposition (PECVD). The thickness of the back-side passivation dielectric layer 250 can range from 100 nm to 1,000 nm, but smaller and larger thicknesses are also possible.

[0231] Reference Figure 26F A back-side polymer dielectric layer 260 can be formed over a back-side passivation dielectric layer 250. Generally, the back-side polymer dielectric layer 260 can be a dielectric polymer layer. For example, the back-side polymer dielectric layer 260 can be formed by spin-coating and curing a photosensitive polyimide. The photosensitive polyimide can be exposed and developed by photolithography to form an opening over the area of ​​the connection pad 640. An anisotropic etching process using the back-side polymer dielectric layer 260 as an etching mask can be performed to etch unmasked portions through the back-side passivation dielectric layer 250 and the back-side isolation dielectric layer 230. The connection pad 640 can be used as an etch stop structure. A terminal via (TV) cavity 269 can be formed through the back-side polymer dielectric layer 260, the back-side passivation dielectric layer 250, and the back-side isolation dielectric layer 230. Additional terminal via cavities (not shown) can be formed to physically expose source layers (such as a metal source layer 440).

[0232] refer to Figure 26G A metal pad material such as TiN, TaN, and / or WN can be deposited in the end via cavity 269, and at least one bonding pad material can subsequently be deposited. This at least one bonding pad material may comprise, for example, a pad metal such as copper, aluminum, or an alloy thereof, and an under-bump metallization (UBM) material stack to facilitate subsequent attachment of solder material thereon. For example, the at least one bonding pad material may comprise a vertical stack of copper portions and under-bump metallization (UBM) stack portions, or a vertical stack of aluminum portions and UBM stack portions. An exemplary UBM stack portion may comprise, from bottom to top, a Ti / Cu layer, a nickel layer, and a Cu layer.

[0233] The at least one bonding pad material and metal pad material can then be patterned, for example, by applying and patterning a photoresist layer over it, and by transferring the pattern in the photoresist layer through the at least one bonding pad material and metal pad material. Various bonding pads 16 can be formed directly on corresponding bonding pads in the bonding pads 640. Additional bonding pads can be formed directly on the distal surface of the source layer (such as the doped semiconductor material layer 218), such as... Figure 21At least one source bonding pad 14 is shown. Bonding lines 15 can be bonded to corresponding bonding pads in bonding pads (14, 16), such as... Figure 21 As shown in the diagram. Backside bonding lines 715 can be bonded to each backside bonding pad 716. Alternatively, the bonding pads 16 can be omitted, and bonding lines 15 can be deposited into the TV cavity 269 to directly and physically contact the bonding pads 340, similar to... Figure 23Q The configuration shown.

[0234] Generally, at least one back-side dielectric layer (230, 250, 260) may be formed over the source layers (such as the doped semiconductor material layer 218 and the metal source layer 640). Each back-side bonding pad 16 may be formed above the distal surface of the at least one back-side dielectric layer (230, 250, 260). Each back-side bonding pad 16 may include a via portion extending through the at least one back-side dielectric layer (230, 250, 260). The at least one back-side dielectric layer (230, 250, 260) may include a back-side polymer dielectric layer 260 that contacts the metal portion of the composite bonding pad (238, 640) and extends over the source layers (such as the doped semiconductor material layer 218 and the metal source layer 640). In one embodiment, at least one back-side dielectric layer (230, 250, 260) may comprise a stack of silicon oxide layers (such as back-side isolation dielectric layer 230), silicon nitride layers (such as back-side passivation dielectric layer 250), and dielectric polymer layers (such as back-side polymer dielectric layer 260). At least a subset of the back-side bonding pads 16 may be formed across at least one back-side dielectric layer (230, 250, 260) on the distal surface of the respective composite connection pads (238, 640).

[0235] At least one back-side bonding pad 16 may be electrically connected to the via structure 8P and may be electrically isolated from the source layer (such as the doped semiconductor material layer 218 and the metal source layer 640). At least one back-side bonding pad 16 may be formed over the dielectric material portion 65 and may have regional overlap with the dielectric material portion 65 in a plan view. Each composite connection pad (238, 640) may contact the distal surface of the corresponding via structure 8P (such as the corresponding pad connecting to the via structure 8P1) and may contact the proximal surface of the corresponding back-side bonding pad 16.

[0236] In one embodiment, the source layer (218, 440) includes a first portion of conductive material (such as a doped semiconductor material layer 218) electrically connected to an end portion of the vertical semiconductor channel 60 remote from the interface between the logic die 700 and the memory die 1000. Through-hole structures (such as pad-connected through-hole structure 8P1) may have a vertical range greater than the vertical thickness of the alternating stacks (32, 46) and may extend vertically through the dielectric material portion 65. Connecting pads (238, 640) may contain a second portion of conductive material (including semiconductor connecting pad 238) and may contact the distal surface of the through-hole structure (such as pad-connected through-hole structure 8P1) and may be electrically isolated from the source layer (218, 440).

[0237] In one embodiment, the source layer (218, 440) contacts the distal horizontal surface of the alternating stack (32, 46), and the bonding pad (238, 640) contacts the distal horizontal surface of the dielectric material portion 65.

[0238] In one embodiment, the conductive material comprises a doped semiconductor material. In one embodiment, the vertical semiconductor channel 60 has doping of a first conductivity type, and the conductive material comprises a doped semiconductor material having doping of a second conductivity type opposite to the first conductivity type. In one embodiment, a first portion of the conductive material (including the doped semiconductor material layer 218) contacts the distal horizontal surface of the alternating stacks (32, 46), and a second portion of the conductive material (including semiconductor interconnect pads 238) contacts the distal horizontal surface of the dielectric material portion 65.

[0239] In one embodiment, the source layer (218, 440) may include a stack of source barrier pads 442 and a metal layer 444, the source barrier pads contacting the distal surface of a first portion of conductive material (including the doped semiconductor material layer 218), the metal layer comprising the first portion of metallic material and covering the source barrier pads 442. The connection pads (238, 640) include a stack of pad barrier pads 642 and a pad metal portion 644, the pad barrier pads contacting the distal surface of a second portion of conductive material (including the semiconductor connection pad 238), the pad metal portion comprising the second portion of metallic material. In one embodiment, the source barrier pads 442 and 642 have the same material composition and the same thickness.

[0240] In one embodiment, a through-hole structure (such as a pad-connected through-hole structure 8P1) includes a metal barrier layer 82 and a metal filler portion 84, the metal barrier layer being in contact with the sidewalls of a second portion of conductive material and a dielectric material portion 65, the metal filler portion being spaced apart from the connection pads (238, 640) and the dielectric material portion 65 by the metal barrier layer 82.

[0241] refer to Figure 26H This illustrates another embodiment of a third alternative configuration of the joining assembly, which can be based on... Figure 26G The bonding assembly is derived by omitting the ion implantation process that forms the source cap region 606. In this case, the doped semiconductor material layer 218 directly contacts the end portion of the vertical semiconductor channel 60. The doped semiconductor material layer 218 includes part of a source layer that serves as a common source for all vertical NAND strings including the vertical semiconductor channel 60.

[0242] Referring to all the accompanying drawings and various embodiments of the present disclosure, a semiconductor structure is provided including a memory die 1000 bonded to a logic die 700. The memory die 1000 includes: alternating stacks of insulating layers 32 and conductive layers 46; memory stack structures 55 extending through the alternating stacks (32, 46), wherein each memory stack structure in the memory stack structures 55 includes a corresponding vertical semiconductor channel 60 and a corresponding memory film 50; a dielectric portion 65 contacting the sidewalls of the alternating stacks (32, 46); and a source layer {218, 240, (218, 440)} containing a first conductive material and electrically connected to an end portion of the vertical semiconductor channel 60 remote from the interface between the logic die 700 and the memory die 1000.

[0243] In one embodiment, the semiconductor structure further includes a via structure 8P (such as a pad-connected via structure 8P1 or a source-connected via structure 8P2), the via structure having a vertical range greater than the vertical thickness of the alternating stacks (32, 46) and extending vertically through the dielectric material portion 65; and connection pads {340, (238, 640)}, the connection pads contacting the distal surface of the via structure and electrically isolated from the source layer {218, 240, (218, 440)}. In one embodiment, the connection pad 340 comprises a second conductive material (e.g., a metallic material) different from the first conductive material. In another embodiment, the connection pad 340 comprises a second portion of the first conductive material.

[0244] In one embodiment, the back-side bonding pad 16 is located above the dielectric material portion 65, electrically connected to the through-hole structure 8P, and electrically isolated from the source layer {218, 240, (218, 440)}.

[0245] In one embodiment, at least one back-side dielectric layer (230, 250, 250) may be located on alternating stacks (32, 46) and dielectric material portions 65. A back-side bonding pad 16 is located on the distal surface of at least one back-side dielectric layer (230, 250, 250). In one embodiment, the back-side bonding pad 16 includes a via portion extending through at least one back-side dielectric layer (230, 250, 250).

[0246] In one embodiment, the connection pads {340, (238, 640)} may contact the distal surface of a through-hole structure (such as pad-to-through-hole structure 8P1) and the proximal surface of the back-side bonding pad 16. In one embodiment, the connection pads {340, (238, 640)} include a metallic portion (such as pad metallic portion (344, 644)); and at least one back-side dielectric layer (230, 250, 250) contacts the distal surface of the metallic portion and extends over the source layers {218, 240, (218, 440)}.

[0247] In one embodiment, the source layer {218, 240, (218, 440)} includes at least one of the following: a doped semiconductor material layer 218; and a metal material layer (240, 440) having the same material composition as the metal material portion (such as the pad metal portion (344, 644)).

[0248] In one embodiment, the connection pads (238, 640) comprise a vertical stack of doped semiconductor material portions (such as semiconductor connection pads 238) and metal material portions 640; and the source layers (218, 440) comprise a vertical stack of a doped semiconductor material layer 218 and a metal material, the doped semiconductor material layer having the same material composition as the doped semiconductor material portions (such as semiconductor connection pads 238), and the metal material having the same material composition as the metal material portions 640.

[0249] In one embodiment, at least one back-side dielectric layer (230, 250, 260) comprises a stack of a silicon oxide layer (including a back-side isolation dielectric layer 230), a silicon nitride layer (including a back-side passivation dielectric layer 250), and a dielectric polymer layer (including a back-side polymer dielectric layer 260).

[0250] In one embodiment, the distal portion of the through-hole structure 8P protrudes from a horizontal plane comprising the horizontal interface between the connection pads {340, (238, 640)} and the dielectric material portion 65 in a vertical direction pointing away from the interface between the logic die 700 and the memory die 1000. In one embodiment, the through-hole structure 8P includes: a metal barrier layer 82 comprising a metal nitride material; and a metal filler portion 84 embedded in the metal barrier layer 82, not in contact with the connection pads {340, (238, 640)} and spaced apart from the connection pads {340, (238, 640)} by a cap portion of the metal barrier layer 82, the cap portion being contained within the distal portion of the through-hole structure 8P.

[0251] In one embodiment, the distal surface of the memory film 50 lies in a horizontal plane including the horizontal interface between the source layers {218, 240, (218, 440)} and the alternating stack (32, 46), or the distal surface of the memory film is closer to the interface between the logic die 700 and the memory die 1000 than the interface between the source layers {218, 240, (218, 440)} and the alternating stack (32, 46) is closer to the interface between the logic die 700 and the memory die 1000.

[0252] In one embodiment, the interface between the semiconductor material of the vertical semiconductor channel 60 and the source layer {218, 240, (218, 440)} protrudes from a horizontal plane including the horizontal interface between the source layer {218, 240, (218, 440)} and the alternating stack (32, 46) in a vertical direction pointing away from the interface between the logic die 700 and the memory die 1000.

[0253] In one embodiment, the logic die 700 includes peripheral circuitry configured to operate memory elements in the memory stack structure 55 and drive the conductive layer 46.

[0254] Various embodiments of this disclosure can be used to provide a bonding assembly for a memory die 1000 and a logic die 700, the bonding assembly including a back-side bonding pad 16 and a source layer {218, 240, (218, 440)} that laterally connects the distal end portion of the vertical semiconductor channel 60 of the memory stack structure 55 and a source-connected through-hole structure 8P2. The pad-connected through-hole structure 8P1 provides a vertical electrical connection through the memory levels of the memory die 100 to the back-side bonding pad 16.

[0255] Various embodiments of this disclosure can provide any one or more of the following advantages. By increasing the surface area of ​​the semiconductor channel above the dielectric material portion 65, the contact resistance between the semiconductor channel 60 and the source line can be reduced. Figure 23D The ion implantation shown controls the dopant distribution at the ends of the semiconductor channel. Planar spacing can be achieved via silicon oxide deposition during source region formation. Memory cells can be erased using GIDL or well erase methods, increasing erasure flexibility. The aspect ratio of the pad region can be improved to enhance step coverage at the pad region. Finally, the step height of the polyimide layer 260 can be reduced, resulting in a decrease in polyimide thickness.

[0256] While specific preferred embodiments have been mentioned above, it will be understood that the claims are not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the claims. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments in which the words “comprising” or “including” are used. While embodiments using specific structures and / or configurations are shown in this disclosure, it should be understood that the claims can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure, the semiconductor structure comprising a memory die bonded to a logic die, the memory die comprising: Alternating stacking of insulating and conductive layers; A memory stack structure extending through the alternating stacks, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; The dielectric material portion is in contact with the alternately stacked sidewalls; A source layer comprising a first conductive material and electrically connected to the end portion of the vertical semiconductor channel remote from the interface between the logic die and the memory die and physically exposed after removal of the carrier substrate, wherein the source layer contacts the outer wall of the vertical semiconductor channel within the memory opening filling structure. The distal surface of the memory film lies within a horizontal plane including the horizontal interface between the source layer and the alternating stack, or the distal surface of the memory film is closer to the interface between the logic die and the memory die than the interface between the source layer and the alternating stack is closer to the interface between the logic die and the memory die. The interface between the semiconductor material of the vertical semiconductor channel and the source layer protrudes from the horizontal plane including the horizontal interface between the source layer and the alternating stack in a vertical direction pointing away from the interface between the logic die and the memory die.

2. The semiconductor structure according to claim 1, wherein: The vertical semiconductor channel comprises a doped semiconductor material having a first conductivity type; and The source layer comprises a doped semiconductor material having a second conductivity type that is opposite to the first conductivity type.

3. The semiconductor structure of claim 2 further includes a source cap region, the source cap region comprising a doped semiconductor material portion having the second conductivity type and located directly on the end portion of a corresponding vertical semiconductor channel in the vertical semiconductor channel, wherein the source layer contacts each source cap region in the source cap region.

4. The semiconductor structure according to claim 1, further comprising: A through-hole structure having a vertical range greater than the vertical thickness of the alternating stacks and extending vertically through the dielectric material portion; and A connection pad, the connection pad comprising a second conductive material different from the first conductive material, contacting the distal surface of the through-hole structure and electrically isolated from the source layer.

5. The semiconductor structure according to claim 4, wherein the second conductive material comprises a metallic material.

6. The semiconductor structure of claim 5, wherein the connection pad comprises a pad blocking pad and a pad metal portion, the pad blocking pad comprising a metal blocking material and contacting the distal horizontal surface of the dielectric material portion, and the pad metal portion comprising the metal material and contacting the pad blocking pad; and The through-hole structure includes a metal barrier layer and a metal filler portion. The metal barrier layer contacts the sidewalls of the pad blocking pad and the dielectric material portion. The metal filler portion is spaced apart from the connecting pad and the dielectric material portion through the metal barrier layer.

7. The semiconductor structure of claim 6, wherein the distal portion of the metal barrier layer protrudes from the horizontal interface between the dielectric material portion and the connection pad and enters the connection pad, and is laterally surrounded by the connection pad.

8. The semiconductor structure of claim 4 further includes a back-side bonding pad located above the dielectric material portion, contacting the distal surface of the bonding pad and electrically isolated from the source layer.

9. The semiconductor structure of claim 8, further comprising at least one back-side dielectric layer, wherein the back-side bonding pad is located on the distal surface of the at least one back-side dielectric layer, wherein the back-side bonding pad includes a via portion extending through the at least one back-side dielectric layer.

10. The semiconductor structure of claim 4, further comprising a bonding wire that contacts the distal surface of the connection pad and is electrically isolated from the source layer.

11. The semiconductor structure of claim 1, wherein the logic die includes peripheral circuitry configured to operate memory elements in the memory stack structure and drive the conductive layer.

12. A method for forming a semiconductor structure, the method comprising: A memory die is formed on a substrate, wherein the memory die includes: a memory stack structure extending vertically through alternating stacks of insulating and conductive layers; a dielectric material portion contacting the sidewalls of the alternating stacks; and a through-hole structure extending vertically through the dielectric material portion, wherein each memory stack structure in the memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; After removing the carrier substrate, the distal ends of each vertical semiconductor channel and the distal ends of the through-hole structure are physically exposed. A source layer comprising a first conductive material is directly formed on the semiconductor material at the distal end of each of the vertical semiconductor channels; and Connection pads containing a second conductive material different from the first conductive material are directly formed on the through-hole structure and the dielectric material portion, wherein the connection pads are electrically isolated from the source layer. in: The vertical semiconductor channel comprises a doped semiconductor material having a first conductivity type; and The first conductive material comprises a doped semiconductor material having a second conductivity type opposite to the first conductivity type. in: The second conductive material comprises a metallic material; and The method includes removing a first portion of the metal material covering the source layer without removing a second portion of the metal material from above the via structure, wherein the connection pads include the second portion of the metal material, or in: The second conductive material comprises a metallic material; and The method includes patterning the metal material into a first portion of the metal material covering the source layer and a second portion of the metal material located above the through-hole structure.

13. The method of claim 12, further comprising: The first conductive material is patterned to form a first conductive material layer, the first conductive material layer contacting the semiconductor material at the distal end of each of the vertical semiconductor channels; A back-side isolation dielectric layer is formed above the first conductive material layer and above the through-hole structure; as well as An opening is formed through the back-side isolation dielectric layer, wherein the distal surface of the through-hole structure is physically exposed.

14. The method of claim 13, wherein: The second conductive material is deposited on the distal surface of the through-hole structure through the opening in the back-side insulating dielectric layer; and The method includes patterning the second conductive material, wherein the second conductive material contacts the remainder of the through-hole structure, including the connecting pads.

15. The method of claim 12, further comprising: At least one back-side dielectric layer is formed above the source layer and the connection pad; as well as A back-side bonding pad is formed directly through the at least one back-side dielectric layer on the distal surface of the at least one back-side dielectric layer.

16. A semiconductor structure, the semiconductor structure comprising a memory die bonded to a logic die, the memory die comprising: Alternating stacking of insulating and conductive layers; A memory stack structure extending through the alternating stacks, wherein each memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; The dielectric material portion is in contact with the alternately stacked sidewalls; A source layer comprising a first portion of conductive material and electrically connected to an end portion of the vertical semiconductor channel remote from the interface between the logic die and the memory die and physically exposed after removal of the carrier substrate, wherein the source layer contacts the outer wall of the vertical semiconductor channel within the memory opening filling structure; A through-hole structure having a vertical range greater than the vertical thickness of the alternating stacks and extending vertically through the dielectric material portion; and A connection pad, the connection pad comprising a second portion of the conductive material, contacting the distal surface of the through-hole structure and electrically isolated from the source layer. The distal surface of the memory film lies within a horizontal plane including the horizontal interface between the source layer and the alternating stack, or the distal surface of the memory film is closer to the interface between the logic die and the memory die than the interface between the source layer and the alternating stack is closer to the interface between the logic die and the memory die. The interface between the semiconductor material of the vertical semiconductor channel and the source layer protrudes from the horizontal plane including the horizontal interface between the source layer and the alternating stack in a vertical direction pointing away from the interface between the logic die and the memory die.

17. The semiconductor structure of claim 16, wherein the conductive material comprises a metallic material.

18. The semiconductor structure according to claim 16, wherein: The source layer contacts the alternatingly stacked distal horizontal surface; and The connecting pad contacts the distal horizontal surface of the dielectric material portion.

19. The semiconductor structure according to claim 18, wherein: The source layer comprises a stack of source barrier pads and metal material layers, the source barrier pads contacting the alternately stacked distal horizontal surfaces, and the metal material layers comprising the first portion of the metal material and covering the source barrier pads; and The connection pad includes a layer stack of pad blocking pads and pad metal portions, the pad blocking pads contacting the distal horizontal surface of the dielectric material portion, and the pad metal portion comprising the second portion of the metal material.

20. The semiconductor structure of claim 19, wherein the source barrier pad and the pad barrier pad have the same material composition and the same thickness.

21. The semiconductor structure according to claim 16, wherein: The vertical semiconductor channel is doped with a first conductivity type; and The conductive material comprises a doped semiconductor material having a second conductivity type opposite to the first conductivity type.

22. The semiconductor structure according to claim 21, wherein: The first portion of the conductive material contacts the distal horizontal surface of the alternating stacks; and The second portion of the conductive material contacts the distal horizontal surface of the dielectric material portion.

23. The semiconductor structure according to claim 22, wherein: The source layer further includes a stack of a source barrier pad and a metal material layer, wherein the source barrier pad contacts the distal surface of the first portion of the conductive material, and the metal material layer contains the first portion of the metal material and covers the source barrier pad; and The connection pad also includes a layer stack of pad blocking pads and pad metal portions, the pad blocking pads contacting the distal surface of a second portion of the conductive material, and the pad metal portions comprising the second portion of the metal material.

24. The semiconductor structure according to claim 23, wherein the through-hole structure comprises: A metal barrier layer, the metal barrier layer being in contact with the sidewalls of the second portion of the conductive material and the dielectric material portion; and The metal filler portion is spaced apart from the connection pad and the dielectric material portion by the metal barrier layer.

25. The semiconductor structure according to claim 16, wherein: The connection pads include a metallic portion; and At least one back-side dielectric layer contacts the distal surface of the metal material portion and extends over the source layer.

26. The semiconductor structure according to claim 16, wherein: The source layer includes a first layer stack, the first layer stack including a doped semiconductor material layer and a metal source layer, the doped semiconductor material layer including the first portion of the conductive material, and the metal source layer contacting the distal surface of the doped semiconductor material layer; and The connection pads include a stack of semiconductor connection pads and metal connection pads, the semiconductor connection pads containing the second portion of the conductive material, and the metal connection pads contacting the distal surface of the semiconductor connection pads.

27. The semiconductor structure according to claim 26, wherein: The metal source layer includes a source barrier pad and a metal material layer, the source barrier pad contacts the doped semiconductor material layer, and the metal material layer includes a first portion of metal material and contacts the source barrier pad; and The metal connection pad includes a pad blocking pad and a pad metal portion, the pad blocking pad contacting the semiconductor connection pad, and the pad metal portion containing a second portion of the metal material.

28. The semiconductor structure according to claim 16, further comprising: At least one back-side dielectric layer covering the source layer and the connection pads; and A back-side bonding pad or bonding line extends through the at least one back-side dielectric layer, contacts the distal surface of the bonding pad, and is electrically isolated from the source layer.

29. The semiconductor structure of claim 16, wherein the distal portion of the through-hole structure protrudes from a horizontal plane including the horizontal interface between the connection pad and the dielectric material portion in a vertical direction pointing away from the interface between the logic die and the memory die.

30. A method for forming a semiconductor structure, the method comprising: A memory die is formed on a substrate, wherein the memory die includes: a memory stack structure extending vertically through alternating stacks of insulating and conductive layers; a dielectric material portion contacting the sidewalls of the alternating stacks; and a through-hole structure extending vertically through the dielectric material portion, wherein each memory stack structure in the memory stack structure includes a corresponding vertical semiconductor channel and a corresponding memory film; After removing the carrier substrate, the distal ends of each vertical semiconductor channel and the distal ends of the through-hole structure are physically exposed. Simultaneously depositing conductive material on the material at the distal end of each vertical semiconductor channel in the vertical semiconductor channel and on the distal end of the through-hole structure; and The conductive material is patterned into multiple portions, wherein a source layer comprising a first portion of the conductive material is formed on the distal end of each vertical semiconductor channel in the vertical semiconductor channel, and a connection pad comprising a second portion of the conductive material is formed on the through-hole structure and electrically isolated from the source layer.

31. The method of claim 30, wherein the conductive material comprises a layer stack, the layer stack comprising a metal barrier pad layer and a continuous metal material layer.

32. The method of claim 30, wherein: The vertical semiconductor channel comprises a doped semiconductor material having a first conductivity type; and The conductive material comprises a layer of continuously doped semiconductor material having a second conductivity type that is opposite to the first conductivity type.

33. The method of claim 32, further comprising: A stack of layers, including a metal barrier pad layer and a continuous metal material layer, is deposited directly on the distal surface of the continuous doped semiconductor material layer. as well as The same etch mask is used to pattern the layer stack and the conductive material, wherein the source layer includes a first remaining portion of the layer stack, and the connection pads include a second remaining portion of the layer stack.

34. The method of claim 32, further comprising implanting a dopant of the second conductivity type into the material at the distal end of each of the vertical semiconductor channels to form a source cap region having dopant of the second conductivity type, wherein the source layer is formed directly on the source cap region.

35. The method of claim 30, wherein: The memory die includes a first bonding structure electrically connected to the memory stack structure and the conductive layer; and The method includes: A logic die is provided, the logic die including a semiconductor device and a second bonding structure electrically connected to the semiconductor device; When the carrier substrate is attached to the memory die, the logic die is attached to the memory die by bonding the second bonding structure to the first bonding structure; and After the logic die is attached to the memory die, the carrier substrate is separated from the memory die.

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