Gallium oxide diode device and method of making the same

Abstract

The application is suitable for the technical field of semiconductor device manufacturing, and provides a gallium oxide diode device and a preparation method thereof. The method comprises the following steps: cleaning a gallium oxide epitaxial layer, depositing a dielectric layer above the epitaxial layer; spin-coating photoresist above the dielectric layer, heating the photoresist to make the photoresist reflow to form an inclined surface; etching the photoresist and the dielectric layer, and removing the photoresist; taking the dielectric layer as a mask, etching the gallium oxide epitaxial layer and the dielectric layer; spin-coating photoresist above the plane of the dielectric layer; covering a metal mask above the gallium oxide diode device, removing the photoresist and the dielectric layer; sputtering a P-NiO material to form a P-NiO layer, and stripping the metal mask; and electron beam evaporation of metal to obtain a cathode and an anode. The application provides a new preparation method for the gallium oxide diode device.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor device manufacturing, and particularly relates to a gallium oxide diode device and a preparation method thereof. BACKGROUND

[0002] In recent years, super-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices, and are expected to replace traditional Si-based power devices in certain specific fields. However, the mirror force-induced barrier reduction effect is a bottleneck problem that limits the characteristics of gallium oxide Schottky diodes. Due to the great difficulty of P-type injection of gallium oxide, the strict requirement of field plate structure on dielectric quality, and the dielectric reliability problem, it is imperative to develop a new terminal structure.

[0003] The angle grinding terminal is one of the important terminal technologies for improving the power diode. The conventional preparation method is to first prepare a P-type layer by injection or epitaxy, and then realize the angle grinding terminal by small-angle inclined angle etching technology. However, gallium oxide lacks P-type doping technology, and cannot realize the angle grinding terminal by the above-mentioned method. Therefore, it is urgent to develop a new gallium oxide diode device preparation technology to realize the gallium oxide angle grinding terminal structure and improve the device voltage resistance. SUMMARY

[0004] The gallium oxide diode device and the preparation method thereof are provided in the embodiments of the application to realize a new preparation method of the gallium oxide diode device.

[0005] The application is realized by the following technical solutions:

[0006] In a first aspect, the embodiments of the application provide a gallium oxide diode device preparation method, comprising:

[0007] Depositing a dielectric layer on the upper surface of the gallium oxide epitaxial layer;

[0008] Preparing a first shielding layer on the dielectric layer, and the vertical section of the first shielding layer is trapezoidal;

[0009] Etching the dielectric layer and the first shielding layer to expose the gallium oxide epitaxial layer, form a dielectric bevel with an angle less than or equal to 10°, and remove the first shielding layer;

[0010] Etching the gallium oxide epitaxial layer and the dielectric layer with the dielectric layer as a mask to form a gallium oxide epitaxial layer bevel with an angle less than or equal to 10°;

[0011] Preparing a metal mask layer on the gallium oxide epitaxial layer and the bevel of the dielectric layer;

[0012] Removing the dielectric layer, preparing a P-NiO layer on the gallium oxide epitaxial layer and the metal mask layer, and removing the metal mask layer;

[0013] A first electrode is prepared on the upper surface of the P-NiO layer, a gallium oxide substrate is prepared on the lower surface of the gallium oxide epitaxial layer, and a second electrode is prepared on the lower surface of the gallium oxide substrate.

[0014] With reference to the first aspect, in some possible implementation manners, the material of the first shielding layer is photoresist; the first shielding layer is prepared on the dielectric layer, and a vertical section of the first shielding layer is in the shape of a trapezoid, including: spin-coating photoresist on the dielectric layer to form a first photoresist layer; performing photoetching, exposure and development operations on the first photoresist layer to obtain a first pattern area; and high-temperature heating the first pattern area to make the first photoresist layer reflow to form an inclined surface.

[0015] With reference to the first aspect, in some possible implementation manners, the metal mask layer is prepared on the gallium oxide epitaxial layer and the inclined surface of the dielectric layer, including: preparing a second shielding layer on the upper surface of the dielectric layer, the material of the second shielding layer being photoresist, and a vertical section of the second shielding layer being in the shape of a rectangle; preparing the metal mask layer on the gallium oxide epitaxial layer, the inclined surface of the dielectric layer and the upper surface of the second shielding layer; and removing the second shielding layer.

[0016] With reference to the first aspect, in some possible implementation manners, the material of the dielectric layer is SiO2 or SiN.

[0017] With reference to the first aspect, in some possible implementation manners, the dielectric layer and the first shielding layer are etched to expose the gallium oxide epitaxial layer, to form a dielectric inclined surface with an inclined surface angle less than or equal to 10°, including: by adjusting the ICP etching power and the proportion of etching gases SF6 and O2, the etching rate of the first shielding layer and the dielectric layer is adjusted, the gallium oxide epitaxial layer is exposed, the angle of the dielectric inclined surface is controlled, and the dielectric inclined surface with the inclined surface angle less than or equal to 10° is formed.

[0018] With reference to the first aspect, in some possible implementation manners, the gallium oxide epitaxial layer and the dielectric layer are etched with the dielectric layer as a mask, to form a gallium oxide epitaxial layer inclined surface with an inclined surface angle less than or equal to 10°, including: by adjusting the ICP etching power and the etching gas pressure, the etching rate of the gallium oxide epitaxial layer is made equal to the etching rate of the dielectric layer, and the gallium oxide epitaxial layer inclined surface with the inclined surface angle less than or equal to 10° is formed.

[0019] With reference to the first aspect, in some possible implementation manners, when the gallium oxide epitaxial layer is etched with the dielectric layer as a mask, part of the plane of the gallium oxide epitaxial layer is reserved.

[0020] With reference to the first aspect, in some possible implementation manners, the metal mask is obtained by electron beam evaporation or sputtering metal.

[0021] In a second aspect, the embodiment of the present application provides a gallium oxide diode device, comprising: a gallium oxide substrate; a gallium oxide epitaxial layer formed on the upper surface of the gallium oxide substrate, the gallium oxide epitaxial layer being in a convex shape on the side away from the gallium oxide substrate, and the angle of the convex surface being less than or equal to 10°; a P-NiO layer formed on the convex part of the gallium oxide epitaxial layer; a first electrode formed on the P-NiO layer; and a second electrode formed on the lower surface of the gallium oxide substrate.

[0022] Compared with the prior art, the embodiment of the present application has the following beneficial effects:

[0023] The present application forms a small-angle gallium oxide inclined surface and a P-type layer of the gallium oxide diode device by means of medium deposition, etching, covering a metal mask, sputtering a P-NIO material, and the like, thereby obtaining the gallium oxide diode device, providing a new preparation method for the gallium oxide diode device, and realizing a gallium oxide angle grinding terminal structure and improving the voltage resistance of the device.

[0024] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0026] Figure 1 is a flowchart of a gallium oxide diode device preparation method provided by an embodiment of the present application;

[0027] Figure 2 is a schematic diagram of a gallium oxide diode device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0028] In the following description, specific details such as specific system structures, techniques, etc. are presented in order to thoroughly understand the embodiments of the present application, but it should be understood by those skilled in the art that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits and methods are omitted to avoid unnecessary details that hinder the description of the present application.

[0029] It should be understood that the word “comprise” or variations such as “comprises” or “comprising”, when used in this specification and in the accompanying claims, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] It should also be understood that the term “and / or” when used in this specification and in the following claims is intended to mean one or the other or both of the associated listed items and that no combinations of one or more items included in the processes, methods, systems or computer readable media are intended to be excluded.

[0031] As used in this specification and in the claims, the terms “if’ and “when” can be interpreted to mean “upon” or “in response to a determination” or “in response to a detection” depending on the context. Similarly, the phrase “if it is determined” or “if [a described condition or event] is detected” can be interpreted to mean “upon determining” or “in response to a determining” or “upon detecting [the described condition or event]” or “in response to a detection [of the described condition or event]” depending on the context.

[0032] In addition, in the description of the application and in the following claims, the terms “first”, “second”, “third”, etc. are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0033] Reference in the specification to “one embodiment” or “some embodiments” or “an embodiment” or “some implementations” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, the appearances of the phrases “in one embodiment”, “in some embodiments”, “in other embodiments”, “in additional embodiments”, and so on, in various places in the specification are not necessarily all referring to the same embodiment, unless otherwise specifically noted. The terms “comprise”, “comprises”, “comprising”, “include”, “includes”, “including” and their variants are meant to be construed as “including but not limited to”, unless otherwise specifically noted.

[0034] In recent years, super-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices, and are expected to replace traditional Si-based power devices in certain specific fields. However, the mirror force-induced barrier reduction effect is a bottleneck problem that limits the characteristics of gallium oxide Schottky diodes. Due to the great difficulty of P-type injection of gallium oxide, the strict requirements of field plate structure on dielectric quality, and the dielectric reliability problem, it is imperative to develop new terminal structures.

[0035] Grinding angle terminal is one of the important terminal technologies of the power diode, and the conventional preparation method is to first prepare a P-type layer by injection or epitaxy, and then realize the grinding angle terminal by small angle inclined angle etching technology. However, gallium oxide lacks P-type doping technology, and cannot realize the grinding angle terminal by the above method, so it is urgent to develop a new gallium oxide diode device preparation technology to realize the gallium oxide grinding angle terminal structure and improve the device voltage resistance.

[0036] Based on the above problems, the gallium oxide diode device preparation method in the embodiment of the application forms a small-angle gallium oxide bevel and a P-type layer of a gallium oxide diode device through medium deposition, etching, covering a metal mask, sputtering P-NIO material and other means, obtains a gallium oxide diode device, provides a new preparation method for the gallium oxide diode device, realizes the gallium oxide grinding angle terminal structure, and improves the device voltage resistance.

[0037] Figure 1 is a schematic flowchart of the gallium oxide diode device preparation method provided by an embodiment of the application, and Figure 1 The gallium oxide diode device preparation method is described in detail as follows.

[0038] In step 101, a medium layer is deposited on the upper surface of the gallium oxide epitaxial layer.

[0039] For example, after the gallium oxide epitaxial layer is cleaned, the medium layer is deposited on the upper surface of the gallium oxide epitaxial layer.

[0040] For example, the material of the medium layer is SiO2 or SiN.

[0041] In step 102, a first shielding layer is prepared on the medium layer, and the vertical section of the first shielding layer is trapezoidal.

[0042] For example, the material of the first shielding layer is photoresist; the first shielding layer is prepared on the medium layer, and the vertical section of the first shielding layer is trapezoidal, including: spin coating photoresist on the medium layer to form a first photoresist layer; performing photoetching, exposure and development operations on the first photoresist layer to obtain a first pattern area; high-temperature heating the first pattern area to make the first photoresist layer reflow to form a bevel.

[0043] In step 103, the medium layer and the first shielding layer are etched to expose the gallium oxide epitaxial layer, form a medium bevel with an angle less than or equal to 10°, and remove the first shielding layer.

[0044] Exemplarily, etching the dielectric layer and the first shielding layer to expose the gallium oxide epitaxial layer to form a dielectric bevel with a bevel angle less than or equal to 10° includes: adjusting the ICP etching power and the ratio of etching gases SF6 and O2, adjusting the etching rate of the first shielding layer and the dielectric layer to expose the gallium oxide epitaxial layer, controlling the angle of the dielectric bevel, and forming a dielectric bevel with a bevel angle less than or equal to 10°.

[0045] In step 104 , the gallium oxide epitaxial layer and the dielectric layer are etched using the dielectric layer as a mask to form a bevel of the gallium oxide epitaxial layer with a bevel angle less than or equal to 10°.

[0046] Exemplarily, using the dielectric layer as a mask, etching the gallium oxide epitaxial layer and the dielectric layer to form a bevel of the gallium oxide epitaxial layer with a bevel angle less than or equal to 10°, including: adjusting the ICP etching power and the etching gas pressure so that the etching rate of the gallium oxide epitaxial layer is equal to the etching rate of the dielectric layer, thereby forming a bevel of the gallium oxide epitaxial layer with a bevel angle less than or equal to 10°.

[0047] Exemplarily, the optimal range of the bevel angle for forming the gallium oxide epitaxial layer is less than or equal to 5°.

[0048] Illustratively, when the gallium oxide epitaxial layer is etched using the dielectric layer as a mask, a portion of the plane of the gallium oxide epitaxial layer is retained.

[0049] In step 105 , a metal mask layer is formed on the gallium oxide epitaxial layer and on the inclined surface of the dielectric layer.

[0050] Exemplarily, a metal mask layer is prepared on the inclined surfaces of the gallium oxide epitaxial layer and the dielectric layer, including: preparing a second shielding layer on the upper surface of the dielectric layer, the second shielding layer being made of photoresist, and the vertical cross-section of the second shielding layer being rectangular; preparing a metal mask layer on the gallium oxide epitaxial layer, on the inclined surface of the dielectric layer, and on the upper surface of the second shielding layer; and removing the second shielding layer.

[0051] Illustratively, the metal mask is formed by electron beam evaporation or sputtering of metal.

[0052] In step 106 , the dielectric layer is removed, a P-NiO layer is formed on the gallium oxide epitaxial layer and the metal mask layer, and the metal mask layer is removed.

[0053] In step 107 , a first electrode is formed on the upper surface of the P-NiO layer, a gallium oxide substrate is formed on the lower surface of the gallium oxide epitaxial layer, and a second electrode is formed on the lower surface of the gallium oxide substrate.

[0054] For example, when preparing the first electrode on the upper surface of the P-NiO layer, it is necessary to spin-coat photoresist, then perform photolithography, exposure, and development operations on the photoresist to obtain the second pattern area, and then electron beam evaporate the electrode material to obtain the first electrode.

[0055] Exemplarily, the second electrode is formed by electron beam evaporation of an electrode material on the lower surface of the gallium oxide substrate.

[0056] Exemplarily, the material used for the first electrode and the second electrode also includes a semiconductor material.

[0057] The gallium oxide diode device preparation method described above forms a small-angle gallium oxide bevel and a P-type layer of the gallium oxide diode device through medium deposition, etching, covering a metal mask, sputtering P-NiO material, and the like, obtains the gallium oxide diode device, provides a new preparation method for the gallium oxide diode device, realizes a gallium oxide angle polishing terminal structure, and improves the device voltage resistance.

[0058] Optionally, Figure 2 The gallium oxide diode device prepared by the method of the embodiment, the gallium oxide diode device includes: a gallium oxide substrate 4; a gallium oxide epitaxial layer 3 formed on the upper surface of the gallium oxide substrate 4, the side of the gallium oxide epitaxial layer 3 away from the gallium oxide substrate 4 is in a boss shape, and the bevel angle of the boss shape is less than or equal to 10°; a P-NiO layer 2 formed on the boss-shaped part of the gallium oxide epitaxial layer 3; a first electrode 1 formed on the P-NiO layer 2; and a second electrode 5 formed on the lower surface of the gallium oxide substrate 4.

[0059] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the application.

[0060] It should be noted that the information interaction, execution process and the like between the above devices / units, since the same concept as the method embodiment of the application, the specific functions and the technical effects brought by it, specific can refer to the method embodiment part, here will not be repeated.

[0061] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above-mentioned division of each functional unit and module is exemplified, and in actual application, the above-mentioned functions can be completed by different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be realized in the form of hardware or software. In addition, the specific names of each functional unit and module are only for easy distinction, and do not limit the protection scope of the present application. The specific working process of the units and modules in the above system can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0062] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described or recorded in detail in a certain embodiment can be referred to the related description of other embodiments.

[0063] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware or a combination of computer software and electronic hardware. Whether the functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0064] In the embodiments provided in the present application, it should be understood that the disclosed apparatus / network device and method can be implemented in other ways. For example, the above-described apparatus / network device embodiments are only schematic, for example, the division of the modules or units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed mutually can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0065] The units described as separate components can or can not be physically separated, and the components shown as units can or can not be physical units, that is, they can be located in one place, or can be distributed on a plurality of network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0066] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for preparing a gallium oxide diode device, characterized in that: include: Depositing a dielectric layer on the upper surface of the gallium oxide epitaxial layer; preparing a first shielding layer on the dielectric layer, wherein the vertical cross-section of the first shielding layer is trapezoidal; Etching the dielectric layer and the first shielding layer to expose the gallium oxide epitaxial layer, forming a dielectric bevel with a bevel angle less than or equal to 10°, and removing the first shielding layer; Using the dielectric layer as a mask, etching the gallium oxide epitaxial layer and the dielectric layer to form a bevel of the gallium oxide epitaxial layer with a bevel angle less than or equal to 10°; wherein, when etching the gallium oxide epitaxial layer using the dielectric layer as a mask, a portion of the plane of the gallium oxide epitaxial layer is retained; preparing a metal mask layer on the gallium oxide epitaxial layer and on the inclined surface of the dielectric layer; removing the dielectric layer, forming a P-NiO layer on the gallium oxide epitaxial layer and the metal mask layer, and removing the metal mask layer; A first electrode is prepared on the upper surface of the P-NiO layer, a gallium oxide substrate is prepared on the lower surface of the gallium oxide epitaxial layer, and a second electrode is prepared on the lower surface of the gallium oxide substrate.

2. The method for preparing a gallium oxide diode device according to claim 1, wherein: The material of the first shielding layer is photoresist; The first shielding layer is prepared on the dielectric layer, wherein the vertical cross-section of the first shielding layer is trapezoidal, and comprises: Spin-coating photoresist on the dielectric layer to form a first photoresist layer; Performing photolithography, exposure, and development operations on the first photoresist layer to obtain a first pattern area; The first pattern area is heated at a high temperature to cause the first photoresist layer to reflow and form an inclined surface.

3. The method for preparing a gallium oxide diode device according to claim 1, wherein: The step of preparing a metal mask layer on the inclined surfaces of the gallium oxide epitaxial layer and the dielectric layer comprises: A second shielding layer is prepared on the upper surface of the dielectric layer, wherein the second shielding layer is made of photoresist and has a rectangular vertical cross-section; preparing a metal mask layer on the gallium oxide epitaxial layer, on the inclined surface of the dielectric layer, and on the upper surface of the second shielding layer; The second shielding layer is removed.

4. The method for preparing a gallium oxide diode device according to claim 1, wherein: The dielectric layer is made of SiO2 or SiN.

5. The method for preparing a gallium oxide diode device according to claim 1, wherein: The etching of the dielectric layer and the first shielding layer to expose the gallium oxide epitaxial layer and form a dielectric bevel with a bevel angle less than or equal to 10° includes: By adjusting the ICP etching power and the ratio of etching gases SF6 and O2, the etching rates of the first shielding layer and the dielectric layer are adjusted to expose the gallium oxide epitaxial layer, and the angle of the dielectric bevel is controlled to form a dielectric bevel with a bevel angle less than or equal to 10°.

6. The method for preparing a gallium oxide diode device according to claim 1, wherein: The step of etching the gallium oxide epitaxial layer and the dielectric layer using the dielectric layer as a mask to form a bevel of the gallium oxide epitaxial layer having a bevel angle less than or equal to 10° comprises: By adjusting the ICP etching power and the etching gas pressure, the etching rate of the gallium oxide epitaxial layer is made equal to the etching rate of the dielectric layer, forming a bevel of the gallium oxide epitaxial layer with a bevel angle less than or equal to 10°.

7. The method for preparing a gallium oxide diode device according to claim 6, wherein: When the gallium oxide epitaxial layer is etched using the dielectric layer as a mask, a portion of the plane of the gallium oxide epitaxial layer is retained.

8. The method for preparing a gallium oxide diode device according to claim 1, wherein: The metal mask layer is obtained by electron beam evaporation or metal sputtering.

9. A gallium oxide diode device, characterized in that: The gallium oxide diode device is prepared by the method for preparing the gallium oxide diode device according to any one of claims 1 to 8, comprising: Gallium oxide substrate; A gallium oxide epitaxial layer is formed on the upper surface of the gallium oxide substrate, wherein the side of the gallium oxide epitaxial layer away from the gallium oxide substrate is in a convex shape, and the angle of the convex shape is less than or equal to 10°; wherein the gallium oxide epitaxial layer still has a partially flat surface; A P-NiO layer formed on the terrace-shaped portion of the gallium oxide epitaxial layer; a first electrode formed on the P-NiO layer; The second electrode is formed on the lower surface of the gallium oxide substrate.

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