A high-voltage-resistant enhanced double-heterojunction gate HEMT and a preparation method thereof

Abstract

The application relates to a high-voltage-resistant reinforced double-heterojunction gate HEMT and a preparation method thereof, which comprises a nucleation layer, a buffer layer, a p-type buried layer, a channel layer, an insertion layer and a barrier layer which are sequentially stacked on a substrate, and a double-heterojunction gate, a source and a drain are arranged on the barrier layer, wherein the double-heterojunction gate is composed of a PNP double-heterojunction cap layer and a gate metal layer on the double-heterojunction cap layer. The double-heterojunction gate in the device is in contact with the barrier layer, can deplete the two-dimensional electron gas of the channel, makes the threshold voltage of the device increase, and when the device wants to reach the conduction state, the PNP double-heterojunction serves as two face-to-face diodes, the two diodes consume a certain voltage drop, makes the voltage reaching the channel layer decrease, and further makes the threshold voltage of the device increase, and the PNP double-heterojunction can prevent the electrons from entering the channel layer from the gate, thereby reducing the gate leakage current and improving the breakdown voltage of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a high-voltage enhancement-mode double heterojunction gate HEMT and a preparation method thereof. BACKGROUND

[0002] In order to adapt to the increasing power density, working frequency, high temperature adaptability, switching speed and voltage application range requirements of power electronic systems, power electronic devices with high power and high working frequency have gradually become a research hotspot in the field of power semiconductors. GaN-based HEMT makes full use of the advantages of GaN material such as high band gap, high thermal conductivity, high critical breakdown field strength, etc., and gradually becomes the mainstream of power devices and has a wide and promising application prospect. However, in actual circuit application, the conventional GaN-based HEMT device needs a negative voltage power supply to turn off the device, which not only increases the risk of circuit misopening, but also increases the power consumption of the entire circuit. Therefore, the enhancement-mode GaN-based HEMT device is more suitable for the design of power electronic circuits, and is a research hotspot and a difficult problem to be solved at present.

[0003] In addition, for power electronic devices, high breakdown voltage can expand the potential application range of GaN HEMT, so another research focus of GaN-based HEMT devices is to improve the breakdown voltage of the device. In the common AlGaN / GaN HEMT, because of the factors such as gate leakage, buffer layer leakage, and electric field concentration effect near the edge of the gate and drain, the device will often be broken down in advance, and has not reached the theoretical limit of GaN material, which limits the large-scale application of GaN-based HEMT devices. SUMMARY

[0004] The application provides a high-voltage enhanced double heterojunction gate HEMT with high threshold voltage, high breakdown voltage and low leakage current and a preparation method thereof. The HEMT device has higher threshold voltage, smaller gate leakage current and higher breakdown voltage by introducing the double heterojunction gate. The PNP type double heterojunction structure is grown on the barrier layer, and the p-type nitride material in contact with the barrier layer can deplete the two-dimensional electron gas (2DEG) of the channel, so that the threshold voltage of the device is increased. At the same time, the PNP type double heterojunction can be regarded as two facing diodes, when the device reaches the on state, the two diodes will consume a certain voltage drop, so that the voltage reaching the channel layer is reduced, and a higher gate voltage is required to make the device conduct, that is, the threshold voltage of the device is further increased. In addition, the setting of the PNP type double heterojunction can prevent electrons from entering the channel layer from the gate, thereby reducing the gate leakage current and improving the breakdown voltage of the device. On the other hand, the device of the application introduces a p-type buried layer on the buffer layer, which improves the energy band of the channel layer and the buffer layer, prevents electrons from entering the buffer layer, thereby reducing the leakage current of the buffer layer and further improving the voltage resistance characteristics of the device.

[0005] In order to achieve the above-mentioned purpose, the application adopts the following technical scheme:

[0006] A high-voltage enhanced double heterojunction gate HEMT, comprising: a substrate, a nucleation layer, a buffer layer, a p-type buried layer, a channel layer, an insertion layer and a barrier layer which are sequentially stacked on the substrate, wherein a double heterojunction gate, a source electrode and a drain electrode are arranged on the barrier layer, and the double heterojunction gate is composed of a PNP double heterojunction cap layer and a gate metal layer on the double heterojunction cap layer.

[0007] The PNP double heterojunction cap layer is composed of a P-type nitride and an N-type nitride, the hole concentration of the P-type nitride is 1E17-1E18, and the thickness of the N-type nitride is 50-100 nm.

[0008] The thickness of the P-type nitride is 50-100 nm, and the thickness of the N-type nitride is 50-100 nm.

[0009] The p-type buried layer is selected from a p-type nitride, the hole concentration of the p-type nitride is 1E17-1E18, and the thickness of the p-type nitride is 50-200 nm.

[0010] The P-type nitride and the N-type nitride are selected from one of GaN, AlGaN, InGaN, AlInN and AlInGaN.

[0011] The source electrode and the drain electrode extend to a certain depth in the barrier layer.

[0012] The double heterojunction gate is located between the source electrode and the drain electrode, and a passivation layer is arranged between the double heterojunction gate and the source electrode and the drain electrode.

[0013] The channel layer is GaN channel layer, the thickness is 100-500nm; the insertion layer is AlN insertion layer, the thickness is 1-2nm; the barrier layer is AlGaN barrier layer, the thickness is 15-30nm.

[0014] The buffer layer is GaN buffer layer, AlGaN buffer layer or AlInGaN buffer layer, the thickness is 2-5μm; the nucleation layer is AlN nucleation layer, the thickness is 15-50nm.

[0015] The passivation layer is SiNx, SiO2, HfO2 or Al2O3.

[0016] A preparation method of a high-voltage-enhanced double-heterojunction gate HEMT, comprising the following steps:

[0017] Magnetron sputtering an AlN nucleation layer on a substrate;

[0018] Epitaxially growing a buffer layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a P-type nitride layer, an N-type nitride layer and a P-type nitride layer on the AlN nucleation layer in sequence, the P-type nitride layer, the N-type nitride layer and the P-type nitride layer forming a PNP double-heterojunction layer;

[0019] Etching the PNP double-heterojunction epitaxial layer to form a PNP double-heterojunction cap layer;

[0020] Depositing a passivation layer;

[0021] Etching a specific region of the passivation layer to form source / drain openings extending to a certain depth of the barrier layer;

[0022] Depositing a metal layer at the source / drain openings to form ohmic-contact source / drain electrodes;

[0023] Etching the passivation layer above the PNP double-heterojunction cap layer to form a gate opening;

[0024] Depositing a metal layer at the gate opening to form a Schottky-contact gate electrode. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a HEMT device structure schematic diagram of an embodiment of the present application.

[0026] Figure 2 is a transfer characteristic diagram of a HEMT device of an embodiment of the present application.

[0027] Figure 3 is a HEMT device schematic diagram of an embodiment of the present application.

[0028] Figure 4is a breakdown characteristic diagram of the HEMT device of an embodiment of the present application.

[0029] Figure 5 is a process flow diagram of the HEMT device of an embodiment of the present application. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings of the present application. The described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, other embodiments obtained by those skilled in the art without creative efforts are within the scope of the present application. In the following embodiments, the experimental methods are conventional methods unless otherwise specified, and the reagents and materials are commercially available unless otherwise specified.

[0031] Spatially relative terms such as "beneath", "below", "lower", "above", "upper", and the like, are used to describe an element's position relative to another element as illustrated in the figures. These terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0032] In addition, terms such as "first", "second", and the like are used to describe various elements, layers, regions, sections, and the like, and are not intended to be limiting. The use of "have", "has", "including", "comprising", "consisting", and the like, are open-ended terms that are intended to mean that the elements or features being described are present, but not excluding additional elements or features. Unless the context clearly indicates otherwise.

[0033] As Figure 1 An embodiment of the present application provides a high-voltage-enhanced double-heterojunction gate HEMT, which comprises a substrate 1, a nucleation layer 2, a buffer layer 3, a p-type buried layer 4, a channel layer 5, an insertion layer 6, and a barrier layer 7 on the substrate 1, a PNP double-heterojunction cap layer 8, a source electrode 10, and a drain electrode 11 provided on the barrier layer 7, and a passivation layer 9 provided between the double-heterojunction cap layer 8 and the source electrode 10 and the drain electrode 11.

[0034] The nucleation layer 2 is selected to be an AlN nucleation layer, and the thickness thereof is selected to be 15 nm to 50 nm, and preferably, the thickness thereof is 15 nm. The buffer layer 3 is selected to be a GaN buffer layer, an AlGaN buffer layer, or an AlInGaN buffer layer, and preferably, the buffer layer 3 is selected to be a GaN buffer layer. The thickness of the buffer layer 3 is 2-5 μm, and preferably, the thickness thereof is 2.6 μm.

[0035] The p-type buried layer 4 is selected to be a p-type nitride, and the hole concentration thereof is 1E17-1E18, and the thickness thereof is 50-200 nm, and preferably, the thickness thereof is 100 nm. The channel layer 5 is preferably a GaN channel layer, and the thickness thereof is 100-500 nm.

[0036] The insertion layer 6 is an AlN insertion layer, and the thickness is 1-2 nm, preferably, the thickness is 1 nm. The barrier layer 7 is an AlGaN barrier layer, and the thickness is 15-30 nm, preferably, the thickness is 20 nm, and the Al component is 24%.

[0037] The PNP double heterojunction cap layer 8 is composed of a P-type nitride and an N-type nitride, and the thickness of the P-type nitride is 50-100 nm, and the thickness of the N-type nitride is 50-100 nm. The hole concentration of the P-type nitride is 1E17-1E18, and the thickness of the N-type nitride is 50-100 nm. As shown in the figure, the PNP double heterojunction cap layer 8 is composed of a P-type nitride layer 8-1, an N-type nitride layer 8-2, and a P-type nitride layer 8-3, which form two facing diodes. When the device needs to reach the on state, the two diodes will consume a certain voltage drop, so that the voltage reaching the channel layer is reduced. At this time, a higher gate voltage is needed to make the device conduct, that is, the threshold voltage of the device is further improved. Figure 1

[0038] The gate metal 12 is arranged on the PNP double heterojunction cap layer 8 to form a PNP double heterojunction gate. As shown in the figure, the source 10 and the drain 11 are arranged on the two sides of the double heterojunction gate, and in a preferred embodiment, the source 10 and the drain 11 extend to a certain depth in the barrier layer 7. The PNP double heterojunction gate is close to the source 10. Figure 1

[0039] Based on the above-mentioned high-voltage enhanced double heterojunction gate HEMT device structure, referring to Figure 5 , the preferred embodiment of the present application also provides a preparation method of the device, which has a simple process flow, high feasibility, and good stability of the prepared device. The method comprises the following steps:

[0040] S1, a sapphire substrate 1 is selected, and the sapphire substrate is sequentially placed in acetone, ethanol, and deionized water for ultrasonic cleaning for 12 minutes, then washed with deionized water, and finally dried with N2 to remove pollutants on the surface of the substrate.

[0041] S2, the cleaned substrate is placed in a reaction furnace and vacuumized until the vacuum degree is 5x10 -3 Pa. Ar gas is introduced, and the Al target is pre-sputtered for 10 min. Then, nitrogen gas is introduced, the gas pressure is 6.5x10 -2 Pa, the sputtering voltage is 360 V, the substrate is aligned with the Al target, and the deposition of the AlN nucleation layer 2 starts, and the thickness is 15 nm.

[0042] ​​S3, MOCVD process is selected, and trimethylaluminum (TMAl) is used as aluminum source, trimethylgallium (TMGa) is used as gallium source, ammonia (NH3) is used as nitrogen source, and Cp2Mg is used as magnesium source. A 2.6 μm GaN buffer layer 3, a 100 nm P-type buried layer 4, a 400 nm GaN channel layer 5, a 1 nm AlN insertion layer 6, a 20 nm AlGaN barrier layer 7, a 50 nm first p-GaN layer 8-1, a 50 nm n-GaN layer 8-2, and a 50 nm second p-GaN layer 8-3 are sequentially grown on the AlN nucleation layer. The first p-GaN layer 8-1, the n-GaN layer 8-2, and the second p-GaN layer 8-3 form a double heterojunction layer 8.

[0043] S4, an inductively coupled plasma etching (ICP) process is used to etch a selected region of the double heterojunction layer 8 to the surface of the AlGaN barrier layer 7, forming a double heterojunction cap layer.

[0044] S5, an ion enhanced chemical vapor deposition (PECVD) process is selected to deposit a SiNx passivation layer 9 on the surface of the AlGaN barrier layer 7 and the surface of the double heterojunction layer 8.

[0045] S6, an inductively coupled plasma etching (ICP) process is used to etch a selected region of the SiNx passivation layer 9 to form source and drain openings, which extend to a certain depth of the barrier layer.

[0046] S7, an electron beam evaporation process is used to deposit Ti / Al / Ni / Au metal electrodes at the source and drain openings, respectively, and then rapid annealing is performed at 850°C in a nitrogen atmosphere for 40 s to form ohmic contact source 10 and drain 11.

[0047] S8, an inductively coupled plasma etching (ICP) process is used to etch the double heterojunction cap layer region of the SiNx passivation layer 9 to form a gate opening.

[0048] S9, an electron beam evaporation process is used to deposit a Ni / Au metal electrode at the gate opening, and then annealing is performed at a temperature of 30°C for 10 min in a nitrogen atmosphere to form a Schottky contact gate.

[0049] The device structure of the preferred embodiment is selected, and the performance of the device is tested. Figure 2 The transfer characteristic diagram of the preferred embodiment HEMT device is shown in the figure. As can be seen from the figure, the threshold voltage of the device can reach 8.4 V. It can be seen that due to the introduction of the PNP double heterojunction layer, the p-type nitride material in contact with the barrier layer can deplete the two-dimensional electron gas (2DEG) of the channel, so that the threshold voltage of the device is increased. At the same time, the Figure 3As shown in the device principle diagram, the PNP type double heterojunction itself can be regarded as forming two face-to-face diodes, when the device wants to reach the on state, the two diodes will consume a certain voltage drop, so that the voltage reaching the channel layer is reduced. Therefore, a higher gate voltage is needed to make the device conduct, that is, the threshold voltage of the device is further improved.

[0050] Figure 4 The breakdown characteristic diagram of the preferred embodiment HEMT device is shown. Due to the introduction of the PNP type double heterojunction and the p-type buried layer, not only the gate leakage current is reduced, but also the buffer layer leakage current is reduced (as shown in Figure 3 ), so the voltage withstanding characteristic of the device is improved. As can be seen from Figure 4 , the breakdown voltage of the device can reach 2227V.

[0051] The above embodiment is the preferred embodiment of the present application, but the implementation of the present application is not limited by the above embodiment, any change, modification, replacement, combination, simplification made without departing from the spirit and principles of the present application should be an equivalent replacement method, which is included in the protection scope of the present application.

Claims

1. A high-voltage resistant enhancement-mode double heterojunction gate HEMT, characterized by, include: A sapphire substrate is provided with an AlN nucleation layer, a GaN buffer layer, a p-type buried layer, a GaN channel layer, an AlN insertion layer, and an AlGaN barrier layer stacked sequentially on the substrate. The Al composition of the AlGaN barrier layer is 24%, and its thickness is 15-30 nm. A source and drain electrode, as well as a double heterojunction gate electrode between the source and drain electrode, are disposed on the barrier layer. A passivation layer is disposed between the double heterojunction gate electrode and the source and drain electrode. The double heterojunction gate electrode consists of a PNP double heterojunction cap layer and a gate metal layer located on the double heterojunction cap layer. The PNP double heterojunction cap layer is composed of P-type nitride, N-type nitride, and P-type nitride stacked sequentially. The hole concentration of the P-type nitride electrode is 1E17-1E18, and its thickness is 50-100 nm. The thickness of the N-type nitride electrode is 50-100 nm. The p-type buried layer is a p-type nitride with a hole concentration of 1E17~1E18 and a thickness of 50~200nm.

2. The double heterojunction gate HEMT of claim 1, characterized in that, The P-type nitride and N-type nitride are selected from GaN, AlGaN, InGaN, AlInN, and AlInGaN.

3. The double hetero-gate HEMT according to claim 1 or 2, characterized in that, The source and the drain extend to a certain depth in the barrier layer.

4. The double heterojunction gate HEMT according to claim 1 or 2, characterized in that, The thickness of the GaN channel layer is 100~500nm; the thickness of the AlN insertion layer is 1~2nm.

5. The double heterojunction gate HEMT of claim 3, characterized in that, The thickness of the buffer layer is 2~5μm; the thickness of the AlN nucleation layer is 15~50nm.

6. The double heterojunction gate HEMT of claim 3, wherein, The passivation layer is SiNx, SiO2, HfO2 or Al2O3.

7. A method for manufacturing a high-voltage resistant enhancement-mode double heterojunction gate HEMT, characterized by, Includes the following steps: A nucleation layer of AlN is magnetron sputtered onto the substrate; A GaN buffer layer, a p-type buried layer, a GaN channel layer, an AlN insertion layer, an AlGaN barrier layer, a p-type nitride layer, an N-type nitride layer, and a p-type nitride layer are sequentially epitaxially grown on an AlN nucleation layer. The Al composition of the AlGaN barrier layer is 24%, and its thickness is 15-30 nm. The p-type nitride layer, the N-type nitride layer, and the p-type nitride layer form a PNP double heterojunction layer. The hole concentration of the p-type nitride is 1E17-1E18, and its thickness is 50-100 nm. The thickness of the N-type nitride is 50-100 nm. The p-type buried layer is a p-type nitride with a hole concentration of 1E17-1E18 and a thickness of 50-200 nm. Etching the PNP double heterojunction layer forms a PNP double heterojunction cap layer; Deposition of passivation layer; Etch a specific area of ​​the passivation layer to form source / drain openings extending to a certain depth into the barrier layer; Deposit a metal layer at the source / drain opening to form an ohmic contact source / drain; Etching the passivation layer above the PNP double heterojunction cap layer forms a gate opening; A metal layer is deposited at the gate opening to form a Schottky contact gate. The gate and the PNP double heterojunction cap layer form a double heterojunction gate located between the source and drain. A passivation layer is located between the double heterojunction gate and the source and drain.

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