Refresh operations on dedicated blocks of memory cells

Abstract

Apparatus and techniques are described for periodically refreshing the wordline voltages of blocks in a memory device. In one aspect, each block stores the same number of bits per cell. For example, one block may be reserved for single-level cell (SLC) data, and another block may be reserved for multi-level cell (MLC) data. A common refresh voltage signal may be applied to the blocks in a group, where the voltage signal is optimized based on the number of bits stored by the memory cells of the group. For SLC blocks, the refresh voltage signal may reduce the floating voltage of the wordline. For MLC blocks, the refresh voltage signal may increase the floating voltage of the wordline.

Description

Background Art

[0001] The present technology relates to the operation of storage devices and memory devices.

[0002] Semiconductor memory devices have become increasingly common in a variety of electronic devices. For example, nonvolatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials (such as floating gates) or charge-trapping materials can be used in such memory devices to store charge that represents a data state. The charge-trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is the bit-cost scalable (BiCS) architecture, which includes a stack of alternating conductive and dielectric layers.

[0004] For example, memory devices include memory cells that may be arranged in blocks. However, there are various challenges in operating such memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A is a block diagram of an exemplary storage device.

[0006] Figure 1B Shown Figure 1A An example of a temperature sensing circuit 116 is shown.

[0007] Figure 2 It shows Figure 1A A block diagram of one embodiment of the sensing block 51 is shown.

[0008] Figure 3A Depicts Figure 1A An exemplary implementation of a power control circuit 115 for providing voltages to a block of memory cells is shown, wherein separate voltage drivers are provided for n bits per cell and m bits per block of cells.

[0009] Figure 3B Exemplary voltage drivers consistent with voltage drivers 350 and 352 are depicted for selected blocks.

[0010] Figure 3C Exemplary voltage drivers consistent with voltage drivers 351 and 353 are depicted for unselected blocks.

[0011] Figure 3D Depicts Figure 1A Another exemplary implementation of the power control circuit 115 for providing voltage to a block of memory cells is provided, wherein a common voltage driver is provided for n bits per cell and m bits per block of cells.

[0012] Figure 3E Depicts the Figures 3A to 3D An example of active blocks 357a and passive blocks 357b-357d in a consistent group of blocks.

[0013] Figure 3F Depicts Figure 3A 1 and 2. Further exemplary details of the pre-switched control line 325, the pass transistor 322, and the post-switched control line 303 are shown in FIG.

[0014] Figure 4 In an exemplary 3D configuration, Figure 3A 1 is a perspective view of a memory device 400 of blocks BLK0-BLK7.

[0015] Figure 5 An exemplary transistor 520 is depicted.

[0016] Figure 6 Shown Figure 4 FIG. 1 is an exemplary cross-sectional view of a portion of block BLK0 including NAND strings 700 n and 710 n .

[0017] Figure 7A Depicts the Figure 4 and Figure 6 An exemplary view of NAND strings in consistent block BLKO.

[0018] Figure 7B Shows the connection to Figure 7A An exemplary view of the memory cells of WL3 in sub-block SB0 of FIG. 1 , with corresponding NAND strings, bit lines, and sensing circuits.

[0019] Figure 8A Depicted are exemplary Vth distributions for SLC memory cells storing one bit per cell.

[0020] Figure 8B Depicted are exemplary Vth distributions for an MLC memory cell storing two bits per cell.

[0021] Figure 8C Depicted are exemplary Vth distributions for an MLC memory cell storing three bits per cell.

[0022] Figure 9A Plotted is the average upper tail Vth of erased state memory cells as a function of the number of read operations.

[0023] Figure 9B Graphs are plotted showing the Fail Bit Count (FBC) or number of read errors as a function of the number of read operations for an SLC memory cell (curve 910) and an MLC memory cell (curve 911).

[0024] Figure 10A Plotted are the average upper tail Vth of erased-state SLC memory cells as a function of the number of read operations for unselected blocks in a bank and different refresh voltages.

[0025] Figure 10B Depicts the Figure 10A Consistent curves of average upper tail Vth of erased-state SLC memory cells as a function of number of read operations for a selected block in a group and different refresh voltages.

[0026] Figure 10C Another example of a graph depicting the average upper tail Vth of erased-state SLC memory cells as a function of the number of read operations for unselected blocks in a bank and different refresh voltages is depicted.

[0027] Figure 10D Depicts the Figure 10C Another example of a consistent curve of average upper tail Vth of erased-state SLC memory cells as a function of number of read operations for a selected block in a bank and different refresh voltages.

[0028] Figure 11A A flow chart of an exemplary process for refreshing word line voltages in a bank is depicted.

[0029] Figure 11B Depicts Figure 1A Used for Figure 11A An exemplary table of the refresh voltage signal setting circuit 119 of step 1107.

[0030] Figure 12A Depicts the Figure 11A A first example of voltage signals in a consistent read operation.

[0031] Figure 12B Depicts the Figure 11A A second example of voltage signals in a consistent read operation.

[0032] Figure 13 Examples of word line voltages during refresh operations are depicted for high, medium, and low amplitude refresh voltages.

[0033] Figure 14A Examples of word line voltages during a read operation and a refresh operation with a high magnitude refresh voltage Vread are depicted.

[0034] Figure 14B Examples of word line voltages during a read operation and a refresh operation with a medium magnitude refresh voltage Vint are depicted.

[0035] Figure 14CExamples of word line voltages during a read operation and a refresh operation with a low-amplitude refresh voltage Vss are depicted.

[0036] Figure 15 Depicts the Figure 3A Example of selected block BLK0 and unselected block BLK1 in the consistent group block GRP0. DETAILED DESCRIPTION

[0037] Apparatus and techniques are described for periodically refreshing word line voltages of blocks in a memory device.

[0038] In a memory device, memory cells may be arranged in a Figure 4 Memory cells may be joined to each other in NAND strings, such as Figure 7A As depicted. Furthermore, memory cells can be arranged in 2D or 3D structures. In a 3D memory structure, memory cells can be arranged in stacked vertical NAND strings, where the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connected to the memory cells. Each NAND string can have a pillar shape that intersects the word lines to form a memory cell. In a 2D memory structure, memory cells can be arranged in horizontal NAND strings on a substrate. The memory cells in a block can undergo programming, reading, and erasing operations.

[0039] Each memory cell can be associated with a data state according to the write data in the program command. Based on the data state of the memory cell, the memory cell will remain in the erased state or be programmed to the programmed data state. For example, in a block of one bit per cell, there are two data states, including an erased state and a programmed state. See Figure 8A In a two-bit per cell block, there are four data states, including an erased state and three higher data states, which are referred to as the A, B, and C data states. Figure 8B In a three-bit per cell block, there are eight data states, including an erased state and seven higher data states, which are referred to as the A, B, C, D, E, F, and G data states. Figure 8C In a four-bit-per-cell block, there are sixteen data states, including the erased state and fifteen higher data states. Blocks with a single bit per cell are called single-level cell (SLC) blocks, while blocks with multiple bits per cell are called multi-level cell (MLC) blocks.

[0040] After programming the memory cell, the data can be read back in a read operation. A read operation can involve applying a series of read voltages to a selected word line while a sense circuit determines whether the cell connected to the selected word line is in a conductive state (on) or a non-conductive state (off). If the cell is in a non-conductive state, the Vth of the memory cell exceeds the read voltage. The read voltage is set to a level that is expected to be between the threshold voltages of adjacent data states. During a read operation, a read pass voltage (Vread), such as 8-9V, is applied to the unselected word lines to provide the associated memory cells in a strongly conductive state.

[0041] However, when the memory cell is idle, the Vth of the memory cell can change between programming or reading operations based on changes in the word line voltage. In particular, the word line voltage can rise from the channel coupling of the NAND string. For example, in one possible coupling rise mechanism, a pass voltage is applied to the unselected word line during a sensing operation such as a read operation or a verify test for a programming operation, and then ramped down to 0V. This ramp down causes a downward coupling of the channel voltage. See, for example, Figure 12A Curves 1231 and Figure 12B The falling coupling then dissipates and the channel voltage increases to a nominal level, close to 0V, while the word line voltage is floating. See, for example, Figure 12A Curves 1232 and Figure 12B This results in the word line voltage coupling rising to a positive voltage such as about 4-5 V. See, for example, Figure 12A Curve 1204 and Figure 12B 1244 in FIG. A positive word line voltage is desirable because it tends to keep the Vth of the memory cell at a stable level. Over time, such as a few minutes, the word line voltage discharges, causing the Vth of the memory cell to shift. See FIG. Figures 8A-8C .

[0042] When the wordline voltage of a block is discharged, the block is in a first read or cold read state. This occurs when the memory device is powered on or when the coupled-up wordline voltage has discharged after a sensing operation. When the wordline voltage of a block is coupled-up, the block is in a second read or hot read state. This can occur only after a sensing operation has been performed.

[0043] Refresh operations may be performed periodically to maintain a positive word line voltage during idle times.A refresh operation may involve applying a refresh voltage signal to the word line at a pass voltage level and then floating the word line voltage.

[0044] However, a type of disturbance known as delayed read disturb (DRD) can increase the upper tail Vth of erased state memory cells, such as Figures 8A to 8C、 Figure 9A and 10A to 10D As depicted in Figure 2, uncorrectable read errors may result. This disturbance is caused by a coupled rising word line voltage that provides weak programming of erased-state memory cells. DRD is a function of various factors, such as the number of read operations, the time period between consecutive read operations, the number of program-erase (PE) cycles, and the operating temperature of the memory device. DRD is particularly severe for heavily cycled blocks and accelerates in severity at higher temperatures. DRD is also more severe for SLC blocks than for MLC blocks.

[0045] The technology provided herein solves the above and other problems. In one aspect, each block stores the same number of bits per cell. For example, one block is reserved for SLC data and another block is reserved for MLC data. In another example, one block is reserved for three bits per cell and another block is reserved for four bits per cell.

[0046] Group blocks are related blocks because they can be selected simultaneously by a common group selection signal. See e.g. Figure 3A 、 Figure 3D and Figure 3F . Group blocks are configured in this manner to provide a more efficient layout on the memory device. A common refresh voltage signal can be applied to blocks in a group that is optimized based on the number of bits per cell stored by the memory cells of the group. For example, the amplitude of the refresh voltage signal for an SLC block can be lower than that for an MLC block. For an SLC block, the refresh voltage signal can reduce the floating voltage of the word line. For an MLC block, the refresh voltage signal can increase the floating voltage of the word line. For another example, the duration of the refresh voltage signal for an SLC block can be longer than that for an MLC block.

[0047] The optimization can also be performed based on the temperature and the number of PE cycles. For example, when the number of PE cycles is higher, the amplitude can also be lower. Figure 11B The amplitude can range from high voltages (such as the read pass voltage) to intermediate voltages, to 0V and even negative voltages. Figure 13 .

[0048] In one possible scenario, one block in the group is selected for a read operation, while the remaining blocks in the group are not selected and receive a refresh voltage signal. In another possible scenario, each block in the group receives a refresh voltage signal. The refresh voltage signal can be periodically applied to the blocks in the group.

[0049] These and other features are discussed further below.

[0050] Figure 1Ais a block diagram of an exemplary memory device. A memory device 100, such as a non-volatile memory system, may include one or more memory dies 108. The memory die 108 or chip includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. The memory structure 126 is addressable via word lines via a set of row decoders 124 and via bit lines via column decoders 132. The read / write circuitry 128 includes a plurality of sense blocks 51, 52, ..., 53 (sense circuits) and allows pages of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 as the one or more memory dies 108 (e.g., a removable memory card). The controller may be separate from the memory dies. Commands and data are transmitted between a host 140 and the controller 122 via a data bus 120, and between the controller and the one or more memory dies 108 via line 141.

[0051] The memory structure may be a 2D memory structure or a 3D memory structure. The memory structure may include one or more arrays of memory cells, the one or more arrays of memory cells comprising a 3D array. The memory structure may include a monolithic 3D memory structure in which multiple memory levels are formed above (rather than in) a single substrate (such as a wafer) without an intermediate substrate. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels having an array of memory cells with active areas disposed above a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above or within the substrate.

[0052] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126 and includes a state machine, an on-chip address decoder 114, a power control module 115 (power control circuitry), a temperature sensing circuit 116, a timing circuit 117, a PE cycle counter circuit 118, and a refresh voltage signal setting circuit 119. A storage area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, the state machine is programmed by software. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry).

[0053] An on-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. A power control module 115 controls the power and voltages provided to the word lines, select gate lines, bit lines, and source lines during memory operations. The power control module may include drivers for the word lines, SGS and SGD transistors, and source lines. See also Figures 3A to 3F In one approach, the sensing block may include a bit line driver. The temperature sensing circuit 116 may detect the temperature of the memory device during its useful life (e.g., every minute). The timing circuit 117 may count time and determine when the elapsed time has elapsed for initiating a refresh operation of the block as discussed herein. For example, see Figure 11A Group 1107 in.

[0054] The PE cycle counting circuit 118 can track the number of program-erase (PE) cycles of a block and classify the block into categories based on the number of PE cycles. For example, a block can be classified into a first category, a second category, and a third category representing the beginning, middle, and end of the life of the block, respectively. The classification of SLC blocks can be different from the classification of MLC blocks because SLC blocks can generally experience more PE cycles than MLC blocks in their life. In addition, blocks can be reclassified periodically, and the number of blocks in each group can change over time. In another example, blocks are classified based on whether the number of PE cycles is above or below a threshold. See, for example, Figure 11B The thresholds P-E_th1 and P-E_th2 in .

[0055] The refresh voltage signal setting circuit 119 can set the optimal characteristics of the refresh voltage signal for the group of blocks involved in the refresh operation based on the number of bits per cell stored in the block. The characteristics can include amplitude and timing. For example, see Figure 13 Circuit 119 may also use information from circuits 116-118 to set an optimal refresh voltage amplitude. For example, circuit 119 may evaluate the number of PE cycles for a block by comparing the number of PE cycles to a threshold value, such as P-E_th1 for SLC blocks and P-E_th2 for MLC blocks. Figure 11B Circuit 119 may also take into account the temperature from temperature sensing circuit 116 .

[0056] An example implementation of the temperature sensing circuit is shown in Figure 1B Circuits 116 - 119 may include hardware, software, and / or firmware for performing the processes described herein.

[0057] In some implementations, some of the components may be combined. In various designs, one or more of the components other than the memory structure 126 (alone or in combination) may be considered to be at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any one of the control circuit 110, the state machine 112, the decoders 114 and 132, the power control module 115, the temperature sensing circuit 116, the timing circuit 117, the PE cycle count circuit 118, the refresh voltage signal setting circuit 119, the sense blocks 51, 52...53, the read / write circuit 128, the controller 122, etc., or any combination thereof.

[0058] The off-chip controller 122 (in one embodiment, a circuit) may include a processor 122e, memory such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct many read errors. RAM 122b may be a DRAM that includes a storage location 122c for uncommitted data. During programming, a copy of the data to be programmed is stored in the storage location 122c until programming is successfully completed. In response to successful completion, the data is erased from the storage location and committed or released to the memory cell block. The storage location 122c may store one or more word lines of data.

[0059] A memory interface 122d may also be provided. The memory interface, which communicates with the ROM, RAM, and processor, is a circuit that provides an electrical interface between the controller and the memory die. For example, the memory interface may change the format or timing of signals, provide a buffer, isolate power surges, latch I / O, etc. The processor may issue commands to the control circuitry 110 (or any other component of the memory die) via the memory interface 122d.

[0060] The memory in the controller 122, such as ROM 122a and RAM 122b, includes code, such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively or in addition, the processor may access code from a subset 126a of the memory structure, such as a reserved area of ​​memory cells in one or more word lines.

[0061] For example, the controller can use code to access the memory structure, such as for programming operations, read operations and erase operations. The code may include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller and enables the controller to access the memory structure during the boot or startup process. The controller can use code to control one or more memory structures. When powered on, the processor 122e takes out the boot code from ROM 122a or subgroup 126a for execution, and the boot code initializes the system components and loads the control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes a driver that performs basic tasks, such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0062] A controller, such as RAM 122b and / or control circuitry 110, may store parameters indicating the expected number of failing bits in a block. These parameters may include, for example, the number of bits per cell stored in the memory cell, the portion of word lines programmed in a block or sub-block, the portion of sub-blocks programmed in a block, the strength of the ECC process used to store and read data in the block, the duration of the pre-read voltage pulse (if used), and read accuracy, such as bit line or word line voltage stabilization time and the number of sensing passes.

[0063] Generally speaking, the control code may include instructions for performing the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below. The control circuitry may be configured to execute instructions for performing the functions described herein.

[0064] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smartphone, a tablet computer, a digital camera) that includes one or more processors, one or more processor-readable memory devices (RAM, ROM, flash memory, hard drive, solid-state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0065] In addition to NAND flash memory, other types of non-volatile memory may be used.

[0066] Semiconductor memory devices include volatile memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices, non-volatile memory devices such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM) and magnetoresistive random access memory (MRAM), as well as other semiconductor elements capable of storing information. Each type of memory device can have a different configuration. For example, a flash memory device can be configured in a NAND configuration or a NOR configuration.

[0067] The memory device may be formed from any combination of passive and / or active components. By way of non-limiting example, passive semiconductor memory components include ReRAM device components, which in some embodiments include a resistivity switching memory element, such as an antifuse or phase change material, and an optional steering element, such as a diode or transistor. Additionally, by way of non-limiting example, active semiconductor memory components include EEPROM and flash memory device components, which in some embodiments include components containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.

[0068] Multiple memory elements can be configured so that they are connected in series or so that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically includes memory elements connected in series. A NAND string is an example of a group of series-connected transistors that includes a memory cell and an SG transistor.

[0069] A NAND memory array can be configured so that the array is composed of multiple strings of memory, where a string is composed of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0070] The semiconductor memory elements located in and / or on the substrate may be arranged in two or three dimensions, such as a 2D memory structure or a 3D memory structure.

[0071] In a 2D memory structure, semiconductor memory elements are arranged in a single plane or in a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an xy-oriented plane) that extends substantially parallel to the main surface of a substrate supporting the memory elements. The substrate can be a wafer on or in which the layers of memory elements are formed, or it can be a carrier substrate to which the memory elements are attached after they are formed. As a non-limiting example, the substrate can include a semiconductor, such as silicon.

[0072] The memory elements can be arranged in a single memory device level in an ordered array, such as in multiple rows and / or columns. However, the memory elements can be arranged in an unconventional or non-orthogonal configuration. The memory elements can each have two or more electrodes or contact lines, such as a bit line and a word line.

[0073] The 3D memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, wherein the z direction is substantially perpendicular to the major surface of the substrate, and the x and y directions are substantially parallel to the major surface of the substrate).

[0074] As a non-limiting example, a 3D memory structure can be arranged vertically as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as a plurality of vertical columns (e.g., columns substantially perpendicular to the major surface of the substrate, i.e., extending in the y-direction), wherein each column has a plurality of memory elements. These columns can be arranged in a 2D configuration, for example, in the xy plane, resulting in a 3D arrangement of memory elements, wherein the elements are located on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0075] By way of non-limiting example, in a 3D NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings that span multiple horizontal memory device levels. Other 3D configurations are contemplated, in which some NAND strings contain memory elements in a single memory level, while other strings contain memory elements that span multiple memory levels. 3D memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.

[0076] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, a monolithic 3D memory array may also have one or more memory layers located at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layers of each memory device level that make up the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic 3D memory array may be shared between memory device levels or have intermediate layers between memory device levels.

[0077] 2D arrays can be formed separately and then packaged together to form a non-monolithic memory device with multiple layers of memory. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrate can be thinned or removed from the memory device levels before stacking, but because the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. In addition, multiple 2D memory arrays or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0078] Typically, associated circuitry is required to operate and communicate with the memory elements. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory elements to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory elements.

[0079] Those skilled in the art will recognize that the technology is not limited to the described 2D and 3D exemplary structures, but encompasses all related memory structures within the spirit and scope of the technology as described herein and as understood by those skilled in the art.

[0080] Figure 1B Shown Figure 1A An example of a temperature sensing circuit 116 is shown. This circuit includes pMOSFETs 131a, 131b, and 134, bipolar transistors 133a and 133b, and resistors R1, R2, and R3. I1, I2, and I3 represent currents. Voutput is the temperature-dependent output voltage provided to analog-to-digital (ADC) converter 129. Vbg is a temperature-independent voltage. Voltage level generation circuit 135 uses Vbg to set multiple voltage levels. For example, a reference voltage can be divided into several levels using a resistor divider circuit.

[0081] The ADC compares Voutput to the voltage levels and selects the closest match in voltage level and outputs the corresponding digital value (VTemp) to the processor 122e. This is data indicating the temperature of the memory device. In one approach, the ROM fuse 123 stores data that correlates the matching voltage level with the temperature. The processor then uses the temperature to set temperature-based parameters in the memory device, such as by utilizing a comparison circuit.

[0082] Vbg is obtained by adding the base-emitter voltage (Vbe) across transistor 131b and the voltage drop across resistor R2. Bipolar transistor 133a has a larger area (factor N) than transistor 133b. PMOS transistors 131a and 131b are equal in size and arranged in a current mirror configuration so that currents I1 and I2 are substantially equal. It follows that Vbg = Vbe + R2 × I2 and I1 = Ve / R1, so I2 = Ve / R1. Therefore, Vbg = Vbe + R2 × kT ln(N) / R1 × q, where T is temperature, k is the Boltzmann constant, and q is the unit of charge. The source of transistor 134 is connected to the supply voltage Vdd, and the node between the drain of the transistor and resistor R3 is the output voltage Voutput. The gate of transistor 134 is connected to the same terminal as the gates of transistors 131 a and 131 b , and the current through transistor 134 mirrors the current through transistors 131 a and 131 b .

[0083] Figure 2 It shows Figure 1A FIG1 is a block diagram of one embodiment of a sense block 51 of FIG1 . The individual sense blocks 51 are divided into one or more core portions called sense circuits 60-63 or sense amplifiers and a common portion called management circuit 190. In one embodiment, each sense circuit is connected to a corresponding bit line and NAND string, and the common management circuit 190 is connected to a group of multiple (e.g., four or eight) sense circuits. Each sense circuit in the group communicates with an associated management circuit via a data bus 176. Thus, there are one or more management circuits in communication with the sense circuits of a group of storage elements (memory cells).

[0084] For example, the sensing circuit 60 operates during a programming cycle to provide a precharge / program-inhibit voltage to an unselected bit line or a program-enable voltage to a selected bit line. The unselected bit line is connected to an unselected NAND string and an unselected memory cell therein. The unselected memory cell can be a memory cell in an unselected NAND string, where the memory cell is connected to a selected or unselected word line. The unselected memory cell can also be a memory cell in a selected NAND string, where the memory cell is connected to an unselected word line. The selected bit line is connected to a selected NAND string and a selected memory cell therein.

[0085] The sensing circuit 60 also operates during a verify test in a programming cycle to sense a memory cell to determine whether it has completed programming by reaching an assigned data state (e.g., as indicated by its Vth exceeding the verify voltage for the assigned data state). The sensing circuit 60 also operates during a read operation to determine the data state to which the memory cell has been programmed. The sensing circuit performs sensing by determining whether the conduction current in the connected bit line is above or below a predetermined threshold level. This indicates whether the Vth of the memory cell is below or above the word line voltage, respectively.

[0086] The sensing circuit may include a selector 56 or switch connected to a transistor 55 (e.g., nMOS). Based on the voltages at the control gate 58 and drain 57 of transistor 55, the transistor may operate as a pass gate or a bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage on the drain, the transistor operates as a pass gate to pass the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, a program inhibit voltage such as 1V-2V may be passed when precharging and inhibiting unselected NAND strings. Alternatively, a program enable voltage such as 0V may be passed to allow programming in the selected NAND string. The selector 56 may pass a power supply voltage Vdd (e.g., 3V-4V) to the control gate of transistor 55 to cause it to operate as a pass gate.

[0087] When the voltage at the control gate is lower than the voltage on the drain, transistor 55 operates as a source follower to set or clamp the bit line voltage at Vcg-Vth, where Vcg is the voltage on the control gate 58 and Vth (e.g., 1V) is the threshold voltage of transistor 55. This assumes that the source line is at 0V. This mode can be used during sensing operations such as read and verify operations. Therefore, transistor 55 sets the bit line voltage based on the voltage output by selector 56. For example, selector 56 can pass Vbl_sense+Vth (e.g., 1.5V) to transistor 55 to provide Vbl_sense (e.g., 0.5V) on the bit line. Vbl selector 173 can pass a relatively high voltage such as Vdd to the drain 57 to provide a source follower mode during sensing operations, wherein the relatively high voltage is higher than the control gate voltage on transistor 55.

[0088] The Vbl selector 173 may pass one or more voltage signals. For example, the Vbl selector may pass a program-inhibit voltage signal that increases from an initial voltage (e.g., 0V) to a program-inhibit voltage (e.g., a voltage Vbl_inh for corresponding bit lines of unselected NAND strings during a programming cycle). The Vbl selector 173 may pass a program-enable voltage signal, such as 0V, for corresponding bit lines of a selected NAND string during a programming cycle. For example, the Vbl selector may select a bit line from the selected NAND string based on a command from the processor 192. Figure 3A The voltage signal of the BL voltage driver 340 in FIG.

[0089] In one approach, the selector 56 of each sense circuit can be controlled separately from the selectors of the other sense circuits. The Vbl selector 173 of each sense circuit can also be controlled separately from the Vbl selectors of the other sense circuits.

[0090] During sensing, the sense node 171 is charged to an initial voltage Vsense_init, such as 3V. The sense node is then transferred to the bit line via transistor 55, and the attenuation of the sense node is used to determine whether the memory cell is in a conductive state or a non-conductive state. Specifically, the comparison circuit 175 determines the attenuation by comparing the sense node voltage with the trip voltage during sensing. If the sense node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is equal to or lower than the verification voltage. If the sense node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is higher than the verification voltage. For example, the sense node latch 172 is set to 0 or 1 by the comparison circuit 175 based on whether the memory cell is in a conductive state or a non-conductive state, respectively. The data in the sense node latch can be a bit that is read by the processor 192 and used to update the trip latch 174. Subsequently, for the next programming cycle, the processor can use the bit in the trip latch and the assigned data states in latches 194-197 to determine whether the memory cell and NAND string is selected or not selected for programming in the programming cycle, thereby passing the appropriate enabling or inhibiting bit line voltage to the bit line, respectively. Latches 194-197 can be considered data latches or user data latches because they store the data to be programmed into the memory cell.

[0091] Management circuit 190 includes a processor 192, four exemplary sets of data latches 194-197 for sensing circuits 60-63, respectively, and an I / O interface 196 coupled between the sets of data latches and data bus 120. A set of three data latches can be provided for each sensing circuit, for example, including separate latches LDL, MDL, and UDL. In some cases, a different number of data latches can be used. In a three-bit per cell embodiment, LDL stores bits for lower page data, MDL stores bits for middle page data, and UDL stores bits for upper page data.

[0092] Processor 192 performs calculations to determine the data stored in the sensed memory cells and stores the determined data in the set of data latches. Each set of data latches 194-197 is used to store data bits determined by processor 192 during a read operation and to store data bits imported from data bus 120 during a program operation, representing write data to be programmed into the memory. I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

[0093] During reads, the system's operation is controlled by a state machine 112, which controls the application of different control gate voltages to the addressed memory cells. As it steps through various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuit can trip at one of these voltages, and the corresponding output will be provided from the sense circuit to the processor 192 via data bus 176. At this point, the processor 192 determines the resulting memory state by considering the trip event of the sense circuit and information about the control gate voltage applied via input line 193 from the state machine. It then calculates the binary encoding of the memory state and stores the resulting data bits in data latches 194-197.

[0094] Some specific implementations may include multiple processors 192. In one embodiment, each processor 192 will include an output line (not shown) so that each output line is wired ORed together. In some embodiments, the output lines are inverted before being connected to the wired OR line. This configuration makes it possible to quickly determine when the programming process is complete during the program verification test because the state machine receiving the wired OR can determine when all programmed bits have reached the desired level. For example, when each bit reaches its desired level, a logic zero for that bit will be sent to the wired OR line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sense circuits, the state machine needs to read the wired OR line eight times, or logic is added to the processor 192 to accumulate the results of the relevant bit lines so that the state machine only needs to read the wired OR line once. Similarly, by properly selecting the logic levels, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0095] During a program or verify operation of a memory cell, the data to be programmed (write data) is stored in the set of data latches 194-197 from the data bus 120. During reprogramming, a corresponding set of data latches of a memory cell may store data indicating when to enable reprogramming of the memory cell based on the programming pulse magnitude.

[0096] Under the control of the state machine, the programming operation applies a series of programming pulses to the control gates of the addressed memory cells. The amplitude of each programming pulse can be gradually increased by one step from the previous programming pulse during the process, which is called incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the readback memory state relative to the desired memory state. When the two are consistent, the processor 192 sets the bit line to program inhibit mode, such as by updating its latch. This inhibits the memory cell coupled to the bit line from further programming, even if additional programming pulses are applied to its control gate.

[0097] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some implementations, the data latches are implemented as shift registers so that parallel data stored therein is converted to serial data for the data bus 120, and vice versa. All of the data latches corresponding to a read / write block of memory cells can be connected together to form a block shift register so that data blocks can be input or output via serial transmission. Specifically, the read / write circuit module group is arranged so that its data latch group shifts data into or out of the data bus in sequence, just as if they were part of a shift register for the entire read / write block.

[0098] The data latch indicates when the associated memory cell reaches certain milestones of the programming operation. For example, the latch can identify that the Vth of the memory cell is below a specific verification voltage. The data latch indicates whether the memory cell is currently storing one or more bits from a page of data. For example, the LDL latch can be used to store the next page of data. When the next page bit is stored in the associated memory cell, the LDL latch is flipped (e.g., from 0 to 1). For three bits per cell, when the middle or upper page bit, respectively, is stored in the associated memory cell, the MDL or UDL latch is flipped. This occurs when the associated memory cell completes programming.

[0099] Figure 3A Depicts Figure 1AFIG1 is an exemplary implementation of a power control circuit 115 for providing voltage to a block of memory cells, wherein separate voltage drivers are provided for n bits per cell and m bits per block of cells. In one approach, the circuit shown may be repeated for each plane of the die. In this example, the memory structure 126 includes a first block GRP0, which includes blocks BLK0 to BLK3, and a second block GRP1, which includes blocks BLK4 to BLK7. In one approach, the GRP0 block is reserved for storing n bits per cell, and the GRP1 block is reserved for storing m>n bits per cell. For example, GRP0 may have SLC cells (n=1) and GRP1 may have three-level MLC cells (m=3). In another example, GRP0 may have three-level MLC cells (n=3) and GRP1 may have four-level MLC cells (m=4). n and m are positive integers. For simplicity, two blocks are depicted, but in practice, there may be more blocks in the memory device. The blocks may be in one or more planes.

[0100] Figure 1A The set of row decoders 124 includes a row decoder that is configured to provide a voltage to the word line and select gate control line of each block via a pass transistor 322 (switch). The set of row decoders can include a corresponding row decoder for each block. For example, row decoders RD0-RD3 are provided for blocks BLK0-BLK3 in GRP0, respectively, and row decoders RD4-RD7 are provided for blocks BLK4-BLK6 in GRP1, respectively. Each row decoder can provide a voltage signal on a pre-switched control line 325 located before the pass transistor, for example, between the row decoder and the pass transistor. If the pass transistor is turned on, the signal is passed to the corresponding word line, for example, after the switch, for example as a post-switched control line 303.

[0101] For example, in GRP0, BLK0 has a pre-switched control line 313a located before the pass transistor 313, and a post-switched control line 313b located after the pass transistor 313. BLK1 has a pre-switched control line 314a located before the pass transistor 314, and a post-switched control line 314b located after the pass transistor 314. BLK2 has a pre-switched control line 315a located before the pass transistor 315, and a post-switched control line 315b located after the pass transistor 315. BLK3 has a pre-switched control line 316a located before the pass transistor 316, and a post-switched control line 316b located after the pass transistor 314.

[0102] In GRP1, BLK4 has a pre-switched control line 317a located before the pass transistor 317, and a post-switched control line 317b located after the pass transistor 317. BLK5 has a pre-switched control line 318a located before the pass transistor 318, and a post-switched control line 318b located after the pass transistor 318. BLK6 has a pre-switched control line 319a located before the pass transistor 319, and a post-switched control line 319b located after the pass transistor 319. BLK7 has a pre-switched control line 320a located before the pass transistor 320, and a post-switched control line 320b located after the pass transistor 320.

[0103] The control circuitry can provide a group select signal to a pass transistor that connects the block to the corresponding row decoder. In one approach, the group select signal is connected to the control gate of the pass transistor of the block. A group of blocks can be selected at a time by asserting the corresponding group select signal to provide the pass transistor in a conductive state. The pass transistors of the block are either all on or all off at a given time. If the pass transistor is on (conductive), the corresponding word line of the block provides the voltage from the row decoder of the block. If the pass transistor is off (non-conductive), the corresponding row decoder of the block is disconnected from the corresponding word line, allowing the voltage on the corresponding word line to float.

[0104] For example, a first set of select signals for GRP0 can be provided on a first set of select lines 323, which in turn are connected to a plurality of sets of pass transistors 313-316, e.g., switches that are respectively connected to word lines and select gate lines of BLK0-BLK3. Similarly, a second set of select signals for GRP1 can be provided on a second set of select lines 312, which in turn are connected to a plurality of sets of pass transistors 317-320, which in turn are respectively connected to word lines and select gate lines of BLK4-BLK7.

[0105] The row decoder can connect the voltage signal on the global control line 302 to the pre-switched control line of each block and ultimately to the post-switched control line such as the word line. Voltages from multiple voltage drivers such as drivers 350-353 are provided on the global control line.

[0106] In an exemplary implementation, separate voltage drivers are provided for n bits per cell and m bits per block of cells. Additionally, within each group, separate voltage drivers are provided for selected and unselected blocks. For example, in GRP0, a voltage driver 350 is provided for n bits per selected cell, and a voltage driver 351 is provided for n bits per unselected cell. The voltage signal provided by voltage driver 350 is referred to as CG0 to indicate the selected control gates of the memory cells of GRP0. The voltage signal provided by voltage driver 351 is referred to as UCG0 to indicate the unselected control gates of the memory cells of GRP0.

[0107] Similarly, in GRP1, a voltage driver 352 is provided for selected m bits per cell block, and a voltage driver 353 is provided for unselected m bits per cell block. The voltage signal provided by the voltage driver 352 is referred to as CG1 to indicate the selected control gates of the memory cells of GRP1. The voltage signal provided by the voltage driver 353 is referred to as UCG1 to indicate the unselected control gates of the memory cells of GRP1. Figure 3B is an exemplary voltage driver among the voltage drivers 350 and 352 for the selected block, and Figure 3C ⊂ is an exemplary voltage driver among the voltage drivers 351 and 353 for unselected blocks.

[0108] In some cases, due to the capacitance of the word line, the delay of the word line voltage may change based on the change in voltage on the global control line 302 and the pre-switched control line 325. If the pass transistor is turned off too soon, in some cases the timing requirement may not be met and the word line voltage may not reach the voltage on the global control line 302 and the pre-switched control line 325. For example, see Figure 12B Curves 1243 and 1243a in FIG.

[0109] The various components comprising the row decoders can receive commands from a controller, such as the state machine 112 or the controller 122, to perform the functions described herein. Each read decoder can be configured to route the appropriate refresh voltage signal to the word line of the corresponding block. In one approach, one block receives the refresh voltage signal at a time. In another approach, multiple blocks with the same number of bits per cell receive a common refresh voltage signal simultaneously. In another approach, one or more blocks with n bits per cell receive a first refresh voltage signal, while one or more blocks with m bits per cell receive a second refresh voltage signal.

[0110] The p-well voltage driver 330 provides a voltage Vp-well to the p+ contact 612b in the p-well region 611b via the conductive path 682, for example. Figure 6In one approach, the p-well region 611b is common to the block. The block also shares a set of bit lines 342. A source line (SL) voltage driver 331 provides a voltage Vsl to the n+ contact 612c in the p-well region 611b, for example, via a local interconnect 651.

[0111] The bit line voltage driver 340 includes a voltage source that provides voltages to the bit line 342, such as a program-inhibit voltage signal, a program-enable voltage signal, a precharge voltage signal, and a voltage for sensing. The program-inhibit voltage signal has a magnitude of 1V to 2V, for example, to inhibit programming in a NAND string. The program-enable voltage signal has a magnitude of 0V, for example, to allow programming of a selected memory cell in a NAND string. The precharge voltage signal has a magnitude of 1V to 2V, for example, to precharge the channel of the NAND string. The voltage for sensing may have a magnitude of 0.5V, for example, to facilitate sensing of a selected memory cell in a NAND string during a read operation or a verify test.

[0112] Figure 3B An exemplary voltage driver consistent with voltage drivers 350 and 352 for a selected block is depicted. The voltage driver may include a selected data word line (WL) driver 347 that provides a voltage on a selected data word line during a program or read operation in a selected block of the bank. Driver 347 may provide a precharge voltage and a program voltage on WLn during a program cycle of a program operation. Driver 348 may provide a voltage on unselected word lines in the selected block. For example, driver 348 may be used to apply a precharge voltage and a pass voltage on unselected word lines during a program cycle of a program operation.

[0113] The voltage driver may also include an SGD driver 346 for selected and unselected sub-blocks. For example, the SGD driver 346 may provide one voltage signal for the selected sub-block and another voltage signal for the unselected sub-blocks. The SGD driver provides a voltage to a control line connected to the control gate of the SGD transistor (the drain-side select gate transistor).

[0114] The voltage drivers may also include an SGS driver for the block 345. In one option, the SGS driver is common to different sub-blocks in a block and provides voltage to the control lines connected to the control gates of the SGS transistors (source side select gate transistors).

[0115] Figure 3CExemplary voltage drivers consistent with voltage drivers 351 and 353 are depicted for unselected blocks. WL driver 349 can be used to apply refresh voltage signals to the word lines of unselected blocks in the bank. Also in the unselected blocks, SGD driver 355 provides a voltage signal to the SGD transistor, and SGS driver 356 provides a voltage signal to the SGS transistor.

[0116] Figure 3D Depicts Figure 1A Another exemplary embodiment of the power control circuit 115 for providing voltage to a memory cell block includes a common voltage driver for both n bits per cell and m bits per cell block. In this case, voltage driver 353a is provided for the selected block and operates in either n-bit per cell or m-bit per cell mode based on a select signal, which is a control signal from the control circuit. Voltage driver 352a is provided for the unselected blocks and operates in either n-bit per cell or m-bit per cell mode based on the selected signal. This approach can reduce the amount of circuitry. In the n-bit per cell mode, voltage driver 353a provides voltage signal CG0 to GRP0, and voltage driver 352a provides voltage signal UCG0 to GRP0. In the m-bit per cell mode, voltage driver 353a provides voltage signal CG1 to GRP1, and voltage driver 352a provides voltage signal UCG1 to GRP1.

[0117] exist Figure 3A and 3D In a method, one or more voltage drivers among the voltage drivers are connected to a set of row decoders for a first group of blocks and a set of row decoders for a second group of blocks. The one or more voltage drivers are configured to output a first voltage signal to unselected blocks in the first group of blocks during a corresponding read operation of a selected word line of a selected block in the first group of blocks, and to output a second voltage signal to unselected blocks in the second group of blocks during a corresponding read operation of a selected word line of a selected block in the second group of blocks.

[0118] Figure 3E Depicts the Figures 3A to 3D 357d in a consistent group of blocks. An active block may refer to a selected block that is read, while a passive block may refer to an unselected block that is not read. As mentioned, the blocks in a group of blocks share a common group select signal GRPSEL on the group select line 358. Additionally, among the blocks in a group, if a block is first accessed (read) and then remains passive while other blocks in the same group are being accessed, such accessed block may be referred to as a "first accessed block." The word line of the first accessed block receives a UCG bias while another block in the same group is being accessed with a CG bias.

[0119] Since a chunk consists of multiple blocks, most of the blocks will be in the "first accessed block" state. It is desirable to improve DRD in the first accessed block.

[0120] In the group of blocks shown, if some of the blocks are SLC and others are MLC, a common deviation UCG cannot be optimized for both types of blocks. For example, a low value of UCG would be optimal for an SLC block, but would cause an MLC block to transition to a first read state. A high value of UCG would be optimal for an MLC block, but could cause DRD for the SLC block. By dedicating the blocks in the group to storing the same number of bits per cell, the UCG can be optimized for each block. The SLC block can receive an optimal UCG and the MLC block can receive a different optimal UCG. This approach resolves the fundamental conflict between reducing read errors in SLC blocks and read errors in MLC blocks (e.g., three-bit per cell blocks and four-bit per cell blocks) in memory devices such as 3D NAND. For SLC blocks, it is desirable to have the word line voltage relatively low when the block is not being operated, while for MLC blocks, it is desirable to keep the word line voltage relatively high.

[0121] The technology described herein achieves this by having a dedicated set of SLC blocks and implementing separate designs for these blocks. Once a separate set of SLC blocks is provided, the separate designs can be implemented in two ways. The first approach is to use a separate design such as Figure 3A The SLC blocks and MLC blocks in the LC are provided with physically separate connections (such as CG / UCG lines). In this way, the SLC blocks can be treated differently from the MLC blocks.

[0122] The second approach provides the same connection lines (such as CG / UCG lines) for both SLC and MLC blocks. Then, during an operation, such as a read operation, a determination is made as to whether the operation is being performed on a dedicated SLC group of blocks or a dedicated MLC group of blocks. Based on this determination, a corresponding set of voltage waveforms (e.g., with corresponding voltage amplitudes and timings) is applied to that group of blocks (even if they are passive or unselected blocks in the group) and the connected circuitry. This can include different refresh read amplitudes for the SLC group compared to the MLC group.

[0123] This technique offers a trade-off between reducing DRD read errors and first read state errors to minimize errors on both SLC and MLC blocks. It also increases the read disturb capability of the memory device without increasing errors due to the transition from the first read state to the second read state. This provides a significant improvement, especially at the end of a block's life. It also reduces failure rates, increases yield, and reduces ECC frequency (thereby improving cost efficiency).

[0124] Figure 3F Depicts Figure 3A3. Detailed description of pre-switched control line 325, pass transistor 322, and post-switched control line 303 of GRPO. In GRPO, RD0 is connected to pre-switched control line 313a, pass transistor 313, and post-switched control line 313b, e.g., word lines WL0, WL1, ..., WL95 of BLK0. Exemplary pre-switched control line 313c is connected to the drain terminal of a corresponding pass transistor 313e, which in turn has a source terminal connected to a corresponding post-switched control line 313d (e.g., WL0). RD1 is connected to pre-switched control line 314a, pass transistor 314, and post-switched control line 314b of BLK1. RD2 is connected to pre-switched control line 315a, pass transistor 315, and post-switched control line 315b of BLK2. RD3 is connected to pre-switched control line 316a, pass transistor 316, and post-switched control line 316b of BLK3. A first set of select signals for GRPO, GRPO_SEL, is provided to the control gates of pass transistors 313-316 on a first set of select lines 323. The pass transistors may be MOSFETs that conduct when the voltage on the control line is sufficiently high, e.g., when GRPO_SEL is asserted, and do not conduct when the voltage on the control line is sufficiently low or 0V, e.g., when GRPO_SEL is de-asserted (not asserted).

[0125] In GRP1, RD4 is connected to a pre-switched control line 317a, a pass transistor 317, and a post-switched control line 317b, such as word lines WL0-WL95 of BLK4. RD5 is connected to a pre-switched control line 314a, a pass transistor 318, and a post-switched control line 318b of BLK5. RD6 is connected to a pre-switched control line 319a, a pass transistor 319, and a post-switched control line 319b of BLK6. RD7 is connected to a pre-switched control line 320a, a pass transistor 320, and a post-switched control line 320b of BLK7. A first set of select signals for GRP1, GRP1_SEL, is provided on a second set of select lines 312 to the control gates of pass transistors 317-320. The pass transistors can be MOSFETs, which, as discussed, conduct when GRP1_SEL is asserted and de-conduct when GRP1_SEL is de-asserted.

[0126] As described above, when a group block is selected, the word line voltage of the associated block is no longer floating, but is driven by the voltage provided by the row decoder. In one case, a group block is selected to perform a read operation on the selected block of the group. For the selected block, a control gate read voltage can be applied to the selected word line, while a read pass voltage is applied to the unselected word lines. Figure 3A 、 Figure 3D and Figure 3EIn the , these voltages are referred to as CG. At the same time, a refresh operation can be performed on the unselected blocks by applying a common refresh voltage signal to the word lines of the unselected blocks. Figure 3A 、 Figure 3D and Figure 3E In the CMOS, this voltage is called UCG. Figure 13 An example is provided in .

[0127] For example, in GRP0, BLK0 can be a selected block, and BLK1-BLK3 can be unselected blocks. The refresh voltage signal for GRP0 can be a first voltage signal customized for the characteristics of the GRP0 block, including n bits per cell. The refresh voltage signal for GRP1 can be a second voltage signal different from the first voltage signal, the first voltage signal customized according to the characteristics of the GRP1 block, including m bits per cell, where m>n. The two refresh voltage signals can differ in amplitude and timing (e.g., duration).

[0128] A memory device can have multiple groups of blocks that store n bits per cell and multiple groups of blocks that store m bits per cell. Typically, there can be two or more types of blocks, each storing a different number of bits per cell. The refresh voltage signal can be customized for each type of group to optimize refresh operations by minimizing read errors.

[0129] Figure 4 In an exemplary 3D configuration, Figure 3A A perspective view of a memory device 400 with blocks BLK0-BLK7 is shown. On the substrate are exemplary blocks BLK0-BLK7 of memory cells (storage elements), along with peripheral regions containing circuitry used by the blocks. Peripheral regions 404 extend along the edges of each block, while peripheral regions 405 are located at the ends of the group of blocks. The circuitry may include voltage drivers that can be connected to the control gate layers, bit lines, and source lines of the blocks. In one approach, the control gate layers at a common height in the blocks are driven together. Substrate 451 may also carry circuitry beneath the blocks and one or more lower metal layers patterned in conductive paths to carry the circuitry's signals. The blocks are formed in a middle region 452 of the memory device. In an upper region 453 of the memory device, one or more upper metal layers are patterned in conductive paths to carry the circuitry's signals. Each block includes a stacked region of memory cells, with alternating layers of the stack representing word lines. In one possible approach, each block has opposing layered sides, with vertical contacts extending upward from the layered sides to the upper metal layer to form connections to the conductive paths. While eight blocks are depicted as an example, there are typically many more blocks extending in the x-direction and / or the y-direction.

[0130] In one possible approach, the blocks are arranged in a plane, and the length of the plane in the x-direction represents the direction in which the signal path to the word line extends in one or more upper metal layers (the word line or SGD line direction), and the width of the plane in the y-direction represents the direction in which the signal path to the bit line extends in one or more upper metal layers (the bit line direction). The z-direction represents the height of the memory device. The blocks can also be arranged in multiple planes.

[0131] In such Figures 4 to 7B In the stacked memory device shown in FIG, multiple groups of connected memory cells can be arranged in NAND strings that extend vertically upward from a substrate. In one approach, the bottom (or source terminal) of each NAND string contacts the substrate, such as a well region, and the top (or drain terminal) of each NAND string is connected to a corresponding bit line.

[0132] Figure 5 An exemplary transistor 520 is depicted. The transistor includes a control gate CG, a drain D, a source S, and a channel CH, and can represent, for example, a memory cell or select gate transistor. The drain terminal of the transistor is optionally connected to a bit line BL via one or more other transistors in the NAND string, and the source terminal of the transistor is optionally connected to a source line SL via one or more other transistors in the NAND string.

[0133] Figure 6 Shown Figure 4 FIG2 is an exemplary cross-sectional view of a portion of block BLK0 including NAND strings 700n and 710n. In this example, NAND strings 700n and 710n are in different sub-blocks SB0 and SB1, respectively. The block includes a stack 610 of alternating conductive layers (word line layers) and dielectric layers. These layers can be rectangular plates having a height in the z-direction, a width in the y-direction, and a length in the x-direction.

[0134] The stack is depicted as comprising one layer but may alternatively comprise one or more layers of alternating conductive and dielectric layers.The stack comprises a set of alternating conductive and dielectric layers in which memory holes are formed during the manufacturing process.

[0135] The conductive layers include SGS, WLDS, WL0-WL95, WLDD, and SGD(0). The conductive layers connected to the control gates of the memory cells are referred to as word lines, and the conductive layers connected to the control gates of the source-side select gate transistors and the control gates of the drain-side select gate transistors are referred to as source-side control lines and drain-side control lines, respectively. WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells that are not qualified to store user data. The dummy memory cells may have the same structure as the data memory cells, but the controller deems the memory cells ineligible to store any type of data, including user data. One or more dummy memory cells may be provided at the drain and / or source ends of the NAND string of memory cells to provide a gradual transition in the channel voltage gradient. WL0-WL95 are data word lines connected to the data memory cells that are qualified to store user data. By way of example only, the stack includes ninety-six data word lines. DL is an exemplary dielectric layer.

[0136] A top 610t and a bottom 610b of the stack are shown. WL95 is the topmost data word line or conductive layer, and WL0 is the bottommost data word line or conductive layer.

[0137] The NAND string is formed by etching a memory hole in the stack and then depositing multiple thin layers of material along the sidewalls of the memory hole. Memory cells are formed in the areas where the word lines intersect the multiple thin layers, and select gate transistors are formed in the areas where the SGS and SGD control lines intersect the multiple thin layers. For example, drain-side select gate transistor 716 is formed where the SGD control line intersects the multiple thin layers, SGS transistor 701 (source-side select gate transistor) is formed where the SGS control line intersects the multiple thin layers, top-most data memory cell 714 is formed where the WL95 word line intersects the multiple thin layers, and bottom-most data memory cell 703 is formed where the WL0 word line intersects the multiple thin layers.

[0138] The multiple thin layers may form an annular layer and may be deposited, for example, using atomic layer deposition. For example, these layers may include a blocking oxide layer 663, a charge trapping layer 664 or film (such as silicon nitride (Si3N4) or other nitride), a tunnel layer 665 (e.g., a gate oxide), and a channel 660 (e.g., comprising polysilicon). A dielectric core 666 (e.g., comprising silicon dioxide) may also be provided. The word lines or control lines may comprise a metal, such as tungsten. In this example, all layers are disposed in the memory hole. In other approaches, some of the layers may be disposed in the word line or control line layers. The multiple thin layers form a pillar-shaped active area (AA) of the NAND string.

[0139] The stack is formed on a substrate 611. In one approach, the substrate includes a p-well region 611a connected to the source terminals of the NAND strings (see also Figure 3A ). The p-well region may include an epitaxial region 612 that extends upward adjacent to the source-side select gate transistor. The p-well region may include an n+ contact 612c connected to a local interconnect 651 to receive the source line voltage and a p+ contact 612b connected to a conductive path 682 to receive the p-well voltage. The local interconnect 651 may include a conductive material 651b, such as a metal surrounded by an insulating material 651a to prevent electrical conduction with the metal of the adjacent word line. In one possible implementation, the p-well region is formed in an n-well 613, which in turn is formed in a p-type semiconductor region 614 of the substrate.

[0140] NAND string 700n has a source terminal 700s connected to the p-well at the bottom 610b of the stack 610. NAND string 700n also has a drain terminal at the top 610t of the stack connected to bit line BL0 via a bit line contact 680 comprising n-type material.

[0141] A NAND string can be considered to have a floating channel because the length of the channel is not formed on the substrate.

[0142] When programming a memory cell, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and travel through the tunnel layer. The Vth of the memory cell increases proportionally to the amount of stored charge. During an erase operation, the electrons return to the channel.

[0143] Figure 7A Shown with Figure 4 and Figure 6 An exemplary view of NAND strings in a consistent block BLK0. The NAND strings are arranged in a 3D configuration in the sub-blocks of the block. Each sub-block includes multiple NAND strings, of which one example NAND string is depicted. For example, SB0, SB1, SB2, and SB3 include example NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings have the same Figure 6Consistent data word lines, dummy word lines, and select gate lines. Each sub-block includes a group of NAND strings that extend in the x-direction and have a common SGD line or control gate layer. NAND strings 700n, 710n, 720n, and 730n are located in sub-blocks SB0, SB1, SB2, and SB3, respectively. Block programming can be performed based on the word line and sub-block programming order. One option is to program memory cells in different word line portions in different sub-blocks, one sub-block at a time, before programming the memory cells of the next word line. For example, this can involve programming WL0 in SB0, SB1, SB2, and SB2, then programming WL1 in SB0, SB1, SB2, and SB2, and so on. For example, the word line programming order can start with WL0 (source end word line) and end at WL95 (drain end word line).

[0144] Another option is to program each sub-block before continuing to the next sub-block. For example, SB0 can be programmed in WL0-WL95, then SB1 can be programmed in WL0-WL95, etc.

[0145] NAND strings 700n, 710n, 720n, and 730n have channels 700a, 710a, 720a, and 730a, respectively. Additionally, NAND string 700n includes an SGS transistor 701, a dummy memory cell 702, data memory cells 703-714, a dummy memory cell 715, and an SGD transistor 716. NAND string 710n includes an SGS transistor 721, a dummy memory cell 722, data memory cells 723-734, a dummy memory cell 735, and an SGD transistor 736. NAND string 720n includes an SGS transistor 741, a dummy memory cell 742, data memory cells 743-754, a dummy memory cell 755, and an SGD transistor 756. NAND string 730 n includes an SGS transistor 761 , a dummy memory cell 762 , data memory cells 763 - 774 , a dummy memory cell 775 , and an SGD transistor 776 .

[0146] This example depicts one SGD transistor at the drain terminal of each NAND string, and one SGS transistor at the source terminal of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in a NAND string.

[0147] Figure 7B Shows the connection to Figure 7AAn exemplary view of the memory cells of WL3 in sub-block SB0 of FIG. 1 , with corresponding NAND strings, bit lines, and sensing circuits. Figure 7A Memory cell 706 and channel 700a of NAND string 700n in SB0 of FIG. SB0 also includes memory cells 706a, 706b, and 706c in NAND strings 701n, 702n, and 703n, respectively, having channels 700b, 700c, and 700d, respectively, and connected to bit lines BL1, BL2, and BL3, respectively. Bit lines BL0-BL3 are connected to Figure 2 Sensing circuits 60-63.

[0148] In a programming cycle, memory cells 706 and 706a can be examples of selected and unselected memory cells, respectively, in which case NAND strings 700n and 701n are examples of selected and unselected NAND strings, respectively, and bit lines BL0 and BL1 are examples of selected and unselected bit lines, respectively.

[0149] Figure 8A Depicted is an exemplary Vth distribution for an SLC memory cell storing one bit per cell. Figures 8A to 8C , the vertical axis represents a number of memory cells on a logarithmic scale, and the horizontal axis represents Vth in volts.

[0150] During a programming operation, the final Vth distribution can be achieved by using one or more programming passes. For example, each stage can be programmed using incremental step pulses. During a programming pass, a program-verify iteration is performed on the selected word line. The program-verify iteration includes a programming portion, in which a programming voltage is applied to the word line, followed by a verification portion in which one or more verification tests are performed. Each programmed state has a verification voltage that is used to verify the state.

[0151] Vth distributions 800 and 800a represent the erased state (Er) without and with DRD, respectively. The higher Vth distribution 800a is caused by DRD, which increases the Vth of the upper tail of the erased state memory cells. Vth distributions 801 and 801a represent the programmed data state (P) in the second read state and the first read state, respectively. The higher Vth distribution 801 is caused by coupling the rising word line voltage, while the lower Vth distribution 801a is caused by the discharge in the word line voltage.

[0152] A verification voltage of a program state is Vv, and a read voltage for distinguishing two states is Vr.

[0153] DRD is primarily caused by residual voltages on the word lines. These voltages induce temperature-dependent charge hopping during program-erase cycles through traps created in the dielectric tunnel layer 665. This charge movement under the influence of the residual word line voltage results in a continuous upward shift in the erased state as long as the residual word line voltage persists.

[0154] For particularly heavily cycled SLC blocks, DRD presents a reliability issue and can prevent memory devices from meeting read disturb and data retention specifications. Furthermore, if appropriate countermeasures, such as those presented in this article, are not implemented, DRD is expected to become a serious problem in future memory devices. DRD also impacts specifications regarding operating temperature and the qualification of memory devices based on PE cycles. Furthermore, as MLC endurance requirements increase, DRD is expected to become a concern for MLC blocks as well.

[0155] Charging the residual wordline voltage helps reduce DRD, but it can push memory cells into the undesirable first read state. This increases read errors because the read voltage is tuned to the second read state. The solution is to optimize the refresh operation to keep the memory cells in the optimal read state. Refresh operations can be performed by applying a voltage signal to the wordline with a sufficiently high amplitude to maintain programmed memory cells in the second read state while minimizing DRD for erased memory cells.

[0156] The best solution observed that blocks that are more susceptible to DRD errors are different from blocks that are more susceptible to first read state errors. For example, SLC blocks (especially at end of life) are more susceptible to DRD than MLC blocks. In addition, MLC blocks are more susceptible to first read state errors than SLC blocks due to the smaller margin between the Vth distributions of adjacent data states.

[0157] The best solution can adjust the amplitude of the refresh voltage signal for a block based on the block's sensitivity to DRD and first read state errors. The amplitude can range from a high level such as Vread (typically the highest voltage applied to unselected word lines during a read operation) to Vss or even a negative voltage (if available on the memory device).

[0158] Three exemplary scenarios are discussed. In the first scenario, the amplitude is high, such as Vread. This may be optimal for blocks that are not susceptible to DRD errors but need to be kept in the second read state to avoid first read state errors. Such blocks may include MLC blocks with relatively low PE cycles, for example, less than Figure 11B P-E_th2 in. See Figure 14A is an exemplary scenario for a read operation and a refresh operation using a high amplitude refresh voltage signal.

[0159] In the second scenario, the amplitude is a medium level, such as Vint1 or Vint2 ( Figure 11B This may be optimal for blocks that are susceptible to DRD errors but need to be strictly kept in the second read state. Such blocks may include, for example, MLC blocks with three bits per cell, MLC blocks with relatively high PE cycles, such as in Figure 11B MLC blocks larger than P-E_th2. Figure 14B This is an exemplary scenario for a read operation and a refresh operation using a medium amplitude refresh voltage signal.

[0160] In this case, a trade-off is made between the requirements to reduce both DRD errors and first state errors. A mid-level between the highest and lowest amplitudes can be determined based on factors such as workload (e.g., the expected frequency of read operations). If the expected frequency is relatively high, the mid-level can be relatively low because read operations will provide frequent coupled increases in the word line voltage. The mid-level should maintain the word line voltage within a high enough range to avoid first read state errors and a low enough range to avoid DRD errors.

[0161] In the third scenario, the amplitude is a low level, such as Vss or a negative voltage ( Figure 11B This may be best for chunks that are severely affected by DRD errors and do not need to be kept in the second read state. Such chunks may include SLC blocks with relatively high PE cycles, e.g., greater than Figure 11B P-E_th1 in. See Figure 14C This is an exemplary scenario for a read operation and a refresh operation using a medium amplitude refresh voltage signal.

[0162] In general, the characteristics of the refresh voltage signal, such as amplitude, frequency, and duration or pulse width, can be optimized taking into account factors such as operating temperature, user / system workload, number of PE cycles, and number of bits per cell. In addition, these characteristics can be dynamically adjusted based on factors such as temperature changes, which can affect the discharge rate of the word line voltage and the magnitude of DRD. These characteristics can also be adjusted based on changes in the accuracy of the programming operation that affect the edges between data states, and therefore adjust the sensitivity to DRD or first read state errors. Higher accuracy corresponds to larger edges between adjacent states. An example of increasing programming accuracy and reducing the Vth width of each state is to perform multiple programming operations instead of a single programming operation and / or use a smaller step size for programming.

[0163] For example, for MLC blocks with relatively high precision and relatively high margins between adjacent states, the refresh voltage amplitude can be relatively low. In this case, a larger Vth downshift can reduce the DRD of the erased state without causing first read state errors in the programmed state.

[0164] Figure 8B Depicted is an exemplary Vth distribution for an MLC memory cell storing two bits per cell. The Er state without DRD and with DRD are represented by Vth distributions 810 and 810a, respectively. The AC data states are represented by Vth distributions 811-813 in the second read state and 811a-813a in the first read state, respectively. The verify voltages are VvA-VvC, and the read voltages are VrA-VrC. In this example, the downward Vth shift due to the first read state is greater for the A state than for the B and C states. For higher data states, the coupling rise voltage between the channel and the word line is typically insufficient to capture more electrons in the charge-trapping layer of the memory cell. This is due to the screening effect of electrons already present in the charge-trapping layer of the memory cell and providing a high Vth. Instead, electrons in the charge-trapping layer are more easily attracted to the control gate / word line and away from the channel, resulting in a downward Vth shift. The data retention effect can also be used for higher data states where charge is lost from the charge trapping layer, causing the Vth to shift downward.

[0165] Figure 8C Depicted are exemplary Vth distributions for an MLC memory cell storing three bits per cell. The Er state without and with DRD are represented by Vth distributions 820 and 820a, respectively. The AG data state is represented by Vth distributions 821-827 in the second read state, and by Vth distributions 821a-827a in the first read state, respectively.

[0166] The verify voltages for the AG state are VvA-VvG, respectively. A set of read voltages for the AG state includes VrA-VrG, respectively. In one approach, the read voltages can be optimized for the second read state. In this example, Vth distributions 821-824 for the AD state, respectively, have a Vth upshift in the second read state. Vth distributions 826 and 827 for the F and G states, respectively, have a small Vth downshift in the second read state.

[0167] Typically, using a high amplitude for periodic refresh voltage operation is helpful for memory cells in a programmed data state, but detrimental to memory cells in an erased state. Therefore, the amplitude should be set carefully based on various factors as described herein.

[0168] Figure 9APlots the average upper-tail Vth (ranging from 1 to 1200) of erased memory cells as a function of the number of read operations. The vertical and horizontal axes are on linear scales. For SLC memory cells with 100K PE cycles, the data was at room temperature of 25°C. No read refresh operations were performed. Due to an increase in delayed read disturb, Vth increases with additional read operations. Vth increases relatively quickly, then increases more slowly as additional read operations are performed. SLC memory cells are particularly susceptible to DRD.

[0169] Figure 9B Plots depict the FBC (Failure Bit Count) or number of read errors for an SLC memory cell (curve 910) and an MLC memory cell (curve 911) as a function of the number of read operations. The vertical and horizontal axes are on linear scales. The FBC is an average value and is normalized to 0 for both SLC and MLC cells. The data is at room temperature of 25°C. Curve 910 is for an SLC memory cell with 100K PE cycles, and curve 911 is for an MLC memory cell with 3K PE cycles. The memory cells are at end-of-life. No read refresh operations were performed.

[0170] Due to delayed read disturb, FBC increases much more rapidly for SLC cells than for MLC cells. Generally, DRD has a greater effect when there are fewer bits per cell. One reason for this difference is that MLC cells have a shorter lifetime in terms of PE cycles, as they experience greater stress during programming. SLC cells have a longer lifetime and therefore experience DRD as PE cycles accumulate. There are also other differentiating factors between SLC and MLC cells that make SLC cells more susceptible to DRD. As mentioned, countermeasures for DRD involve discharging the wordline voltage. However, this increases the risk of first read state errors, especially for MLC cells.

[0171] The solution involves providing dedicated groups of blocks on the memory chip that are reserved for storing a predetermined number of bits per cell. For example, some groups can be reserved for SLC cells and other groups for MLC cells. In addition, the refresh voltage signal can be customized (optimized) to each type of group based on the number of bits per cell. Optimizing the refresh voltage signal minimizes read errors. In the optimization, the amplitude and timing of the refresh voltage signal can be different for each group of blocks based on the number of bits per cell.

[0172] 10A to 10DThis figure provides different examples of the effects of different voltage signals on the erased state upper tail Vth. The vertical axis plots the erased state upper tail Vth on a linear scale, and the horizontal axis plots the number of read operations on a linear scale. The data is for SLC cells with 75K PE cycles at a high temperature of 85°C. Within a group of blocks, the selected block is actively read, while the unselected blocks are passive blocks that are biased when the selected block is read. In each of these figures, each curve suggests a different design setting in the memory device.

[0173] Figure 10A The graph depicts the average upper tail Vth of erased SLC memory cells as a function of the number of read operations on unselected blocks in the group and different refresh voltages. Curve 1000 represents a refresh voltage amplitude of Vcelsrc=1V. Curve 1001 represents a refresh voltage amplitude of Vss=0V. Curve 1002 represents a refresh voltage amplitude of 4V. That is, in the case of curves 1000 and 1001, the refresh voltage amplitude is maintained for a period of time after the read occurs, such as Figure 13 In the case of curve 1002, the refresh voltage amplitude is the final voltage Vfinal during the voltage ramp down on the word line when the pass transistor is turned off, such as in Figure 13 The curve shows that a lower refresh voltage amplitude for the SLC cell is better because it results in a lower Vth upper tail.

[0174] Figure 10B Depicts the Figure 10A Graphs showing the average upper tail Vth of erased state SLC memory cells as a function of the number of read operations on a selected block in a group and at different refresh voltages are shown. Curve 1010 represents a refresh voltage amplitude of Vcelsrc = 1V and is similar to curve 1000. Curve 1011 represents a refresh voltage amplitude of Vss = 0V and is similar to curve 1001. Curve 1012 represents a refresh voltage amplitude of 4V and is slightly higher than curve 1002. Read operations on the selected block increase Vth.

[0175] Figure 10C Another example of a curve depicting the average upper tail Vth of erased SLC memory cells as a function of the number of read operations for unselected blocks in a group and different refresh voltages. The refresh voltage amplitude is the final voltage when the pass transistor is turned off at the end of a read operation. Curve 1020 represents a refresh voltage amplitude of Vdd = 2V. Curve 1021 represents a refresh voltage amplitude of 3V. Curve 1012 represents a refresh voltage amplitude of 4V. The curves show that Vth gradually increases as the refresh voltage amplitude increases.

[0176] Figure 10DDepicts the Figure 10C Another example of a consistent curve of the average upper tail Vth of erased state SLC memory cells as a function of the number of read operations for a selected block in a group and different refresh voltages. Curve 1030 represents a refresh voltage amplitude of Vdd=2V. Curve 1031 represents a refresh voltage amplitude of 3V. Curve 1032 represents a refresh voltage amplitude of 4V. The curves show that Vth increases with increasing refresh voltage amplitude. However, the two higher amplitudes result in similar Vth for the selected block (curves 1031 and 1032), while the Vth of the unselected blocks with the two higher amplitudes is significantly different (curves 1021 and 1022).

[0177] The curve indicates that refresh operations can help reduce read errors of erased state memory cells. For example, the refresh operation can be optimized by adjusting the amplitude of the refresh voltage signal based on the number of bits per cell in the block.

[0178] The amplitude can also be optimized based on the number of PE cycles. In one approach, an active wear leveling process can be provided for the blocks so that they have a similar number of PE cycles. Thus, even as the PE cycles increase, a common optimal refresh voltage can be used for the blocks. The number of PE cycles can be tracked by enterprise solid-state devices (SSDs) and client SSD systems. One solution is to classify the blocks into different categories, such as beginning of life, intermediate, and end of life, based on the reading of the PE cycle counter.

[0179] Further optimization can be performed based on temperature.

[0180] However, a refresh operation can often provide the best trade-off between minimizing read errors due to DRD and those caused by memory cells entering the first read state. As a system-level solution, a refresh operation can be selectively applied to blocks at higher risk of DRD errors or first read state errors without affecting other blocks. Refresh operations are applicable to both SLC and MLC. Refresh operations can increase the read disturb capability of a memory device without increasing errors due to the transition from the first read state to the second read state, which is particularly important for end-of-life blocks. Refresh operations can help reduce failure rates, increase yields, and reduce ECC frequency, thereby reducing costs.

[0181] Figure 11AA flow chart depicts an exemplary process for refreshing word line voltages in a bank. Step 1100 involves starting a read operation on a selected block in a bank storing a predetermined number of bits per cell. That is, the block is reserved for storing a predetermined number of bits per cell. Therefore, a refresh voltage signal that is optimal for the number of bits per cell can be applied to each bank. Step 1101 includes asserting a block select signal for the bank to provide a pass transistor in a conductive state. This results in driving the word line voltage. Step 1102 includes applying a control gate read voltage to a selected word line of the selected block. See Figure 12A and Figure 12B Simultaneously, step 1103 includes applying a read pass voltage to the unselected word lines of the selected block.

[0182] Step 1104 includes sensing the memory cells connected to the selected word line. Step 1105 includes ramping down the voltage on the unselected word lines. Step 1106 includes deasserting the block select signal for the bank to provide the pass transistors in a non-conducting state. This results in a floating word line voltage.

[0183] Step 1107 can be performed on unselected blocks simultaneously with reading the selected block.Step 1107 includes applying a refresh voltage signal to the word lines of the unselected blocks in the group, wherein the voltage signal is tailored to refresh the floating word line voltage based on a predetermined number of bits per cell.

[0184] Steps 1101, 1107, and 1106 may be followed in a periodic refresh operation following a read operation. In an exemplary implementation, after a corresponding read operation for a selected block in a first group of blocks, a set of row decoders for the first group of blocks is configured to periodically and simultaneously apply a first voltage signal to a word line of each block in the first group of blocks, and after a corresponding read operation for a selected word line of a selected block in a second group of blocks, a set of row decoders for the second group of blocks is configured to periodically and simultaneously apply a second voltage signal to a word line of each block in the second group of blocks.

[0185] In another case, no read operation is performed for the group. Instead, all blocks in the group undergo a refresh operation. In this case, steps 1101, 1107, and 1106 are performed, but the refresh voltage signal of step 1107 is applied to each block in the group. In one method, multiple blocks in the group can be refreshed simultaneously.

[0186] Typically, refresh operations can be performed at fixed intervals. Although refresh operations are scheduled when read commands are received at the same time, read commands can take priority and refresh operations can be performed after read operations are completed. For example, see 14A to 14C .

[0187] In an exemplary implementation, a method includes performing a first voltage refresh operation on a word line of a first block of memory cells, the performing the first voltage refresh operation comprising connecting a first voltage signal from a voltage driver to a first set of pass transistors connected to the word line of the first block and asserting a group select signal for the first set of pass transistors, wherein the first voltage signal is tailored to refresh a floating voltage of the word line of the first block when the memory cells of the first block store n bits per cell. The method further includes performing a second voltage refresh operation on the word line of a second block of memory cells, independent of the performing the first voltage refresh operation, the performing the second voltage refresh operation comprising connecting a second voltage signal from the voltage driver to a second set of pass transistors connected to the word line of the second block and asserting a group select signal for the second set of pass transistors, wherein the second voltage signal is tailored to refresh a floating voltage of the word line of the second block when the memory cells of the second block store m>n bits per cell.

[0188] Figure 11B Depicts Figure 1A Used for Figure 11A FIG10 is an exemplary table of the refresh voltage signal setting circuit 119 of step 1107 of FIG10. As mentioned, the amplitude of the refresh voltage signal in the refresh operation can be optimized based on factors such as the number of bits per cell and the number of PE cycles. In this example, it is classified as a small amount if the number of PE cycles is below a threshold, or as a large amount if the number of PE cycles is above a threshold. For example, for an SLC block, if the number of PE cycles is below a first threshold P-E_th1, the amplitude of the refresh voltage signal can be a first intermediate voltage Vint1. If the number of PE cycles is at or above P-E_th1, the amplitude of the refresh voltage signal can be 0V or a negative voltage. This approach is based on the increased sensitivity to DRD errors at higher PE cycles of SLC blocks, where relatively less attention is paid to maintaining the second read state. Effectively lowering the refresh voltage signal to a low level such as Vss helps to reduce DRD errors as PE cycles increase.

[0189] For an MLC block, if the number of P-E cycles is below a second threshold P-E_th2, the amplitude of the refresh voltage signal is Vhigh, such as Vread. If the number of P-E cycles is at or above P-E_th2, the amplitude of the refresh voltage signal is a second intermediate voltage Vint2. In one method, P-E_th2 < P-E_th1. For example, P-E_th2 can be 5K in an MLC block with a 10K P-E cycle lifetime, and P-E_th1 can be 50K in an SLC block with a 100K P-E cycle lifetime. Additionally, Vint2 can be greater than Vint1 because it is often more important to hold the programmed memory cells in the second read state for an MLC block than for an SLC block.

[0190] This method is also based on the increased sensitivity to DRD errors at higher P-E cycles of the erased cells in an MLC block, while balancing the need to also maintain the second read state of the programmed cells. Reducing the refresh voltage signal to an intermediate level helps reduce DRD errors while maintaining the second read state of the programmed cells as the P-E cycles increase. Reducing the refresh voltage signal to 0V would likely be an overcompensation for reducing DRD errors at the cost of increasing first read state errors.

[0191] Figure 12A Depicts a first example of the voltage signals in a read operation Figure 11A consistent with. In this example, at the start of the read operation, the word line voltage is reset to 0V (curve 1200). VWL represents the word line voltage. For a selected word line (the word line being read), curves 1206 and 1207 represent the read voltages of VrA and VrE, respectively. These voltages are used in the lower page read operation of the memory cells storing three bits per cell. During each read voltage, a sense operation occurs. Curve 1208 represents the selected word line voltage returning to 0V.

[0192] Curves 1201 - 1203 represent the voltage signals for the unselected word lines. The voltage increases to Vread at t0 (curve 1201), remains at Vread until t5, and then decreases to 0V at t5 - t6 (curve 1203). This decreasing fall of the word line voltage couples to the channel, causing the channel voltage (Vch) to decrease (curve 1231). From t6 - t7, the channel voltage recovers back to 0V (curve 1232), resulting in a corresponding coupled rise of the word line voltage (curve 1204). Subsequently, the word line voltage gradually decreases (curve 1205). For VWL, the solid line represents the drive voltage, and the dashed line represents the floating voltage.

[0193] Curves 1210 and 1211 represent the voltage signals for the SGD and SGS select gate transistors. The voltage increases to a peak level at t0 to provide the select gate transistor in a conductive state, remains at the peak level until t3, and then decreases to 0V at t3-t4. When Vsg decreases below the cutoff voltage, Vcutoff, at t4, the select gate transistor becomes non-conductive, allowing the channel voltage to float. Turning off the select gate transistor before reducing the unselected word line voltage at t5-t6 allows for reduced channel voltage coupling, as discussed. Alternatively, the select gate transistor may not be turned off before reducing the unselected word line voltage. In this case, the channel voltage begins to float when the unselected word line voltage drops below the Vth of the memory cell, thereby shutting off the corresponding channel region.

[0194] Curve 1220 represents the voltage signal of the bit line. Vbl may be set at a small positive level such as 0.5V during a read operation.

[0195] Curves 1230-1233 represent the channel voltage. In one approach from t0-t5, Vch can be set to a level similar to Vbl. As mentioned, due to the voltage transition on the unselected word lines, Vch can decrease from t5-t6 and then recover from t6-t7.

[0196] Figure 12B Depicts the Figure 11A Second example of voltage signals during a consistent read operation. In this example, the unselected word line voltage transitions from a floating level (curve 1240) to Vread (curve 1242). For the selected word line, the voltage signal is initially at 0V (curve 1246) and then at the read voltages of VrA and VrE (curves 1247 and 1248, respectively). Curve 1249 represents the selected word line voltage transitioning to the final voltage Vfinal at t6.

[0197] Curves 1241-1243 represent the voltage signals for the unselected word lines. The voltage increases to Vread at t0 (curve 1241), remains at Vread until t5, and then decreases to Vfinal at t5-t6 (curve 1243). This decrease in word line voltage couples the channel downward, causing the channel voltage (Vch) to decrease at t5-t6 (curve 1271). However, this decrease in coupling is less than Figure 12A From t6 to t7, the channel voltage returns to 0V (curve 1272), causing the corresponding coupling of the word line voltage to increase (curve 1244). Subsequently, the word line voltage gradually decreases (curve 1245).

[0198] If combined Figure 3AAs mentioned, due to the capacitance of the word line, the delay of the word line voltage can change based on the change in the voltage on the pre-switched control line. For example, curve 1243a can represent the change in the pre-switched control line 325a, and curve 1243 can represent the corresponding change in the word line voltage. Before the word line voltage has a chance to reach 0V or other minimum level of the pre-switched control line, the voltage of pre-switched control line 325a is turned off at t6. Instead, the word line voltage reaches a final level where Vfinal > 0V.

[0199] Curves 1250 and 1251 represent the voltage signals of the SGD and SGS select gate transistors, similar to Figure 12A The corresponding voltage signal in .

[0200] Curve 1260 represents the voltage signal of the bit line, similar to Figure 12A The corresponding voltage signal in .

[0201] Curves 1270-1273 represent channel voltages, similar to Figure 12A The corresponding voltage in , but with a smaller dropout coupling.

[0202] Figure 13 Depicted are examples of word line voltages during refresh operations for high, medium, and low amplitude refresh voltages (curves 1300, 1310, and 1320, respectively). The short dashed line represents the floating voltage, and the solid line represents the drive voltage. The long dashed line in curve 1320 also represents the drive voltage.

[0203] In the graph 1300, the graph 1301 represents the initial floating voltage of the word line of the block. The refresh operation starts at t0, when the word line voltage is driven higher (graph 1302) to a high amplitude refresh voltage, such as Vread, and then maintained at Vread (graph 1303) until t2, and then driven lower from t2 to t3 to a final level, such as Vfinal (graph 1304). As shown in conjunction with Figure 12B As discussed, the word line voltage may or may not reach the minimum level provided on the pre-switched control line. The word line voltage is then allowed to float starting at t3, where it floats higher (curve 1305) and then begins to discharge (curve 1306). In this option, the group select signal is asserted from t0-t3.

[0204] Refresh operations with high-amplitude refresh voltages tend to increase the wordline voltage, as depicted by comparing curves 1305 and 1306 with curve 1301. Specifically, with high-amplitude refresh voltages, the voltage signal is typically driven lower before being floated. This results in some downward coupling of the channel and subsequent upward coupling of the channel and wordline voltage. This upward coupling is added to the wordline voltage as the floating begins to provide the increased voltage of curve 1305.

[0205] In curve 1310, two examples of initial floating voltages for the word lines of a block are provided. Curve 1313 represents a low initial floating voltage, and curve 1311 represents a high initial floating voltage. The refresh operation begins at t0, at which time the word line voltage is driven higher (curve 1314) or lower (curve 1312) to Vint and then maintained at Vint (curve 1315) until t3. The word line voltage is then allowed to begin floating at t3, where the word line voltage can float slightly higher and then discharge (curve 1316a) if the initial floating voltage is higher than Vint (curve 1311), or can begin to discharge from the Vint level (curve 1316b) if the initial floating voltage is lower than Vint (curve 1313). For example, Vint can represent a voltage from Figure 11B In this option, select a signal from the t0-t3 assertion group.

[0206] A refresh operation with a medium refresh voltage tends to increase the word line voltage if the word line voltage is relatively low, as depicted by comparing curve 1316b with curve 1313, or tends to decrease the word line voltage if the word line voltage is relatively high, as depicted by comparing curve 1316a with curve 1311.

[0207] In the case of a medium-amplitude refresh voltage, the voltage signal can be driven lower before being floated, as in the case of curve 1312, so there is some downward coupling of the channel and subsequent upward coupling of the channel and the word line voltage. When floating begins, providing a slightly increased voltage after t3 of curve 1316a, upward coupling is added to the word line voltage. If the voltage signal is not driven lower before being floated, as in the case of curve 1314, there is no downward coupling of the channel and subsequent upward coupling of the channel and the word line voltage.

[0208] In curve 1320, curve 1321 represents the initial floating voltage of the word line. In one option, the refresh operation begins at t0, at which time the word line voltage is driven lower (curve 1322) to a low-amplitude refresh voltage such as Vss, and then maintained at Vss (curve 1323) until t3. The word line voltage is then allowed to float starting at t3, where it can float slightly higher and then discharge (curve 1324). In this option, the group select signal is asserted from t0-t3.

[0209] In another option, the word line voltage is also maintained at Vss from t2-t4 (curve 1325). The word line voltage is then allowed to float starting at t4, where it can float slightly higher and then discharge (curve 1326). However, the floating level of curve 1326 is lower than that of curve 1324, which is beneficial for reducing DRD errors in SLC cells, for example. Maintaining the word line voltage at Vss for a longer period helps reduce the floating word line voltage when the group select signal is de-asserted. In this example, for example, the word line voltage is driven at Vss from t0-t4, which is longer than the period from t0-t3, where the word line is driven in curves 1300 and 1310. In this option, the group select signal is asserted from t0-t4.

[0210] This is an example of how the refresh voltage signal for a group block can have a duration tailored to the number of bits per cell of the group. This is in addition to adjusting the amplitude of the refresh voltage signal.

[0211] A refresh operation with a low magnitude refresh voltage tends to reduce the word line voltage, as depicted by comparing curve 1324 to curve 1321 .

[0212] In the case of a low amplitude refresh voltage, the voltage signal is typically driven lower before being floated, as in the case of curve 1322, so there is some downward coupling of the channel and subsequent upward coupling of the channel and the word line voltage. When floating begins to provide an increased voltage after t3, the upward coupling is added to the word line voltage. In an exemplary embodiment, curves 1323 and 1325 represent a first voltage signal maintained at a first voltage (Vss) for a first time period (t1-t4), and curve 1303 represents a second voltage signal maintained at a second voltage (Vread) (greater than the first voltage) for a second time period (t1-t2) (shorter than the first time period).

[0213] Curves 1323 and 1325 also represent first voltage signals maintained at no more than 0V for corresponding time periods (t1-t4), and curve 1303 represents a second voltage signal maintained at greater than 0V for corresponding time periods (t1-t2).

[0214] Curve 1320 represents a first voltage signal, which transitions from an initial voltage (curve 1321) to a corresponding lower voltage (0V) and remains at the lower voltage until the first group block is unselected via the first set of select lines (at t2 or t4). Curve 1300 represents a second voltage signal, which transitions from an initial voltage (curve 1301) to a higher voltage (Vread), remains at the higher voltage (at t1-t2), and then transitions to a corresponding lower voltage (Vfinal). The first group block can store n bits per cell, and the second group block can store m bits per cell. When the second voltage signal is at a corresponding lower voltage, the second group block is unselected via the second set of select lines (at t3).

[0215] Curve 1320 may be an example of a first refresh voltage signal applied to word lines of memory cells connected to a first group of blocks, such as an SLC block, and curve 1300 may be an example of a second refresh voltage signal applied to word lines of memory cells connected to a second group of blocks, such as an MLC block, while the first refresh voltage signal is being applied.

[0216] In an exemplary implementation, the first refresh voltage signal is maintained at a first voltage, such as 0V, and the second refresh voltage signal is maintained at a second voltage, such as Vread, which is higher than the first voltage.

[0217] 14A to 14C An example time period TP1-TP3 between consecutive refresh operations is depicted.The voltage signal for the refresh operation is denoted by Rf, and the voltage signal for the read operation is denoted by Rd.

[0218] Typically, refresh operations can be performed at regular intervals, as long as a read operation is not in progress. If a read operation is in progress, a wait period can be implemented before performing a refresh operation, where the wait period is less than the typical time period between refresh operations. In this example, the first to fourth refresh operations are performed at t1-t2, t3-t4, t7-t8, and t11-t12. The time period TP1 between the first and second read operations is equal to the time period TP2 between the second and third read operations. However, due to the wait period caused by the read operation at t9-t10, the time period TP3 between the third and fourth read operations is greater than TP1 and TP2.

[0219] Read operations are performed at t5-t6 and t9-t10.

[0220] The solid-line curve represents the driving voltage, and the dashed-line curve represents the floating voltage.

[0221] Figure 14AAn example of word line voltages during a read operation and a refresh operation with a high-amplitude refresh voltage Vread is depicted. The high-amplitude refresh voltages for the refresh operations are represented by curves 1400, 1401, 1403, and 1405. Because the high-amplitude refresh voltages are used, each refresh operation increases the word line voltage. The voltage Vread for unselected word lines during a read operation is represented by curves 1402 and 1404.

[0222] Figure 14B An example of word line voltage during a read operation and a refresh operation with a medium refresh voltage Vint is depicted. The medium refresh voltage for the refresh operation is represented by curves 1410, 1411, 1413, and 1415. Since the medium refresh voltage is used, each refresh operation can increase or decrease the word line voltage. For example, the refresh voltages of curves 1410, 1413, and 1415 decrease the word line voltage, and the refresh voltage of curve 1411 increases the word line voltage. The voltage of Vread during the read operation is represented by curves 1412 and 1414.

[0223] Figure 14C An example of the word line voltage during a read operation and a refresh operation with a low-amplitude refresh voltage Vss is depicted. The low-amplitude refresh voltages for the refresh operations are represented by curves 1420, 1421, 1423, and 1425. Because the low-amplitude refresh voltage is used, each refresh operation reduces the word line voltage. The signal at Vread is represented by curves 1422 and 1424.

[0224] Figure 15 Depicts the Figure 3A An example of a selected block BLK0 and an unselected block BLK1 in a consistent group block GRP0. BLK0 includes a group of memory cells 1500-1503, and a group of word lines 1505 are connected to the group of memory cells. BLK1 includes a group of memory cells 1510-1513, and a group of word lines 1515 are connected to the group of memory cells. In one scenario, a read operation is performed on a selected block while a refresh operation is performed on the unselected blocks.

[0225] Thus, it can be seen that in one embodiment, an apparatus includes: a first group of blocks of memory cells, the first group of blocks being reserved for storing n bits per cell, the first group of blocks being simultaneously selectable by a first set of select lines; a set of word lines connected to the memory cells of each block in the first group of blocks; a set of row decoders for the first group of blocks, the set of row decoders including a row decoder for a selected block in the first group of blocks and a row decoder for an unselected block in the first group of blocks, the row decoder for the unselected block in the first group of blocks being configured to apply a first voltage signal to the word line of the unselected block in the first group of blocks, and the row decoder for the selected block in the first group of blocks applying a read voltage to the selected block in the first group of blocks in a corresponding read operation. a selected word line of a second group of memory cells, the second group of blocks being reserved for storing m>n bits per cell, the second group of blocks being simultaneously selectable by a second group of select lines; a group of word lines connected to the memory cells of each block in the second group of blocks; and a group of row decoders for the second group of blocks, the group of row decoders comprising a row decoder for a selected block in the second group of blocks and a row decoder for an unselected block in the second group of blocks, the row decoder for the unselected block in the second group of blocks being configured to apply a second voltage signal different from the first voltage signal to the word line of the unselected block in the second group of blocks, and the row decoder for the selected block in the second group of blocks applying a read voltage to the selected word line of the selected block in the second group of blocks in a corresponding read operation.

[0226] In another specific implementation, a method includes performing a first voltage refresh operation on word lines of a first group of memory cells, the performing the first voltage refresh operation including connecting a first voltage signal from a voltage driver to a first group of pass transistors connected to the word lines of the first group of memory cells, asserting a group select signal for the first group of pass transistors, the first voltage signal being tailored to refresh a floating voltage of the word lines of the first group of memory cells when the memory cells of the first group of memory cells store n bits per cell; and, independent of the performing the first voltage refresh operation, performing a second voltage refresh operation on the word lines of a second group of memory cells, the performing the second voltage refresh operation including connecting a second voltage signal from the voltage driver to a second group of pass transistors connected to the word lines of the second group of memory cells, asserting a group select signal for the second group of pass transistors, the second voltage signal being tailored to refresh a floating voltage of the word lines of the second group of memory cells when the memory cells of the second group of memory cells store m>n bits per cell.

[0227] In another embodiment, an apparatus includes: a first block of memory cells, the first block reserved for storing n bits per cell, the first block being simultaneously selectable by a first set of select lines; a word line connected to the memory cells of the first block; a second block of memory cells, the second block reserved for storing m>n bits per cell, the second block being simultaneously selectable by a second set of select lines; a word line connected to the memory cells of the second block; and a control circuit configured to simultaneously apply a first refresh voltage signal to the word line connected to the memory cells of the first block and a second refresh voltage signal to the word line connected to the memory cells of the second block.

[0228] The above specific embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. In light of the above teachings, many modifications and variations are possible. The described embodiments were chosen in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and with various modifications suitable for the particular use contemplated. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A refreshing device, comprising: a first block of memory cells, the first block being reserved for storing n bits per cell, the first block being simultaneously selectable by a first set of select lines; a set of word lines connected to the memory cells of each block in the first set of blocks; a set of row decoders for the first group of blocks, the set of row decoders comprising a row decoder for a selected block in the first group of blocks and row decoders for unselected blocks in the first group of blocks, the row decoders for the unselected blocks in the first group of blocks being configured to apply a first voltage signal to a word line of the unselected block in the first group of blocks, and the row decoder for the selected block in the first group of blocks applying a read voltage to a selected word line of the selected block in the first group of blocks in a corresponding read operation; a second block of memory cells, said second block being reserved for storing m>n bits per cell, said second block being simultaneously selectable by a second set of select lines; a set of word lines connected to the memory cells of each block in the second set of blocks; and a set of row decoders for the second group of blocks, the set of row decoders including a row decoder for a selected block in the second group of blocks and a row decoder for unselected blocks in the second group of blocks, the row decoders for the unselected blocks in the second group of blocks being configured to apply a second voltage signal different from the first voltage signal to word lines of the unselected blocks in the second group of blocks, and the row decoder for the selected block in the second group of blocks applying a read voltage to a selected word line of the selected block in the second group of blocks in a corresponding read operation; in: the first voltage signal transitions from an initial voltage to a corresponding lower voltage and remains at the lower voltage until the first group of blocks is unselected via the first group of select lines; the second voltage signal transitions from an initial voltage to a higher voltage, remains at the higher voltage, and then transitions to a corresponding lower voltage; and When the second voltage signal is at the corresponding lower voltage, the second group of blocks is unselected via the second group of select lines.

2. The device according to claim 1, wherein: The first voltage signal is configured to reduce a floating voltage of the word lines of the unselected blocks in the first group of blocks; and The second voltage signal is configured to increase a floating voltage of the word lines of the unselected blocks in the second group of blocks.

3. The device according to claim 1 or 2, wherein: maintaining the first voltage signal at a first voltage for a first period of time; and The second voltage signal is maintained at a second voltage greater than the first voltage for a second time period shorter than the first time period.

4. The device according to claim 1 or 2, wherein: Maintaining the first voltage signal at no more than 0V for a corresponding period of time; and The second voltage signal is maintained at a value greater than 0V for a corresponding period of time.

5. The apparatus according to claim 1, wherein: When the first group of blocks is not selected, the voltages of the word lines of the selected block and the unselected blocks of the first group of blocks begin to float; and When the second group of blocks is not selected, voltages of the word lines of the selected block and the unselected blocks of the second group of blocks begin to float.

6. The device according to claim 1 or 2, wherein: Each word line of a respective set of word lines of the first group of blocks is connected to a respective pass transistor; Each pass transistor in the first set of blocks has a control gate connected to the first set of select lines; each word line of the corresponding set of word lines of the second group of blocks is connected to a corresponding pass transistor; and Each pass transistor in the second set of blocks has a control gate connected to the second set of select lines.

7. The device according to claim 1 or 2, wherein: the set of row decoders for the first group of blocks being configured to periodically and simultaneously apply the first voltage signal to the word line of each block in the first group of blocks after the corresponding read operation for the selected word line of the selected block in the first group of blocks; and The set of row decoders for the second set of blocks is configured to periodically and simultaneously apply the second voltage signal to the word line of each block in the second set of blocks after the corresponding read operation for the selected word line of the selected block in the second set of blocks.

8. The device according to claim 1 or 2, wherein: A voltage driver is connected to the set of row decoders of the first group of blocks and to the set of row decoders of the second group of blocks, the voltage driver being configured to output the first voltage signal to the row decoders for the unselected blocks in the first group of blocks during the corresponding read operation of the selected word line of the selected block of the first group of blocks, and to output the second voltage signal to the row decoders for the unselected blocks in the second group of blocks during the corresponding read operation of the selected word line of the selected block of the second group of blocks.

9. A refreshing method, comprising: performing a first voltage refresh operation on a word line of a first block of memory cells, the performing the first voltage refresh operation comprising connecting a first voltage signal from a voltage driver to a first set of pass transistors connected to the word line of the first block, asserting a group select signal for the first set of pass transistors, the first voltage signal being tailored to refresh a floating voltage of the word line of the first block when the memory cells of the first block store n bits per cell; as well as performing a second voltage refresh operation on word lines of a second group of memory cells independently of performing the first voltage refresh operation, the performing the second voltage refresh operation comprising connecting a second voltage signal from the voltage driver to a second group of pass transistors connected to the word lines of the second group of memory cells, asserting a group select signal for the second group of pass transistors, the second voltage signal being tailored to refresh a floating voltage of the word lines of the second group of memory cells when the memory cells of the second group of memory cells store m>n bits per cell; in: The memory cells of the second block are arranged in NAND strings including corresponding channels; and The second voltage signal is configured to increase a floating voltage of the word line of the second block by rising coupling from the channel.

10. The method according to claim 9, wherein: The first voltage signal is tailored to reduce the floating voltage of the word lines of the first block; and The second voltage signal is tailored to increase the floating voltage of the word lines of the second block.

11. The method according to claim 9 or 10, wherein: The duration of the first voltage signal is longer than the duration of the second voltage signal.

12. The method according to claim 9 or 10, wherein: customizing the first voltage signal based on the program-erase cycles of the first block and the n bits per cell; and The second voltage signal is customized based on the program-erase cycles of the second block and the m bits per cell.

13. The method according to claim 9 or 10, wherein: maintaining the first voltage signal at a first voltage for a first period of time; and The second voltage signal is maintained at a second voltage greater than the first voltage for a second time period shorter than the first time period.

14. A refreshing device comprising: a first block of memory cells, the first block being reserved for storing n bits per cell, the first block being simultaneously selectable by a first set of select lines; a word line connected to the memory cells of the first group; a second block of memory cells, said second block being reserved for storing m>n bits per cell, said second block being simultaneously selectable by a second set of select lines; a word line connected to the memory cells of the second block; a control circuit configured to simultaneously apply a first refresh voltage signal to word lines connected to the memory cells of the first group of blocks and a second refresh voltage signal to word lines connected to the memory cells of the second group of blocks, the first refresh voltage signal being configured to lower a floating voltage of the word lines of the first group of blocks and the second refresh voltage signal being configured to increase a floating voltage of the word lines of the second group of blocks; a first set of pass transistors, wherein the first set of pass transistors are connected to a word line of the first block, each pass transistor of the first set of pass transistors having a control gate connected to the first set of select lines; a second set of pass transistors, wherein the second set of pass transistors are connected to a word line of the second block, each pass transistor of the second set of pass transistors having a control gate connected to the second set of select lines; a first set of row decoders, wherein the first set of row decoders is connected to the first set of pass transistors; a second set of row decoders, wherein the second set of row decoders is connected to the second set of pass transistors; and A voltage driver is connected to the first group of row decoders and the second group of row decoders, and is configured to output the first refresh voltage signal to the first group of row decoders and output the second refresh voltage signal to the second group of row decoders.

15. The apparatus according to claim 14, wherein: The first refresh voltage signal is maintained at a first voltage; and The second refresh voltage signal is maintained at a second voltage higher than the first voltage.

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