Reducing read time in memory devices with p-well biasing

Abstract

Apparatus and techniques are described for reducing read times in memory devices. Source region source voltage signals VceIsrC and p-well body voltage signals Vp-well of substrates of NAND strings are controlled to reduce channel resistance. During a read operation, VceIsrC can be temporarily reduced, e.g., with a negative voltage kickback, while Vp-well is not reduced. This negative voltage kickback causes the body bias in the channel of the NAND string to be reduced, thereby reducing the channel resistance and increasing current flow. The negative voltage kickback can be initiated when a bit line clamp transistor is fabricated to be conductive to allow current to flow in the NAND string. The magnitude and duration of the negative voltage kickback can be adjusted based on various factors.

Description

BACKGROUND

[0001] The technology relates to operation of memory devices.

[0002] Semiconductor memory devices have become more prevalent for use in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials, such as floating gates, or charge trapping materials can be used in such memory devices to store charge representative of a data state. Charge trapping materials can be arranged vertically in three-dimensional (3D) stacked memory structures, or arranged horizontally in two-dimensional (2D) memory structures. One example of a 3D memory structure is a bit cost scalable (BiCS) architecture that includes a stack of alternating conductive layers and dielectric layers.

[0004] Memory devices include memory cells that can be arranged in series into NAND strings, for example, with select gate transistors disposed at the ends of the NAND strings to selectively connect the channels of the NAND strings to source lines or bit lines. However, there are various challenges in operating such memory devices. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1A is a block diagram of an example memory device.

[0006] Figure 1B is a block diagram of an arrangement of the memory device 100 of Figure 1A

[0007] Figure 2 is a block diagram showing one embodiment of a sense block 51 of Figure 1A

[0008] Figure 3 shows an example implementation of the power control circuit 115 of Figure 1A

[0009] Figure 4 shows an example memory cell in the memory device of Figure 1A

[0010] Figure 5A shows an example curve of memory cell current versus time for a memory cell of Figure 4

[0011] Figure 5B ​​​​​An exemplary plot showing the relationship of sector failure probability to failure bit count, showing the impact of different read times as shown in Figure 5A

[0012] Figure 6 is a perspective view of an exemplary memory die 600, with blocks disposed in respective planes P0 and PI, consistent with Figure 1A

[0013] Figure 7A shows an exemplary cross-sectional view of a portion of block B0-0 of Figure 6 , including NAND strings 700n in which the conductive path does not extend in memory cells 714 connected to WLn.

[0014] Figure 7B shows an exemplary cross-sectional view of a portion of block B0-0 of Figure 7A at the WL0 level in the x-y plane.

[0015] Figure 7C shows an exemplary cross-sectional view of a portion of block B0-0 of Figure 6 , including NAND strings 700n in which the conductive path CP3 extends in memory cells 714 connected to WLn.

[0016] Figure 8 shows an exemplary view of block B0-0 of Figure 6 and associated bit lines and sense circuitry, with respective NAND strings arranged in sub-blocks.

[0017] Figure 9 shows an exemplary NAND string in a 2D configuration.

[0018] Figure 10 shows a threshold voltage (Vth) distribution for an eight-state memory device.

[0019] Figure 11 shows an exemplary process for reducing read times in NAND strings.

[0020] Figure 12 shows exemplary voltage signals and Icell in a read operation, consistent with Figure 11

[0021] Figure 13 shows a plot of Vkick and / or tkick versus selected sub-blocks, representing distance to WL drivers, consistent with Figure 8 DETAILED DESCRIPTION

[0022] Apparatuses and techniques for reducing read times in memory devices are described. ​​​​

[0023] In some memory devices, memory cells are connected to one another, such as in NAND strings in a block or sub-block. Each NAND string includes a plurality of memory cells connected in series between one or more drain end select gate transistors, referred to as SGD transistors, on a drain end of the NAND string that is connected to a bit line, and one or more source end select gate transistors, referred to as SGS transistors, on a source end of the NAND string or other memory string or group of connected memory cells that is connected to a source line. Select gate transistors are also referred to as select gates. In addition, the memory cells can be arranged with a common control gate line (e.g., word line) that functions as a control gate. A group of word lines extends from a source side of the block to a drain side of the block. See, e.g., Figure 8 The memory cells can also be connected in other ways.

[0024] In 3D memory structures, memory cells can be arranged in stacked, vertical NAND strings in a substrate, where the stack includes alternating conductive layers and dielectric layers. The conductive layers function as word lines that are connected to the memory cells. Each NAND string can have a shape of a pillar that intersects the word lines to form the memory cells. In addition, each NAND string includes various layers that extend vertically in the stack, such as a blocking oxide layer, a charge trapping layer, a tunnel layer, and a channel layer. See, e.g., Figure 7A and Figure 7B .

[0025] In 2D memory structures, memory cells can be arranged in horizontal NAND strings on a substrate. See, e.g., Figure 9 .

[0026] Memory cells can be programmed to have a threshold voltage (Vth) that corresponds to a data state. See, e.g., Figure 10 Vth is a function of the amount of charge stored in the charge storage material of the memory cell. A read operation can be performed to determine Vth, and thus the data state of the memory cell. A read can also be performed in a verify test of a program operation, where Vth of the memory cell is compared to a verify voltage applied to the corresponding word line to determine whether programming of the memory cell is complete. A read can also be performed in a verify test of an erase operation, where Vth of the memory cell is compared to a verify voltage applied to the corresponding word line to determine whether erasing of the memory cell is complete. During a read operation, when a voltage Vwl sel is applied to the word line / control gate of the memory cell, a current Icell in the NAND string is compared to a reference current Iref in a sense circuit. See also, e.g., Figure 2 If Icell < Iref, then Vth > Vwl sel. If Icell > Iref, then Vth < Vwl sel.

[0027] To accurately read a memory cell, Icell should settle at a target level. See, e.g., Figure 5A However, this target conflicts with the goal of having a short read time. In particular, if the word line and bit line do not have sufficient time to settle, shortening the read time can result in an increased faulty bit count. See, e.g., Figure 5B The word line and bit line tend to have a relatively high RC delay, and this problem is expected to worsen in future memory devices.

[0028] The technology presented herein solves the above-referenced and other problems. In one aspect, the source voltage signal Vceiisrc and the body voltage signal Vp-well of a substrate of a NAND string are controlled to reduce channel resistance. During a read operation, Vceiisrc can be temporarily reduced, e.g., a negative voltage kick is provided, while Vp-well remains constant or even increases. See, e.g., Figure 12 t2-t4. In general, Vp-well and Vceiisrc can be set such that Vp-well > Vceiisrc during the voltage kick. This negative voltage kick causes the body bias in the channel of the NAND string to decrease, thereby reducing the channel resistance and increasing the current. The negative voltage kick can be initiated when the bit line clamp transistor is fabricated to be conductive to allow current to flow in the NAND string. Further, the magnitude and duration of the negative voltage kick can be adjusted based on various factors, such as the location of the NAND string in the block and the distance of the NAND string from the word line driver.

[0029] These and other features will be discussed further below.

[0030] Figure 1A is a block diagram of an exemplary memory device. The memory device 100, such as a non-volatile storage system, can include one or more memory dies 108. The memory die 108 or chip includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuits 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuits 128 include a plurality of sense blocks 51, 52,..., 53 (sense circuitry) and allow a page of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. The controller can be located on a separate die 127 from the memory dies 108. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0031] The memory structure can be a 2D memory structure or a 3D memory structure. The memory structure can include one or more arrays of memory cells including a 3D array. The memory structure can include a monolithic 3D memory structure in which multiple levels of memory are formed above (rather than in) a single substrate, such as a wafer, without intervening substrates. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active regions disposed above a silicon substrate. The memory structure can be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is above the substrate or within the substrate.

[0032] The control circuitry 110 cooperates with the read / write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine, an on-chip address decoder 114, and a power control circuitry 115. A storage area 113, such as a cache or buffers, can be provided for storing operational parameters and software / code. In one embodiment, the state machine is programmed by software. In other embodiments, the state machine does not use software and is implemented in hardware (e.g., electrical circuitry) entirely.

[0033] The on-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by the decoders 124 and 132. The power control circuitry 115 controls the power and voltages supplied to the word lines, select gate lines, bit lines, and source lines during memory operations. This power control module can include drivers for the word lines, SGS and SGD transistors, and source lines. See also Figure 3 In one approach, the sense blocks can include bit line drivers.

[0034] In some implementations, some of the components can be combined. In various designs, one or more of the components other than the memory structure 126, alone or in combination, can be considered at least one control circuitry configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuitry can include any one of or a combination of the control circuitry 110, the state machine 112, the decoders 114 and 132, the power control circuitry 115, the sense blocks 51, 52...53, the read / write circuits 128, the controller 122, etc. The state machine is a circuit that can control the operation of the control circuitry 110. In some embodiments, the state machine is implemented or replaced by a microprocessor, microcontroller, and / or RISC processor.

[0035] An off-chip controller 122, which in one embodiment is a circuit, can include a processor 122e, memory such as a ROM 122a and a RAM 122b, and an error-correcting code (ECC) engine 245. The ECC engine can correct a number of read errors. The RAM 122b can be, for example, a DRAM that stores uncommitted data. During programming, a copy of the data to be programmed is stored in the RAM 122b until the programming is successfully completed. In response to successful completion, the data is erased from the RAM 122b and committed or released to the block of memory cells. The RAM 122b can store data for one or more word lines.

[0036] A memory interface 122d can also be provided. The memory interface, which communicates with the ROM, RAM, and processor, is circuitry that provides an electrical interface between the controller and the memory die. For example, the memory interface can change the format or timing of signals, provide a buffer, isolate electrical surges, latch I / O, etc. The processor can issue commands to the control circuit 110 (or any other component of the memory die) via the memory interface 122d.

[0037] The memory in the controller 122, such as the ROM 122a and the RAM 122b, includes code, such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, the processor can access code from a sub-group 126a of the memory structure, such as a reserved area of memory cells in one or more word lines.

[0038] For example, the controller can use code to access the memory structure, such as for programming operations, read operations, and erase operations. The code can include boot code and control code (e.g., a set of instructions). Boot code is software that initializes the controller during a boot or startup process and enables the controller to access the memory structure. The controller can use the code to control one or more memory structures. At power-up, the processor 122e fetches boot code from the ROM 122a or the sub-group 126a for execution, and the boot code initializes the system components and loads control code into the RAM 122b. Once the control code is loaded into the RAM, it is executed by the processor. The control code includes drivers that perform basic tasks, such as controlling and allocating memory, prioritizing processing of instructions, and controlling input and output ports.

[0039] The controller, e.g., RAM 122b and / or control circuitry 110, can store parameters indicative of the expected number of failed bits in a block. These parameters can include, for example, the number of bits per cell stored in the memory cells, the portion of word lines programmed in a block or sub-block, the portion of sub-blocks programmed in a block, the strength of ECC processing used to store and read data in a block, the duration of pre-read voltage pulses if used, and read accuracy, such as bit line or word line voltage settling time and number of sense passes.

[0040] Generally, the control code can include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and to provide voltage waveforms, including those discussed further below. The control circuitry can be configured to execute instructions for performing the functions described herein.

[0041] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smartphone, a tablet, a digital camera) that includes one or more processors, one or more processor-readable memory devices (RAM, ROM, flash memory, hard drives, solid state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host can also include additional system memory, one or more input / output interfaces and / or one or more input / output devices in communication with the one or more processors.

[0042] Other types of non-volatile memory can be used in addition to NAND flash memory.

[0043] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices, non-volatile memory devices, such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0044] The memory devices can be formed of passive elements and / or active elements in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements such as resistive random access memory (ReRAM) or phase change material, and optional steering elements such as diodes or transistors. Further, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric material.

[0045] The plurality of memory elements can be configured such that they are connected in series or such that each element can be individually accessed. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of series-connected transistors including memory cells and SG transistors.

[0046] A NAND memory array can be configured such that the array is composed of a plurality of strings of memory, where a string is composed of a plurality of memory elements that share a single bit line and are accessed as a group. Alternatively, the memory elements can be configured such that each element can be individually accessed, for example a NOR memory array. NAND and NOR memory configurations are examples, and the memory elements can be configured in other ways.

[0047] Semiconductor memory elements located within and / or on a substrate can be arranged in two dimensions or three dimensions, such as a 2D memory structure or a 3D memory structure.

[0048] In a 2D memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. For example, see Figure 9 Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an x-y directional plane) that extends substantially parallel to a major surface of a substrate on or in which the memory elements are formed. The substrate can be a wafer on or in which layers of memory elements are formed, or it can be a carrier substrate to which the memory elements are attached after formation. By way of non-limiting example, the substrate can comprise a semiconductor such as silicon.

[0049] The memory elements can be arranged in a single memory device level in an ordered array, such as in a plurality of rows and / or columns. However, the memory elements can be arranged in irregular or non-orthogonal configurations. The memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0050] A 3D memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, forming a three-dimensional structure (i.e., in the x, y, and z directions, where the z direction is substantially perpendicular to a major surface of the substrate, and the x and y directions are substantially parallel to the major surface of the substrate).

[0051] As a non-limiting example, a 3D memory structure can be arranged vertically as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to a major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements. See, e.g., Figure 7A These columns can be arranged, e.g., in a 2D configuration in the x-y plane, resulting in a 3D arrangement of memory elements with the elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0052] By way of non-limiting example, in a 3D NAND memory array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., x-y) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other 3D configurations are contemplated in which some NAND strings contain memory elements in a single memory level, while other strings contain memory elements that span multiple memory levels. A 3D memory array can also be designed in a NOR configuration and in a ReRAM configuration.

[0053] Generally, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, a monolithic 3D memory array can also have one or more memory tiers that are at least partially within the single substrate. As a non-limiting example, the substrate can comprise a semiconductor, such as silicon. In a monolithic 3D array, the layers that make up each memory device level of the array are generally formed on the layers of the underlying memory device level of the array. However, the layers of adjacent memory device levels of a monolithic 3D memory array can be shared between memory device levels or have intervening layers between memory device levels.

[0054] 2D arrays can be formed individually and then packaged together to form a non-monolithic memory device with multiple tiers of memory. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of one another. The substrates can be thinned or removed from the memory device levels prior to stacking, but because the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Further, multiple 2D memory arrays or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0055] Associated circuitry is generally needed to operate and communicate with memory elements. As a non-limiting example, a memory device can have circuitry for controlling and driving memory elements to implement functions such as programming and reading. This associated circuitry can be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read-write operations can be positioned on a separate controller chip and / or on the same substrate as the memory elements.

[0056] Those skilled in the art will recognize that the technology is not limited to the described 2D example structures and 3D example structures, but encompasses all relevant memory structures within the spirit and scope of the technology as described herein and as understood by those skilled in the art.

[0057] Figure 1B is Figure 1A A block diagram of an arrangement of memory devices 100 in which control circuitry 130 on a first die 130a communicates with memory structures 126 on a separate second die 126b. The control circuitry can communicate with the memory structures and die 126b via a memory interface 131 (e.g., similar to memory interface 122d). Examples of memory interfaces (I / F) include JEDEC’s Common Flash Memory Interface. The technology described herein can be implemented with a control die 130a incorporated with one or more memory dies 126b, in which the memory dies include memory structures 126 and the control die includes control circuitry 130 representing all or a subset of the peripheral circuitry for the memory structures. The control circuitry can be on the same die as the multiple memory units or on a different die from the multiple memory units.

[0058] For example, the memory structure may include non-volatile memory cells. In some embodiments, the memory die and control die are combined. Control circuitry 130 may include a set of circuitry that performs memory operations (e.g., write, read, erase, etc.) on the memory structure. The control circuitry may include a state machine 112, a memory area 113, an on-chip address decoder 114, and power control circuitry 115. In another embodiment, a portion of the read / write circuitry 128 is located on the control die 130a, while another portion of the read / write circuitry is located on the memory die 126b. For example, the read / write circuitry may include a sense amplifier. This sense amplifier may be located on the control die and / or the memory die.

[0059] In an exemplary embodiment, control circuitry 130 is configured to connect to the NAND string and the substrate, and memory interface 131 is connected to the control circuitry. This circuitry can be configured to issue commands via the memory interface to apply different voltage signals to bit lines, word lines, select gate lines, and the substrate including the p-well. For example, the control circuitry can send commands to… Figure 3 The CELSRC driver 332 in the middle issues commands to provide Figure 12 The voltage signal Vcelsrc for curve 1230. This command can include the following sequence: setting Vcelsrc = 0V at t0, setting Vcelsrc = Vcelsrc1 during t0-t2, setting Vcelsrc = Vcelsrc2 during the time period tkick1 from t2 to t4, setting Vcelsrc = Vcelsrc1 during t4-t12, and setting Vcelsrc = 0V at t12. For example, the control circuit can send... Figure 3 The p-well voltage driver 330 in the middle issues commands to provide Figure 12 The voltage signal Vp-well for curve 1240. This command may include the following sequence: set Vp-well = 0V at t0, set Vp-well = Vp-well1 from t0 to t12, and set Vp-well = 0V at t12.

[0060] The term "memory die" can refer to a semiconductor die containing non-volatile memory cells for storing data. The term "control circuit die" can refer to a semiconductor die containing control circuitry for performing memory operations on the non-volatile memory cells on the memory die. Typically, many semiconductor dies are formed from a single semiconductor wafer.

[0061] Figure 2 It is shown Figure 1AFIG. 1 illustrates a block diagram of one embodiment of a sensing block 51. Individual sensing blocks 51 are divided into one or more core portions, referred to as sensing circuits 60-63 or sense amplifiers, and a common portion, referred to as a management circuit 190. In one embodiment, each sensing circuit is connected to a respective bit line and NAND string, and the common management circuit 190 is connected to a group of multiple (e.g., four or eight) sensing circuits. Each sensing circuit in the group communicates with the associated management circuit via a data bus 176. Thus, there is one or more management circuits in communication with a group of sensing circuits of storage elements (memory cells).

[0062] For example, the sensing circuit 60 operates during a program cycle to provide a pre-charge / program-inhibit voltage to unselected bit lines or a program-enable voltage to selected bit lines. An unselected bit line is connected to an unselected NAND string and an unselected memory cell therein. The unselected memory cell can be a memory cell in an unselected NAND string where the memory cell is connected to a selected or unselected word line. The unselected memory cell can also be a memory cell in a selected NAND string where the memory cell is connected to an unselected word line. A selected bit line is connected to a selected NAND string and a selected memory cell therein.

[0063] The sensing circuit 60 also operates during a verify test in a program cycle to sense a memory cell to determine whether it has completed programming by reaching an assigned data state (e.g., as indicated by its Vth exceeding a verify voltage for the assigned data state). The sensing circuit 60 also operates during a read operation to determine a data state to which a memory cell has been programmed. The sensing circuit 60 also operates in an erase operation during a verify test to determine whether a plurality of memory cells have a Vth below a verify voltage. As further described below, the verify test can be performed on memory cells connected to all word lines in a block or memory cells connected to odd or even word lines. The sensing circuit performs sensing by determining whether a conduction current in the connected bit line is above or below a predetermined threshold level. This indicates whether the Vth of the memory cell is below or above the word line voltage, respectively.

[0064] The sense circuit can include a selector 56 or switch connected to the transistor 55 (e.g., nMOS). Based on the voltage at the control gate 58 and the drain 57 of the transistor 55, the transistor can operate as a pass gate or bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage on the drain, the transistor operates as a pass gate to pass the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, a program-inhibit voltage, e.g., 1-2V, can be passed when pre-charging and inhibiting unselected NAND strings. Alternatively, a program-enable voltage, such as 0V, can be passed to allow programming in selected NAND strings. The selector 56 can pass a supply voltage Vdd (e.g., 3-4V) to the control gate of the transistor 55 to cause the transistor to operate as a pass gate.

[0065] When the voltage at the control gate is lower than the voltage on the drain, the transistor 55 operates as a source follower to set or clamp the bit line voltage at Vcg-Vth, where Vcg is the voltage on the control gate 58 and Vth (e.g., 0.7V) is the threshold voltage of the transistor 55. This assumes the source line is at 0V. If Vcelsrc is non-zero, the bit line voltage is clamped at Vcg-Vcelsrc-Vth. Thus, the transistor is sometimes referred to as a bit line clamp (BLC) transistor, and the voltage Vcg on the control gate 58 is referred to as the bit line clamp voltage Vblc. This mode can be used during sensing operations, such as read and verify operations. The bit line voltage is thus set by the transistor 55 based on the voltage output by the selector 56. For example, the selector 56 can pass Vbl_sense+Vth (e.g., 1.5V) to the control gate of the transistor 55 to provide Vbl_sense, e.g., 0.8V, on the bit line. The Vbl selector 173 can pass a relatively high voltage such as Vdd to the drain 57 to provide a source follower mode during sensing operations, which is higher than the control gate voltage on the transistor 55. Vbl refers to the bit line voltage.

[0066] The Vbl selector 173 can pass one of a plurality of voltage signals. For example, for respective bit lines of unselected NAND strings during a program cycle, the Vbl selector can pass a program-inhibit voltage signal that increases from an initial voltage (e.g., 0V) to a program-inhibit voltage (e.g., Vbl_inh). For respective bit lines of selected NAND strings during a program cycle, the Vbl selector 173 can pass a program-enable voltage signal, such as 0V. For example, the Vbl selector can select the voltage signal from the BL voltage drivers 340 in the Figure 3 based on commands from the processor 192. The Vbl selector 173 can pass the voltage signal from the BL voltage drivers 340 in the

[0067] In one approach, the selector 56 of each sense circuit can be controlled separately from the selectors of the other sense circuits. The Vbl selector 173 of each sense circuit can also be controlled separately from the Vbl selectors of the other sense circuits.

[0068] During sensing, the sense node 171 is charged up to an initial voltage Vsense init, such as 3V. The sense node is then passed to the bit line via the transistor 55, and the amount of decay of the sense node is used to determine whether the memory cell is in a conductive state or a non-conductive state. The amount of decay of the sense node also indicates whether the current Icell in the memory cell exceeds the reference current Iref. If Icell <= Iref, the memory cell is in a conductive state, and if Icell > Iref, the memory cell is in a non-conductive state.

[0069] Specifically, the comparison circuit 175 determines the amount of decay by comparing the sense node voltage to a trip voltage at the time of sensing. If the sense node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is at or below the verify voltage. If the sense node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is above the verify voltage. For example, the sense node latch 172 is set to 0 or 1 by the comparison circuit 175 based on whether the memory cell is in a conductive state or a non-conductive state, respectively. The data in the sense node latch can be read by the processor 192 and used to update the bits of the trip latch 174. Subsequently, for the next program loop, the processor can use the bits in the trip latch and the assigned data states in the latches 194-197 to determine whether the memory cell and NAND string are selected for or not selected for programming in the program loop, thereby passing the appropriate enable or inhibit bit line voltage to the bit line, respectively. The latches 194-197 can be considered data latches or user data latches, as they store the data to be programmed into the memory cell.

[0070] The management circuit 190 includes a processor 192, four sets of exemplary data latches 194-197 for the sense circuits 60-63, respectively, and an I / O interface 196 coupled between the data latch sets and the data bus 120. One set of three data latches can be provided for each sense circuit, e.g., including separate latches LDL, MDL, and UDL. In some cases, a different number of data latches can be used. In a three bits per cell implementation, LDL stores bits for a lower page of data, MDL stores bits for a middle page of data, and UDL stores bits for an upper page of data.

[0071] The processor 192 performs computations to determine the data stored in the sensed memory cells and stores the determined data in the set of data latches. Each set of data latches 194-197 is used to store the data bits determined by the processor 192 during a read operation and to store the data bits imported from the data bus 120 during a program operation, which represent the write data to be programmed into the memory. The I / O interface 196 provides an interface between the data latches 194-197 and the data bus 120.

[0072] During a read, the operation of the system is under the control of the state machine 112, which controls the application of different control gate voltages to the addressed memory cells. As it steps through the various predefined control gate voltages corresponding to the various memory states supported by the memory, the sense circuitry can trip at one of these voltages and the corresponding output will be provided from the sense circuitry to the processor 192 via the data bus 176. At this point, the processor 192 determines the resulting memory state by considering the trip event of the sense circuitry and the information about the control gate voltage applied from the state machine via the input line 193. It then computes the binary encoding of the memory state and stores the resulting data bits into the data latches 194-197.

[0073] Some implementations can include multiple processors 192. In one embodiment, each processor 192 will include an output line (not shown) such that each output line is wired or wired together. In some embodiments, the output line is inverted before being connected to the line or line. This configuration enables a quick determination of when the programming process is complete during a program verify test, as the receiving state machine can determine when all programmed bits have reached the desired level. For example, when each bit reaches its required level, a logical zero for that bit will be sent to the line or line (or data one is inverted). When all bits output a 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sense circuits, the state machine needs to read the line or line eight times, or add logic to the processor 192 to accumulate the results of the relevant bit lines such that the state machine only needs to read the line or line once. Similarly, by choosing the logic levels correctly, a global state machine can detect when the first bit changes its state and change the algorithm accordingly.

[0074] During a program or verify operation of the memory cells, the data to be programmed (write data) is stored in the data latch set 194-197 from the data bus 120. During reprogramming, a corresponding set of data latches for the memory cells can store data based on the program pulse magnitude that indicates when the memory cells are enabled for reprogramming.

[0075] Under the control of the state machine, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be incrementally increased by one step from the previous programming pulse during the process, a process known as incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When both are consistent, the processor 192 sets the bit line to a programming-inhibited mode, such as by updating its latch. This prevents further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0076] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some specific implementations, the data latches are implemented as shift registers, such that parallel data stored therein is converted into serial data on the data bus 120 and vice versa. All data latches corresponding to read / write blocks of memory cells can be connected together to form a block shift register, thereby enabling the serial transfer of input or output data blocks. Specifically, the read / write circuit module group is adjusted such that its data latch group shifts data sequentially into or out of the data bus as if they were part of a shift register for the entire read / write block.

[0077] Data latches indicate when an associated memory cell has reached certain milestones in a programming operation. For example, a latch might identify when the Vth of a memory cell is below a specific verification voltage. Data latches also indicate whether a memory cell is currently storing one or more bits from a page of data. For example, an LDL latch can be used to store the next page of data. An LDL latch is toggled (e.g., from 0 to 1) when the next page bit is stored in the associated memory cell. An MDL or UDL latch is toggled for each three-bit cell when the middle or previous page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell has completed programming.

[0078] Figure 3 It shows Figure 1A An exemplary specific implementation of power control circuitry 115 for supplying voltage to blocks of memory cells in a plane is provided. In one approach, the circuitry shown may be repeated for each plane of the die. In this example, memory structure 126 includes a set of four associated blocks B0-0 through B0-3 and another set of four associated blocks B0-4 through B0-7. See also Figure 6 A block can lie in one or more planes. Figure 1ARow decoders 124 provide voltages to word lines and select gate control lines of each block via pass transistors 322. In one approach, a separate row decoder is provided for each block. The row decoders can be provided on one side of the blocks, such as Figure 8 The row decoders provide control signals to the pass transistors that connect the blocks to the row decoders. In one approach, the pass transistors of each group of blocks are controlled by a common control gate voltage. Thus, the pass transistors of a group of blocks are all on or off at a given time. If the pass transistors are on, then the voltage from the row decoder is provided to the corresponding control gate line or word line. If the pass transistors are off, then the row decoder is disconnected from the corresponding control gate line or word line so that the voltage floats on the corresponding control gate line or word line.

[0079] For example, control gate line 312 is connected to pass transistor group 313-316, which in turn are connected to control gate lines B0-4 to B0-7, respectively. Control gate line 317 is connected to pass transistor group 318-321, which in turn are connected to control gate lines B0-0 to B0-3, respectively.

[0080] Generally, programming or read operations are performed on one selected block at a time in a block. Erase operations can be performed on selected blocks or sub-blocks. Row decoders can connect global control lines 302 to local control lines 303. The control lines represent conductive paths. Voltages are provided on the global control lines of many voltage drivers. Some voltage drivers can provide voltages to switches 350 connected to the global control lines. Control pass transistors 324 to transfer the voltages from the voltage drivers to the switches 350.

[0081] Multiple voltage drivers connected to the pass transistors can be provided. For example, selected data word line driver WL_sel driver 347 provides a voltage on a selected data word line during a programming or read operation. For example, WL_sel driver 347 can provide a pre-charge voltage and a program voltage on a selected word line during a program cycle of a program operation, or a read voltage on a selected word line during a read operation. WL_unsel driver 348 provides a voltage on unselected data word lines during a read operation, such as Vread. A dummy word line driver is also provided. WLDD driver 349 provides a voltage on a drain side dummy word line WLDD, and WLDS driver 349a provides a voltage on a source side dummy word line WLDS. WLDD and WLDS can also receive Vread during a read operation. See also Figure 12 .

[0082] The voltage drivers can also include a separate SGD driver for each sub-block. For example, such as in Figure 8The SGD drivers can provide voltages to control lines connected to the control gates of the SGD transistors (drain-side select gate transistors). In one option, the SGS drivers are common to different sub-blocks in a block, and provide voltages to control lines connected to the control gates of the SGS transistors (source-side select gate transistors).

[0083] Various components including the row decoder can receive commands from a controller such as state machine 112 or controller 122 to perform the functions described herein.

[0084] P-well voltage driver 330 provides voltage Vp-well to p+ contact 724 in p-well region 792, e.g., via conductive path 682. See FIG. 6. Figure 7A In one approach, p-well region 792 is common to a group of blocks. These blocks also share a set of bit lines 342. Source line voltage driver (referred to as CELSRC driver 331) provides voltage Vcelsrc to the source end of the NAND strings. For example, Vcelsrc can be provided to n+ contact 723 in p-well region 792, e.g., via local interconnect 723a in FIG. 6. Figure 7A Vcelsrc can be provided to the source end of the NAND strings via the substrate at the same time as Vp-well, as described further below, thereby biasing the NAND strings in a manner that reduces resistance during read operations.

[0085] Bit line voltage driver 340 includes a voltage source that provides a voltage to bit line 342. The bit line voltage for sensing can be, for example, 0.5 V.

[0086] Figure 4 An exemplary memory cell in a memory device is shown. Figure 1A Memory cell 400 is a type of transistor. For example, the memory can be based on an n-channel MOSFET transistor that includes a charge storage layer, such as a charge-trapping material (e.g., SiN) or a floating gate layer (e.g., doped polysilicon). The memory cell can be in a 2D or 3D memory device. The memory cell includes a control gate 401 with voltage Vcg, a drain 403 with voltage Vbl, a source 402 with voltage Vcelsrc, and a body 404 with voltage Vp-well. The drain is connected to a bit line 406 with voltage Vbl via a voltage drop 405, which represents the voltages of other memory cells in the NAND string. Assuming that the voltage drop is negligible, the drain voltage is Vbl and the source voltage is Vcelsrc.

[0087] Various components including the row decoder can receive commands from a controller such as state machine 112 or controller 122 to perform the functions described herein.

[0084] P-well voltage driver 330 provides voltage Vp-well to p+ contact 724 in p-well region 792, e.g., via conductive path 682. See FIG. 6. Figure 7A In one approach, p-well region 792 is common to a group of blocks. These blocks also share a set of bit lines 342. Source line voltage driver (referred to as CELSRC driver 331) provides voltage Vcelsrc to the source end of the NAND strings. For example, Vcelsrc can be provided to n+ contact 723 in p-well region 792, e.g., via local interconnect 723a in FIG. 6. Figure 7A Vcelsrc can be provided to the source end of the NAND strings via the substrate at the same time as Vp-well, as described further below, thereby biasing the NAND strings in a manner that reduces resistance during read operations.

[0085] Bit line voltage driver 340 includes a voltage source that provides a voltage to bit line 342. The bit line voltage for sensing can be, for example, 0.5 V.

[0086] Figure 4 An exemplary memory cell in a memory device is shown. Figure 1A Memory cell 400 is a type of transistor. For example, the memory can be based on an n-channel MOSFET transistor that includes a charge storage layer, such as a charge-trapping material (e.g., SiN) or a floating gate layer (e.g., doped polysilicon). The memory cell can be in a 2D or 3D memory device. The memory cell includes a control gate 401 with voltage Vcg, a drain 403 with voltage Vbl, a source 402 with voltage Vcelsrc, and a body 404 with voltage Vp-well. The drain is connected to a bit line 406 with voltage Vbl via a voltage drop 405, which represents the voltages of other memory cells in the NAND string. Assuming that the voltage drop is negligible, the drain voltage is Vbl and the source voltage is Vcelsrc.

[0087] Various components including the row decoder can receive commands from a controller such as state machine 112 or controller 122 to perform the functions described herein.

[0084] Figure 5A An exemplary plot of memory cell current Icell versus time is shown for a memory cell Figure 4 As mentioned at the outset, for an accurate read of the memory cell, Icell should stabilize at a target level Itarget. However, another goal is for the read time to be as short as possible. To get Icell to stabilize as quickly as possible, it should ramp up or increase to Itarget as quickly as possible. In this example, Icell starts to increase at t = 0. Curves 500, 501, and 502 represent Icell reaching Itarget at progressively longer times ti, t2, and t3, respectively. If the read time is at, for example, ti, the longer read times t2and t3of curves 501 and 502 can result in read errors because Icell has not stabilized. Thus, shortening the read time too much can not be acceptable if the allowed ramp-up time for Icell is too small.

[0088] Figure 5B An exemplary plot of sector failure probability versus failure bit count (FBC) is shown, showing the effect of different read times as shown in Figure 5A A sector is the smallest logical unit of a memory device and can include, for example, 512-2048 kB. A page of data can include, for example, 32 or 64 sectors. As mentioned, shortening the time allowed for Icell to ramp up to Itarget can result in read errors. Figure 5A The cases of curves 500-502 of Figure 5B are represented by curves 510-512, respectively, in For a given desired FBC and a given ramp-up rate, the sector failure probability increases as the read time decreases.

[0089] Figure 6 is a perspective view of an exemplary memory die 600 in which the blocks are disposed in respective planes P0and Pi, consistent with Figure 1A The memory die includes a substrate 601, an intermediate region 602 in which blocks of memory cells are formed, and an upper region 603 in which one or more upper metal layers are patterned to form bit lines. Planes P0and Pi represent respective isolation regions formed in the substrate 601. In addition, a first block sequence 605 of n blocks (labeled B0-0through B0-n-1) is formed in P0, and a second block sequence 615 of n blocks (labeled Bi-0through Bi-n-1) is formed in Pi. Each plane can have associated row and column control circuitry, such as row decoders 124, read / write circuitry 128, and column decoders 132 of Figure 1A .

[0090] In one approach, control circuitry 110, which can be located in a peripheral region of the die, can be shared between the planes. Each plane can have a separate set of bit lines.

[0091] By providing blocks of memory cells in multiple planes, parallel operations can be performed in the planes. For example, blocks in different planes can be erased simultaneously.

[0092] The substrate 601 can also carry circuitry under the blocks, and one or more lower metal layers that are patterned in conductive paths to carry signals for the circuitry.

[0093] In this example, the memory cells are formed in vertical NAND strings in the blocks, consistent with Figure 7A Each block includes a stacked region of memory cells, with the stacked, alternating layers representing word lines. In one possible approach, each block has opposite, layered sides from which vertical contacts extend upward to the upper metal layer to form connections to the conductive paths. While two planes are shown as an example, other examples can use four or more planes. One plane per die is also possible.

[0094] While the above example involves a 3D memory device with vertically extending NAND strings, the techniques provided herein are also applicable to 2D memory devices in which the NAND strings extend horizontally on the substrate, consistent with Figure 9 .

[0095] Figure 7A An example cross-sectional view of a portion of a block B0-0 of Figure 6 includes a NAND string 700n in which the conductive paths do not extend in the memory cells 714 connected to WLn. The block includes a stack 700 of alternating conductive layers (word line layers) and dielectric layers. The layers can be rectangular slabs with a height in the z-direction, a width in the y-direction, and a length in the x-direction. The example conductive layers include SGS, WLDS, WL0, WL1, WL2... WLn-1, WLn, WLn+1... WL94, WL95, WLDD, and SGD. WLn represents the selected word line for a read or program operation. The dielectric layers are shown by a stippled pattern and include example dielectric layers DL. The conductive layers extend in a memory hole MH (see also Figure 7B ).

[0096] The stack is depicted as including one layer but can optionally include one or more layers of alternating conductive and dielectric layers. The stack includes a set of alternating conductive and dielectric layers in which a memory hole is formed during fabrication.

[0097] The conductive layers include SGS, WLDS, WL0-WL95, WLDD, and SGD(0) in addition to the 96 data word lines in this example, though the number of data word lines can be greater than or less than 96.

[0098] The conductive layers connected to the control gates of the memory cells are referred to as word lines, and the conductive layers connected to the control gates of the source side select gate transistors and the control gates of the drain side select gate transistors are referred to as source side control lines and drain side control lines, respectively. WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells. The dummy memory cells can have the same structure as the data memory cells, but the controller considers the memory cells ineligible to store any type of data including user data. One or more dummy memory cells can be provided at the drain end and / or the source end of the NAND string of memory cells to provide a gradual transition of the channel voltage gradient. WL0-WL95 are data word lines connected to data memory cells that are eligible to store user data.

[0099] The top 710t and the bottom 710b of the stack are shown. WL95 is the topmost data word line, and WL0 is the bottommost data word line.

[0100] The NAND strings are formed by etching memory holes in the stack, and then depositing a plurality of thin layers of material along the sidewalls of the memory holes. Memory cells are formed in regions where a word line intersects the plurality of thin layers, and select gate transistors are formed in regions where the SGS and SGD control lines intersect the plurality of thin layers. For example, a drain side select gate transistor 716 is formed where the SGD control line intersects the plurality of thin layers, a source side select gate transistor 701 is formed where the SGS control line intersects the plurality of thin layers, and a selected memory cell 714 is formed where WLn intersects the plurality of thin layers.

[0101] The plurality of thin annular layers can be deposited, for example, using atomic layer deposition. For example, the layers can include a blocking oxide layer 763, a charge trapping layer 764 or film such as silicon nitride (Si3N4) or other nitride, a tunnel layer 765 (e.g., gate oxide), and a channel layer 766 (e.g., including polysilicon). A dielectric core 793 (e.g., containing silicon dioxide) can also be provided. The word lines or control lines can contain a metal such as tungsten. In this example, all of the layers are disposed in the memory hole. In other approaches, some of the layers can be disposed in the word line or control line layers. The plurality of thin layers form a columnar active region of the NAND string.

[0102] The stack is formed on a substrate 601. In one approach, the substrate includes a p-well region 792 connected to the source end of the NAND string (see also FIG. 7A). The p-well region 792 can be formed by implanting p-type dopants into the substrate 601. The p-well region 792 can be formed prior to the stack, or the stack can be formed on the substrate 601 and then the p-well region 792 can be formed by implanting p-type dopants into the substrate 601. Figure 3). The p-well region can include an epitaxial region 792a that extends upward adjacent to the SGS layer. The p-well region can include an n+ contact 723 connected to a local interconnect 723a (a conductive path or source line) to receive Vcelsrc, and a p+ contact 724 connected to a conductive path 724a to receive Vp-well. The local interconnect and conductive path can contain a conductive material, such as metal surrounded by insulating material, to prevent metal conduction with adjacent word lines. In one possible implementation, the p-well region 792 can be formed in an n-well 791, which in turn is formed in a p-type semiconductor region 720 of the substrate.

[0103] The NAND string 700n has a source end 700s connected to the p-well at the bottom 610b of the stack 610. The NAND string 700n also has a drain end 700d connected to the bit line BLO at the top 610t of the stack via a bit line contact 680 that contains n-type material.

[0104] NAND strings that employ this 3D configuration are considered to have floating body channels because the length of the channel is not formed on the substrate.

[0105] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. The electrons are attracted from the channel into the charge trapping layer and through the tunnel layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the channel of the NAND string is charged, such as by applying a positive erase pulse to the substrate, causing the electrons to return from the charge trapping layer to the channel.

[0106] During a read operation, Vcelsrc and Vp-well can be applied to contacts 723 and 724, respectively. In this example, the application of Vcelsrc can result in a conductive path CP1 or channel extending from contact 723 to WLn. CP1 is formed in the p-well. Specifically, CP1 extends under the SGS control line to one side of the SGS control line and in a portion 766a (see FIG. 7B) of the channel layer 766 that forms an inversion layer. The inversion layer is a channel in which current can pass between the source and drain terminals of each memory cell connected to WLDS to WLn-1. The SGS control line and the word lines WLDS to WLn-1 receive a voltage, e.g., Vread, that is high enough to place the corresponding transistors in a conductive state, allowing the inversion layer to form. In addition, in this example, the voltage applied to WLn is not high enough to place the memory cell 714 in a conductive state. Thus, CP1 terminates at WLn-1. CP1 is biased at Vcelsrc. Figure 7B

[0107] ​Also during the read operation, Vbl is applied at the bit line BL. Conductive path CP2 is formed in a via 740 that extends from the bit line to the top of the NAND string. CP3 continues the conductive path CP2 in the portion 766a of the channel layer 766 from the SGD control line to WLn+1. CP2 extends to one side of the SGD control line and extends in the portion 766a of the channel layer 766 in which the inversion layer is formed. The inversion layer is a channel in which current can pass between the source and drain terminals of each memory cell connected to WLDD to WLn+1. The SGD control line and the word lines WLDD to WLn+1 receive a voltage, e.g., Vread, that is high enough to place the corresponding transistors in a conductive state, thereby allowing the inversion layer to form. In this example, the memory cell 714 is in a non-conductive state so that CP2 terminates at WLn-1. CP2 is biased at Vcelsrc + Vbl.

[0108] Referring to Figure 7C , which is an example in which the memory cell 714 is in a conductive state.

[0109] When Vp-well is applied to the p-well via the contact 724, the remaining portion of the channel layer in which the inversion layer is not formed (see, e.g., portion 766b in Figure 7B ) is biased at Vp-well. This is a result of the bottom 766c of the channel layer 766 contacting the epitaxial region 792a of the p-well at the bottom of the NAND string. Because the inversion layer is confined to the portion 766a of the channel layer adjacent to the tunneling layer 765, the remaining portion 766b of the channel layer is available to be biased at Vp-well. Thus, the channel layer 766 can be simultaneously biased at Vcelsrc and Vp-well, which can be equal or different.

[0110] By providing a temporary kick down of Vcelsrc (Vkick) while not reducing Vp-well during the ramp up of Icell (see also Figure 12 ), the ramp up time can be shortened without increasing the number of read errors. For example, by reducing Vcelsrc from an initial voltage (e.g., 1.3 V) to a reduced voltage (e.g., 1 V) and keeping Vp-well constant at the initial voltage or another voltage greater than the reduced voltage, the Vth of the memory cell is reduced. Thus, the resistance in the channel is also reduced, and Icell can ramp up faster. This result can be understood by observing the formula for the threshold voltage (Vth) of a memory cell transistor, which is: V FB is the flat band voltage. φF is the bulk potential. The third term is the voltage across the oxide due to the depletion layer charge. In the third term, ε is the permittivity of silicon, q is the electronic charge, Na is the substrate doping density, V SBis the source-to-body voltage, and C is the gate oxide capacitance per unit area. With the cell voltage Vceiisrc and the body voltage Vp-well, reducing Vceiisrc also reduces V SB This, in turn, reduces Vth. Generally, as Vth decreases and as Vgate-to-source increases, Icell increases.

[0111] The kickback in Vceiisrc does not cause the transistor junction to be forward biased, as long as Vkick is not too large. Generally, in one approach, Vkick should be less than about 0.7 V. In Figure 7A and 7C The conductive path is shown by diagonal shading.

[0112] In the example of Figure 7A , the NAND string extends vertically on a substrate, the source end contacts a p-well of the substrate, and a source voltage signal Vceiisrc and a body voltage signal Vp-well are applied to the p-well.

[0113] Figure 7B An example cross-sectional view of a block portion of Figure 7A in the x-y plane at the WL0 level is shown. Layers of the NAND string 700n are shown, including a blocking oxide layer 763, a charge trapping layer 764, a tunnel layer 765, and a channel layer 766. Also shown is a dielectric core 793. As mentioned, the channel layer 766 includes a portion 766a adjacent to the tunnel layer 765. An inversion layer is formed in portion 766a to carry Vceiisrc in CP1, while another portion 766b of the channel layer acts as a body of the memory cell and is biased at Vp-well. Thus, a portion of the channel layer is biased by a source voltage signal Vceiisrc, and another portion of the channel layer is biased by a body voltage signal Vp-well. The inversion layer is formed by biasing the portion of the channel layer with the source voltage signal.

[0114] Figure 7C An example cross-sectional view of a portion of block B0-0 of Figure 6 is shown, including a NAND string 700n, with a conductive path CP3 extending in a memory cell 714 connected to WLn. In this example, the memory cell 714 is in a conductive state, such that a single continuous conductive path CP3 extends from contact 723 through a portion of the p-well, and through an entire length of the channel layer 766. CP3 is biased at Vceiisrc.

[0115] Figure 8 An example cross-sectional view of a portion of block B0-0 of Figure 6An exemplary view of a block B0-0 and associated bit lines and sense circuitry, where respective NAND strings are arranged in sub-blocks. The NAND strings are arranged in a 3D configuration in the sub-blocks of the block. Each sub-block SB0-SB3 includes a plurality of NAND strings. Three exemplary NAND strings are shown as a simplification. For example, SB0 includes NAND strings 700n, 700n1, and 700n2, SB1 includes NAND strings 710n, 710n1, and 710n2, SB2 includes NAND strings 720n, 720n1, and 720n2, and SB3 includes NAND strings 730n, 730n1, and 730n2. The NAND strings have consistent data word lines, dummy word lines, and select gate lines. Figure 7A Each sub-block includes a set of NAND strings that extend in the x-direction and have a common SGD line or control gate layer. In particular, SGD(0)-SGD(3) are located in SB0-SB3, respectively.

[0116] Programming of the block can be done based on a word line programming order. One option is to program memory cells in different word line portions located in different sub-blocks one sub-block at a time, before programming memory cells of a next word line. For example, this can involve programming WL0 in SB0, SB1, SB2, and SB3, then programming WL1 in SB0, SB1, SB2, and SB3, and so on. For example, the word line programming order can start at WL0 (source end word line) and end at WL95 (drain end word line).

[0117] In erase operations, the entire block is typically erased, but partial block erase is also possible.

[0118] In this example, each NAND string includes a plurality of memory cells between an SGS transistor and an SGD transistor. In other examples, more than one SGD transistor and / or SGS transistor can be provided for each NAND string. The number of dummy memory cells can also vary. For example, NAND string 700n includes SGS transistor 701, dummy memory cell 702, data memory cells 703-710, dummy memory cell 711, and SGD transistor 712. NAND string 710n includes SGS transistor 721, dummy memory cell 722, data memory cells 723-730, dummy memory cell 731, and SGD transistor 732. NAND string 720n includes SGS transistor 741, dummy memory cell 742, data memory cells 743-750, dummy memory cell 751, and SGD transistor 752. NAND string 730n includes SGS transistor 761, dummy memory cell 762, data memory cells 763-770, dummy memory cell 771, and SGD transistor 772.

[0119] This example shows one SGD transistor at the drain end of each NAND string, and one SGS transistor at the source end of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in the NAND strings.

[0120] A set of bit lines, including example bit lines BL0-BL2, are connected to the NAND strings. Each bit line is connected to a respective set of NAND strings, including one NAND string in each sub-block. For example, BL0 is connected to NAND strings 700n, 710n, 720n, and 730n, BL1 is connected to NAND strings 700n1, 710n1, 720n1, and 730n1, and BL2 is connected to NAND strings 700n2, 710n2, 720n2, and 730n2. Each bit line is also connected to a respective sense circuit, consistent with Figure 2 sense circuits 60-63. For example, BL0-BL2 are connected to sense circuits SC0-SC2, respectively.

[0121] In this example, the row decoder 124 is located at one side of the block, in the peripheral region of the substrate, consistent with Figure 6 the control circuit 110 shown in FIG. 1. The row decoder routes voltage signals to the word lines via conductive paths 810. In one approach, the conductive paths extend vertically in the z-direction to the upper region 603, then horizontally in the y-direction, then vertically downward in the -z-direction in vias that contact the word lines. The side of the block can have a stepped shape, where the vias can contact the edges of each word line. In this example, it is assumed that the stepped shape is closest to SB0. Thus, the RC delay of the word line voltage signals will be smallest for SB0 and largest for SB3. The distance between the row decoder and the sub-blocks is considered to increase gradually for SB0-SB3. To accommodate the varying RC delays for the different sub-blocks, the voltage kickback of Vcelsrc and the duration of the voltage kickback can be adjusted based on the sub-block being read, such as Figure 13 shown in FIG. 1.

[0122] Figure 9An exemplary NAND string in a 2D configuration is shown. The techniques discussed herein for controlling Vceiisrc and Vp-well to increase Iceii ramp-up time can be used in 2D memory devices as well as the 3D memory devices described above. Channels in a 2D memory device extend horizontally in a substrate rather than in a vertically extending channel layer. In this example, a substrate 900 includes a p-well 903 within an n-well 902, which in turn is in a p-substrate 901. Vp-well and Vceiisrc are provided to the p-well via contacts 910 and 911, respectively. A NAND string 919 is disposed on the substrate and includes select gate transistors and memory cells. For example, the NAND string includes an SGS transistor 920, memory cells 921, 922, and 923 connected to WLDS, WL0, and WL1, respectively, memory cells 924, 925, and 926 connected to WLn-1, WLn, and WLn+1, respectively, memory cells 927 and 928 connected to WL95 and WLDD, respectively, and an SGD transistor 929. Doped regions in the substrate (e.g., doped regions 911-917) act as sources and drains for the transistors. Vbl is provided to doped region 917. When appropriate voltages are provided to the NAND string, an inversion layer or channel 940 is formed in the p-well. The rest of the p-well 903a is biased at Vp-well.

[0123] An exemplary memory cell 924 includes a tunnel layer 930, a floating gate layer 931, a blocking oxide layer 932, and a control gate 933.

[0124] In this example, the NAND string extends horizontally on a substrate, a source voltage signal is applied to an n+ contact in the p-well, and a body voltage signal is applied to a p+ contact in the p-well.

[0125] In 2D or 3D configurations, in one approach, a source voltage signal is applied to an n+ contact in the p-well, and a body voltage signal is applied to a p+ contact in the p-well.

[0126] Figure 10 Threshold voltage (Vth) distributions for an eight-state memory device are shown. As an example, eight data states, or three bits per cell, are shown. The techniques herein are applicable to other modes, including one or more bits per cell. The vertical axis depicts the number of memory cells on a log scale, and the horizontal axis depicts threshold voltage on a linear scale. The Vth distribution can represent all memory cells in a block connected to a word line. After an erase block, a Vth distribution 1000 representing an erased state is obtained. The erase operation is complete when the Vth of all or almost all of the memory cells is below a verify voltage VvEr.

[0127] The memory cells then undergo programming operations. Each memory cell will have an assigned data state. Some memory cells are assigned to an erase state and are not programmed. In this example, most memory cells are programmed to higher states, such as AF, which are represented by Vth distributions 1001-1007 respectively. These memory cells undergo verification testing using verification voltages VvA-VvG.

[0128] In a read operation, memory cells are read by applying read voltages VrA-VrG to selected word lines. In one method, one page of data is read at a time. For example, VrA and VrE can be used to read the lower page data (and...). Figure 12 (Consistent), VrB, VrD, and VrF can be used to read intermediate page data, and VrC and VrG can be used to read upper page data.

[0129] Figure 11 An exemplary process for reducing read time in a NAND string is illustrated. Step 1100 initiates a sensing operation (e.g., read or verification) on a selected memory cell in the NAND string. For example, the memory cell could be... Figure 7A The memory cell 714 is connected to WLn. Selected memory cells in multiple NAND strings can be read simultaneously.

[0130] Next, steps 1101-1103 are performed. These steps may occur at least partially simultaneously, and may be performed within a certain timeframe. Figure 12 The t0-t2 period occurs. Step 1101 includes setting the word line voltage. The selected word line WLn can receive read voltages (e.g., VrA-VrG), such as... Figure 12 As shown in curve 1200, the remaining unselected word lines can receive voltage Vread, such as... Figure 12 As shown in curve 1210. Vread can be, for example, 8-9V, and is provided to memory cells connected to unselected word lines in a highly conductive state. This allows sensing of Vth of selected memory cells in the NAND string without interference from other memory cells in that NAND string. A voltage such as 6V can be provided to the SGS transistor and selected SGD transistor to make these transistors also in a highly conductive state, as... Figure 12 Curves 1211 and 1212 are shown in the figure. A voltage such as 0V can be supplied to unselected SGD transistors to put them in a non-conductive state, as shown in the figure. Figure 12 As shown in curve 1213, the selected SGD transistor is located in the sub-block where the read occurs. The unselected SGD transistor is located in the remaining unselected sub-blocks.

[0131] Step 1102 includes setting Vblc to a voltage that prevents current from flowing in the NAND string, such as...Figure 12 curve 1201 in FIG. 12B. This can be Figure 2 a positive voltage on the control gate 58 of the BLC transistor 55 in FIG. 12B. The positive voltage can be about 1.5 V, for example, no more than the sum of, for example, the Vth and Vceiisrc of the BLC transistor 55, such that the BLC transistor 55 is in a non-conductive state.

[0132] Step 1103 includes increasing Vceiisrc and Vp-well to an initial voltage, such as 1.3 V, as shown at curves 1230 and 1240, respectively, in FIG. 12B. Figure 12

[0133] Next, steps 1104 and 1105 are performed. These steps can occur at least partially concurrently, and can occur during t2-t4 in FIG. 12C. Figure 12 Step 1104 includes setting Vblc at a voltage that allows current Icell to flow in the NAND string, such as 2.5 V. Vblc can be set to a level above the sum of the Vth and Vceiisrc of the BLC transistor, such as above 0.7 + 1.3 = 2 V. When the BLC transistor is conductive, Vbl follows Vblc - Vth - Vceiisrc.

[0134] Step 1105 includes decreasing Vceiisrc by Vkick over a specified time period tkick while keeping Vp-well constant, such as Figure 12 as shown at curves 1230 and 1240, respectively, in FIG. 12B. Generally, Vp-well and Vceiisrc can be set such that Vp-well > Vceiisrc during the voltage kick. Vp-well can remain constant or increase during this voltage kick. That is, Vp-well can not decrease during this voltage kick. Figure 12 curve 1241 in FIG. 12B shows the option of increasing Vp-well during the voltage kick.

[0135] Vkick is the amount by which Vceiisrc is temporarily decreased from a first voltage Vceiisrcl. Vkick can be, for example, 0.2-0.5 V. As discussed, the voltage kick increases Icell by decreasing the channel resistance.

[0136] Step 1106 includes increasing Vceiisrc back to the initial voltage at the end of tkick, such as Figure 12 as shown by curve 1230 at t4-t6 in FIG. 12C. Step 1107 includes comparing Icell to a reference current, such as Figure 12 as shown by curve 1250 at t7-t8 in FIG. 12D. The sensing process is complete at step 1108.

[0137] ​Optionally, step 1107 compares Icell to the reference current during more than one read voltage, such as during Figure 12 VrE at t10-tl 1. The sensing process is complete at step 1108.

[0138] Figure 12 Exemplary voltage signals and Icell in a read operation are shown, consistent with Figure 11 This example involves reading lower page data in an eight-state memory device using read voltages VrA and VrE. At plot 1200, the voltage of the selected word line VWL_sel is increased from 0 V to VrA at t0-tl. The WL driver is requested to change VWL_sel from 0 V to VrA at t0, but the actual voltage increase is delayed because of the relatively large RC delay of the word line layers. Optionally, in the example of a spiked VWL_sel, VWL_sel is increased by requesting an output greater than VrA, then requesting an output of 0 V, then requesting an output of VrA.

[0139] In the first sensing period t7-t8, VWL_sel = VrA. Then, VWL_sel is increased to VrE at t9-tl 0 to sense in the second sensing period t10-tl 1.

[0140] Plot 1210 shows the voltage of the unselected word lines VWL_unsel from WLDS to WLn-1 and WLn+1 to WLDD in, for example Figure 7A Vread, for example 8-9 V, at t0-t2. The WL driver is requested to change VWL_unsel from 0 V to Vread at t0, but the actual voltage increase is delayed because of the relatively large RC delay of the word line layers. Plot 121 1 shows the voltage of the SGS transistor Vsgs. Vsgs is increased from 0 V to, for example, 6 V at t0-t2. Plot 1212 shows the voltage of the selected SGD transistor Vsgd_sel. Vsgd_sel and Vsgs are increased from 0 V to, for example, 6 V at t0 to about tl. Vsgd_sel will likely reach the requested voltage before Vsgs reaches the requested voltage because the RC of the SGD layer is smaller compared to the SGS layer.

[0141] Plot 1220 shows the voltage of the unselected word lines VWL_unsel from WLDS to WLn-1 and WLn+1 to WLDD in, for example Figure 2the BLC transistor to remain in a non-conductive state, but to prepare it for transition to a conductive state. Recall that the BLC transistor is in a non-conductive state if the gate-to-source voltage does not exceed the Vth of the BLC transistor. With Vcelsrc = 1.3 V, Vth = 0.7 V, and Vcg at 1.5 V, Vcg - Vcelsrc < Vth, or 1.5 V - 1.3 V = 0.2 V, which is less than 0.7 V. Vblc is increased from the first voltage to a second voltage Vblc2, e.g., 2.5 V, at t2-t3. The second voltage places the BLC transistor in a conductive state because Vcg - Vcelsrc > Vth, or 2.5 V - 1 V = 1.5 V, which is greater than 0.7 V. This provides a conductive path from the NAND string to the sense circuit that allows Icell to ramp up. Typically, the BLC transistor is controlled by the sense circuit to bias the drain end of the NAND string. During the voltage kick-down of Vcelsrc, the bias can include a positive voltage that is high enough to allow current to flow in the NAND string if the selected memory cell is in a conductive state. The control circuit can be configured to issue a command via the memory interface to cause the bit line clamp transistor to transition from a non-conductive state to a conductive state at the start of the temporary voltage kick-down, e.g., at t2. For the remainder of the sensing operation, e.g., until t12, the bit line clamp transistor can remain in a conductive state.

[0142] The increase of Vblc to Vblc2 overlaps with the voltage kick of Vcelsrc at t2-t4. The start of the increase of Vblc at t2 can be at the same time as the start of the voltage kick-down. At t3-t4, Vblc is decreased to a third voltage Vblc3, e.g., 2 V, which can be greater than Vblc1. The third voltage places the BLC transistor in a conductive state because Vcg - Vcelsrc > Vth, or 2 V - 1 V = 1 V, which is greater than 0.7 V.

[0143] The example involves increasing the control gate voltage of the bit line clamp transistor from a first voltage to a second voltage at a first portion of the temporary voltage kick-down, e.g., t2-t3, and decreasing the control gate voltage from the second voltage to a third voltage at a second portion of the temporary voltage kick-down, e.g., t3-t4. The example also involves increasing the control gate voltage of the bit line clamp transistor from the third voltage to a fourth voltage after the temporary voltage kick-down, where sensing of the selected memory cell occurs with the control gate voltage of the bit line clamp transistor at the fourth voltage. By providing Vblc3 < Vblc4, Ipeak1 does not become too high. In another option, Vblc3 > Vblc4.

[0144] At t4-t6, Vblc is increased to a fourth voltage Vblc4, e.g., 2.2V, which is suitable for sensing. In one approach, Vblc2 > Vblc3. Using a higher Vblc2 (compared to Vblc4 used during sensing) during the decrease of Vcelsrc can help increase the ramp-up rate of Icell. The decrease of Vblc from t3-t4 helps stabilize Icell. In another option, Vblc2 < Vblc4.

[0145] Curve 1230 shows the source voltage signal Vcelsrc. Vcelsrc is increased from 0V to a first voltage Vcelsrci, e.g., 1.3V, at t0-ti, and is stable at ti-t2. At t2, Vcelsrc is requested to decrease by a voltage Vkick, e.g., 0.3V, thus decreasing the channel resistance of the NAND string, as discussed. This decrease is referred to as a voltage kick-down. For example, Vcelsrc remains at a second, reduced voltage Vcelsrc2, e.g., 1V, until t4, at which time the voltage is requested to return to Vcelsrci. Vcelsrc can remain at Vcelsrci during the rest of sensing, e.g., until ti2. In this example, the value of Vcelsrc is equal before and after the voltage kick-down. Optionally, Vcelsrc before the voltage kick-down is different than Vcelsrc after the voltage kick-down. Typically, the resistance of the channel layer is decreased by a temporary voltage kick-down of the source voltage signal while the bulk voltage signal remains at its respective first voltage Vp-welli.

[0146] Curve 1240 shows the bulk voltage signal Vp-well. In this example, Vp-well is increased from 0V to a first voltage Vp-welli (which can be equal to Vcelsrci) at t0-ti, and is stable at ti-t2, similar to the increase of Vcelsrc. Optionally, Vp-welli is different than Vcelsrci. Vp-well can remain constant at Vp-welli for the rest of the sensing process at t2-ti2. Optionally, the value of Vp-well can change during tkick. For example, Vp-well can increase during tkick. Curve 1241 shows the option of Vp-well increasing to Vp-well2 > Vp-welli during the voltage kick. In one approach, Vcelsrci < Vp-welli during tkick.

[0147] Curve 1250 shows the current Icell in the NAND string involved in the sensing process. Icell is zero at t0-t2 because the BLC transistor is non-conductive. Icell reaches Ipeak at about t3. At t2, Icell starts to increase to a peak level Ipeakl. At t4-t6, Icell decreases to a target level Itarget for sensing because Vcelsrc increases. In this example, Ipeakl is greater than Itarget. This can help increase the ramp-up rate of Icell. In other options, Ipeakl can be less than or equal to Itarget. In an example consistent with curve 1250, the sensing circuit is configured to sense the selected memory cell in the NAND string after the temporary voltage is kicked back down, and the peak current in the NAND string during the temporary voltage kick back down is greater than the target current in the NAND string during sensing of the selected memory cell. Curve 1250 is based on the selected memory cell being in a conductive state, e.g., VwL_sel > Vth of the selected memory cell. If the selected memory cell is not in a conductive state, Icell will be lower.

[0148] Curves 1260 and 1270 represent a comparison case where Vp-well has a kick back down at the same time as the kick back down in Vcelsrc. Curve 1260 represents both Vcelsrc and Vp-well. Vcelsrc and Vp-well increase from 0 V to a first voltage Vcelsrcl at t0-tl and stabilize at tl-t2. At t2, Vcelsrc and Vp-well are requested to decrease Vkick. Since both voltages decrease together, there is no decrease in the channel resistance of this NAND string. Vcelsrc and Vp-well remain at the decreased second voltage Vcelsrc2 until t4, at which time they are requested to return to Vcelsrcl. Vcelsrc and Vp-well remain at Vcelsrcl during sensing.

[0149] Curve 1270 shows the comparison current Icell_comp consistent with curve 1260. Icell_comp is zero at t0-t2. At t2, Icell_comp increases to a peak level Ipeak2, which can be less than Ipeakl. At t5-t7, Icell decreases to Itarget because Vcelsrc increases. Icell_comp reaches Vpeak at about t4, which is later than when Icell reaches Vpeak at about t3 in curve 1250. This demonstrates that Icell has a higher ramp-up rate using the techniques described herein. Since Icell_comp reaches Vpeak at a later time, the sensing is delayed and the overall time of the read operation is increased.

[0150] exist Figure 12 In the example, the voltage of the body voltage signal remains constant at Vp-well1 throughout the entire temporary voltage downswing (e.g., from t2-t4). Additionally, the voltage of the body voltage signal is equal to the voltage of the source voltage signal at the start of the temporary voltage downswing, for example, at t2. Furthermore, the voltage of the source voltage signal during sensing is equal to the voltage of the source voltage signal during the temporary voltage downswing (e.g., Vcelsrc1). Additionally, a bit-line clamp transistor is connected to the drain terminal of the NAND string, and the control circuitry is configured to temporarily increase the control gate voltage of the bit-line clamp transistor during the temporary voltage downswing (e.g., increase it to Vblc2).

[0151] Figure 13 The curves showing the relationship between Vkick and / or tkick and the selected sub-block represent the distance to the WL driver, and... Figure 8 Consistent. As mentioned, during a read operation on a NAND string, the magnitude and duration of this negative voltage bounce can be adjusted based on various factors, such as the position of the NAND string within the block and its distance from the WL driver. In one approach, this is implemented by adjusting Vkick and / or tkick based on the sub-block being read. Assume SB0 is the closest WL driver and SB3 is the farthest. Therefore, SB3 has the largest RC delay when setting the word line voltage. The solution is to provide progressively larger Vkick and / or tkick for sub-blocks that are progressively farther away from the WL driver. Typically, when performing a read operation on a NAND string in a selected sub-block, Vkick and / or tkick can be set according to the position of the selected sub-block among multiple sub-blocks of the block.

[0152] By adjusting Vkick and / or tkick, read time can be kept constant across sub-blocks.

[0153] In one approach, the NAND string involved in the read operation is located in a selected sub-block of a block, and the control circuitry is configured to adjust the amount and / or duration of the temporary voltage downslip of Vcelsrc based on the location of the selected sub-block within the block.

[0154] Thus, it can be seen that in one implementation, an apparatus includes control circuitry configured to connect to a sense circuit and a NAND string, the NAND string including a source terminal and a drain terminal, the drain terminal connected to the sense circuit, and the NAND string including a plurality of memory cells, the plurality of memory cells including a selected memory cell; and a memory interface connected to the control circuitry. The control circuitry is configured to issue a command via the memory interface to bias the NAND string with a source voltage signal and a bulk voltage signal, the source voltage signal and the bulk voltage signal increasing to respective first voltages, after which the source voltage signal has a temporary voltage kick down without the bulk voltage signal decreasing, and to control the sense circuit to bias the drain terminal of the NAND string during the temporary voltage kick down and to sense the selected memory cell after the temporary voltage kick down.

[0155] In another implementation, a method includes increasing a current in a channel of a NAND string to a peak level, increasing the current including applying a source voltage signal and a bulk voltage signal to the NAND string, the source voltage signal and the bulk voltage signal increasing to respective first voltages, after which the source voltage signal has a temporary voltage kick down without the bulk voltage signal decreasing; and after increasing the current to the peak level, decreasing the current to a target level and sensing a selected memory cell in the NAND string.

[0156] In another implementation, an apparatus includes control circuitry configured to connect to a substrate and to a NAND string on the substrate, the substrate including an n+ contact and a p+ contact, the NAND string including a source terminal, a drain terminal, a channel layer, and a plurality of memory cells, and the control circuitry to perform a read operation on a selected memory cell in the plurality of memory cells is configured to: apply a source voltage signal to the n+ contact, the source voltage signal including a temporary voltage kick down; apply a bulk voltage signal to the p+ contact, a voltage of the bulk voltage signal being greater than a voltage of the source voltage signal during the temporary voltage kick down; and after the temporary voltage kick down, sense a current in the NAND string.

[0157] The foregoing implementations of the application have been described in accordance with the underlying principles thereof. It is to be understood that the foregoing description has been presented for purposes of illustration and description, and is not intended to be exhaustive or to limit the application to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the application be limited not with this detailed description, but rather by the claims appended hereto.

Claims

1. A memory device, comprising: control circuitry (110, 122) configured to connect to a sense circuit (60-63) and a NAND string (700n, 700n1, 700n2; 710n, 710n1, 710n2; 720n, 720n1, 720n2; 730n, 730n1, 730n2) that includes a source terminal (700s) and a drain terminal (700d) that connects to the sense circuit and that includes a plurality of memory cells (703-710; 763-770) that includes a selected memory cell (714); 723-730；743-750； and a memory interface (131) that connects to the control circuitry, the control circuitry configured to issue commands via the memory interface to bias the NAND string with a source voltage signal (Vcelsrc) and a body voltage signal (Vp-well) that increase to respective first voltages (Vcelsrc1, Vp-well1) after which the source voltage signal has a temporary voltage kick-down (Vcelsrc2) without the body voltage signal decreasing, and to control the sense circuit to bias the drain terminal of the NAND string during the temporary voltage kick-down and to sense the selected memory cell after the temporary voltage kick-down; wherein: the sense circuit includes a bit line clamp transistor (55); and the control circuitry is configured to issue commands via the memory interface to cause the bit line clamp transistor to transition from a non-conductive state to a conductive state at a start (t2) of the temporary voltage kick-down.

2. The memory device of claim 1, wherein: the NAND string extends vertically on a substrate (601); the source terminal contacts a p-well (792) of the substrate; and the control circuitry is configured to apply the source voltage signal and the body voltage signal to the p-well.

3. The memory device of claim 2, wherein: the control circuitry is configured to apply the source voltage signal to an n+ contact (723) in the p-well and to apply the body voltage signal to a p+ contact (724) in the p-well.

4. The memory device of claim 2, wherein: the NAND string includes a channel layer (766); and the control circuitry is configured to bias a portion of the channel layer with the source voltage signal and to bias another portion of the channel layer with the body voltage signal.

5. The memory device of claim 4, wherein: an inversion layer is formed by biasing the portion of the channel layer with the source voltage signal.

6. The memory device of claim 4, wherein: the control circuitry is configured to reduce a resistance of the channel layer with the temporary voltage kick-down of the source voltage signal without the body voltage signal decreasing. ​ ​ 7. The memory device of claim 1, wherein: the NAND string is in a selected sub-block of a block; and the control circuit is configured to adjust a magnitude (Vkick) and / or duration (tkick) of the temporary voltage kick-down based on a location of the selected sub-block in the block.

8. The memory device of claim 1, wherein: the NAND string extends horizontally on a substrate (601); and the control circuit is configured to apply the source voltage signal to an n+ contact (723) in a p-well (792) of the substrate and to apply the body voltage signal to a p+ contact (724) in the p-well of the substrate.

9. The memory device of claim 1, wherein: a peak current in the NAND string during the temporary voltage kick-down is greater than a target current in the NAND string during the sensing of the selected memory cell.

10. The memory device of claim 1, wherein: the body voltage signal remains at its respective first voltage (Vp-well1) during the temporary voltage kick-down.

11. A method of operating a memory device, comprising: increasing a current in a channel layer (766) of a NAND string (700n, 700n1, 700n2; 710n, 710n1, 710n2; 720n, 720n1, 720n2; 730n, 730n1, 730n2) to a peak level, the increasing the current including applying a source voltage signal (Vcelsrc) and a body voltage signal (Vp-well) to the NAND string, the source voltage signal and the body voltage signal increasing to respective first voltages (Vcelsrc1, Vp-well1), after which the source voltage signal has a temporary voltage kick-down (Vcelsrc) and the body voltage signal does not decrease; and after increasing the current to the peak level, decreasing the current to a target level and sensing a selected memory cell in the NAND string; wherein: a bit line clamp transistor (55) is connected to a drain terminal (700d) of the NAND string, the method further comprising: increasing a control gate voltage (Vblc) of the bit line clamp transistor from a first voltage (Vblc1) to a second voltage (Vblc2) during a first portion (t2-t3) of the temporary voltage kick-down; and decreasing the control gate voltage of the bit line clamp transistor from the second voltage to a third voltage (Vblc3) during a second portion (t3-t4) of the temporary voltage kick-down.

12. The method of claim 11, wherein: the NAND string extends vertically on a substrate (601); a source terminal (700s) of the NAND string is in contact with a p-well (792) of the substrate; and the source voltage signal and the body voltage signal are applied to the p-well.

13. The method of claim 11, further comprising: increasing the control gate voltage of the bit line clamp transistor from the third voltage to a fourth voltage (Vblc4) after the temporary voltage kick-down, wherein the sensing of the selected memory cell occurs with the control gate voltage of the bit line clamp transistor at the fourth voltage.

14. A memory device, comprising: control circuitry configured to connect to a substrate and to a NAND string on the substrate, the substrate comprising an n+ contact and a p+ contact, the NAND string comprising a source terminal, a drain terminal, a channel layer, and a plurality of memory cells, and the control circuitry for performing a read operation on a selected memory cell of the plurality of memory cells is configured to: apply a source voltage signal to the n+ contact, the source voltage signal comprising a temporary voltage kick-down; apply a bulk voltage signal to the p+ contact, a voltage of the bulk voltage signal being greater than a voltage of the source voltage signal during the temporary voltage kick-down; and sense a current in the NAND string after the temporary voltage kick-down; wherein: a bit line clamp transistor is connected to the drain terminal of the NAND string; and the control circuitry is configured to temporarily increase a control gate voltage of the bit line clamp transistor during the temporary voltage kick-down.

15. The memory device of claim 14, wherein: the voltage of the bulk voltage signal remains constant throughout the temporary voltage kick-down.

16. The memory device of claim 14, wherein: the voltage of the bulk voltage signal is equal to the voltage of the source voltage signal at a beginning of the temporary voltage kick-down.

17. The memory device of claim 14, wherein: a voltage of the source voltage signal during the sensing is equal to the voltage of the source voltage signal at the beginning of the temporary voltage kick-down.

Images