Semiconductor die including dummy metal pads and methods of forming the same

Abstract

The first semiconductor die includes a first semiconductor device over a first substrate, a first interconnect level dielectric layer embedding first metal interconnect structures and over the first semiconductor device, a first pad level dielectric layer embedding first bonding pads and over the first interconnect level dielectric layer, and first edge seal structures laterally surrounding the first semiconductor device. Each of the first edge seal structures extends vertically from the first substrate to a distal surface of the first pad level dielectric layer and includes a respective first pad level ring structure that extends continuously around the first semiconductor device. At least one row of first dummy metal pads is embedded in the first pad level dielectric layer between a pair of respective first edge seal structures. Second pad level ring structures embedded in a second semiconductor die are bondable to the row of first dummy metal pads.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. non-provisional application No. 16 / 879,146, filed May 20, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates in general to the field of semiconductor devices, and more particularly to a semiconductor die including dummy metal pads for edge sealing enhancement and a method of forming the same. Background Technology

[0004] Semiconductor memory devices may include a memory array and driver circuitry located on the same substrate. However, the driver circuitry occupies valuable space on the substrate, thereby reducing the available space of the memory array. Summary of the Invention

[0005] According to one aspect of this disclosure, a structure is provided including a first semiconductor die. The first semiconductor die includes: a first semiconductor device located above a first substrate; a first interconnect-level dielectric layer embedded in a first metal interconnect structure and located above the first semiconductor device; a first pad-level dielectric layer embedded in a first bonding pad and located above the first interconnect-level dielectric layer; a first edge-sealing structure laterally surrounding the first semiconductor device, wherein each of the first edge-sealing structures extends vertically from the first substrate to a horizontal plane including a bonding surface of the first bonding pad, and includes a corresponding first pad-level ring structure extending continuously around the first semiconductor device; and at least one row of first dummy metal pads embedded in the first pad-level dielectric layer, wherein the first dummy metal pads are not electrically connected to the first edge-sealing structure or the first metal interconnect structure.

[0006] According to another aspect of this disclosure, a method for forming a structure is provided. The method includes forming a first semiconductor die by: forming a first semiconductor device over a first substrate; forming a first interconnect-level dielectric layer over the first semiconductor device into which a first metal interconnect structure is embedded; and forming a first pad-level dielectric layer over the first interconnect-level dielectric layer into which first bonding pads are embedded, a first edge sealing structure including a first pad-level ring structure, and at least one row of first dummy metal pads. The first edge sealing structure laterally surrounds the first semiconductor device; each of the first edge sealing structures extends vertically from the first substrate to a horizontal plane including a bonding surface of the first bonding pads; and a row of first dummy metal pads is formed between a pair of first edge sealing structures. Attached Figure Description

[0007] Figure 1A This is a schematic vertical cross-sectional view of the device region of a first semiconductor die after the formation of the interconnect layer dielectric layer, according to an embodiment of the present disclosure.

[0008] Figure 1B yes Figure 1A A top view of the first semiconductor die. Vertical plane A-A' represents... Figure 1A The device area shown in the figure.

[0009] Figure 1C It is along Figure 1B The vertical plane C-C' Figure 1A and Figure 1B A schematic vertical cross-sectional view of the first semiconductor die region.

[0010] Figure 1D It is along Figure 1C The horizontal plane D-D' Figures 1A to 1C A horizontal cross-sectional view of the first semiconductor die.

[0011] Figure 1E It is along Figure 1C The horizontal plane E-E' Figures 1A to 1C A horizontal cross-sectional view of the first semiconductor die.

[0012] Figure 1F It is along Figure 1C The horizontal plane F-F' Figures 1A to 1C A horizontal cross-sectional view of the first semiconductor die.

[0013] Figure 1G It is along Figure 1C The horizontal plane G-G' Figures 1A to 1C A horizontal cross-sectional view of the first semiconductor die.

[0014] Figure 2AThis is a schematic vertical cross-sectional view of the device region of a first semiconductor die after the formation of the first pad connection level dielectric layer and the first pad connection via structure, according to an embodiment of this disclosure.

[0015] Figure 2B yes Figure 2A A vertical cross-sectional view of the peripheral region of the first semiconductor die.

[0016] Figure 2C yes Figure 2A and Figure 2B Top view of the first semiconductor die.

[0017] Figure 3A This is a schematic vertical cross-sectional view of the device region of a first semiconductor die after the formation of a first bonding pad, a first pad hierarchy ring structure, and at least one row of first dummy metal pads, according to an embodiment of this disclosure.

[0018] Figure 3B yes Figure 3A A vertical cross-sectional view of the peripheral region of the first semiconductor die.

[0019] Figure 3C yes Figure 3A and Figure 3B Top view of the first semiconductor die.

[0020] Figure 4A This is a schematic vertical cross-sectional view of the device region of a second semiconductor die after the formation of a second bonding pad, a second pad hierarchy ring structure, and at least one row of second dummy metal pads, according to an embodiment of this disclosure.

[0021] Figure 4B yes Figure 4A A vertical cross-sectional view of the peripheral region of the second semiconductor die.

[0022] Figure 4C yes Figure 4A and Figure 4B Top view of the second semiconductor die.

[0023] Figure 5 This is a perspective view showing the alignment of a first wafer including multiple instances of a first semiconductor die and a second wafer including multiple instances of a second semiconductor die according to an embodiment of the present disclosure.

[0024] Figure 6A This is a vertical cross-sectional view of the bonding assembly of a first semiconductor die and a second semiconductor die according to an embodiment of the present disclosure.

[0025] Figure 6B yes Figure 6A Vertical cross-sectional view of the peripheral area of ​​the joint component.

[0026] Figure 6C yes Figure 6A and Figure 6B A plan view of the joining components at the joining interface.

[0027] Figure 6D yes Figures 6A to 6C A perspective view of the periphery of the joining components.

[0028] Figure 6E yes Figures 6A to 6D Another vertical cross-sectional view of the peripheral area of ​​the joint component.

[0029] Figure 7 This is a vertical cross-sectional view of the bonding assembly after the back side of the first semiconductor die has been thinned, according to an embodiment of the present disclosure.

[0030] Figure 8 This is a vertical cross-sectional view of the bonding assembly after the formation of the back-side dielectric layer, external bonding pads, and solder balls, according to an embodiment of this disclosure.

[0031] Figures 9A to 9J It is an alternative configuration of the peripheral region of the joining component according to various embodiments of this disclosure. Detailed Implementation

[0032] Driver circuitry can be formed on individual semiconductor dies from a memory device, and the semiconductor dies can be joined to each other via metal-to-metal bonding between two sets of metal bonding pads. The presence of continuously extending metal pads on the bonding surfaces of the semiconductor dies adversely affects the bonding due to the concave deformation of the pads after planarization, resulting in voids and reduced bonding strength. Therefore, prior art bonding pads are not continuous to avoid concave deformation. However, discontinuous bonding pads leave areas between the pads that are susceptible to moisture and contaminants entering from the outside of the bonding assembly of the two dies. Embodiments of this disclosure provide a semiconductor die that includes dummy metal pads in an edge-sealing structure that more effectively blocks the diffusion of moisture and / or contaminants without significantly weakening the bonding strength at the edges of the bonding assembly.

[0033] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0034] The same reference numerals denote the same or similar elements. Unless otherwise stated, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements that provide a shared edge or surface. If two or more elements are not in direct contact with each other, the two elements are “separated” from each other. As used herein, a first element positioned “on” a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the second element, the first element is positioned “directly” on the second element. As used herein, if there is a conductive path made of at least one conductive material between the first element and the second element, the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure in which the shape or composition of at least one of its components is subsequently modified.

[0035] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of uniform or non-uniform continuous structure whose thickness is less than that of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0036] As used herein, the first and second surfaces are “vertically coincident” if the second surface is above or below the first surface and if there is a vertical or substantially vertical plane that includes both the first and second surfaces. A substantially vertical plane is a plane that extends in a straight line along an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0037] As used herein, a “memory level” or “memory array level” refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) that includes the topmost surface of the memory element array and a second horizontal plane that includes the bottommost surface of the memory element array. As used herein, a “through-stack” element refers to an element that extends vertically through the memory level.

[0038] As used in this article, "semiconductor material" refers to a material with a conductivity of 1.0 × 10⁻⁶ m / s. -5S / m to 1.0×10 5 Materials with electrical conductivity in the range of S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the absence of electrical dopants in the presence of S / m. -5 Materials with electrical conductivity ranging from S / m to 1.0 S / m can be produced by appropriate doping with electrodopersive agents, exhibiting conductivity ranging from 1.0 S / m to 1.0 × 10⁻⁶. 5 Doped materials with electrical conductivity in the range of S / m. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band of the band structure, or an n-type dopant that adds electrons to the conduction band of the band structure. As used herein, “conductive material” refers to a material with conductivity greater than 1.0 × 10⁻⁶ S / m. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a material with a conductivity of less than 1.0 × 10⁻⁶ S / m. -5 Materials with an electrical conductivity of S / m.

[0039] As used herein, "heavily doped semiconductor material" refers to a material doped with an electrical dopant at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted into a crystalline material by an annealing process (e.g., from an initial amorphous state). 5 Semiconductor materials with a conductivity of S / m. "Doped semiconductor materials" can be heavily doped semiconductor materials, or can include those exhibiting a conductivity of 1.0 × 10⁻⁶ S / m. -5 S / m to 1.0×10 5 Semiconductor materials with electrical dopant concentrations (i.e., p-type and / or n-type dopant) in the range of S / m. "Intrinsic semiconductor material" refers to a semiconductor material undoped with electrical dopants. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. Doped semiconductor materials can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material comprising at least one metallic element. All conductivity measurements were performed under standard conditions.

[0040] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are joined together, for example, by flip-chip bonding or another chip-to-chip bonding method. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of executing as many external commands simultaneously as the total number of planes therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. When the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each storage block contains multiple pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for read operations.

[0041] refer to Figures 1A to 1G This shows a first semiconductor die 900 in a first configuration. Figure 1B and Figures 1D to 1G This view corresponds to the entire area of ​​the first semiconductor die 900 and the adjacent cut areas subsequently removed during the die dicing process. The first semiconductor die 900 includes a first substrate 908, a first semiconductor device 920 overlying the first substrate 908, a first interconnect-level dielectric material layer (290, 960) overlying the first semiconductor device, and a first metal interconnect structure 980 embedded in the first interconnect-level dielectric material layer (290, 960). In one embodiment, the first substrate 908 may be a first substrate, such as a commercially available silicon wafer having a thickness in the range of 500 micrometers to 2 mm.

[0042] Discrete substrate recesses can be formed in the upper portion of the first substrate 908 by applying a photoresist layer above the top surface of the first substrate 908, photolithographically patterning the photoresist layer to form a discrete aperture array, and transferring the pattern of the discrete aperture array into the upper portion of the first substrate by performing an anisotropic etching process. The photoresist layer can then be removed, for example, by ashing. The depth of each discrete substrate recess can range from 500 nm to 10,000 nm, but smaller and larger depths are also possible. A through-substrate liner 386 and a through-substrate via structure 388 can be formed within each discrete substrate recess.

[0043] Generally, the first semiconductor device 920 may include any semiconductor device known in the art. In one embodiment, the first semiconductor die 900 includes a memory die and may include a memory device such as a three-dimensional NAND memory device. In an exemplary example, the first semiconductor device 920 may include a vertically alternating stack of insulating layer 32 and conductive layer 46, and a two-dimensional array of memory openings extending vertically through the vertically alternating stack (32, 46). The conductive layer 46 may include word lines of the three-dimensional NAND memory device.

[0044] A memory aperture fill structure 58 may be formed within each memory aperture. The memory aperture fill structure 58 may include a memory film and a vertical semiconductor channel contacting the memory film. The memory film may include a barrier dielectric, a tunneling dielectric, and a charge storage material located between the barrier dielectric and the tunneling dielectric. The charge storage material may include a charge trapping layer (such as a silicon nitride layer) or multiple discrete charge trapping regions (such as floating gates or discrete portions of a charge trapping layer). In this case, each memory aperture fill structure 58 and adjacent portions of the conductive layer 46 constitute a vertical NAND string. Alternatively, the memory aperture fill structure 58 may include any type of non-volatile memory element, such as a resistive memory element, a ferroelectric memory element, a phase-change memory element, etc. The memory device may include an optional horizontal semiconductor channel layer 10 connected to the bottom end of each vertical semiconductor channel, and an optional dielectric spacer layer 910 providing electrical isolation between the first substrate 908 and the horizontal semiconductor channel layer 10.

[0045] The conductive layer 46 may be patterned to provide plateau regions, wherein each overlying conductive layer 46 has a smaller lateral extent than any underlying conductive layer 46. Contact via structures (not shown) may be formed in the plateau regions on the conductive layer 46 to provide electrical connections to the conductive layer 46. Dielectric material portions 65 may be formed around each vertically alternating stack (32, 46) to provide electrical isolation between adjacent vertically alternating stacks (32, 46).

[0046] Through the dielectric material portion 65, the optional dielectric spacer layer 910, and the horizontal semiconductor channel layer 10, a through-memory-level via cavity can be formed. Optional through-memory-level dielectric liner 486 and through-memory-level via structure 488 can be formed within each through-memory-level via cavity. Each through-memory-level dielectric liner 486 contains a dielectric material, such as silicon oxide. Each through-memory-level via structure 488 can be formed directly on a corresponding through-substrate via structure within the through-substrate via structure 388.

[0047] The first interconnect layer dielectric material layer (290, 960) may include a first near-side interconnect layer dielectric material layer 290 with embedded contact via structures and bit lines 982, and a first far-side interconnect layer dielectric material layer 960 embedded in a subgroup of a first metal interconnect structure 980 located above the first near-side interconnect layer dielectric material layer 290. The bit lines 982 are a subgroup of the first metal interconnect structure 980 and may electrically contact a drain region above a semiconductor channel located at the top of the memory opening-fill structure 58. The contact via structures contact various nodes of the first semiconductor device. Generally, the first metal interconnect structure 980 may be electrically connected to the first semiconductor device 920. The near-side subgroup of the first metal interconnect structure 980 may be located within the first far-side interconnect layer dielectric material layer 960. Interconnect metal lines and interconnect metal via structures, as subgroups of the first metal interconnect structure 980, may be embedded in the first far-side interconnect layer dielectric material layer 960. In an exemplary example, the first metal interconnect structure 980 may include a first memory-side metal layer M1 and a second memory-side metal layer M2, the first memory-side metal layer including memory-side first-level metal lines and the second memory-side metal layer including memory-side second-level metal lines.

[0048] Each of the first near-side interconnect dielectric layer 290 and the first far-side interconnect dielectric layer 960 may contain a dielectric material such as undoped silicate glass, doped silicate glass, organosilicon glass, silicon nitride, dielectric metal oxide, or combinations thereof. The first far-side interconnect dielectric layer 960 may include one or more dielectric diffusion barrier layers (not explicitly shown). In this case, each dielectric diffusion barrier layer embedded in the first far-side interconnect dielectric layer 960 may contain silicon carbide (i.e., silicon carbonitride "SiCN", also known as silicon carbide nitride), silicon nitride (Si3N4), silicon oxynitride, or any other dielectric material that effectively blocks the diffusion of copper. In one embodiment, each dielectric diffusion barrier layer embedded in the first far-side interconnect dielectric layer 960 may contain a dielectric material with a dielectric constant less than 5, such as SiCN with a dielectric constant of about 3.8, to reduce the RC delay of the first metal interconnect structure 980. Each dielectric diffusion barrier layer may have a thickness ranging from 10 nm to 300 nm.

[0049] At least one first edge sealing structure (688, 984, 986) may be formed around the periphery of the first semiconductor die 900 through the dielectric material portion 65 and the first interconnect level dielectric material layer (290, 960). For example, at least one trench may be formed extending vertically through the dielectric material portion 65 and optionally through a lower level of the first interconnect level dielectric material layer (290, 960), and the at least one trench may subsequently be filled with at least one metallic material to form at least one first metal trench via structure 688. A plurality of nested first metal trench via structures 688 may be formed. Each first metal trench via structure 688 extends continuously along the periphery of the first semiconductor die 900 and completely laterally encapsulates the first semiconductor device 920. The entire bottom surface of each of the first metal trench via structures 688 may contact the top surface of the first substrate 908.

[0050] Each of the at least one first edge sealing structures (688, 984, 986) may include a metal ring structure (984, 986). The metal ring structure (984, 986) may include at least one first through-hole level ring structure 984, which overlays a corresponding first metal trench communication hole structure in the at least one first metal trench communication hole structure 688 and is formed at the corresponding metal through-hole level. Additionally, the metal ring structure (984, 986) in each of the first edge sealing structures (688, 984, 986) may include at least one first line level ring structure 986. Each first line level ring structure 986 overlays a corresponding first metal trench communication hole structure in the at least one first metal trench communication hole structure 688 and is formed at the corresponding metal line level. Generally, each first edge sealing structure (688, 984, 986) includes at least one set of continuous conductive material portions that extend vertically from the first substrate 908 to the top surface of the first interconnect level dielectric material layer (290, 960). Each first edge sealing structure (688, 984, 986) includes a set of continuous conductive material portions that laterally surround the first semiconductor device 920 without any openings passing through it.

[0051] In one embodiment, each of the at least one first edge sealing structures (688, 984, 986) may include a first metal trench via structure 688 and a corresponding subgroup of ring structures (984, 986) that provide a corresponding continuous barrier layer laterally surrounding the first semiconductor device 920 without any lateral openings. Each of the at least one first edge sealing structures (688, 984, 986) extends vertically from the first substrate 908 to the topmost surface of the first distal interconnect level dielectric layer 980. Each subgroup of the first metal interconnect structures 980 within the first edge sealing structures (688, 984, 986) may include at least one first line-level ring structure 986 and at least one first via-level ring structure 984. Each first line-level ring structure 986 may be formed as a single continuous ring structure at the metal line level, which laterally encloses the entire first semiconductor structure 920. Each via-level ring structure 984 can be formed as a single continuous ring structure at the metal via level, which laterally encapsulates the entire first semiconductor structure 920.

[0052] The first metal trench via structure 688 contacts a corresponding annular peripheral portion of the top surface of the first substrate 908 and laterally surrounds the first semiconductor device 920. A vertical stack of metal ring structures (984, 986) extends vertically from the annular top surface of a corresponding first metal trench via structure 688 to the topmost surface of the first interconnect dielectric layer (290, 960). Each first edge sealing structure (688, 984, 986) may include: a corresponding first metal trench via structure 688 that contacts a corresponding annular peripheral portion of the top surface of the first substrate 908; and a corresponding vertical stack of metal ring structures (984, 986) that extends vertically from the annular top surface of the corresponding first metal trench via structure 688 to the topmost surface of the first interconnect dielectric layer (290, 260). Each metal ring structure in the metal ring structures (984, 986) may be formed simultaneously with a corresponding subgroup of the first metal interconnect structure 980 formed at the same level, and may have the same vertical thickness and the same material composition as a corresponding first metal interconnect structure in the first metal interconnect structure 980 having the same vertical separation distance from the first substrate 908 (i.e., located at the same level).

[0053] refer to Figures 2A to 2CA layer stack comprising a first interconnect capping dielectric diffusion barrier layer 962 and a first pad connection level dielectric layer 964 can be formed. The first interconnect capping dielectric diffusion barrier layer 962 may contain a dielectric material that blocks copper diffusion. In one embodiment, the first interconnect capping dielectric diffusion barrier layer 962 may contain silicon nitride, silicon carbide, silicon oxynitride, or a stack thereof. In one embodiment, the first interconnect capping dielectric diffusion barrier layer 962 may contain a dielectric material with a dielectric constant less than 5, such as silicon carbide with a dielectric constant of about 3.8. The thickness of the first interconnect capping dielectric diffusion barrier layer 962 may range from 5 nm to 50 nm, but smaller and larger thicknesses are also possible.

[0054] The first pad connection level dielectric layer 964 may comprise undoped silicate glass (i.e., silicon oxide), doped silicate glass, organosilicon glass, silicon nitride, or dielectric metal oxide, and / or substantially composed of the above. The thickness of the first pad connection level dielectric layer 964 may range from 100 nm to 3,000 nm, but smaller and larger thicknesses are also possible. The first pad connection level dielectric layer 964 may have a flat top surface.

[0055] A photoresist layer (not shown) may be applied over the first pad connection level dielectric layer 964 and may be photolithographically patterned to form discrete openings in the region of the topmost metal interconnect structure overlying the first metal interconnect structure 980. Furthermore, annular openings may be formed in the photoresist layer overlying the first edge sealing structures (688, 984, 986). Each annular opening may be formed over a corresponding vertical stack of the metal ring structures (984, 986).

[0056] An anisotropic etching process can be performed to transfer the pattern of openings in the photoresist layer through the first pad-connect level dielectric layer 964 and the first interconnect capping dielectric diffusion barrier layer 962. First pad-connect via cavities are formed in the region overlying the metal interconnect structure 980 and the first edge sealing structure (688, 984, 986) through the first pad-connect level dielectric layer 964 and the first interconnect capping dielectric diffusion barrier layer 962. The top surface of the topmost metal interconnect structure in the first metal interconnect structure 980 can be physically exposed at the bottom of each first pad-connect via cavity. Trench cavities can be formed through the first pad-connect level dielectric layer 964 and the first interconnect capping dielectric diffusion barrier layer 962 above each vertical stack of metal ring structures (984, 986). The top surface of the metal ring structures (984, 986) can be physically exposed at the bottom of each trench cavity.

[0057] In one embodiment, each bonding pad may have a rectangular or rounded rectangular shape with sides parallel to the first horizontal direction hd1 and the second horizontal direction hd2. The dimensions of each bonding pad along the first horizontal direction hd1 and the dimensions of each bonding pad along the second horizontal direction hd2 are in the range of 2 micrometers to 60 micrometers. Each first pad connects to a via cavity formed within a corresponding region of the topmost metal interconnect structure 980.

[0058] A pad-connect layer metal barrier and a pad-connect layer metal filler can be sequentially deposited in the first pad-connect via cavity. The pad-connect layer metal barrier comprises a conductive metal barrier material, such as TiN, TaN, and / or WN. The conductive metal barrier material blocks copper diffusion. The thickness of the pad-connect layer metal barrier can range from 4 nm to 80 nm, such as 8 nm to 40 nm, but smaller and larger thicknesses are also possible. The pad-connect layer metal filler may include copper, which can be deposited by a combination of a copper seed layer deposition process using physical vapor deposition and a copper plating process to fill the remaining volume of the first pad-connect via cavity.

[0059] Excess portions of the pad-connect layer metal filler and pad-connect layer metal barrier layer covering the horizontal plane of the top surface of the first pad-connect layer dielectric layer 964 can be removed through a planarization process such as chemical mechanical planarization. The remaining portions of the pad-connect layer metal filler and pad-connect layer metal barrier layer filling the first pad-connect via cavity constitute a first pad-connect via structure 968. Each first pad-connect via structure 968 may include a pad-connect layer metal barrier liner 968A and a pad-connect layer metal filler portion 968B. The pad-connect layer metal barrier liner 968A is a patterned remainder of the pad-connect layer metal barrier layer, and the pad-connect layer metal filler portion 968B is a patterned remainder of the pad-connect layer metal filler material. The top surface of the first pad-connect via structure 968 may lie in the same horizontal plane as the top surface of the first pad-connect layer dielectric layer 964.

[0060] The pad-connect layer metal filler material filling the trench cavity and the remaining portion of the pad-connect layer metal barrier layer constitute a first pad-connect layer ring structure 994. Each first pad-connect layer ring structure 994 may include a pad-connect layer ring liner 994A and a pad-connect layer ring filler material portion 994B. The pad-connect layer ring liner 994A is a patterned remaining portion of the pad-connect layer metal barrier layer, and the pad-connect layer ring filler material portion 994B is a patterned remaining portion of the pad-connect layer metal filler material. The top surface of the first pad-connect layer ring structure 994 may lie in the same horizontal plane as the top surface of the first pad-connect layer dielectric layer 964. Each first pad-connect layer ring structure 994 may be incorporated into a lower first edge seal structure in a first edge seal structure (688, 984, 986). Therefore, each first edge sealing structure (688, 984, 986, 994) may include a first metal trench communication hole structure 688, at least one first through hole layer ring structure 984, at least one first line layer ring structure 986, and a first pad connection layer ring structure 994.

[0061] refer to Figures 3A to 3C A first pad-level dielectric layer 974 and an optional first pad-level diffusion barrier layer 976 may be formed over the first pad-connecting dielectric layer 964. The first pad-level dielectric layer 974 may comprise undoped silicate glass, doped silicate glass, organosilicon glass, silicon nitride, or dielectric metal oxide, and / or substantially composed of the above. The thickness of the first pad-level dielectric layer 974 may range from 300 nm to 3,000 nm, but smaller and larger thicknesses are also possible. The first pad-level dielectric layer 974 may have a flat top surface. The first pad-level diffusion barrier layer 976 comprises a dielectric diffusion barrier material, such as silicon nitride or silicon carbide. The thickness of the first pad-level diffusion barrier layer 976 may range from 5 nm to 50 nm, but smaller and larger thicknesses are also possible.

[0062] A photoresist layer (not shown) may be applied over a first pad-level diffusion barrier layer 976 and may be photolithographically patterned to form discrete openings in each region of the first pad-connecting via structure 968. In other words, each discrete opening in the photoresist layer overlays a corresponding first pad-connecting via structure 968. The area of ​​each discrete opening in the photoresist layer may be larger than the area overlaying the first pad-connecting via structure 968. Each discrete opening in the photoresist layer may have the shape of a bonding pad that will subsequently be formed. For example, each discrete opening in the photoresist layer may have a rectangular or rounded rectangular shape with sides parallel to a first horizontal direction hd1 and a second horizontal direction hd2. The dimensions of each opening along the first horizontal direction hd1 and the dimensions of each opening along the second horizontal direction hd2 are in the range of 2 micrometers to 60 micrometers.

[0063] Furthermore, annular openings may be formed in the region of the photoresist layer overlying the first pad connection layer ring structure 994. Optionally, multiple nested annular openings may be formed through the photoresist layer. Additionally, pad-shaped openings may be formed through the photoresist layer between each pair of adjacent annular openings in the photoresist layer, and optionally within the innermost annular opening and optionally outside the outermost annular opening. The pad-shaped openings may have approximately the same dimensions as the discrete openings formed within the first edge seal structures (688, 984, 986, 994) above the first pad connection via structure 968. In one embodiment, a row of pad-shaped openings may be formed between each pair of adjacent nested annular openings. Furthermore, a row of pad-shaped openings may be formed within the innermost first edge seal structure (688, 984, 986, 994), and a row of pad-shaped openings may be formed outside the outermost first edge seal structure (688, 984, 986, 994). Each row of pad-shaped openings can be arranged along the periphery of the semiconductor die, so that the first semiconductor device 920 of the semiconductor die is laterally enclosed by each row of pad-shaped openings.

[0064] An anisotropic etching process can be performed to transfer the pattern of openings in the photoresist layer through the first pad-level diffusion barrier layer 976 and the first pad-level dielectric layer 974. First pad cavities are formed beneath discrete openings in the photoresist layer, passing through the first pad-level diffusion barrier layer 976 and the first pad-level dielectric layer 974, within a region enclosed by the first edge sealing structures (688, 984, 986, 994). The top surface of a single pad-connected via structure 968 can be physically exposed at the bottom of each first pad cavity. Each first pad cavity may have a rectangular or rounded rectangular horizontal cross-sectional shape, such that the dimension of each first pad cavity along the first horizontal direction hd1 is in the range of 2 micrometers to 60 micrometers, and the dimension of each first pad cavity along the second horizontal direction hd2 is in the range of 2 micrometers to 60 micrometers. In one embodiment, each first pad cavity may have a square or rounded square horizontal cross-sectional shape, such that the dimensions of each first pad cavity along the first horizontal direction hd1 and the dimensions of each first pad cavity along the second horizontal direction hd2 are the same. In this case, the dimensions of each first pad cavity along the first horizontal direction hd1 and along the second horizontal direction hd2 may be in the range of 2 micrometers to 60 micrometers, such as 4 micrometers to 30 micrometers. The sidewalls of the first pad cavity may be vertical, or may have a tapered angle (such as a tapered angle in the range of 3 degrees to 10 degrees) relative to the vertical direction that is greater than 0 degrees and less than 30 degrees.

[0065] Annular cavities can be formed through the first pad-level diffusion barrier layer 976 and the first pad-level dielectric layer 974 beneath each annular opening in the photoresist layer. The annular cavities can extend to the top surface of a corresponding first pad-connection layer ring structure in the first pad-connection layer ring structure 994. The annular top surface of the first pad-connection layer ring structure 994 can be physically exposed at the bottom of each annular cavity. Multiple nested annular cavities can be formed through the first pad-level diffusion barrier layer 976 and the first pad-level dielectric layer 974. Additionally, dummy pad-shaped cavities can be formed through the first pad-level diffusion barrier layer 976 and the first pad-level dielectric layer 974 beneath each pad-shaped opening in the photoresist layer. A row of dummy pad-shaped cavities can be formed between each pair of adjacent annular cavities through the first pad-level diffusion barrier layer 976 and the first pad-level dielectric layer 974, and optionally inside the innermost annular cavity and optionally outside the outermost annular cavity. The dummy pad cavities may have approximately the same dimensions as the discrete cavities formed inside the first edge sealing structures (688, 984, 986, 994) above the first pad connection via structure 968. In one embodiment, a row of dummy pad cavities may be formed between each pair of adjacent nested annular cavities. Additionally, a row of dummy pad cavities may be formed inside the innermost first edge sealing structure (688, 984, 986, 994) and outside the outermost first edge sealing structure (688, 984, 986, 994). Each row of dummy pad cavities may be arranged along the periphery of the semiconductor die such that the first semiconductor device 920 of the semiconductor die is laterally encapsulated by each row of dummy pad cavities. The photoresist layer may then be removed, for example, by ashing.

[0066] A first bonding pad liner layer and a first metal pad filler material may be sequentially deposited in the first pad cavity, the annular cavity, and the dummy pad cavity. The first bonding pad liner layer comprises a metal nitride material, such as TiN, TaN, and / or WN. A conductive metal barrier material may be used to block copper diffusion. The first bonding pad liner layer is formed on the top surface of the first pad connection via structure 968, on the top surface of the first pad connection layer annular structure 994, on the sidewalls of the first pad layer diffusion barrier layer 976 and the first pad layer dielectric layer 974, and on a portion of the top surface of the pad connection layer dielectric layer 964 surrounding each dummy pad cavity. The thickness of the first bonding pad liner layer may be in the range of 4 nm to 80 nm, such as 8 nm to 40 nm, but smaller and larger thicknesses are also possible. The first metal pad filler material may include copper, which may be deposited by a combination of a copper seed layer deposition process using physical vapor deposition and a copper plating process to fill the remaining volume of the first pad cavity.

[0067] Excess portions of the first metal pad filler material and the first bonding pad liner layer covering the horizontal plane including the first pad-level diffusion barrier layer 976 can be removed by a planarization process such as chemical mechanical planarization. The remaining portions of the first metal pad filler material and the first bonding pad liner layer filling the first pad cavity constitute the first bonding pad 988. The remaining portions of the first metal pad filler material and the first bonding pad liner layer filling the annular cavity constitute the first pad-level ring structure 989. Each remaining portion of the first metal pad filler material and the first bonding pad liner layer filling the dummy pad cavity constitutes a first dummy metal pad 987. The first dummy metal pad 987 is not connected to any first metal interconnect structure 980 or first edge sealing structure (688, 984, 986, 994) and does not contact any other metal structure. Therefore, the first dummy metal pad 987 is electrically floated at this processing step.

[0068] Each first bonding pad 988 may include a first bonding pad liner 988A and a first metal pad filler portion 988B. The first bonding pad liner 988A is a patterned remainder of the first bonding pad liner layer, and the first metal pad filler portion 988B is a patterned remainder of the first metal pad filler material. The top surface of the first bonding pad 988 may lie in the same horizontal plane as the top surface of the first pad level diffusion barrier layer 976. Each first pad level ring structure 989 may include a pad level ring liner (not explicitly shown) and a pad level ring filler portion (not explicitly shown). Each first dummy metal pad 987 may include a first dummy pad liner (not explicitly shown) and a first dummy pad filler portion (not explicitly shown). The pad level ring liner and the first dummy pad liner may have the same material composition and the same thickness as the first bonding pad liner 988A. The pad layer ring filler portion and the first dummy pad filler portion may have the same material composition and the same thickness as the first metal pad filler portion 988B.

[0069] Generally, the first bonding pad 988 is formed directly on the top surface of the first pad connection via structure 966 within the remaining volume of the first pad cavity. Each first bonding pad 988 includes a first bonding pad liner 988A and a first metal pad filler portion 988B and / or consists of the above, wherein the first bonding pad liner contains a metal nitride material, and the first metal pad filler portion is embedded in the bonding pad liner 988A.

[0070] Each first pad level ring structure 989 is directly formed on and electrically contacts a corresponding first edge sealing structure in the first edge sealing structures (688, 984, 986, 994), and is incorporated into the corresponding first edge sealing structure in the first edge sealing structures (688, 984, 986, 994). At least one first edge sealing structure (688, 984, 986, 994, 989) is formed in the first semiconductor die 900. Each of the at least one first edge sealing structures (688, 984, 986, 994, 989) can extend vertically from the top surface of the first substrate 908 to the topmost surface of the first pad level dielectric layer 974, and can extend to the topmost surface of the first pad level diffusion barrier layer 976. At least one row of first dummy metal pads 987 embedded in the first pad-level diffusion barrier layer 976 and the first pad-level dielectric layer 974 may be located between each pair of adjacent first edge seal structures (688, 984, 986, 994, 989). A row of first dummy metal pads 987 may be formed inside the innermost first edge seal structure among the first edge seal structures (688, 984, 986, 994, 989). Alternatively or additionally, a row of first dummy metal pads 987 may be formed outside the outermost first edge seal structure among the first edge seal structures (688, 984, 986, 994, 989).

[0071] Generally, the first pad-level ring structure 989, the first dummy metal pad 987, and the first bonding pad 988 can be formed by forming cavities in the first pad-level dielectric layer 974, simultaneously depositing at least one metal material in each cavity, and removing excess portions of the at least one material above a horizontal plane including the distal surface of the first pad-level dielectric layer 974. These steps form first edge-sealing structures (688, 984, 986, 994, 989) that laterally surround the first semiconductor device 920 and include the first pad-level ring structure 989. Each of the first edge-sealing structures (688, 984, 986, 994, 989) extends vertically from the first substrate 908 to a horizontal plane including the distal surface of the first pad-level dielectric layer 974 and the bonding surface of the first bonding pad 988. A first dummy metal pad 987 is formed between a pair of corresponding first edge sealing structures (688, 984, 986, 994, 989).

[0072] In one embodiment, each of the first edge sealing structures (688, 984, 986, 994, 989) includes a corresponding metal trench communication structure in the metal trench communication structure 688 and a corresponding vertical stack in the vertical stack of metal ring structures (984, 986, 994, 989). In one embodiment, the first edge sealing structures (688, 984, 986, 994, 989) laterally surround the first semiconductor device 920. Each of the first edge sealing structures (688, 984, 986, 994, 989) extends vertically from the first substrate 908 to at least one horizontal plane including the distal surface of the first pad-level dielectric layer 974 and the bonding surface of the first bonding pad 988. Each of the first edge sealing structures (688, 984, 986, 994, 989) includes a corresponding first pad-level ring structure 989 that extends continuously around the first semiconductor device 920. At least one row of first dummy metal pads 987 is embedded in a first pad-level dielectric layer 974. A row of first dummy metal pads 987 is located between a pair of first edge sealing structures (688, 984, 986, 994, 989).

[0073] In one embodiment, the first pad-level ring structure 989 and the first dummy metal pad 987 have the same vertical thickness and the same material composition. In one embodiment, the first bonding pad 988 may have the same vertical thickness as the first dummy metal pad 987. In one embodiment, all sidewalls of the first dummy metal pad 987 contact the first pad-level dielectric layer 974, and all bottom surfaces of the first dummy metal pad 987 contact a corresponding dielectric surface, which may be the top surface of the first pad-connecting layer dielectric layer 964.

[0074] In one embodiment, each first pad-level ring structure in the first pad-level ring structure 989 includes a plurality of straight, laterally extending segments parallel to a corresponding sidewall in the sidewall of the first semiconductor die 900. For example, the straight, laterally extending segments may be parallel to a first horizontal direction hd1 or a second horizontal direction hd2. In one embodiment, each first bonding pad in the first bonding pad 988 has a corresponding rectangular shape having sidewalls of a corresponding length ranging from 2 micrometers to 60 micrometers, and each first pad-level ring structure in the first pad-level ring structure 989 has a uniform width ranging from 50% to 200% of the average sidewall length of the rectangular shape of the first bonding pad 988. In one embodiment, the first edge sealing structures (688, 984, 986, 994, 989) are electrically grounded to the first substrate 908. In one implementation, the first edge sealing structures (688, 984, 986, 994, 989) are nested within each other without direct contact between them.

[0075] refer to Figures 4A to 4C This illustration shows a second semiconductor die 700 according to an embodiment of the present disclosure. The second semiconductor die 700 includes a second substrate 708, a second semiconductor device 720 overlying the second substrate 708, a second interconnect-level dielectric layer 760 overlying the second semiconductor device 720, and a second metal interconnect structure 780 embedded in the second interconnect-level dielectric layer 760. In one embodiment, the second semiconductor device 720 may include at least one complementary metal-oxide-semiconductor (CMOS) circuit including a field-effect transistor. In one embodiment, the second substrate 708 may be a second substrate, such as a commercially available silicon substrate having a thickness in the range of 500 micrometers to 1 mm.

[0076] Generally, the second semiconductor device may include any semiconductor device that can be operated in conjunction with the first semiconductor device in the first semiconductor die 900 to provide enhanced functionality. In one embodiment, the first semiconductor die 900 includes a memory die, and the second semiconductor die 700 includes a logic die that includes support circuitry (i.e., peripheral circuitry) for operating memory devices (such as a three-dimensional memory element array) within the memory die. In one embodiment, the first semiconductor die 900 may include a three-dimensional memory device that includes a three-dimensional memory element array, word lines (which may include subgroups of conductive layers 46), and bit lines 982, and the second semiconductor device 720 of the second semiconductor die 700 may include peripheral circuitry for operating the three-dimensional memory element array. Peripheral circuitry may include: one or more word line driver circuits that drive word lines of the three-dimensional memory element array of the first semiconductor die 900; one or more bit line driver circuits that drive bit lines 982 of the first semiconductor die 900; one or more word line decoder circuits that decode the addresses of the word lines; one or more bit line decoder circuits that decode the addresses of bit lines 982; one or more sense amplifier circuits that sense the state of the memory elements within the memory opening-filled structure 58 of the first semiconductor die 900; a source power supply circuit that provides power to the horizontal semiconductor channel layer 10 in the first semiconductor die 900; a data buffer and / or latch; and / or any other semiconductor circuitry that may be used to operate the three-dimensional memory device of the first semiconductor die 900.

[0077] The second interconnect layer dielectric material layer 760 may comprise a dielectric material such as undoped silicate glass (e.g., silicon oxide), doped silicate glass, organosilicon glass, silicon nitride, dielectric metal oxide, or combinations thereof. In an exemplary example, the second metal interconnect structure 780 may comprise a first logic-side metal layer D1 and a second logic-side metal layer D2, the first logic-side metal layer comprising logic-side first-level metal lines, and the second logic-side metal layer comprising logic-side second-level metal lines.

[0078] The second interconnect-level dielectric layer 760 may include one or more dielectric diffusion barrier layers (not explicitly shown). In this case, each dielectric diffusion barrier layer embedded in the second interconnect-level dielectric layer 760 may comprise silicon carbide (SiCN), silicon nitride (Si3N4), silicon oxynitride, or any other dielectric material that effectively blocks the diffusion of copper. In one embodiment, each dielectric diffusion barrier layer embedded in the second interconnect-level dielectric layer 760 may comprise a dielectric material with a dielectric constant less than 5 (such as SiCN with a dielectric constant of about 3.8) to reduce the RC delay of the first metal interconnect structure 980. Each dielectric diffusion barrier layer may have a thickness in the range of 10 nm to 300 nm. At least one edge sealing structure (not shown) may be formed around the periphery of the second semiconductor die 700 through the second interconnect-level dielectric layer 760 in the same manner as the first semiconductor die 900. Each edge sealing structure in the at least one edge sealing structure in the second semiconductor die 700 may include a metal trench via structure, at least one via-level ring structure, and at least one line-level ring structure. Each edge-sealing structure in the second semiconductor die 700 includes a set of continuous conductive material portions that laterally surround the second semiconductor device 720 without any openings passing through it. Each edge-sealing structure in at least one of the edge-sealing structures in the second semiconductor die 700 extends vertically from the second substrate 708 to the top surface of the second interconnect level dielectric material layer 780.

[0079] At least one second edge sealing structure (588, 784, 786) may be formed around the periphery of the second semiconductor die 700 through the second interconnect layer dielectric material layer 760. Processing steps for forming the first edge sealing structure (688, 984, 986) may be performed while making any necessary modifications to form the second edge sealing structure (588, 784, 786). Each second edge sealing structure (588, 784, 786) may include a second metal trench via structure 588, at least one second via layer ring structure 784, and at least one second wire layer ring structure 786.

[0080] Can be performed on the second semiconductor die 700 Figures 2A to 2C The processing steps involve modifying the photolithographic pattern to form a pad connection layer structure. Specifically, a layer stack including a second interconnect capping dielectric diffusion barrier layer 762 and a second pad connection layer dielectric layer 764 can be formed over the second interconnect layer dielectric material layer 760.

[0081] Layers that can pass through the second interconnect capping dielectric diffusion barrier layer 762 and the second pad connection level dielectric layer 764 are stacked to form a second pad connection via structure 768 and a second pad connection level ring structure 794. Each second pad connection via structure 768 may include a pad connection level metal barrier liner 768A and a pad connection level metal filler portion 768B. Each second pad connection via structure 768 may be formed on a corresponding topmost metal interconnect structure in the topmost metal interconnect structure of the second metal interconnect structure 780.

[0082] At least one second pad connection layer ring structure 794 may be formed on and incorporated into the respective second edge seal structure (588, 784, 786). Therefore, each second edge seal structure (588, 784, 786, 794) may include a second metal trench through-hole structure 588, at least one second through-hole layer ring structure 784, at least one second line layer ring structure 786, and a second pad connection layer ring structure 794.

[0083] Subsequently, a second pad-level dielectric layer 774 and an optional second pad-level diffusion barrier layer 776 may be formed on the second pad-connection level dielectric layer 764. The second pad-level dielectric layer 774 may comprise undoped silicate glass, doped silicate glass, organosilicon glass, silicon nitride, or dielectric metal oxide, and / or substantially composed of the above. The thickness of the second pad-level dielectric layer 774 may range from 300 nm to 3,000 nm, but smaller and larger thicknesses are also possible. The second pad-level dielectric layer 774 may have a flat top surface. The second pad-level diffusion barrier layer 776 comprises a dielectric diffusion barrier material, such as silicon nitride or silicon carbide. The thickness of the second pad-level diffusion barrier layer 776 may range from 5 nm to 50 nm, but smaller and larger thicknesses are also possible.

[0084] A photoresist layer (not shown) may be applied over the second pad-level diffusion barrier layer 776 and may be photolithographically patterned to form discrete openings in each region of the second pad-connecting via structure 768. In other words, each discrete opening in the photoresist layer overlays a corresponding second pad-connecting via structure 768. The area of ​​each discrete opening in the photoresist layer may be larger than the area overlaying the second pad-connecting via structure 768. Each discrete opening in the photoresist layer may have the shape of a bonding pad that will subsequently be formed. For example, each discrete opening in the photoresist layer may have a rectangular or rounded rectangular shape with sides parallel to the second horizontal direction hd1 and the second horizontal direction hd2. The dimensions of each opening along the second horizontal direction hd1 and the dimensions of each opening along the second horizontal direction hd2 are in the range of 2 micrometers to 50 micrometers.

[0085] Furthermore, annular openings may be formed in the region of the photoresist layer overlying the second pad connection layer ring structure 794. Multiple nested annular openings may be formed through the photoresist layer. Additionally, pad-shaped openings may be formed through the photoresist layer between each pair of adjacent annular openings in the photoresist layer, and optionally within the innermost annular opening and optionally outside the outermost annular opening. The pad-shaped openings may have approximately the same dimensions as the discrete openings formed within the second edge seal structures (588, 784, 786, 794) above the second pad connection via structure 768. In one embodiment, a row of pad-shaped openings may be formed between each pair of adjacent nested annular openings. Furthermore, a row of pad-shaped openings may be formed within the innermost second edge seal structure (588, 784, 786, 794), and a row of pad-shaped openings may be formed outside the outermost second edge seal structure (588, 784, 786, 794). Each row of pad-shaped openings can be arranged along the periphery of the semiconductor die, so that the second semiconductor device 720 of the semiconductor die is laterally enclosed by each row of pad-shaped openings.

[0086] An anisotropic etching process can be performed to transfer the pattern of openings in the photoresist layer through the second pad-level diffusion barrier layer 776 and the second pad-level dielectric layer 774. Second pad cavities are formed beneath discrete openings in the photoresist layer, passing through the second pad-level diffusion barrier layer 776 and the second pad-level dielectric layer 774, within the region enclosed by the second edge sealing structures (588, 784, 786, 794). The top surface of the individual pad-connected via structure 768 can be physically exposed at the bottom of each second pad cavity. Each second pad cavity may have a rectangular or rounded rectangular horizontal cross-sectional shape, such that the dimension of each second pad cavity along the second horizontal direction hd1 is in the range of 2 micrometers to 50 micrometers, and the dimension of each second pad cavity along the second horizontal direction hd2 is in the range of 2 micrometers to 50 micrometers. In one embodiment, each second pad cavity may have a square or rounded square horizontal cross-sectional shape, such that the dimensions of each second pad cavity along the second horizontal direction hd1 and hd2 are the same. In this case, the dimensions of each second pad cavity along the second horizontal direction hd1 and hd2 may be in the range of 2 micrometers to 50 micrometers, such as 4 micrometers to 30 micrometers. The sidewalls of the second pad cavities may be vertical, or may have a taper angle greater than 0 degrees and less than 30 degrees relative to the vertical direction (such as a taper angle in the range of 3 degrees to 10 degrees).

[0087] Annular cavities can be formed through the second pad-level diffusion barrier layer 776 and the second pad-level dielectric layer 774 beneath each annular opening in the photoresist layer. The annular cavities can extend to the top surface of a corresponding second pad-connection layer ring structure in the second pad-connection layer ring structure 794. The annular top surface of the second pad-connection layer ring structure 794 can be physically exposed at the bottom of each annular cavity. Multiple nested annular cavities can be formed through the second pad-level diffusion barrier layer 776 and the second pad-level dielectric layer 774. Additionally, dummy pad-shaped cavities can be formed through the second pad-level diffusion barrier layer 776 and the second pad-level dielectric layer 774 beneath each pad-shaped opening in the photoresist layer. A row of dummy pad-shaped cavities can be formed between each pair of adjacent annular cavities through the second pad-level diffusion barrier layer 776 and the second pad-level dielectric layer 774, and optionally inside the innermost annular cavity and optionally outside the outermost annular cavity. The dummy pad cavities may have approximately the same dimensions as the discrete cavities formed inside the second edge sealing structures (588, 784, 786, 794) above the second pad connection via structure 768. In one embodiment, a row of dummy pad cavities may be formed between each pair of adjacent nested annular cavities. Additionally, a row of dummy pad cavities may be formed inside the innermost second edge sealing structure (588, 784, 786, 794), and a row of dummy pad cavities may be formed outside the outermost second edge sealing structure (588, 784, 786, 794). Each row of dummy pad cavities may be arranged along the periphery of the semiconductor die such that the second semiconductor device 720 of the semiconductor die is laterally encapsulated by each row of dummy pad cavities. The photoresist layer may then be removed, for example, by ashing.

[0088] The second bonding pad liner layer and the second metal pad filler material can be sequentially deposited in the second pad cavity, the annular cavity, and the dummy pad cavity. The second bonding pad liner layer comprises a metal nitride material, such as TiN, TaN, and / or WN. A conductive metal barrier material can block copper diffusion. The second bonding pad liner layer is formed on the top surface of the second pad connection via structure 768, on the top surface of the second pad connection layer annular structure 794, on the sidewalls of the second pad layer diffusion barrier layer 776 and the second pad layer dielectric layer 774, and on a portion of the top surface of the second pad connection layer dielectric layer 764 surrounding each dummy pad cavity. The thickness of the second bonding pad liner layer can be in the range of 4 nm to 80 nm, such as 8 nm to 40 nm, but smaller and larger thicknesses are also possible. The second metal pad filler material may include copper, which can be deposited by a combination of a copper seed layer deposition process using physical vapor deposition and a copper plating process to fill the remaining volume of the second pad cavity.

[0089] Excess portions of the second metal pad filler material and the second bonding pad liner layer covering the horizontal plane of the top surface, including the second pad-level diffusion barrier layer 776, can be removed by a planarization process such as chemical mechanical planarization. The remaining portions of the second metal pad filler material and the second bonding pad liner layer filling the second pad cavity constitute the second bonding pad 788. The remaining portions of the second metal pad filler material and the second bonding pad liner layer filling the annular cavity constitute the second pad-level ring structure 789. Each remaining portion of the second metal pad filler material and the second bonding pad liner layer filling the pad cavity constitutes a second dummy metal pad 787. The second dummy metal pad 787 is not connected to any second metal interconnect structure 780 or second edge sealing structure (588, 784, 786, 794) and does not contact any other metal structure. Therefore, the second dummy metal pad 787 is electrically floated at this processing step.

[0090] Each second bonding pad 788 may include a second bonding pad liner 788A and a second metal pad filler portion 788B. The second bonding pad liner 788A is a patterned remainder of the second bonding pad liner layer, and the second metal pad filler portion 788B is a patterned remainder of the second metal pad filler material. The top surface of the second bonding pad 788 may lie in the same horizontal plane as the top surface of the second pad level diffusion barrier layer 776. Each second pad level ring structure 789 may include a pad level ring liner (not explicitly shown) and a pad level ring filler portion (not explicitly shown). Each second dummy metal pad 787 may include a second dummy pad liner (not explicitly shown) and a second dummy pad filler portion (not explicitly shown). The pad level ring liner and the second dummy pad liner may have the same material composition and the same thickness as the second bonding pad liner 788A. The pad layer ring filler portion and the second dummy pad filler portion may have the same material composition and the same thickness as the second metal pad filler portion 788B.

[0091] Generally, the second bonding pad 788 is formed directly on the top surface of the second pad connection via structure 766 within the remaining volume of the second pad cavity. Each of the second bonding pads 788 includes a second bonding pad liner 788A and a second metal pad filler portion 788B and / or consists of the above, wherein the second bonding pad liner contains a metal nitride material, and the second metal pad filler portion is embedded in the second bonding pad liner 788A.

[0092] Each second pad-level ring structure 789 is directly formed on and electrically contacts a corresponding second edge sealing structure in the second edge sealing structures (588, 784, 786, 794), and is incorporated into the corresponding second edge sealing structure in the second edge sealing structures (588, 784, 786, 794). At least one second edge sealing structure (588, 784, 786, 794, 789) is formed in the second semiconductor die 700. Each of the at least one second edge sealing structures (588, 784, 786, 794, 789) may extend at least vertically from the top surface of the second substrate 708 to the topmost surface of the second pad-level dielectric layer 774, and may extend to the topmost surface of the second pad-level diffusion barrier layer 776. At least one row of second dummy metal pads 787 embedded in the second pad-level diffusion barrier layer 776 and the second pad-level dielectric layer 774 may be located between each pair of adjacent second edge seal structures (588, 784, 786, 794, 789). A row of second dummy metal pads 787 may be formed inside the innermost second edge seal structure among the second edge seal structures (588, 784, 786, 794, 789). Additionally or alternatively, a row of second dummy metal pads 787 may be formed outside the outermost second edge seal structure among the second edge seal structures (588, 784, 786, 794, 789).

[0093] Generally, the second pad-level ring structure 789, the second dummy metal pad 787, and the second bonding pad 788 can be formed by forming cavities in the second pad-level dielectric layer 774, simultaneously depositing at least one metal material in each cavity, and removing excess portions of the at least one material above a horizontal plane including the distal surface of the second pad-level dielectric layer 774. These steps form second edge-sealing structures (588, 784, 786, 794, 789) that laterally surround the second semiconductor device 720 and include the second pad-level ring structure 789. Each of the second edge-sealing structures (588, 784, 786, 794, 789) extends vertically from the second substrate 708 to a horizontal plane including the distal surface of the second pad-level dielectric layer 774 and the bonding surface of the second bonding pad 788. A second dummy metal pad 787 is formed between a pair of corresponding second edge sealing structures (588, 784, 786, 794, 789).

[0094] In one embodiment, each of the second edge sealing structures (588, 784, 786, 794, 789) includes a corresponding metal trench communication structure in the metal trench communication structure 588 and a corresponding vertical stack in the vertical stack of metal ring structures (784, 786, 794, 789). In one embodiment, the second edge sealing structures (588, 784, 786, 794, 789) laterally surround the second semiconductor device 720. Each of the second edge sealing structures (588, 784, 786, 794, 789) extends at least vertically from the second substrate 708 to a horizontal plane including the distal surface of the second pad-level dielectric layer 774 and the bonding surface of the second bonding pad 788. Each of the second edge sealing structures (588, 784, 786, 794, 789) includes a corresponding second pad-level ring structure 789 that extends continuously around the second semiconductor device 720. At least one row of second dummy metal pads 787 is embedded in a second pad-level dielectric layer 774. A row of second dummy metal pads 787 is located between a pair of second edge sealing structures (588, 784, 786, 794, 789).

[0095] In one embodiment, the second pad layer ring structure 789 and the second dummy metal pad 787 have the same vertical thickness and the same material composition. In one embodiment, the second bonding pad 788 may have the same vertical thickness as the second dummy metal pad 787. In one embodiment, all sidewalls of the second dummy metal pad 787 contact the second pad layer dielectric layer 774, and all bottom surfaces of the second dummy metal pad 787 contact a corresponding dielectric surface, which may be the top surface of the second pad connection layer dielectric layer 764.

[0096] In one embodiment, each second pad-level ring structure in the second pad-level ring structure 789 includes a plurality of straight, laterally extending segments parallel to a corresponding sidewall in the sidewall of the second semiconductor die 700. For example, the straight, laterally extending segments may be parallel to a second horizontal direction hd1 or a second horizontal direction hd2. In one embodiment, each second bonding pad in the second bonding pad 788 has a corresponding rectangular shape having sidewalls of a corresponding length ranging from 2 micrometers to 50 micrometers, and each second pad-level ring structure in the second pad-level ring structure 789 has a uniform width ranging from 50% to 200% of the average sidewall length of the rectangular shape of the second bonding pad 788. In one embodiment, the second edge sealing structures (588, 784, 786, 794, 789) are electrically grounded to the second substrate 708. In one embodiment, the second edge sealing structures (588, 784, 786, 794, 789) are nested within each other without direct contact.

[0097] The second bonding pad 788 can be arranged in a mirror pattern of the first bonding pad 988. Each second pad level ring structure 789 can be formed in a corresponding area corresponding to the mirror area of ​​a corresponding row of first dummy metal pads 987. Each row of second dummy metal pads 787 can be formed in a corresponding area corresponding to the mirror area of ​​a corresponding first pad level ring structure 989.

[0098] refer to Figure 5 A first wafer 1900, comprising a plurality of first semiconductor dies 900, and a second wafer 1700, comprising a plurality of second semiconductor dies 700, can be aligned with each other for bonding. Each second bonding pad 788 faces a corresponding first bonding pad among the first bonding pads 988. Each pair of facing first bonding pads 988 and second bonding pads 788 can be aligned to maximize the area overlap between the first bonding pads 988 and the second bonding pads 788. If the first bonding pads 988 and the second bonding pads 788 have different areas, each overlap area between a pair of facing first bonding pads 988 and second bonding pads 788 can be the same as the area of ​​the smaller bonding pad between a pair of facing first bonding pads 988 and second bonding pads 788. If the first bonding pad 988 and the second bonding pad 788 have the same area, then the overlap area between a pair of facing first bonding pads 988 and second bonding pads 788 can be in the range of 90% to 100% of the area of ​​the first bonding pad 988 (which is the same as the area of ​​the second bonding pad 788), such as 95% to 100%.

[0099] In addition, each pair of facing first semiconductor dies 900 and second semiconductor dies 700 can be aligned such that each second pad level ring structure 789 faces a corresponding row of first dummy metal pads 987, and each row of second dummy metal pads 787 faces a corresponding first pad level ring structure 989.

[0100] refer to Figures 6A to 6E Each pair of facing first semiconductor dies 900 and second semiconductor dies 700 can contact each other such that each first bonding pad 988 contacts a corresponding second bonding pad 788, with corresponding area overlap between them. The components of the first semiconductor dies 900 and second semiconductor dies 700 are annealed at a high temperature ranging from 250 degrees Celsius to 400 degrees Celsius to induce copper diffusion at each interface between the respective facing first bonding pads 988 and the respective facing second bonding pads 788. The duration of the annealing process at high temperature can range from 5 minutes to 2 hours, but shorter or longer annealing durations are also possible. Each pair of facing first bonding pads 988 and second bonding pads 788 are bonded to each other during the high-temperature annealing process. A first exemplary bonding structure including the first semiconductor die 900 and the second semiconductor die 700 can be formed.

[0101] According to aspects of this disclosure, each row of first dummy metal pads 987 is bonded to a corresponding second edge sealing structure in the second edge sealing structures (588, 784, 786, 794, 789). For example, each row of first dummy metal pads 987 may be bonded to a second pad-level ring structure 789. Each first edge sealing structure (688, 984, 986, 994, 989) may be bonded to a corresponding row of second dummy metal pads 787. For example, each first pad-level ring structure 989 may be bonded to a corresponding second dummy metal pad 787. Each first pad-level ring structure 989 may contact the horizontal surface of the second pad-level dielectric layer 974. Each second pad-level ring structure 789 may contact the horizontal surface of the first pad-level dielectric layer 974.

[0102] A first edge sealing structure (688, 984, 986, 994, 989) is electrically connected to (i.e., electrically shorted to) a first substrate 908. A second edge sealing structure (588, 784, 786, 794, 789) is electrically connected to a second substrate 708. Figure 6EIn an alternative embodiment shown, the first substrate 908 may be replaced by a combination of a first back-side dielectric layer 930, a conductive material layer 932, a second back-side dielectric layer 940, and a third back-side dielectric layer 950. In this case, a first edge sealing structure (688, 984, 986, 994, 989) may be electrically connected to the conductive material layer 932. In an exemplary example, the first back-side dielectric layer 930 may comprise silicon oxide, the conductive material layer 932 may comprise a heavily doped semiconductor or metallic material (such as TiN, TaN, WN, W, Mo, Ru, Co, and / or combinations thereof), the second back-side dielectric layer 940 may comprise a combination of silicon oxide and silicon nitride, and the third back-side dielectric layer 950 may comprise polyimide (PI).

[0103] refer to Figure 7 The first substrate 908 can be thinned from the back side by grinding, polishing, anisotropic etching, or isotropic etching. The thinning process can continue until the horizontal portion through the substrate liner 386 is removed, and the horizontal surface of the through-substrate via structure 388 is physically exposed. Generally, thinning the back side of the first substrate 908, which can be the substrate of a memory die, physically exposes the end surface of the through-substrate via structure 388. The thickness of the first substrate 908 after thinning can range from 1 micrometer to 30 micrometers, such as 2 micrometers to 15 micrometers, but smaller and larger thicknesses are also possible.

[0104] refer to Figure 8 A back-side insulating layer 934 may be formed on the back side of the first substrate 908. The back-side insulating layer 934 comprises an insulating material, such as silicon oxide. The thickness of the back-side insulating layer 934 may range from 50 nm to 500 nm, but smaller and larger thicknesses are also possible. A photoresist layer (not shown) may be applied over the back-side insulating layer 934 and may be photolithographically patterned to form openings over regions of the through-substrate via structure 388. An etching process may be performed to form via cavities through the back-side insulating layer 934 beneath each opening in the photoresist layer. The top surface of the through-substrate via structure 388 may be physically exposed through the back-side insulating layer 934 at the bottom of each via cavity.

[0105] At least one metallic material may be deposited into the opening through the back-side insulating layer 934 and deposited on the flat surface of the back-side insulating layer 934 to form a metallic material layer. The at least one metallic material may include copper, aluminum, ruthenium, cobalt, molybdenum, and / or any other metallic material that may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, vacuum evaporation, or other deposition methods. For example, a metal nitride liner material (such as TiN, TaN, or WN) may be deposited directly on the physically exposed surface of the through-hole structure 388, deposited on the sidewalls of the opening through the back-side insulating layer 934, and deposited on the physically exposed flat surface of the back-side insulating layer 934. The thickness of the metal nitride liner material may range from 10 nm to 100 nm, but smaller and larger thicknesses are also possible. At least one metallic filler material, such as copper or aluminum, may be deposited on top of the metal nitride liner material. In one embodiment, the at least one metallic filler material may comprise a stack of highly conductive metal layers (such as copper or aluminum layers) and a stack of under-bump metallurgy (UBM) layers for bonding solder balls thereon. Exemplary UBM layer stacks include, but are not limited to, Al / Ni / Au stacks, Al / Ni / Cu stacks, Cu / Ni / Au stacks, Cu / Ni / Pd stacks, Ti / Ni / Au stacks, Ti / Cu / Ni / Au stacks, Ti-W / Cu stacks, Cr / Cu stacks, and Cr / Cu / Ni stacks. The thickness of the metal material layer above the flat horizontal surface of the back-side insulating layer 934 can range from 0.5 micrometers to 10 micrometers, such as 1 micrometer to 5 micrometers, but smaller and larger thicknesses are also possible.

[0106] At least one metal filler material and a metal material layer may then be patterned to form discrete back-side bonding pads 936, thereby contacting a corresponding through-substrate via structure 388. The back-side bonding pads 936 may serve as external bonding pads, which can be used to electrically connect various nodes within the first semiconductor die 900 and the second semiconductor die 700 to external nodes, such as bonding pads on a package substrate or C4 bonding pads of another semiconductor die. For example, solder material portions 938 may be formed on the back-side bonding pads 936, and a C4 bonding process or a wire bonding process may be performed to electrically connect the back-side bonding pads 936 to external active nodes.

[0107] Generally, a back-side bonding pad 936 may be formed on the back surface of a first semiconductor die 900 (which may be a memory die), the back surface being located on the opposite side of the bonding interface between the first bonding pad 988 and the second bonding pad 788. A through-substrate via structure 388 may extend vertically through the first semiconductor die 900 and may provide electrical connection between the back-side bonding pad 936 and the subgroup of bonding pads (988, 788).

[0108] Figures 9A to 9J Alternative configurations of the peripheral region of the joining component according to various embodiments of the present disclosure are shown. Figures 9A to 9J The arrows indicate portions of the first pad-level diffusion barrier layer 976 and the second pad-level diffusion barrier layer 776 that prevent moisture or contaminants from entering the region containing the first semiconductor device 920 or the second semiconductor device 720 from outside the bonding assembly of the first semiconductor die 900 and the second semiconductor die 700. Various configurations of the bonding assembly reduce the intrusion of moisture and contaminants by employing dummy metal pads (987, 787), which increase the diffusion path for moisture and contaminants. These configurations also reduce noise effects during high-frequency operation.

[0109] refer to Figure 9A This can be achieved by employing two first edge sealing structures in a first edge sealing structure including a corresponding first pad layer ring structure 989 and three second edge sealing structures in a second edge sealing structure including a corresponding second pad layer ring structure 789, and by omitting the first dummy metal pad 987. Figure 8 The exemplary structure yields a first alternative configuration of the exemplary structure. In this case, the horizontal surface of the second pad-level ring structure 789 is accessible to the first pad-level diffusion barrier layer 976.

[0110] refer to Figure 9B This can be achieved by employing three first edge sealing structures in a first edge sealing structure including a corresponding first pad layer ring structure 989 and two second edge sealing structures in a second edge sealing structure including a corresponding second pad layer ring structure 789, and by omitting the first dummy metal pad 987. Figure 8 The exemplary structure yields a second alternative configuration of the exemplary structure. In this configuration, the horizontal surface of the second pad-level ring structure 789 is accessible to the first pad-level diffusion barrier layer 976.

[0111] refer to Figure 9C This can be achieved by employing two first edge sealing structures from a first edge sealing structure including a corresponding first pad layer ring structure 989, one first edge sealing structure excluding the first pad layer ring structure, and three second edge sealing structures from a second edge sealing structure including a corresponding second pad layer ring structure 789, and by omitting the first dummy metal pad 987. Figure 8 The exemplary structure yields a third alternative configuration of the exemplary structure.

[0112] refer to Figure 9DThis can be achieved by employing three first edge sealing structures in a first edge sealing structure including a corresponding first pad level ring structure 989, two second edge sealing structures in a second edge sealing structure including a corresponding second pad level ring structure 789, and a second edge sealing structure excluding the second pad level ring structure and contacting a row of second dummy metal pads 787, and by omitting the first dummy metal pads 987. Figure 8 The exemplary structure yields a fourth alternative configuration of the exemplary structure.

[0113] refer to Figure 9E This can be achieved by employing two first edge sealing structures from a first edge sealing structure including a corresponding first pad level ring structure 989, two first edge sealing structures from a first edge sealing structure excluding the first pad level ring structure and contacting a corresponding first dummy metal pad 987, two second edge sealing structures from a second edge sealing structure including a corresponding second pad level ring structure 789, and two second edge sealing structures from a second edge sealing structure excluding the second pad level ring structure, and by omitting the second dummy metal pad 787. Figure 8 The exemplary structure yields a fifth alternative configuration of the exemplary structure.

[0114] refer to Figure 9F This can be achieved by employing two first edge sealing structures in a first edge sealing structure including a corresponding first pad layer ring structure 989 and three second edge sealing structures in a second edge sealing structure including a corresponding second pad layer ring structure 789, and by omitting the second dummy metal pad 787. Figure 8 The exemplary structure yields a sixth alternative configuration of the exemplary structure. In this configuration, the horizontal surface of the first pad-level ring structure 989 is accessible to the second pad-level diffusion barrier layer 776.

[0115] refer to Figure 9G This can be achieved by employing three first edge sealing structures in a first edge sealing structure including a corresponding first pad layer ring structure 989 and two second edge sealing structures in a second edge sealing structure including a corresponding second pad layer ring structure 789, and by omitting the second dummy metal pad 787. Figure 8 The exemplary structure yields a seventh alternative configuration of the exemplary structure. In this configuration, the horizontal surface of the first pad-level ring structure 989 is accessible to the second pad-level diffusion barrier layer 776.

[0116] refer to Figure 9HThis can be achieved by employing two first edge sealing structures from a first edge sealing structure including a corresponding first pad level ring structure 989, one first edge sealing structure excluding the first pad level ring structure and contacting a row of first dummy metal pads 987, and three second edge sealing structures from a second edge sealing structure including a corresponding second pad level ring structure 789, and by omitting the second dummy metal pad 787. Figure 8 The exemplary structure yields an eighth alternative configuration of the exemplary structure.

[0117] refer to Figure 9I This can be achieved by employing three first edge sealing structures in a first edge sealing structure including a corresponding first pad level ring structure 989, two second edge sealing structures in a second edge sealing structure including a corresponding second pad level ring structure 789, and a second edge sealing structure excluding the second pad level ring structure, and by omitting the second dummy metal pad 787. Figure 8 The exemplary structure yields a ninth alternative configuration of the exemplary structure.

[0118] refer to Figure 9J This can be achieved by employing two first edge sealing structures from a first edge sealing structure including a corresponding first pad level ring structure 989, two first edge sealing structures from a first edge sealing structure excluding the first pad level ring structure, two second edge sealing structures from a second edge sealing structure including a corresponding second pad level ring structure 789, and two second edge sealing structures from a second edge sealing structure excluding the second pad level ring structure and contacting a corresponding second dummy metal pad 787, and by omitting the first dummy metal pad 987. Figure 8 The exemplary structure yields a tenth alternative configuration of the exemplary structure.

[0119] Referring to all the accompanying drawings and various embodiments of this disclosure, a structure including a first semiconductor die (which may be the first semiconductor die 900 or the second semiconductor die 700 as described above) is provided. Ordinal numbers refer only to the order of similar elements and are not part of the proper nouns for any element. The first semiconductor die (900 or 700) includes: a first semiconductor device (920 or 720) located above a first substrate (908 or 708); a first interconnect-level dielectric layer {(290, 960) or 760} embedded in a first metal interconnect structure (980 or 780) and located above the first semiconductor device (920 or 720); a first pad-level dielectric layer (974 or 774) embedded in a first bonding pad (988 or 788) and located above the first interconnect-level dielectric layer {(290, 960) or 760}; and a first edge sealing structure {(688, 984, 986, 994, 989) or (588, 784, 786, 794)}. The first edge sealing structure laterally surrounds the first semiconductor device (920 or 720), wherein each of the first edge sealing structures {(688, 984, 986, 994, 989) or (588, 784, 786, 794, 789)} extends vertically from the first substrate (908 or 708) to a horizontal plane including a bonding surface of a first bonding pad (988 or 788), and includes a corresponding first pad level ring structure (989 or 789) extending continuously around the first semiconductor device (920 or 720); and at least one row of first dummy metal pads (987 or 787) embedded in a first pad level dielectric layer (974 or 774). The first dummy metal pads are not electrically connected to the first edge sealing structure or the first metal interconnect structure.

[0120] In one implementation, each row of first dummy metal pads (987 or 787) is located between a pair of corresponding first edge sealing structures {(688,984,986,994,989) or (588,784,786,794,789)}.

[0121] In the bonding assembly of the first semiconductor die 900 and the second semiconductor die 700, each of the first edge sealing structures (688, 984, 986, 994, 989) within the first semiconductor die 900 extends vertically from the first substrate 908 to a horizontal plane including the bonding interface between the first bonding pad 988 and the second bonding pad 788. Similarly, in the bonding assembly of the first semiconductor die 900 and the second semiconductor die 700, each of the second edge sealing structures (588, 784, 786, 794, 789) within the second semiconductor die 700 extends vertically from the second substrate {708 or (730, 732, 740, 750)} to a horizontal plane including the bonding interface between the first bonding pad 988 and the second bonding pad 788.

[0122] Although specific embodiments have been mentioned for the foregoing, it should be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments in which the words “comprising” or “including” are used. While embodiments using specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A structure comprising a first semiconductor die, wherein the first semiconductor die comprises: a first semiconductor device on a first substrate; a first interconnect-level dielectric layer embedding first metal interconnect structures and over the first semiconductor device; a first pad-level dielectric layer embedding first bonding pads and over the first interconnect-level dielectric layer; first edge seal structures laterally surrounding the first semiconductor device, wherein each of the first edge seal structures extends vertically from the first substrate to a horizontal plane comprising a bonding surface of the first bonding pads, and comprises a respective first pad-level ring structure that extends continuously around the first semiconductor device; and at least one row of first dummy metal pads embedded in the first pad-level dielectric layer, wherein the first dummy metal pads are not electrically connected to the first edge seal structures or the first metal interconnect structures.

2. The structure of claim 1, wherein each row of first dummy metal pads is between a pair of respective first edge seal structures.

3. The structure of claim 1, wherein: the first pad-level ring structures and the first dummy metal pads have a same vertical thickness and have a same material composition; and the first bonding pads have a same vertical thickness as the first dummy metal pads.

4. The structure of claim 1, wherein each of the first edge seal structures comprises: a respective metal moat via structure contacting a respective annular perimeter portion of a top surface of the first substrate; and a respective vertical stack of metal ring structures extending vertically from an annular top surface of the respective metal moat via structure to a bottom surface of the respective first pad-level ring structure.

5. The structure of claim 4, wherein each of the metal ring structures has a same vertical thickness and a same material composition as a respective one of the first metal interconnect structures having a same vertical separation distance from the first substrate.

6. The structure of claim 1, wherein the first edge seal structures are nested with one another without direct contact therebetween.

7. The structure of claim 1, wherein: all sidewalls of the first dummy metal pads contact the first pad-level dielectric layer; and all bottom surfaces of the first dummy metal pads contact respective dielectric surfaces.

8. The structure of claim 1, wherein each of the first pad-level ring structures comprises a plurality of straight laterally-extending segments parallel to a respective one of sidewalls of the first semiconductor die.

9. The structure of claim 1, wherein: ​ ​ each of the first bond pads has a respective rectangular shape having side lengths in a range of 2 microns to 60 microns; and each of the first pad-level ring structures has a uniform width in a range of 50% of an average of the side lengths of the rectangular shapes of the first bond pads to 200% of the average of the side lengths of the rectangular shapes of the first bond pads.

10. The structure of claim 1, wherein the first edge seal structure is electrically grounded to the first substrate.

11. The structure of claim 1, further comprising a second semiconductor die, the second semiconductor die comprising: a second semiconductor device over a second substrate; a second pad-level dielectric layer embedding second bond pads and over the second substrate; at least one row of second dummy metal pads embedded in the second pad-level dielectric layer, wherein each row of second dummy metal pads is bonded to a respective one of the first edge seal structures by a metal-to-metal bond.

12. The structure of claim 11, wherein the second semiconductor die comprises a second edge seal structure laterally surrounding the second semiconductor device and comprising respective second pad-level ring structures continuously extending around the second semiconductor device, wherein each of the second edge seal structures extends vertically from the second substrate to a horizontal plane comprising a bonding interface between the first bond pads and the second bond pads.

13. The structure of claim 12, wherein each row of first dummy metal pads is bonded to a respective one of the second edge seal structures.

14. The structure of claim 12, wherein each of the second edge seal structures comprises: a respective metal moat via structure contacting a respective annular peripheral portion of a horizontal surface of the second substrate; and a respective vertical stack of metal ring structures vertically extending from an annular top surface of the respective metal moat via structure to a horizontal surface of the respective second pad-level ring structure.

15. A method of forming a structure, the method comprising forming a first semiconductor die by: forming a first semiconductor device over a first substrate; forming a first interconnect-level dielectric layer embedding first metal interconnect structures over the first semiconductor device; and forming a first pad-level dielectric layer embedding first bond pads, a first edge seal structure comprising first pad-level ring structures, and at least one row of first dummy metal pads over the first interconnect-level dielectric layer, wherein: the first edge seal structure laterally surrounds the first semiconductor device; ​ Each of the first edge seal structures extends vertically from the first substrate to a horizontal plane that includes a bonding surface of the first bonding pad; and A row of first dummy metal pads is formed between a pair of the first edge seal structures.

16. The method of claim 15, wherein the first pad-level ring structure, the first dummy metal pads, and the first bonding pad are formed by forming cavities in the first pad-level dielectric layer, simultaneously depositing at least one metal material in each of the cavities, and removing excess portions of the at least one material from above the horizontal plane that includes a distal surface of the first pad-level dielectric layer.

17. The method of claim 15, further comprising forming metal moat via structures that contact respective annular peripheral portions of a top surface of the first substrate and laterally surround the first semiconductor device; and forming a vertical stack of metal ring structures that extends vertically from an annular top surface of a respective one of the metal moat via structures to a topmost surface of the first interconnect-level dielectric material layer, wherein each of the first edge seal structures includes a respective one of the metal moat via structures and a respective one of the vertical stack of metal ring structures.

18. The method of claim 15, further comprising: forming a second semiconductor die by forming a second semiconductor device over a second substrate, forming a second pad-level dielectric layer over the second semiconductor device, and forming second bonding pads and at least one row of second dummy metal pads in the second pad-level dielectric layer; and bonding the second semiconductor die to the first semiconductor die such that each row of second dummy metal pads is bonded to a respective one of the first edge seal structures by a metal-to-metal bond.

19. The method of claim 18, wherein: the method further comprises forming second edge seal structures in the second semiconductor die; each of the second edge seal structures includes a respective second pad-level ring structure that extends continuously around the second semiconductor device; and each of the second edge seal structures extends vertically from the second substrate to a horizontal plane that includes a bonding interface between the first bonding pad and the second bonding pad.

20. The method of claim 19, wherein each row of first dummy metal pads is bonded to a respective one of the second edge seal structures.

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