Memory blocks with separately driven source regions to improve performance

Abstract

Apparatus and techniques are described for providing separate source regions in a substrate under a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform programming and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with insulating material. Contacts to the source regions can include columnar contacts that extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, programming operations apply different voltages to the respective source regions during a verify test of a programming operation.

Description

Background Technology

[0001] This technology relates to the operation of memory devices.

[0002] Semiconductor memory devices have become increasingly common in a variety of electronic devices. For example, non-volatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charges representing data states. For example, charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure. An example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture, which includes a stack of alternating conductive and dielectric layers.

[0004] Memory devices include memory cells that can be arranged in series to form NAND strings, for example, where select-gate transistors are located at the ends of the NAND string to selectively connect the channels of the NAND string to source lines or bit lines. However, various challenges exist in operating such memory devices. Attached Figure Description

[0005] Figure 1A This is a block diagram of an example memory device.

[0006] Figure 1B yes Figure 1A A block diagram of the arrangement of the memory device 100, wherein the control circuitry 130 on the first die 130a communicates with the memory structure 126 on a separate second die 126b.

[0007] Figure 2 It is shown Figure 1A A block diagram of one embodiment of the sensing block 51.

[0008] Figure 3 It shows Figure 1A An exemplary specific implementation of a power control circuit 115 for supplying voltage to a block of memory cells in a plane.

[0009] Figure 4A This is a perspective view of an exemplary memory die 400, wherein blocks are disposed in corresponding planes P0 and P1, and... Figure 1A Consistent.

[0010] Figure 4B It shows Figure 1A An exemplary transistor 450 in the memory structure 126.

[0011] Figure 5A It shows Figure 4AAn exemplary view of the NAND string in block B0-0.

[0012] Figure 5B It shows Figure 5A An exemplary top view of block B0-0 and the corresponding NAND string, bit line and sensing circuitry.

[0013] Figure 5C It shows Figure 5A and Figure 5B A cross-sectional view of a 700n NAND string.

[0014] Figure 6A It shows Figure 4A An exemplary configuration of block B0-0 is shown, wherein separate source regions SRC1, SRC2 and SRC3 are located in substrate 404.

[0015] Figure 6B It shows Figure 4A Exemplary configurations of blocks B0-0 and B1-0 are shown, in which separate source pole regions SRC1, SRC2 and SRC3 are illustrated.

[0016] Figure 7A It shows Figure 6A The curve showing the relationship between the average programming threshold voltage (Vth) of the NAND string in the block and the distance to the word line (WL) driver.

[0017] Figure 7B It shows Figure 6A A graph showing the relationship between the threshold voltage (Vth) of the NAND string in the block and the distance to the word line (WL) driver, which illustrates the effect of different voltages at the source regions SRC1-SRC3 during the verification operation of the G-state memory cell.

[0018] Figure 8A Example I(A) is shown Figure 6A A top view of the block, in this embodiment, the cylindrical contact to the source region is located within the block.

[0019] Figure 8B It shows Figure 8A The block is a cross-sectional view along line AA.

[0020] Figure 8C It shows Figure 8A The block is a cross-sectional view along line BB.

[0021] Figure 9A Example I(B) is shown Figure 6A A top view of the block, in this embodiment, the cylindrical contacts to the source region are located outside the block.

[0022] Figure 9B It shows Figure 9A The block is a cross-sectional view along line BB.

[0023] Figure 10 Example I(C) is shown Figure 6A A top view of the block, in this embodiment I(C), the contacts to the source region are located inside and outside the block, and the source region includes different source lines.

[0024] Figure 11A A top view of a block with a single source pole region (SRC) is shown, wherein the contacts to the source pole region include planar contacts at the edge of the block.

[0025] Figure 11B It shows Figure 11A The block is a cross-sectional view along line AA.

[0026] Figure 11C It shows Figure 11A The block is a cross-sectional view along line BB.

[0027] Figure 12A It shows Figure 8A The details of the block area along path 820 are consistent with those of embodiments I(A)-I(C).

[0028] Figure 12B It shows Figure 12A The section view of this block area along path 820.

[0029] Figure 12C It shows the relationship with Figure 12B A consistent initial configuration of block regions, wherein substrate 404 is formed.

[0030] Figure 12D It shows the following Figure 12C The configuration of the block region, wherein an insulating region is formed in the substrate.

[0031] Figure 12E It shows the following Figure 12D The configuration of the block region, wherein a stack of layers is formed on the substrate.

[0032] Figure 12F It shows the following Figure 12E The configuration of the block region, in which memory holes and NAND strings are formed in the stack.

[0033] Figure 12G It shows the following Figure 12F The configuration of the block region, wherein trenches are formed in the stack.

[0034] Figure 12H It shows the following Figure 12G The configuration of the block region, in which metal is deposited in the stacked layers via the trench.

[0035] Figure 12I It shows the following Figure 12H The configuration of the block region, in which metal is removed from the trench.

[0036] Figure 13A Example II is shown Figure 6A A top view of the block, in this embodiment, different planar contacts to the source region are provided at the edge of the block.

[0037] Figure 13B It shows Figure 13A The block is a cross-sectional view along line AA.

[0038] Figure 13C It shows Figure 13A The block is a cross-sectional view along line BB.

[0039] Figure 13D It shows Figure 13A Details of the block area along path 1320.

[0040] Figure 13E It shows Figure 13D A cross-sectional view of the block area along path 1320 in embodiment II(A).

[0041] Figure 13F It shows the relationship with Figure 12B A consistent initial configuration of block regions in which a crystalline silicon substrate is formed.

[0042] Figure 13G It shows the following Figure 13F The configuration of the block region, wherein an insulating region is formed in the substrate.

[0043] Figure 13H It shows the following Figure 13G The configuration of the block region, wherein a stack of layers is formed on the substrate and memory holes are formed in the stack.

[0044] Figure 13I It shows the following Figure 13H The configuration of the block region, wherein an epitaxial region is formed at the bottom of the memory hole.

[0045] Figure 13J1 It shows the following Figure 13I The configuration of the block region, wherein trenches are formed in the stack.

[0046] Figure 13J2 It shows Figure 13J1 A top view of the block area.

[0047] Figure 13J3 It shows the following Figure 13J1The configuration of the block region, in which external columnar voids are formed to provide a wider portion of the trench.

[0048] Figure 13J4 It shows Figure 13J3 A top view of the block area.

[0049] Figure 13K It shows the following Figure 13J3 The configuration of the block region, wherein metal is deposited in the stacked layers via trenches 1330 and external columnar voids 1331.

[0050] Figure 13K1 It shows Figure 13K A top view of the block area.

[0051] Figure 13L It shows the following Figure 13K The configuration of the block region, in which metal is removed from the trench.

[0052] Figure 13M It shows the following Figure 13L The configuration of the block region, in which an insulating layer is deposited in the trench.

[0053] Figure 13M1 It shows Figure 13M A top view of the block area.

[0054] Figure 13N It shows the following Figure 13M The configuration of the block region, in which conductive material is deposited in the trench.

[0055] Figure 13N1 It shows Figure 13N A top view of the block area.

[0056] Figure 13O It shows the following Figure 13N The configuration of the block region, wherein internal cylindrical voids are formed to remove a portion of the conductive material in the widened area of ​​the trench, thereby forming separate planar contacts for each source region of the block.

[0057] Figure 13O1 It shows Figure 13O A top view of the block area.

[0058] Figure 14A Example II(B) is shown Figure 13D A cross-sectional view of the block area, in this embodiment, an insulating region is formed in a substrate comprising multiple layers, and a stack is formed on the substrate.

[0059] Figure 14B It shows the method for forming Figure 14AThe configuration of the block region is formed in which trenches and external columnar voids are formed vertically extending in the stack, and the external columnar voids are formed between the source regions.

[0060] Figure 14C It shows the following Figure 14B The configuration of the block region, in which the insulating layer is deposited in the trench and etched through the bottom.

[0061] Figure 14D It shows the following Figure 14C The configuration of the block region, in which conductive material is deposited in the trench.

[0062] Figure 14E It shows the following Figure 14D The configuration of the block region, wherein an internal cylindrical void is formed to remove a portion of the conductive material in the external cylindrical void, thereby forming a separate planar contact for each source region of the block.

[0063] Figure 15A The process for fabricating a stack of alternating layers on a substrate including separated source regions is shown.

[0064] Figure 15B It shows the use of in Figure 15A The process of creating cylindrical contacts in the source region.

[0065] Figure 15C It shows the use of in Figure 15A The process of creating the source region planar contact during the process.

[0066] Figure 16 The process for programming blocks is shown.

[0067] Figure 17 The threshold voltage (Vth) distribution of an eight-state memory device is shown.

[0068] Figure 18 Exemplary voltage signals for performing programming operations using different source region voltages are shown, and... Figure 16 Consistent. Detailed Implementation

[0069] Apparatus and techniques for providing memory blocks with separately driven source regions are described. Performance can be improved, for example, by providing a narrower threshold voltage profile.

[0070] In some memory devices, memory cells are joined together, such as in NAND strings within a block or sub-block. Each NAND string includes: a plurality of memory cells connected in series between one or more drain-side select-gate transistors (called SGD transistors) at the drain end of the NAND string's connection bit line; and one or more source-side select-gate transistors (called SGS transistors) at the source end of the NAND string or other memory strings or connected groups of memory cells at the source end of the connection source line. The select-gate transistor is also called the select gate. Furthermore, the memory cells may be arranged with a common control gate line (e.g., a word line) serving as the control gate. Memory cells can be connected in other types of strings and in other ways.

[0071] In a 3D memory structure, memory cells can be arranged in stacked vertical NAND strings on a substrate, where the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connecting to the memory cells. Each NAND string may have the shape of an upright cylinder intersecting the word lines to form a memory cell. Additionally, each NAND string includes various layers extending vertically within the stack. The source terminals of the NAND strings are connected to source regions in the substrate, and the drain terminals of the NAND strings are connected to bit lines. See, for example. Figures 5A-5C .

[0072] In a 2D memory structure, memory cells can be arranged in horizontal NAND strings on a substrate.

[0073] The expectation remains that shrinking such memory devices will improve performance, increase capacity, and reduce cost. However, maintaining consistent performance is challenging. For example, programming and erasing speeds vary across memory cell blocks due to variations in the distance from the NAND string to the row decoder that provides the drive voltage. One potential solution is to reduce the page size to below the standard 16kB page size. In this case, the memory cell block can be divided into smaller, separate blocks, although this increases chip size and reduces customizability. Another potential solution is to develop process improvements that reduce the variation in resistance and capacitance between word lines within the block. Using a row decoder on opposite sides of the block may also be helpful.

[0074] The technology provided herein solves the aforementioned and other problems. In one aspect, separate source regions are provided in the substrate beneath the block. These source regions can be driven separately by corresponding voltage drivers to provide benefits such as more uniform programming and erasing speeds and narrower threshold voltage distributions. In one method, a single source region is provided, and insulating regions 604 and 605 are provided by etching trenches and filling these trenches with an insulating material. Figure 6AThis divides the single source region into multiple source regions SRC1-SRC3. Contacts to the source regions can be provided in different ways. The contacts extend from above the block to the substrate to provide a conductive path to the source regions for carrying voltage signals. For example, one or more cylindrical contacts 801-806 ( Figure 8A The cylindrical contacts 900, 905, and 910 may extend through the block for each source region. The cylindrical contacts 900, 905, and 910 may also extend through the block in the lateral region 920. In another method, one or more planar contacts 602b1-602b3 and 603b1-603b3 ( Figure 13A For each source region, it extends through the block. Individual planar contacts can be formed in trenches along the opposite long edges of the block, and through cylindrical voids 1332 etched through the trenches. Figure 13O1 ) and utilizing insulating component 1302 ( Figure 13D Filling the cylindrical gaps divides the contact point into separate contacts.

[0075] On the other hand, during the verification test of the programming operation, different voltages Vsrcl-Vsrc3 are applied to the corresponding source regions. Figure 18 ).

[0076] These and other features will be discussed further below.

[0077] Figure 1A This is a block diagram of an exemplary storage device. Memory device 100, such as a non-volatile memory system, may include one or more memory dies 108. Memory die 108 or a chip includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines via row decoder 124 and via bit lines via column decoder 132. Read / write circuitry 128 includes a plurality of sensing blocks 51, 52, ..., 53 (sensing circuitry) and allows for parallel reading or programming of pages of memory cells. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. The controller may reside on a die 127 separate from the memory dies 108. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0078] The memory structure can be a 2D memory structure or a 3D memory structure. The memory structure may include one or more memory cell arrays, including 3D arrays. The memory structure may include a monolithic 3D memory structure in which multiple memory stages are formed on (but not in) a single substrate (such as a wafer), without intermediate substrates. The memory structure may include any type of non-volatile memory, which is monolithically formed in one or more physical stages of memory cell arrays having active regions disposed on a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate.

[0079] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126 and includes a state machine, on-chip address decoder 114, and power control circuitry 115. Storage area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, the state machine is programmed by software. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry).

[0080] On-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control circuitry 115 controls the power and voltage supplied to the word lines, select gate lines, bit lines, and source lines during memory operations. This power control module may include drivers for word lines, SGS and SGD transistors, and source lines. See also... Figure 3 In one approach, the sensing block may include a bitline driver.

[0081] In some specific implementations, some components of the components may be combined. In various designs, one or more components (alone or in combination) of the components other than memory structure 126 may be considered as at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any or a combination of control circuit 110, state machine 112, decoders 114 and 132, power control circuit 115, sensing blocks 51, 52...53, read / write circuit 128, controller 122, etc. A state machine is a circuit that controls the operation of control circuit 110. In some implementations, the state machine is implemented or replaced by a microprocessor, microcontroller, and / or RISC processor.

[0082] The off-chip controller 122 (in one embodiment, circuitry) may include a processor 122e, memories such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct numerous read errors. RAM 122b may be, for example, DRAM storing uncommitted data. During programming, a copy of the data to be programmed is stored in RAM 122b until programming is successfully completed. In response to successful completion, the data is erased from RAM 122b and committed or released to a memory cell block. RAM 122b may store data for one or more word lines.

[0083] A memory interface 122d may also be provided. The memory interface, which communicates with the ROM, RAM, and processor, is a circuit that provides an electrical interface between the controller and the memory die. For example, the memory interface can change the format or timing of signals, provide buffers, isolate surges, latch I / O, etc. The processor can issue commands to the control circuitry 110 (or any other component of the memory die) via the memory interface 122d.

[0084] The memories in controller 122, such as ROM 122a and RAM 122b, include code such as a set of instructions, and the processor is operable to execute that set of instructions to provide the functionality described herein. Alternatively or otherwise, the processor may access the code from a subset 126a of the memory structure, such as reserved areas of memory cells in one or more word lines.

[0085] For example, the controller can use code to access memory structures, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is the software that initializes the controller during boot or startup and enables it to access memory structures. The controller can use the code to control one or more memory structures. Upon power-up, processor 122e fetches boot code from ROM 122a or subset 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0086] Generally, control code may include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below. Control circuitry may be configured to execute instructions for performing the functions described herein.

[0087] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0088] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0089] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM) devices; non-volatile memory devices, such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM); and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured with NAND or NOR.

[0090] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0091] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, comprising memory cells and SG transistors.

[0092] NAND memory arrays can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0093] Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as 2D memory structures or 3D memory structures.

[0094] In a 2D memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0095] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0096] Arrange a 3D memory array such that the memory elements occupy multiple planes or multiple memory device levels to form a three-dimensional structure (i.e., in the x, y and z directions, where the z direction is substantially perpendicular to the main surface of the substrate and the x and y directions are substantially parallel to the main surface of the substrate).

[0097] As a non-limiting example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements. These columns can be arranged in a 2D configuration, for example, in the xy-plane, resulting in a 3D arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a 3D memory array.

[0098] By way of non-limiting example, in a 3D NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The 3D memory array can also be designed in both NOR and ReRAM configurations.

[0099] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers located at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layer constituting each memory device level of the array is typically formed on the layer of the lower memory device level of the array. However, the layers of adjacent memory device levels in a monolithic 3D memory array may be shared between memory device levels or there may be intermediate layers between memory device levels.

[0100] 2D arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0101] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0102] Those skilled in the art will recognize that this technology is not limited to the described 2D and 3D exemplary structures, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0103] Figure 1B yes Figure 1A A block diagram of the arrangement of a memory device 100, wherein control circuitry 130 on a first die 130a communicates with a memory structure 126 on a separate second die 126b. The control circuitry may communicate with the memory structure and die 126b via a memory interface 131 (e.g., similar to memory interface 122d). Examples of memory interfaces (I / F) include JEDEC's Common Flash Memory Interface. The techniques described herein can be implemented using a control die 130a incorporated into one or more memory dies 126b, wherein the memory die includes the memory structure 126, and the control die includes control circuitry 130 representing all or a subset of the peripheral circuitry of the memory structure. The control circuitry may be located on the same die as the plurality of memory cells or on a different die than the plurality of memory cells.

[0104] For example, the memory structure may include non-volatile memory cells. In some embodiments, the memory die and control die are combined. Control circuitry 130 may include a set of circuitry that performs memory operations (e.g., write, read, erase, etc.) on the memory structure. The control circuitry may include a state machine 112, a memory area 113, an on-chip address decoder 114, and power control circuitry 115. In another embodiment, a portion of the read / write circuitry 128 is located on the control die 130a, while another portion of the read / write circuitry is located on the memory die 126b. For example, the read / write circuitry may include a sense amplifier. This sense amplifier may be located on the control die and / or the memory die.

[0105] The term "memory die" can refer to a semiconductor die containing non-volatile memory cells for storing data. The term "control circuit die" can refer to a semiconductor die containing control circuitry for performing memory operations on the non-volatile memory cells on the memory die. Typically, many semiconductor dies are formed from a single semiconductor wafer.

[0106] Figure 2 It is shown Figure 1A A block diagram of one embodiment of the sensing block 51. The individual sensing block 51 is divided into one or more core portions referred to as sensing circuits 60-63 or sensing amplifiers, and a common portion referred to as management circuitry 190. In one embodiment, each sensing circuit is connected to a corresponding bit line and NAND string, and the common management circuitry 190 is connected to a group of multiple (e.g., four or eight) sensing circuits. Each sensing circuit in the group communicates with its associated management circuitry via a data bus 176. Therefore, there are one or more management circuits communicating with the sensing circuitry of a group of memory elements (memory cells).

[0107] As an example, sensing circuit 60 operates during a programming cycle to provide a precharge / programming-suppression voltage to an unselected positioning line or a programming-enable voltage to a selected positioning line. The unselected positioning line is connected to an unselected NAND string and an unselected memory cell therein. An unselected memory cell can be a memory cell within an unselected NAND string, where the memory cell is connected to a selected or unselected word line. An unselected memory cell can also be a memory cell within a selected NAND string, where the memory cell is connected to an unselected word line. The selected bit line is connected to the selected NAND string and the selected memory cell therein.

[0108] The sensing circuit 60 also operates during a verification test in the programming cycle to sense memory cells, thereby determining whether they have been programmed by reaching an assigned data state (e.g., as indicated by a verification voltage Vth exceeding the assigned data state). The sensing circuit 60 also operates during a read operation to determine the data state to which the memory cell has been programmed. The sensing circuit 60 also operates during an erase operation in the verification test to determine whether multiple memory cells have a Vth below the verification voltage. The sensing circuit performs sensing by determining whether the conduction current in the connected bit lines is above or below a predetermined threshold level. This indicates whether the Vth of the memory cell is below or above the word line voltage, respectively.

[0109] The sensing circuit 60 also operates in the disable operation as described initially, for permanently increasing the threshold voltage of the select gate transistor to prevent access to memory cells. The sensing circuit determines whether Vth of the select gate transistor is higher than the verification voltage Vverify applied to the control gate of the select gate transistor.

[0110] The sensing circuit may include a selector 56 or a switch connected to transistor 55 (e.g., nMOS). Based on the voltage at the control gate 58 and drain 57 of transistor 55, the transistor may operate as a transmission gate or a bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage at the drain, the transistor operates as a transmission gate to pass the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, a programming-suppression voltage such as 1V to 2V may be passed when pre-charging and suppressing an unselected NAND string. Alternatively, a programming-enable voltage such as 0V may be passed to allow programming in a selected NAND string. Selector 56 may pass a supply voltage Vdd (e.g., 3V to 4V) to the control gate of transistor 55 to make it operate as a transmission gate.

[0111] When the voltage at the control gate is lower than the voltage at the drain, transistor 55 operates as a source follower to set or clamp the bit line voltage at Vcg-Vth, where Vcg is the voltage at the control gate 58 and Vth (e.g., 1V) is the threshold voltage of transistor 55. This assumes the source line is at 0V. This mode can be used during sensing operations such as read and verification operations. Therefore, the bit line voltage is set by transistor 55 based on the voltage output by selector 56. For example, selector 56 can pass Vbl_sense + Vth (e.g., 1.5V) to transistor 55 to provide Vbl_sense (e.g., 0.5V) on the bit line. Vbl selector 173 can pass a relatively high voltage, such as Vdd, to the drain 57, which is higher than the control gate voltage on transistor 55, to provide source follower mode during sensing operations.

[0112] Vbl selector 173 can transmit one of a plurality of voltage signals. For example, the Vbl selector can transmit a program-suppress voltage signal that increases from an initial voltage (e.g., 0V) to a program-suppress voltage (e.g., the voltage Vbl_inh for the corresponding bit line of an unselected NAND string during a programming cycle). Vbl selector 173 can also transmit a programming-enable voltage signal, such as 0V, for the corresponding bit line of a selected NAND string during a programming cycle. For example, the Vbl selector can select from a program-enable voltage signal based on a command from processor 192. Figure 3 The voltage signal of the BL voltage driver 340 in the middle.

[0113] In one approach, the selector 56 of each sensing circuit can be controlled separately from the selectors of other sensing circuits. The Vbl selector 173 of each sensing circuit can also be controlled separately from the Vbl selectors of other sensing circuits.

[0114] During sensing, sensing node 171 is charged until an initial voltage Vsense_init, such as 3V, is reached. The sensing node is then passed to bit lines via transistor 55, and the amount of decay of the sensing node is used to determine whether the memory cell is in a conductive or non-conductive state. Specifically, comparator circuit 175 determines the amount of decay by comparing the sensing node voltage with a trip voltage during sensing. If the sensing node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is equal to or lower than the verification voltage. If the sensing node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is higher than the verification voltage. For example, the comparator circuit 175 sets the sensing node latch 172 to 0 or 1 based on whether the memory cell is in a conductive or non-conductive state. The data in the sensing node latch can be read by processor 192 and used to update bits of trip latch 174. Subsequently, for the next programming cycle, the processor can use the bits in the trip latch and the allocated data state in latches 194-197 to determine whether the memory cell and NAND string are selected for or not for programming in the programming cycle, thereby passing the appropriate enable or suppress bit line voltage to the bit line respectively. Latches 194-197 can be considered as data latches or user data latches because they store the data to be programmed into the memory cell.

[0115] The management circuitry 190 includes a processor 192, four sets of exemplary data latches 194-197 for the sensing circuits 60-63, and an I / O interface 196 coupled between the data latch sets and the data bus 120. Each sensing circuit may be provided with a set of three data latches, for example, including individual latches LDL, MDL, and UDL. In some cases, different numbers of data latches may be used. In a three-bit implementation per unit, the LDL stores bits for the next page of data, the MDL stores bits for intermediate page data, and the UDL stores bits for the previous page of data.

[0116] Processor 192 performs calculations to determine the data stored in the sensed memory cells and stores the determined data in the set of data latches. Each set of data latches 194-197 stores data bits determined by processor 192 during a read operation and data bits imported from data bus 120 during a programming operation; these data bits represent write data to be programmed into memory. I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

[0117] During a read operation, the system operates under the control of state machine 112, which controls the supply of different control gate voltages to the addressed memory cell. As it progresses through various predefined control gate voltages corresponding to different memory states supported by the memory, a sensing circuit can trip at one of these voltages, and the corresponding output is provided from the sensing circuit to the processor 192 via data bus 176. The processor 192 then determines the resulting memory state by considering the tripping event of the sensing circuit and information about the control gate voltages applied via input line 193 from the state machine. It then calculates the binary code of the memory state and stores the resulting data bits in data latches 194-197.

[0118] Some implementations may include multiple processors 192. In one implementation, each processor 192 will include output lines (not shown) such that each output line is wire-ORed together. In some implementations, the output lines are inverted before being connected to the wires or lines. This configuration allows for rapid determination of when the programming process is complete during programming verification testing, as the state machine receiving the wires or lines can determine when all programmed bits have reached the desired level. For example, when each bit reaches its desired level, a logic zero for that bit is sent to the wire or line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing circuits, the state machine needs to read the wires or lines eight times, or logic can be added to the processor 192 to accumulate the results of the relevant bit lines, so that the state machine only needs to read the wires or lines once. Similarly, by correctly selecting the logic levels, the global state machine can detect when the first bit changes its state and adjust the algorithm accordingly.

[0119] During the programming or verification operation of a memory cell, the data to be programmed (written data) is stored in data latch groups 194-197 from the data bus 120. During reprogramming, the corresponding set of data latches for the memory cell can store data indicating when the memory cell can be reprogrammed based on the programming pulse magnitude value.

[0120] Under the control of the state machine, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be incrementally increased by one step from the previous programming pulse during the process, a process known as incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When both are consistent, the processor 192 sets the bit line to a programming-inhibited mode, such as by updating its latch. This prevents further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0121] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some specific implementations, the data latches are implemented as shift registers so that parallel data stored therein is converted into serial data for the data bus 120 and vice versa. All data latches corresponding to read / write blocks of memory cells can be connected together to form a block shift register, thereby enabling the serial transfer of input or output data blocks. Specifically, the read / write circuit module group is adjusted such that its data latch group shifts data sequentially into or out of the data bus as if they were part of a shift register for the entire read / write block.

[0122] Data latches indicate when an associated memory cell has reached certain milestones in a programming operation. For example, a latch might identify when the Vth of a memory cell is below a specific verification voltage. Data latches also indicate whether a memory cell is currently storing one or more bits from a page of data. For example, an LDL latch can be used to store the next page of data. An LDL latch is toggled (e.g., from 0 to 1) when the next page bit is stored in the associated memory cell. An MDL or UDL latch is toggled for each three-bit cell when the middle or previous page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell has completed programming.

[0123] Figure 3 It shows Figure 1A An exemplary specific implementation of power control circuitry 115 for supplying voltage to blocks of memory cells in a plane is provided. In one approach, the circuitry shown may be repeated for each plane of the die. In this example, memory structure 126 includes a set of four associated blocks B0-0 through B0-3 and another set of four associated blocks B0-4 through B0-7. See also Figure 4A A block can lie in one or more planes. Figure 1AThe line decoder 124 provides voltage to the word lines and the select gate control lines for each block via the transmission transistor 322. In one method, a separate line decoder is provided for each block. The line decoder may be provided on one side of the block, such as... Figure 6A As in the middle, or provided at opposite ends of the block. The line decoder can also be shared by two blocks, each block located in, for example... Figure 4A In one of the two planes, P0 and P1.

[0124] The line decoder provides control signals to the transfer transistors, which connect blocks to the line decoder. In one approach, the transfer transistors for each block are controlled by a common control gate voltage. Therefore, all transfer transistors in a block are either on or off at a given time. If a transfer transistor is on, a voltage from the line decoder is supplied to the corresponding control gate line or word line. If a transfer transistor is off, the line decoder is disconnected from the corresponding control gate line or word line, causing the voltage to float on the corresponding control gate line or word line.

[0125] For example, control gate line 312 is connected to transmission transistor groups 313-316, which are in turn connected to control gate lines B0-4 to B0-7, respectively. Control gate line 317 is connected to transmission transistor groups 318-321, which are in turn connected to control gate lines B0-0 to B0-3, respectively.

[0126] Typically, programming or reading operations are performed on a selected block at a time within a block. Erasing operations can be performed on a selected block or a sub-block. The line decoder connects global control line 302 to local control line 303. Control lines represent conductive paths. Voltage is supplied on the global control lines of many voltage drivers. Some voltage drivers can supply voltage to switch 350 connected to the global control line. Control transfer transistor 324 is used to transfer voltage from the voltage driver to switch 350.

[0127] The voltage driver may include a selected data word line (WL) driver 347 that provides voltage on the selected data word line during programming or read operations. Driver 347 may provide a pre-charge voltage and a programming voltage on WLn during a programming cycle of a programming operation. Driver 348 may be used for unselected data word lines. A dummy word line driver may also be provided if dummy word lines are used.

[0128] The voltage driver may also include a separate SGD driver for each sub-block. For example, such as in Figure 5AIn this block, SGD drivers 346, 346a, 346b, and 346c may be provided for SB0, SB1, SB2, and SB3, respectively. The SGD drivers provide voltage to control lines connected to the control gate of the SGD transistor (drain-side selected gate transistor). In one option, the SGS driver 345 is common to different sub-blocks within the block and provides voltage to control lines connected to the control gate of the SGS transistor (source-side selected gate transistor).

[0129] Various components, including the line decoder, can receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

[0130] A substrate (e.g., p-well) voltage driver 330 provides a voltage Vsub to the substrate. Source region voltage drivers 331a, 331b, and 331c provide voltage signals to three source regions SRC1, SRC2, and SRC3 in the substrate, respectively.

[0131] Bit line voltage driver 340 includes a voltage source that supplies voltage to a set of bit lines 342. This set of bit lines can also be shared by multiple blocks.

[0132] In such Figure 4A In the stacked memory device depicted in Figure 6, multiple sets of connected memory cells can be arranged in NAND strings that extend vertically upward from the substrate. In one approach, the bottom (or source end) of each NAND string contacts the substrate, for example, a well region, and the top (or drain end) of each NAND string is connected to a corresponding bit line.

[0133] Figure 4A This is a perspective view of an exemplary memory die 400, wherein multiple blocks are arranged in corresponding planes P0 and P1, and... Figure 1A Consistent. The memory die includes a substrate 404, an intermediate region 402 in which memory cell blocks are formed, and an upper region 403 in which one or more upper metal layers are patterned to form bit lines and other conductive paths. Planes P0 and P1 represent corresponding isolation regions formed in the substrate 404. Additionally, a first block sequence 405 (labeled B0-0 to B0-n-1) of n blocks is formed in P0, and a second block sequence 415 (labeled B1-0 to B1-n-1) of n blocks is formed in P1. Each plane may have associated row and column control circuitry, such as... Figure 1A The row decoder 124, the read / write circuit 128, and the column decoder 132.

[0134] In one approach, control circuitry 110, which can be located in a peripheral region of the die, can be shared between planes. Each plane may have a separate set of bit lines.

[0135] By providing memory cell blocks in multiple planes, parallel operations can be performed in the planes. For example, blocks in different planes can be erased simultaneously.

[0136] The substrate 404 may also carry circuitry below the block, as well as one or more lower metal layers that are patterned in the conductive path to carry signals of the circuitry.

[0137] In this example, memory cells are formed in vertical NAND strings within a block. Each block includes a stacked area of ​​memory cells, where alternating stacked layers represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upwards to an upper metal layer to form connections with conductive paths. While two planes are shown as an example, other examples may use four or more planes. One plane per die is also possible.

[0138] While the examples above relate to 3D memory devices with vertically extending NAND strings, the techniques presented herein are also applicable to 2D memory devices in which the NAND strings extend horizontally on a substrate.

[0139] Figure 4B It shows Figure 1A An exemplary transistor 450 in the memory structure 126. The transistor includes a control gate CG, a drain D, a source S, and a channel CH, and may represent, for example, a memory cell or a select-gate transistor. The drain terminal of the transistor is optionally connected to a bit line BL via one or more other transistors in the NAND string, and the source terminal of the transistor is optionally connected to a source line SL via one or more other transistors in the NAND string. The transistor may represent, for example, a memory cell or a select-gate transistor.

[0140] Figure 5A It shows Figure 4AAn exemplary view of the NAND strings in block B0-0. The NAND strings are arranged in a 3D configuration within the sub-blocks of the block. Each sub-block includes multiple NAND strings, with an example NAND string depicted. For example, SB0, SB1, SB2, and SB3 include example NAND strings 500n, 510n, 520n, and 530n, respectively. The NAND strings have data word lines, dummy word lines, and select gate lines. Each sub-block includes a set of NAND strings that extend in the x-direction and have a common SGD line or control gate layer. NAND strings 500n, 510n, 520n, and 530n are located in sub-blocks SB0, SB1, SB2, and SB3, respectively. The block can be programmed based on the word line programming order. One option is to program memory cells in different word line portions located in different sub-blocks one at a time, before programming memory cells in the next word line. For example, this could involve programming WL0 in SB0, SB1, SB2, and SB3, then programming WL1 in SB0, SB1, SB2, and SB3, and so on. For instance, the word line programming sequence could begin with WL0 (source extreme word line) and end with WL7 (drain extreme word line). For simplicity, this example includes eight data word lines. In practice, much more word lines would be used, such as 64, 96, or more.

[0141] In an erase operation, the entire block is usually erased, but partial block erasure is also possible, such as by erasing selected sub-blocks of the block and / or by erasing a subset of memory cells connected to the word line, which is less than the entire word line.

[0142] Multiple memory cells of B0-0 are arranged in NAND strings, wherein each NAND string includes a continuous charge trapping layer along the length of the NAND string. NAND strings 500n, 510n, 520n, and 530n have channels 500a, 510a, 520a, and 530a, respectively. Additionally, NAND string 500n includes an SGS transistor 501, dummy memory cells 502, data memory cells 503-514, dummy memory cells 515, and an SGD transistor 516. NAND string 510n includes an SGS transistor 521, dummy memory cells 522, data memory cells 523-534, dummy memory cells 535, and an SGD transistor 536. NAND string 520n includes an SGS transistor 541, dummy memory cells 542, data memory cells 543-554, dummy memory cells 555, and an SGD transistor 556. NAND string 530n includes SGs transistor 561, dummy memory cell 562, data memory cells 563-574, dummy memory cell 575, and SGD transistor 576.

[0143] This example illustrates one SGD transistor at the drain terminal of each NAND string and one SGS transistor at the source terminal of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines sGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in the NAND string.

[0144] Figure 5B It shows Figure 5A An exemplary top view of block B0-0 and the corresponding NAND strings, bit lines, and sensing circuitry. This view is located in the xy plane. Each circle represents a NAND string. In this example, the block is divided into three subsets 580-582, which correspond to three separate source regions SRC1-SRC3, respectively. Figure 6A Consistent. The first subset 580 includes bit lines BL0 to BLa and associated NAND strings and sensing circuitry. The second subset 581 includes bit lines BLa+1 to BLb and associated NAND strings and sensing circuitry. The third subset 582 includes bit lines BLb+1 to BLc and associated NAND strings and sensing circuitry. Each subset represents a subset of NAND strings in the block that are in contact with the corresponding source region. Different subsets of NAND strings are in contact with different source regions SRC1-SRC3, respectively. Moreover, these different subsets of the NAND strings are in contact with different subsets of the bit lines, for example, BLa+1 to BLb, BLa+1 to BLb, and BLb+1 to BLc.

[0145] Furthermore, the block was divided into sub-blocks SB0-SB3, and... Figure 5A Consistent. SB0 includes Figure 5A The NAND string 500n and the additional NAND string. SB1 includes... Figure 5A The NAND string 510n and the additional NAND string. SB2 includes... Figure 5A The NAND string 520n and the additional NAND string. SB3 includes... Figure 5A The NAND string 530n and the additional NAND string.

[0146] Each bit line is connected to a corresponding set of NAND strings, including one NAND string in each sub-block. For example, BL0 is connected to NAND strings 500n, 510n, 520n, and 530n in a set of NAND strings 599. Each bit line is also connected to a corresponding sensing circuit, and... Figure 2 The sensing circuits 60-63 are identical. For example, BL0 is connected to sensing circuit SC0.

[0147] In one method, programming operations can be performed on a sub-block at a time, and the programming operation includes verification tests. During the programming operation, a programming pulse is applied to a selected word line. Verification tests are then performed on memory cells connected to the selected word lines within the selected sub-block. Separate verification tests can be performed for each programmed data state. See also Figure 18 An example verification voltage is shown. During the verification test, a verification voltage is applied to the memory cell while the sensing circuit senses the current on the corresponding bit line. For example, SC0 can sense the current on BL0 based on the current in any of the NAND strings 500n, 510n, 520n, and 530n. If this current is lower than a specified level used for all or almost all of the selected NAND strings in the selected sub-block, the sub-block passes the verification test. For example, if no more than 1-5% of the NAND strings in the sub-block fail the verification test, it means the verification test passes. When this current is lower than the specified level used for the NAND strings, it means that the threshold voltage of the selected memory cell in the NAND string is higher than the verification voltage.

[0148] Figure 5C It shows Figure 5A and Figure 5B A cross-sectional view of a 500n NAND string. NAND strings are formed by etching memory holes in a stack and then depositing multiple thin layers of material along the sidewalls of the memory holes. Memory cells are formed in regions where word lines intersect with the multiple thin layers, and select-gate transistors are formed in regions where SGS and SGD control lines intersect with the multiple thin layers.

[0149] Multiple thin layers can be formed into a ring layer and can be deposited, for example, using atomic layer deposition. These layers may include, for example, a barrier oxide layer 663, a charge trapping layer 664 or film (such as silicon nitride (Si3N4) or other nitrides), a tunnel layer 665 (e.g., a gate oxide such as aluminum oxide), and a channel 660 (e.g., comprising polysilicon). A dielectric core 666 (e.g., comprising silicon dioxide) may also be provided. These layers can provide a MANOS or metal (W)-alumina (Al2O3)-nitride (Si3N4)-oxide (SiO2)-silicon (Si) structure. Word lines or control lines may contain metals such as tungsten. In this example, all layers are disposed within memory vias. In other methods, some of the layers may be disposed within word line or control line layers. Multiple thin layers form columnar active regions of a NAND string.

[0150] Figure 6A It shows Figure 4AAn exemplary configuration of block B0-0 is shown, illustrating separate source regions SRC1, SRC2, and SRC3 located in substrate 404. As mentioned initially, block performance can be improved by providing separate source regions in the substrate with separate voltage drivers. In this example, three source regions SRC1-SRC3 are provided in substrate 404. These different source regions may have the same size or different sizes depending on the associated number of NAND strings and / or bit lines. Typically, block performance can be improved by providing two or more source regions.

[0151] Insulating regions 604 and 605 in the substrate separate these source regions. Each insulating region formed in the substrate is located between adjacent source regions among a plurality of separated source regions. For example, insulating region 604 is located between SRC1 and SRC2, and insulating region 605 is located between SRC2 and SRC3.

[0152] The block includes a stacked region 601 in which NAND strings are formed. Region 601 is defined by trenches 602 and 603 at opposite edges of the block. Trenches can be formed to allow the removal of sacrificial layers of the block, as discussed further below. The trenches can then be filled with insulating material only, or with a combination of insulating and conductive materials. The use of conductive material in the trenches provides electrical contact with the source regions, as described further below. Typically, one or more trenches can be provided within the block, at the edge of the block, or at another location within the block.

[0153] Insulating materials 606-608 can be provided in shallow trenches etched on the top of the block. The insulating material can separate one or more selectable gate layers on the top of the block to form different sub-blocks of the block. This example includes sub-blocks SB0-SB3, with... Figure 5A Consistent. One or more select gate layers of each sub-block are connected to the corresponding voltage driver.

[0154] Region 601 of the block includes different parts B0-0a, B0-0b, and B0-0c, corresponding to different source regions SRC1-SRC3, respectively. The NAND string in each part is connected to the corresponding source region at its source end.

[0155] and Figure 5B Consistent bit lines BL0 to BLa, BLa+1 to BLb, and BLb+1 to BLc are connected to the drain terminals of the NAND strings in block portions B0-0a, B0-0b, and B0-0c, respectively. These bit lines extend in the y-direction, perpendicular to trenches 602 and 603 extending in the x-direction and insulating materials 606-608. These bit lines extend parallel to insulating regions 604 and 605.

[0156] Figure 3Word line drivers 347 and 348 are connected to word lines in region 601, for example, at one end 620 of the block. Axis 610 shows the distances from the word line drivers to the different NAND strings in the block, including near distance D0 and far distance D3. In this example, block region B0-0c extends from D0-D1 and is the block region closest to the word line drivers. Block region B0-0b extends from D1-D2 and is the second closest block region to the word line drivers. Block region B0-0a extends from D2-D3 and is the block region farthest from the word line drivers.

[0157] The width of the block is bw, and the length along the long side of the block is D3-D0.

[0158] Figure 6B It shows Figure 4A An exemplary configuration of blocks B0-0 and B1-0 is shown, in which separate source regions SRC1, SRC2, and SRC3 are illustrated. For example, each source region may extend beneath one or more blocks, with each block situated in a separate plane. In this example, each of source regions SRC1-SRC3 extends beneath B0-0 in P0 and beneath B1-0 in P1. This method facilitates the manufacturing process because the number of separate source regions on the substrate is less than in the case where separate source regions are provided for each block. In this case, each source region includes a diffusion region located in the substrate that extends the width (in the y-direction) of multiple blocks and at least the width of one block.

[0159] Figure 7A It shows Figure 6A This is a curve showing the relationship between the average programming threshold voltage (Vth) of the NAND strings in a block and the distance to the word line (WL) driver. This distance corresponds to the column address of the NAND string. NAND strings can be arranged in columns or groups, such as a group of 16 NAND strings. To obtain this data, a fixed number of programming pulses are used to program the memory cells. Vth varies because the RC time constant of the word line voltage signal varies based on the distance from the WL driver. Specifically, curve 700 indicates that NAND strings closer to the WL driver have a lower RC time constant and a faster programming speed, and therefore achieve a higher Vth in response to a fixed number of programming pulses. ΔVth represents the Vth difference, which is the difference between the Vth of the memory cell farthest from the WL driver and the Vth of the memory cell closest to the WL driver. Vth differences exceeding 0.3V have been observed. Variations may also exist for different memory chips manufactured from the same wafer.

[0160] Figure 7B It shows Figure 6AA graph showing the relationship between the threshold voltage (Vth) of the NAND string in the block and the distance to the word line (WL) driver, illustrating the effect of different voltages at the source regions SRC1-SRC3 during the verification operation of the G-state memory cell. The vertical axis shows the Vth of the G-state memory cell in an example where G-state is the highest data state, compared to... Figure 17 Consistent. Curves 700 and 701 represent Vth when the source voltage Vsrc1 is relatively low. Curves 705 and 706 represent Vth when the source voltage Vsrc3 is relatively high. Curves 702-704 represent Vth when the source voltage Vsrc2 is at an intermediate level.

[0161] During sensing operations (such as verification tests or read operations), the current in the NAND string is a function of the bit line voltage at the drain end of the NAND string and the source region voltage at the source end of the NAND string. The Vth of a particular memory cell being read depends on the difference between the voltage applied at the control gate of that cell (applied via the corresponding word line) and the source region voltage. For a particular memory cell relatively far from the WL driver within a block, the control gate resistance will be relatively high. Therefore, for a given source region voltage, the Vth of that particular memory cell will appear higher compared to memory cells closer to the WL driver.

[0162] For example, consider memory cells located near and far from the WL driver, both storing the same amount of charge. Assume that during a read operation, the WL driver outputs VrB( Figure 17 This causes the nearby memory cell to receive VrB and the distant memory cell to receive VrB-0.2V. In this case, the nearby memory cell can be sensed as being in a conductive state (e.g., as a state A cell) because the local WL voltage exceeds the cell's Vth, while the distant memory cell can be sensed as being in a non-conductive state (e.g., as a state B cell) because the local WL voltage does not exceed the cell's Vth. This results in a read error.

[0163] One solution to allow consistent cell Vth readings along word lines at different distances from the WL driver is to calibrate the source voltage for different regions of the block as the distance from the WL driver increases. That is, the source voltage can be an increasing function of the distance from the WL driver; for example, the source voltage can increase as the distance from the WL driver increases. Using this method, in the example above involving VrB, for distant memory cells, the gate-to-source voltage and Vth decrease, causing the local WL voltage to exceed the Vth of that cell. Therefore, distant memory cells will be sensed as being in a conductive state (e.g., as state A cells), the same as nearby memory cells.

[0164] This solution is demonstrated by selecting source region voltages indicated by dashed curves, specifically curves 700, 703, and 706 for blocks B0-0a, B0-0b, and B0-0c. The voltages associated with curves 700, 703, and 706 are Vsrc = Low, Vsrc = Medium, and Vsrc = High, respectively. Exemplary values ​​are 1.5V, 1V, and 0.5V, respectively. This method reduces the Vth variation from ΔVth1 to ΔVth2. As the Vth variation decreases, the Vth distribution of memory cells on the block narrows, and read errors decrease.

[0165] In one possible implementation, during a sensing operation targeting a memory cell associated with one of the source regions, the control circuitry is configured to instruct the corresponding source region voltage driver to set the voltage of the corresponding voltage signal as a function of the distance of one of these memory cells from the word line driver. In other words, the voltage can be set as a function of the distance of one of the source regions from the word line driver, or as a function of the location of the source region within separate source regions.

[0166] The ability to control the voltage of separated source regions can also be helpful in situations such as sensing memory cells with negative threshold voltages. The voltage of separated source regions can be optimized based on other factors such as the location of selected word lines within a block.

[0167] The source voltage can be set based on any desired criterion. Setting the source voltage based on the distance from the WL driver is just one example.

[0168] Figure 8A Example I(A) is shown Figure 6A A top view of the block, in this embodiment, showing cylindrical contacts to the source region located within the block. Typically, one or more conductive paths or contacts can be provided between the source region in the substrate and the metal layer above the stack, such as in... Figure 4A The upper region 403 is shown. In this example, the conductive path includes multiple cylindrical contacts for each of the source regions SRC1-SRC3. For example, cylindrical contacts 801-804 are provided for SRC1 in SB0-SB3 respectively. Cylindrical contact 801 is located in a cylindrical gap 801v (such as a cylindrical hole). Similar cylindrical contacts are provided for SRC2 and SRC3 in SB3, including cylindrical contacts 805 and 806 respectively. The cylindrical contacts are shown as shaded circles and can be provided at various locations (depicted as hollow circles) above the source regions and between the memory holes (MH). In this simplified example, there are 32 NAND strings connected to each source region. In addition, there are 24 NAND strings in each sub-block, with eight NAND strings per source region.

[0169] A larger number of contacts reduces resistance, but takes up space in the block. This example provides one contact for each source region in each sub-block, but other options are possible.

[0170] In this example, the grooves 602 and 603 located at opposite edges of the block include insulation and are not used as contacts to the source region.

[0171] Insulating regions 604 and 605 in the substrate are also shown, which separate the source regions. These insulating regions are located below the word line layer in the block, but are shown for illustrative purposes only. A single bit line BL is shown to illustrate the bit line orientation. This bit line is connected to a NAND string / memory via in each sub-block, for example, to MH0-MH3 in SB0-SB3 respectively.

[0172] The following is a cross-sectional view of the block along a portion of path 820. Path 820 extends across trench 603 to memory hole 811, then to insulating region 604, and then returns across trench 603.

[0173] Each source region may include a diffusion region in the substrate, which extends, for example, the width (bw) of the block in the bit line direction (y direction).

[0174] Figure 8B It shows Figure 8A The block is a cross-sectional view along line AA. The block has eight wordline layers, one SGS layer, and one SGD layer, with... Figure 5A Consistent. The cylindrical contacts 804-806 in SB3 are depicted as upright cylinders that extend from the corresponding source regions SRC1-SRC3 at the bottom of the stack in substrate 404 to the top of the stack or above the top of the stack (e.g., ...). Figure 8C (As shown). For example, each source region SRC1-SRC3 receives the corresponding voltage Vsrc1-Vsrc3 via the corresponding contacts 804-806.

[0175] Figure 8C It shows Figure 8A A cross-sectional view of the block along line BB. This view shows cylindrical contacts 801-804 extending above the stack to a horizontally extending conductive path 810. Figure 8A or Figure 8B (Not shown in the image). Different horizontally extended conductive paths can be provided for each source region to carry different voltage signals.

[0176] Figure 9A Example I(B) is shown Figure 6AA top view of the block, in this embodiment, shows cylindrical contacts to the source region located outside the block. L-shaped contacts 900, 905, and 910 are connected to SRC1, SRC2, and SRC3, respectively, to provide corresponding voltage signals to the source region. Each L-shaped contact includes a cylindrical contact in a lateral region 920 of block B0-0 and a horizontal extension at the bottom of the cylindrical portion. For example, L-shaped contacts 900, 905, and 910 include cylindrical contacts 902, 904, and 909, and horizontal extensions 901, 903, and 908, respectively.

[0177] Figure 9B It shows Figure 9A A cross-sectional view of the block along line BB. This view shows an L-shaped contact 900, which includes a cylindrical contact 902 and a horizontal extension 901 connected to SRC1. An advantage of this method is that the area of ​​the block used for memory holes is not occupied by the cylindrical contacts. However, the horizontal extension involves additional processing. Specifically, trenches can be formed in the substrate and filled with a conductive material to provide the horizontal extension. Subsequently, holes are etched in the stack and filled with a conductive material to provide the cylindrical contacts.

[0178] Figure 10 Example I(C) is shown Figure 6A A top view of the block, in this embodiment I(C), the contacts to the source region are located inside and outside the block, and the source region includes different source lines. Figure 9A The L-shaped contacts 900, 905, and 910 are repeated. Cylindrical contacts 1001-1003 are also provided for SRC1-SRC3 respectively. This method provides a single cylindrical contact for each source region within the block, but multiple cylindrical contacts can also be provided for each source region. Each source region includes multiple parallel rows connected at one end. For example, SRC1 includes exemplary row 1004 and connection member 1005.

[0179] Trenches can be formed in the substrate and filled with a conductive material such as a metal to provide parallel rows and connecting components. Contacts can be provided on the outside and / or inside of the block.

[0180] Figure 11A A top view of a block with a single source region (SRC) is shown, wherein the contacts to the source region include planar contacts at the edge of the block. The planar contacts may have generally flat opposing walls that extend vertically upward from the substrate in the xz plane. The planar contacts may have a generally rectangular cross-section, such as... Figure 11CAs shown. The planar contacts can be continuous wall-shaped contacts. Specifically, trench 602 includes a planar contact 602b and an insulating material 602a, and trench 603 includes a planar contact 603b and an insulating material 603a. Each planar contact contacts the source region SRC to carry a common voltage signal to the SRC. The planar contacts include a conductive material, such as a metal.

[0181] Figure 11B It shows Figure 11A The block is shown in a cross-sectional view along line AA. A planar contact 603b extends the length of the block in the x-direction and extends the height of the block in the z-direction. Because a single planar contact 603b extends the length of the block, it cannot be used to provide different voltage signals to different source regions in the substrate. The technology described further below modifies this configuration to provide separate planar contacts for different source regions.

[0182] Figure 11C It shows Figure 11A The block is shown in a cross-sectional view along line BB. Planar contacts 602b and 603b extend the height of the block and are surrounded on its sides by insulating materials 602a and 603a, respectively.

[0183] Figure 12A It shows Figure 8A The details of the block area along path 820 are consistent with embodiments I(A)-I(C). Positions “1” to “6” are marked along this path. Path 820 extends across trench 603 (from the outer wall 690 of the trench at position “1” to the inner wall 691 of the trench at position “2”) to memory hole 811 (position “3”), at the edge of insulating region 604 (position “4”), through the middle of insulating region 604 to the inner wall of trench 603 (position “5”) and the outer wall of trench 603 (position “6”). Trench 603 is filled with insulating material 603i.

[0184] Figure 12B It shows Figure 12A The block region is shown in cross-sectional view along path 820. The block includes a stack 1200 formed on substrate 404. The stack includes a conductive layer, shown as a shaded rectangle separated by a dielectric layer (used as word lines and select gate lines), the dielectric layer being shown as an open rectangle. Trench 603 filled with insulating elements 603i and memory via 811 are filled with layers and dielectric cores (with...). Figure 5C(Consistent). Insulating regions 604 are formed from positions "4" to "6" in a portion of the substrate. The remainder of the substrate includes a metal layer 1201 to reduce the resistance of the source region SRC2. SRC2 may include a doped polysilicon region (such as n-type polysilicon), an insulating layer 1202 (such as SiN), an n-type polysilicon capping layer 1203, and an insulating layer 1204 (such as an oxide, for example, SiO). The n-type polysilicon may include, for example, polysilicon doped with phosphorus or arsenic.

[0185] The material in the memory hole forms a NAND string NS, wherein the bottom 811b or source end of the NAND string is in contact with SRC1.

[0186] Insulating region 604 extends in the substrate to isolate region SRC2 from region SRC1. Figure 8A As discussed, trench 603 is filled with insulating material 603i.

[0187] Figures 12C to 12I Describes the use of manufacturing Figure 12B The sequence of block regions. Along path 820, positions "1" to "6" and... Figure 12A and Figure 12B Consistent.

[0188] Figure 12C It shows the relationship with Figure 12B An initial configuration of a consistent block region is shown, in which a substrate 404 is formed. Note that additional portions of this substrate extend further below the illustrated substrate 404. The substrate includes a metal layer 1201 and an SRC2 region on the metal layer. Above the SRC2 layer, between oxide (e.g., SiO) layers 1202a and 1202c, is a sacrificial polysilicon layer 1202b, such as p-type polysilicon. The p-type polysilicon may include, for example, polysilicon doped with boron or gallium.

[0189] Figure 12D It shows the following Figure 12C The configuration of the block region, wherein an insulating region is formed in the substrate. Through Figure 8A Trenches are etched in the substrate in the y-direction and filled with insulating material to form an insulating region 604. The insulating region 604 may extend from a height below the bottom of the SRC2 region to a height above the top of the SRC2 region to electrically isolate SRC2 from SRC1.

[0190] Figure 12E It shows the following Figure 12D The configuration is a block region configuration in which a stack of layers is formed on a substrate. The stack 1200 is formed by depositing layers over the substrate. These layers may include dielectric (such as oxide) layers alternating with sacrificial material layers (“s”) (such as SiN).

[0191] Figure 12F It shows the following Figure 12E The configuration is a block region configuration in which memory vias 811 and NAND strings NS are formed in the stack. The memory vias are etched through the layers in the stack. Then, various layers and dielectric cores are deposited in the memory vias to form NAND strings ( Figure 5C ).

[0192] Figure 12G It shows the following Figure 12F The configuration of the block region, wherein trenches 1220 are formed in the stack, such as by etching through the stack in the x direction. Figure 8A The trench portion between positions "1" and "2" extends downwards to the sacrificial polysilicon layer 1202b. The void portion between positions "5" and "6" extends downwards to the insulating region 604. The trench may have a uniform depth. Once the trench is formed, the sacrificial layer ("s") can be removed by supplying etchant into the void. A metal (such as tungsten) can then be supplied into the void to form a conductive layer in the stack, such as... Figure 12H As shown.

[0193] Figure 12H It shows the following Figure 12G The configuration is a block region in which metal is deposited in a stacked layer via the trench. A conductive layer is formed as the metal fills the voids created when the sacrificial layer is removed, as shown by the shaded rectangle. The metal layer also forms as a byproduct within the trench.

[0194] Figure 12I It shows the following Figure 12H The configuration is a block region configuration, in which metal is removed from trench 1220 by means such as etching. Insulators are deposited in trench 1220. Figure 12B The configuration follows Figure 12I The configuration.

[0195] Figure 13A Example II is shown Figure 6AA top view of the block, in this embodiment, shows different planar contacts to the source region provided at the edge of the block. Note that in this example, the planar contacts are located at the edge of the block, but they could also be located elsewhere, including inside the block. For example, trench 602 includes planar contacts 602b1-602b3 respectively to SRC1-SRC3, and trench 603 includes planar contacts 603b1-603b3 respectively to SRC1-SRC3. Adjacent planar contacts are separated from each other by insulating structures such as insulating posts (electrically isolated). For example, planar contacts 602b1 and 602b2 are separated from each other by insulating post 1300, and planar contacts 602b2 and 602b3 are separated from each other by insulating post 1301. Similarly, planar contacts 603b1 and 603b2 are separated from each other by insulating post 1302, and planar contacts 603b2 and 603b3 are separated from each other by insulating post 1303. Posts 1300 and 1302 are aligned and contact with insulating region 604, and posts 1301 and 1303 are aligned and contact with insulating region 605. Further details of the manufacturing process are provided below.

[0196] The following is a cross-sectional view of the block along a portion of path 1320. Path 1320 extends across trench 603 to memory hole 811, then to insulating region 604, and then returns across trench 603.

[0197] Figure 13B It shows Figure 13A The block is shown in a cross-sectional view along line AA. Planar contacts 602b1-602b3 each extend from the top of the stack to the bottom of the stack and to the corresponding source regions SRC1-SRC3, thereby providing separate conductive paths to the respective source regions. Additionally, as mentioned, planar contacts 603b1 and 603b2 are separated from each other by insulating posts 1302, and planar contacts 603b2 and 603b3 are separated from each other by insulating posts 1303. In one method, posts 1302 and 1303 may be upright cylinders comprising insulating material. These posts may have cross-sectional shapes other than circular, such as square, rectangular, or elliptical.

[0198] Figure 13C It shows Figure 13A The block is shown in a cross-sectional view along line BB. Planar contacts 602b1 and 603b1 extend the height of the block and are surrounded on its sides by insulating materials 602a and 603a, respectively.

[0199] Figure 13D It shows Figure 13AThe details of the block area along path 1320 are shown. Positions “1” to “7” are marked along this path. Path 1320 extends across trench 603, starting at the outer wall insulation material 603a1 of the trench at position “1” (see outer wall 690), passing through the planar contact 603b2, reaching the inner wall insulation material 603a2 of the trench at position “2” (see inner wall 691), reaching the memory hole 811 (position “3”), reaching the edge of the insulating area 604 (position “4”), extending along the middle of the insulating area 604 to the widened inner wall insulation material 603a3 of the trench 603 (see widened inner wall 1390) (position “5”), passing through the insulating post 1302 (position “6”), and then reaching the widened outer wall insulation material 603a4 of the trench 603 (see widened outer wall 1391) (position “7”).

[0200] The trench 603 has a width w1 for most of its length, distinguished from the widened section with a width w4 near the insulating post 1302. Specifically, along the centerline of the insulating region 604 in the y-direction, the trench 603 has a width w4 > w1 in the region of the insulating post 1302. Planar contacts 603b1 and 603b2 have a width w2. The insulating post 1302 has a diameter or width w3 > w2. The width is in the y-direction. In the y-direction, each post may be wider than the width of the planar contacts to ensure that adjacent planar contacts are separated from each other and do not short-circuit. For example, the insulating post 1302 with a width w3 is wider than the width w2 of the adjacent planar contacts 603b1 and 603b2 on opposite sides of the post. The formation of the insulating post 1302 is facilitated by increasing the width of the groove 603 in the region of the insulating post 1302, so as to provide a widened inner wall insulating material 603a3 and a widened outer wall insulating material 603a4 for the insulating material 603a.

[0201] Figure 13E It shows Figure 13D A cross-sectional view of the block region in Embodiment II(A). The block includes a stack 1200 formed on a substrate 404. The stack includes a conductive layer shown as a shaded rectangle separated by a dielectric layer (used as word lines and select gate lines), the dielectric layer shown as an open rectangle. From positions “1” to “2”, an outer wall insulating material 603a1, a planar contact 603b2, and an inner wall insulating material 603a2 are provided for a trench 603. At position “3”, a memory via 811 and a NAND string NS are provided. From positions “4” to “7”, an insulating region 604 is formed in a portion of the substrate. At positions “5”, “6”, and “7”, a widened inner wall insulating material 603a3, an insulating pillar 1302, and a widened outer wall insulating material 603a4 are shown.

[0202] In addition to the insulating region 604, the substrate also includes a doped crystalline silicon region 1310, such as p-type silicon. For example, the epitaxial region 1311 of the substrate extends upward from the top surface of the substrate to a height above the SGS layer. The bottom of the NAND string and memory vias contacts the epitaxial region and SRC2.

[0203] As mentioned, the insulating region 604 extends in the substrate to isolate the SRC2 region from the SRC1 region.

[0204] Figures 13F to 13O1 Describes the use of manufacturing Figure 13E The sequence of block regions. Along path 1320, positions "1" to "7" and... Figure 13D Consistent.

[0205] Figure 13F It shows the relationship with Figure 12B A consistent initial configuration of the block region in which a crystalline silicon substrate 404 is formed. This silicon can be doped in situ to provide p-type silicon.

[0206] Figure 13G It shows the following Figure 13F The configuration of the block region, wherein an insulating region is formed in the substrate. Through Figure 11A Trenches are etched in the substrate along the y-direction and filled with insulating material to form an insulating region 604. The insulating region 604 extends from a height below the bottom of the SRC2 region to a height above the top of the SRC2 region.

[0207] Figure 13H It shows the following Figure 13G The configuration is a block region configuration in which a stack of layers is formed on a substrate and a memory hole 811 is formed in the stack. As mentioned, the layer stack includes sacrificial layers “s” alternating with dielectric layers.

[0208] Figure 13I It shows the following Figure 13H The configuration of the block region, wherein an epitaxial region 1311 is formed at the bottom of each memory hole.

[0209] Figure 13J1 It shows the following Figure 13I The configuration of the block region, wherein trenches are formed in the stack. The trench 1330 has a width w1, and... Figure 13D Consistent, and extending from the top of the stack below the bottom of the stack, into insulating region 604 and silicon region 1310.

[0210] Figure 13J2 It shows Figure 13J1 A top view of the block area. A groove 1330 with a width w1 is shown.

[0211] Figure 13J3It shows the following Figure 13J1 The configuration is a block region configuration in which an external cylindrical void is formed to provide a widened portion 1325 of the trench. An external cylindrical void 1331 having a width w2 > w1 extends vertically from the top of the stack below the bottom of the stack, into the insulating region 604. This external cylindrical void overlaps with the trench and is wider than the trench, such that it forms a widened region (e.g., a protrusion or circular protrusion) of the trench 1330. This external cylindrical void is formed between source regions SRC1 and SRC2 and is aligned with the insulating region 604. This configuration can be used to remove sacrificial material from the sacrificial layer “s” in the stack. An internal cylindrical void, further described below, can be formed within the region of the external cylindrical void.

[0212] Figure 13J4 It shows Figure 13J3 A top view of the block area. An external cylindrical gap 1331 with a width w2 > w1 is shown.

[0213] Figure 13K It shows the following Figure 13J3 The configuration is a block region configuration in which metal is deposited in a stacked layer via trench 1330 and external cylindrical voids 1331. Metal is deposited to form a conductive layer including word lines and a select gate layer. A conductive layer, as shown by the shaded rectangle, is formed when metal fills the voids created when the sacrificial layer is removed. Metal layer 1340 is also formed as a byproduct in the trench.

[0214] Figure 13K1 It shows Figure 13K A top view of the block area. Metal layer 1340 is shown. This metal layer is attached to the sides and bottom of the trench as a byproduct of metal deposition.

[0215] Figure 13L It shows the following Figure 13K The configuration of the block region, in which metal is removed from the trenches, such as by etching. Empty trenches 1330 and external cylindrical voids 1331 are re-formed, as... Figure 13J3 As shown.

[0216] Figure 13M It shows the following Figure 13L The configuration of the block region, wherein an insulating layer is deposited in the trench. Positions “1”, “2”, “5” and “7” respectively show the outer wall insulating material 603a1, the inner wall insulating material 603a2, the widened inner wall insulating material 603a3 and the widened outer wall insulating material 603a4.

[0217] Figure 13M1 It shows Figure 13MA top view of the block area. It shows the outer wall insulation material 603a1, the inner wall insulation material 603a2, the widened inner wall insulation material 603a3, and the widened outer wall insulation material 603a4.

[0218] Figure 13N It shows the following Figure 13M The configuration is a block region configuration in which conductive material is deposited in trenches. In this example, the conductive material portion 1350 in the cylindrical voids does not completely fill the voids. Alternatively, the conductive material fills the cylindrical voids. In this example, the conductive material portion 1351 in the trench 1330 fills the trench, contacting SRC2 to form a planar contact 60362. The conductive material may include, for example, a metal or doped polysilicon. For example, p-type polysilicon may include boron-doped polysilicon.

[0219] Figure 13N1 It shows Figure 13N A top view of the block area. Conductive material portions 1350 and 1351 are shown.

[0220] Figure 13O It shows the following Figure 13N The configuration of the block region includes an internal cylindrical void formed to remove a portion of the conductive layer in the widened region of the trench, thereby forming separate planar contacts for each source region of the block. An internal cylindrical void 1332 is etched through the trench at the center of the external cylindrical void to remove a portion 1350 of the conductive material. As a result, a planar contact 603b2 is formed to SRC2, which is separate from planar contact 603b1. The internal cylindrical void prevents electrical contact between these two adjacent planar contacts 603b1 and 603b2. For this purpose, in the y-direction, the width or diameter w3 of the internal cylindrical void is greater than the width w2 of planar contacts 603b1 and 603b2. Each internal cylindrical void divides the conductive material in the trench into two adjacent planar contacts.

[0221] The internal cylindrical gap can be formed within the region of the external cylindrical gap and can share a common longitudinal axis with the external cylindrical gap. The internal and external cylindrical gaps can be aligned with the insulation region 604.

[0222] By depositing insulating elements in the internal cylindrical voids to form insulating pillars 1302, compliance was achieved. Figure 13O configuration Figure 13E The configuration.

[0223] Figure 13O1 It shows Figure 13O A top view of the block area. The internal cylindrical void 1332 is shown.

[0224] Figure 14A Example II(B) is shown Figure 13DA cross-sectional view of the block area, in this embodiment, an insulating region is formed in a substrate comprising multiple layers, and a stack is formed on the substrate. This can be achieved... Figure 12C-12F and Figure 14B-14E This configuration is obtained after the configuration is determined. Figure 14A Similar to Figure 13E , except the substrate.

[0225] The substrate 404 includes an insulating region 604 together with a metal layer 1210, a source region SRC2, an insulating layer 1202, a polysilicon capping layer 1203, and an insulating layer 1204. Widened inner wall insulating material 603a3, insulating pillars 1302, and widened outer wall insulating material 603a4 extend downwards into the insulating region 604. A memory via 811 and the associated NAND string NS extend downwards into SRC2. Outer wall insulating material 603a1, planar contacts 603b2, and inner wall insulating material 603a2 also extend downwards into SRC2 to provide contact with SRC2, which can carry voltage signals.

[0226] Figure 14B It shows the method for forming Figure 14A The configuration is a block region configuration in which trenches 1330 and external cylindrical voids 1331 are formed extending vertically in the stack, and the external cylindrical voids are formed between the source regions. This configuration is similar to Figure 13L The configuration includes an external cylindrical void 1331 with a width w2 > w1, which extends vertically from the top of the stack to below the bottom of the stack, entering the insulating region 604. A trench 1330 has a width w1 and extends vertically from the top of the stack to below the bottom of the stack, entering SRC2. In this configuration, metal has been deposited to form word lines and select gate lines, and byproduct metal has been removed from the voids.

[0227] Figure 14C It shows the following Figure 14B The configuration is a block region configuration in which the insulating layer is deposited in trenches and etched through the bottom. This configuration is similar to... Figure 13M The configuration is as follows: Insulating material is deposited in the trench 1330 and the outer cylindrical void 1331, and etched through at the bottom. This forms an outer wall insulating material 603a1, an inner wall insulating material 603a2, a widened inner wall insulating material 603a3, and a widened outer wall insulating material 603a4.

[0228] Figure 14D It shows the following Figure 14C The configuration is a block region configuration in which conductive material is deposited in trenches. This configuration is similar to... Figure 13NThe configuration is as follows. In this example, the conductive material portion 1350 in the outer cylindrical gap 1331 does not completely fill the gap. In this example, the conductive material portion 1351 in the trench 1330 fills the trench, contacting SRC2, thereby forming a planar contact 603b2.

[0229] Figure 14E It shows the following Figure 14D The configuration of the block region includes an internal cylindrical void to remove a portion of the conductive material from the external cylindrical void, thereby forming a separate planar contact for each source region of the block. This configuration is similar to... Figure 13O The configuration. The internal cylindrical voids 1332 are etched through the external cylindrical voids of the trench to remove the conductive material portion 1350. Figure 14D As a result, a planar contact 603b2 is formed to SRC2, which is separated from the planar contact 603b1. This internal cylindrical gap prevents electrical contact between the two adjacent planar contacts 603b1 and 603b2. Figure 13O1 As shown, the width or diameter w3 of the internal cylindrical void is greater than the width w2 of the planar contacts 603b1 and 603b2. Each internal cylindrical void divides the conductive material in the trench into two adjacent planar contacts.

[0230] By depositing insulating elements in the internal cylindrical voids 1332, compliance was achieved. Figure 14E configuration Figure 14A The configuration.

[0231] Figure 15A A process for fabricating alternating layers on a substrate including separated source regions is illustrated. Step 1500 includes fabricating source regions in the substrate. In one method, a single source region, such as... Figure 11B The source region (SRC) is another approach. Another method is to form a separate source region. The source region can be a source diffusion region in the substrate including at least one doped well. The doped well can be p-type or n-type and has a substantially uniform dopant concentration level. The dopant concentration can be from about 1.0 × 10^15 / cm^3 to 1.0 × 10^18 / cm^3. In another approach, the source region includes different source lines, such as... Figure 10 As shown.

[0232] Step 1501 includes forming insulating regions that divide the source regions into separate source regions. See, for example, [link to relevant documentation]. Figure 8A and Figure 8B The insulation zones 604 and 605.

[0233] Step 1502 includes forming a stack of alternating layers on a substrate. Dielectric material layers (such as oxides) may alternate with sacrificial material layers (such as SiN). See, for example... Figure 12BThe stack is 1200. Figure 15A The process can be Figure 15B or Figure 15C The process. Figure 15B Covering Examples 1(A)-(C), these examples include cylindrical contacts for the source region. Figure 15C Covering Examples 1I(A) and (B), these examples include planar contacts for the source region.

[0234] Figure 15B It shows the use of in Figure 15A The process of creating cylindrical contacts to the source region during the process. Step 1510 includes etching memory holes and cylindrical gaps in the stack. For example, see... Figure 8A The memory vias MH and cylindrical voids 801v. Step 1511 includes the option to etch the cylindrical voids in the lateral region of the stack. Step 1512 includes depositing material into the memory vias to form NAND strings. See also Figure 5C Step 1513 includes depositing conductive material within the cylindrical voids to form cylindrical contacts to the source region. See, for example, [link to relevant documentation]. Figure 8A The cylindrical contacts 801-804. Step 1514 includes etching trenches at the edges of the stack (e.g., along one or both long sides). See, for example, [link to example]. Figure 12G The trench 1220. Step 1515 includes replacing the sacrificial material in the layer with metal via the trench. For example, see... Figure 12H Step 1516 includes removing the byproduct metal from the trench and filling the trench with an insulating material. See, for example, [link to relevant documentation]. Figure 12A and Figure 12B The insulating material 603i in the groove 603.

[0235] Figure 15C It shows the use of in Figure 15A The process of creating the source region planar contacts during the process. Step 1520 includes etching memory vias in the stack. Step 1521 includes depositing material into the memory vias to form NAND strings. Step 1522 includes etching trenches at the edges of the stack. The trenches may extend completely through the stack in the z-direction. The trenches may also extend the length of the stack or block, for example, in Figure 11A In the x-direction. Step 1523 includes etching an external cylindrical void at the location of the insulating region separating the source region in the trench. For example, see... Figure 13J3 and Figure 13J4 The external cylindrical void 1331. Step 1524 includes replacing the sacrificial material in the layer with metal via a trench. For example, see... Figure 13K Step 1525 includes removing byproduct metal from the trench and depositing an insulating layer on the walls of the trench and the external cylindrical voids. See, for example, [link to relevant documentation]. Figure 13MThe outer wall insulating material 603a1, inner wall insulating material 603a2, widened inner wall insulating material 603a3, and widened outer wall insulating material 603a4 are included. This isolates the word line from the conductive material deposited in the next step. Step 1526 includes depositing conductive material in the trench and the outer cylindrical voids to form a contact to the source region. See, for example, [link to relevant documentation]. Figure 13N The conductive material portions 1350 and 1351 and the planar contact 603b2 are located within the stack. At this point, a single contact common to each source region exists at each edge of the stack. The conductive material may extend the entire length of the stack or block.

[0236] Step 1527 includes etching the inner cylindrical voids to remove a portion of the conductive material within the outer cylindrical voids, thereby forming separate planar contacts to the separated source regions. See, for example, [link to relevant documentation]. Figure 13O and 13O1 Internal columnar voids 1332 and Figure 13A The separate planar contacts 602b1-602b3 and 603b1-603b3 are in the middle.

[0237] The voids described herein, including trenches, can be formed using photolithography techniques. For example, a mask containing a photoresist can be deposited on the block or substrate. The mask can be exposed and developed to form a pattern with openings at the desired void locations. An etching process can then be performed to transfer the pattern of the mask to the block or substrate. The mask can then be removed by a cleaning process.

[0238] Figure 16 The process for programming a block is illustrated. Step 1600 initiates the programming loop in the programming operation. This programming operation can generate different Vth levels for memory cells, such as... Figure 17 As shown. Step 1601 includes performing a pre-charge phase. Step 1602 includes performing a programming phase. Step 1603 includes performing a verification phase, including applying different voltages to different source regions of the substrate. For example, as combined with Figure 7B The voltages discussed may be based on the distances of the source region and its associated block region and the NAND string from the word line driver. Step 1604 determines whether to execute the next programming cycle. If step 1604 is true, step 1600 is reached. If step 1604 is false, the programming operation is completed at step 1605. Figure 18 Exemplary details of the pre-charging phase 1807, the programming phase 1808, and the verification phase 1809 are provided.

[0239] Figure 17The threshold voltage (Vth) distribution of an eight-state memory device is shown. As an example, eight data states, or three bits per cell, are shown. In another example, two data states (one bit per cell), four data states (two bits per cell), or sixteen data states (four bits per cell) are used. The vertical axis depicts the number of memory cells on a logarithmic scale, and the horizontal axis depicts the threshold voltage on a linear scale. The Vth distribution can represent all memory cells connected to a word line or in a block. After erasing the block, the Vth distribution 1700 representing the erase state is obtained. The erase operation is complete when the Vth of all or nearly all memory cells is below the verification voltage VvEr.

[0240] The memory cells then undergo a programming operation. Each memory cell will have an assigned data state. Some memory cells are assigned to an erase state and are not programmed. In this example, most memory cells are programmed to higher states, such as AF, which are represented by Vth distributions 1701-1707. These memory cells undergo a verification test using verification voltages VvA-VvG. The memory cells can be read using read voltages VrA-VrG. During the verification test, different voltages can be applied to different source regions, as described herein. Different voltages can also be applied to different source regions in other sensing operations, such as read operations.

[0241] Figure 18 Exemplary voltage signals for performing programming operations using different source region voltages are shown, and... Figure 16 Consistent. The vertical dimension represents voltage, and the horizontal dimension represents time, with time points ranging from t0 to t12. The depicted time period corresponds to a programming cycle and includes a precharge phase 1807 (t0-t2), a programming phase 1808 (t2-t8), and a verification phase 1809 (t9-t12). Voltage signals 1800, 1810, 1820, 1830, 1840, and 1850 represent VWLn (voltage of the selected word line), VWL_unsel (voltage of the unselected word line), Vsgd (voltage of the SGD transistor), Vsgs (voltage of the SGS transistor), Vbl (bit line voltage), and Vsrc (source voltage), respectively. VWL_unsel can include data word lines and dummy word lines.

[0242] The precharge phase is used to charge the channels of the NAND string. During the precharge phase, curve 1801 shows a positive voltage for VWLn, such as 1-2V. In the programming phase, VWLn increases from 0V (curve 1802) at t3 to the pass voltage Vpass (curve 1804), and then increases to the peak level Vpgm at t5 (curve 1805). VWLn then drops back to 0V at t6 before the verification phase 1809. In the verification phase, a verification signal 1806 is applied to the selected word line, and the selected memory cell is sensed during different verification voltages of the verification signal. In this example, the verification voltages are VvE, VvF, and VvG.

[0243] For VWL_unsel, curve 1811 shows the positive voltage during the pre-charge phase, such as 1-2V. During the programming phase, VWL_unsel increases from 0V (curve 1812) to Vpass (curve 1814), and then decreases back to 0V at t12 at the end of the verification phase 1809.

[0244] For Vsgd, curve 1821 shows the positive voltage, such as 4-6V, for all SGD transistors in the block. This allows Vbl to be passed to the channel. For the SGD transistors of the selected NAND string, curve 1822 shows Vsgd_sel during the programming phase, for example, 2.5V. Vsgd_sel is high enough to provide the associated SGD transistor of the selected NAND string with a conductive state, which receives the programming-enable voltage Vbl_en = 0V. For the SGD transistors of the unselected NAND string, curve 1823 shows Vsgd_unsel during the programming phase, for example, 0V. This provides the associated SGD transistor of the unselected NAND string with a non-conductive state. This allows the associated channel to be boosted via capacitive coupling when VWLn and VWL_unsel ramp up from 0V to Vpass. This complements the boost from the precharge phase. Curve 1824 shows Vsgd_sel at an elevated level, such as 4-6V, during the verification phase to allow sensing to occur in the associated NAND string. Curve 1825 shows Vsgd_unsel at 0V during the verification phase because no sensing occurs in the associated NAND string.

[0245] For Vsgs, in one approach, all SGS transistors in the block are connected and receive the same voltage. During the pre-charge phase, curve 1831 shows a positive voltage, such as 4-6V, for all SGS transistors in the block. This allows voltage to be transferred from the substrate to the channel.

[0246] Curve 1834 shows Vsgs = 0V during the programming phase. Curve 1835 shows Vsgd at elevated levels such as 4-6V during the verification phase to allow sensing to occur in selected NAND strings.

[0247] Vbl represents the bit line voltage, which can be set individually for selected and unselected NAND strings. During the precharge phase, curve 1841 shows a positive precharge voltage Vbl_pc for the selected NAND string, such as 2V. Curve 1843 shows 0V for the bit line connected to an unselected NAND string. During the programming phase, curve 1842 shows, for example, a programming-suppression voltage Vbl_inh = 1.5V for an unselected NAND string, and curve 1843 shows, for example, a programming-enable voltage Vbl_en = 0V for the selected NAND string. Curve 1844 shows, for example, Vbl = 0.5V during the verification phase.

[0248] For Vsrc, during the first time period t0-t1 in the precharge phase, curve 1851 shows a positive precharge voltage, such as 2V. In the programming phase, curve 1854 shows a positive Vsrc voltage to help maintain the SGS transistor in a non-conductive state. In this example, a common voltage Vsrc is applied to different source regions during the precharge and programming phases. However, different voltages can also be applied to different source regions during the precharge and / or programming phases. In the verification phase, curves 1855, 1856, and 1857 show voltages Vsrc1, Vsrc2, and Vsrc3 for source regions SRC1, SRC2, and SRC3, respectively. Therefore, different voltages can be applied to different source regions during the verification phase, such as, for example, in combination with... Figure 7B The voltage shown is an example, as discussed.

[0249] Different voltages can also be applied to different source regions during other sensing operations such as read operations, and during erase operations.

[0250] Therefore, it can be seen that in one specific embodiment, an apparatus includes: a substrate; separate source regions located in the substrate; and a block located on the substrate, wherein the block includes a set of NAND strings arranged vertically, different subsets of the set of NAND strings being in contact with different source regions in the separate source regions.

[0251] In another embodiment, a method includes: forming separate source regions in a substrate; forming a stack of alternating layers on the substrate; etching trenches in the stack that extend the height and length of the stack; depositing a conductive material in the trenches that extends the height and length of the stack; and separating the conductive material into separate contacts, wherein each contact is connected to a corresponding source region in the separate source regions.

[0252] In another embodiment, an apparatus includes: a control circuit configured to be connected to a plurality of source region voltage drivers for a plurality of source regions in a substrate, the memory cell block being located on the substrate; and a memory interface connected to the circuit. The control circuit is configured to issue commands via the memory interface to instruct each of the plurality of source region voltage drivers to provide a corresponding voltage signal to a corresponding source region among the plurality of source regions.

[0253] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the intended particular use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. An apparatus for providing a memory block having separately driven source regions, comprising: substrate(404); The separated source regions (SRC1-SRC3) located in the substrate include at least a first source region and a second source region; The insulating region in the substrate located between the first source region and the second source region is used to electrically isolate the first source region and the second source region. and A block (B0-0 to B0-n-1, B1-0 to B1-n-1) located on the substrate, the block comprising a set of NAND strings (500n, 510n, 520n, 530n) arranged vertically, different subsets of the set of NAND strings contacting different source regions in the separated source regions, the different subsets of the set of NAND strings including at least a first subset of NAND strings contacting the first source region and a second subset of NAND strings contacting the second source region; and The device further includes: separate voltage drivers (331a-331c) for the separated source regions, including at least a first voltage driver connected to the first source region and a second voltage driver connected to the second source region.

2. The apparatus according to claim 1, further comprising: A set of bit lines (BL0 to BLa); BLa+1 to BLB; BLb+1 to BLc), wherein the different subsets of the set of NAND strings are in contact with the different subsets of the set of bit lines.

3. The apparatus according to claim 1, wherein: Each source region includes a diffusion region located in the substrate, the diffusion region extending at least the width (bw) of the block.

4. The apparatus according to claim 1, wherein The first subset of the NAND string is located above the first source region and the second subset of the NAND string is located above the second source region.

5. The apparatus according to claim 4, further comprising: A set of bit lines extending in the bit line direction (BL0 to BLa); BLa+1 to BLB; BLb+1 to BLc), wherein the insulating region extends in the bit line direction.

6. The apparatus according to claim 1, further comprising: The contacts (801-804, 602b1-602b3, 603b1-603b3) extend vertically in the block, each contact being connected to a corresponding source region in the separated source regions.

7. The apparatus according to claim 6, wherein: The contacts include cylindrical contacts (801-804).

8. The apparatus according to claim 6, wherein: The contacts include multiple planar contacts (602b1-602b3, 603b1-603b3).

9. The apparatus according to claim 8, further comprising: Insulating posts (1300-1303) separate adjacent planar contacts among the plurality of planar contacts.

10. The apparatus according to claim 9, wherein: Each of the adjacent planar contacts comprises a conductive material; and The insulating post has a width (w4), which is greater than the width (w1) of the conductive material.

11. A method for providing a memory block having separately driven source regions, comprising: A source region is formed in the substrate; One or more insulating regions are formed in the source region to divide the source region into multiple separate source regions (SRC1-SRC3), wherein the multiple separate source regions (SRC1-SRC3) include at least a first source region separated from the second source region by the insulating region; A block is formed on the first source region and the second source region on the substrate. The block includes a set of NAND strings (500n, 510n, 520n, 530n) arranged vertically. The set of NAND strings includes at least a first subset of NAND strings that cover and contact the first source region and a second subset of NAND strings that cover and contact the second source region. and The first voltage driver is connected to the first source region, and the second voltage driver is connected to the second source region.

12. The method of claim 11, further comprising: Trenches (602, 603, 1220) are etched in the stack of the set of NAND strings that includes the block, the trenches extending the height and length (D3-D0) of the stack. A conductive material is deposited in the trench, the conductive material extending the height and length of the block; and The conductive material is separated into separate contacts (801-804, 602b1-602b3, 603b1-603b3), wherein each contact is connected to a corresponding source region in the separated source regions, and each contact includes at least a first contact connected to the first source region and a second contact connected to the second source region.

13. The method according to claim 12, wherein: The separation of the conductive material includes etching columnar voids (801v, 1331) in the conductive material.

14. The method of claim 13, wherein: The cylindrical void has a width (w2) greater than the width (w1) of the conductive material.

15. The method of claim 14, wherein: The cylindrical voids are etched in the widened area of ​​the trench.

16. An apparatus for providing a memory block having separately driven source regions, comprising: The control circuit is configured to be connected to a plurality of source region voltage drivers for a plurality of source regions in a substrate region located below the block, the plurality of source region voltage drivers including at least a first source region voltage driver connected to a first source region and a second source region voltage driver connected to a second source region. and A memory interface is connected to the control circuit, which is configured to issue commands via the memory interface to instruct each of the plurality of source region voltage drivers to provide a corresponding voltage signal to a corresponding source region among the plurality of source regions, including providing a first voltage signal to the first source region and providing a second voltage signal to the second source region, the second voltage signal being different from the first voltage signal.

17. The apparatus according to claim 16, wherein: The control circuit is configured to instruct each source region voltage driver to provide the corresponding voltage signal to the corresponding source region during the verification phase of the programming cycle of the programming operation.

18. The apparatus according to claim 16, wherein: The control circuit is configured to instruct each source region voltage driver to provide the corresponding voltage signal to the corresponding source region during sensing operation.

19. The apparatus according to claim 16, wherein: During a sensing operation for a memory cell associated with one of the source regions, the control circuit is configured to instruct the corresponding source region voltage driver to set the voltage of the corresponding voltage signal as a function of the distance of one of the source regions from the word line driver.

Images