Memory device including auxiliary circuit for adjusting voltage level of word line

Abstract

A storage device includes: a memory cell array including memory cells; a row decoder that selects a word line from word lines connected to the memory cells based on an address received from a memory controller; and a word line voltage generator that provides a word line voltage to the selected word line. The word line voltage generator includes: word line drivers, each corresponding to a word line; and word line undervoltage drive circuitry, each corresponding to a word line, which reduces the word line voltage level output by the word line drivers by different voltage levels based on the address.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0189362, filed on December 18, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The exemplary embodiments of this disclosure described herein relate to a semiconductor memory device, and more specifically, to a memory device including auxiliary circuitry for controlling the voltage levels of word lines. Background Technology

[0003] Semiconductor memories are mainly divided into volatile memories and non-volatile memories. Volatile memories (such as DRAM or SRAM) have fast read and write speeds, but the data stored in volatile memories is lost after power is turned off. In contrast, non-volatile memories retain data even after power is turned off.

[0004] As semiconductor manufacturing processes continue to improve, the resistance of the metal layers in the memory cells of Static Random Access Memory (SRAM) is constantly increasing. When the resistance of the bit lines in SRAM increases, errors may occur during read or write operations. Summary of the Invention

[0005] One aspect provides a storage device that includes auxiliary circuitry that controls the word line voltage level supplied to each word line differently during read or write operations.

[0006] According to one or more example embodiments, a storage device is provided, the storage device comprising: a memory cell array including a plurality of memory cells; a line decoder configured to: select one word line from a plurality of word lines connected to the plurality of memory cells based on an address received from a memory controller; and a word line voltage generator configured to provide a word line voltage to the selected word line. The word line voltage generator includes: a plurality of word line drivers, each corresponding to one of the plurality of word lines; and a plurality of word line undervoltage drive circuits, each corresponding to one of the plurality of word lines, and reducing the word line voltage levels output by the plurality of word line drivers to different voltage levels based on the address.

[0007] According to another aspect of one or more example embodiments, a storage device is provided, comprising: a memory cell array including a first memory cell and a second memory cell; a row decoder configured to: select one of a first word line connected to the first memory cell and a second word line connected to the second memory cell based on an address received from a memory controller; a first word line driver configured to: provide a word line voltage to the first word line when the first word line is selected; a second word line driver configured to: provide a word line voltage to the second word line when the second word line is selected; a first word line undervoltage driving circuit configured to: reduce the voltage level of the first word line to a first voltage level when the first word line is selected; and a second word line undervoltage driving circuit configured to: reduce the voltage level of the second word line to a second voltage level, the second voltage level being greater than the first voltage level, when the second word line is selected.

[0008] According to another aspect of one or more example embodiments, a storage device is provided, comprising: a memory cell array including a plurality of memory cells; a row decoder configured to: select one word line from a plurality of word lines connected to the plurality of memory cells based on an address received from a memory controller; and a word line voltage generator configured to: provide different word line voltage levels to the selected word line based on the address. Attached Figure Description

[0009] The above and other aspects will become apparent from a detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating a storage device according to an example embodiment;

[0011] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of the storage device shown;

[0012] Figure 3 This illustrates an example embodiment. Figure 2 The circuit diagram of the memory cell array of the shown memory device;

[0013] Figure 4 This illustrates the relationship between the example embodiment and Figure 3 A diagram showing the word lines connected to the memory cells of a memory cell array and the word line drivers connected to those word lines;

[0014] Figure 5 This is a diagram illustrating a word line voltage generator according to an example embodiment;

[0015] Figure 6 This illustrates an example embodiment. Figure 5 A diagram of the undervoltage drive circuit for the word line voltage generator;

[0016] Figure 7 This illustrates an example embodiment. Figure 5 A diagram of the undervoltage drive circuit for the word line voltage generator;

[0017] Figure 8 This illustrates an example embodiment. Figure 5 A diagram of the undervoltage drive circuit for the word line voltage generator;

[0018] Figure 9 This illustrates an example embodiment. Figure 5 A diagram of the undervoltage drive circuit for the word line voltage generator;

[0019] Figure 10 A diagram illustrating a word line voltage generator according to an example embodiment; and

[0020] Figure 11 This illustrates an example embodiment. Figure 10 A diagram showing the layout of the word line voltage generator. Detailed Implementation

[0021] Various exemplary embodiments will now be described in detail and clearly so that those skilled in the art can readily implement them.

[0022] Figure 1 This is a block diagram illustrating a storage device according to an example embodiment. (Refer to...) Figure 1 The storage device 1000 may include a storage device 1100 and a memory controller 1200.

[0023] Storage device 1100 can receive input / output signals (IO) from memory controller 1200 via input / output lines, control signals (CTRL) via control lines, and external power supply (PWR) via power lines. Storage device 1100 can receive commands (CMD) and addresses (ADDR) from memory controller 1200. Storage device 1000 can store data in storage device 1100 under the control of memory controller 1200.

[0024] The storage device 1100 may include a storage cell array 1110 and peripheral circuitry 1115. The storage cell array 1110 may have a planar 2D structure or a vertical 3D structure. The storage cell array 1110 may include a plurality of storage cells. The storage cell array 1110 may be located next to or above the peripheral circuitry 1115.

[0025] The peripheral circuitry 1115 may include analog and / or digital circuitry for storing or retrieving data stored in the memory cell array 1110. The peripheral circuitry 1115 may receive an external power supply PWR via a power line and generate internal power at various levels based on the external power supply PWR.

[0026] The peripheral circuit 1115 can receive data from the memory controller 1200 via input / output lines. The peripheral circuit 1115 can store data in the memory cell array 1110 according to the control signal CTRL. Alternatively or additionally, the peripheral circuit 1115 can read data stored in the memory cell array 1110 and provide the read data to the memory controller 1200.

[0027] Figure 2 This illustrates an example embodiment. Figure 1 A block diagram of storage device 1100 of storage device 1000 shown. (Refer to...) Figure 2 The storage device 1100 may include a storage cell array 1110 and peripheral circuitry 1115. The peripheral circuitry 1115 may include a row decoder 1120, a column decoder 1130, an input / output circuit 1140, a word line (WL) voltage generator 1150, and / or control logic 1160.

[0028] The memory cell array 1110 can be connected to multiple word lines WL. The memory cell array 1110 can be connected to the word line voltage generator 1150 via multiple word lines WL.

[0029] The row decoder 1120 can select word lines during write or read operations. The row decoder 1120 can select word lines based on the row address included in the address ADDR.

[0030] The column decoder 1130 can be connected to the memory cell array 1110 via multiple bit lines BL. The column decoder 1130 can select one or more bit lines based on the column address included in the address ADDR.

[0031] The input / output circuit 1140 can be internally connected to the column decoder 1130 via the data line DL, and externally connected to the memory controller 1200 via the input / output lines IO1 to IOn (see reference). Figure 1 During a write operation, the input / output circuit 1140 can receive write data from the memory controller 1200.

[0032] During a read operation, input / output circuitry 1140 can provide data read from memory cell array 1110 to memory controller 1200. Input / output circuitry 1140 can output data via input / output lines IO1 to IOn. The number of input / output lines IO1 to IOn can be determined based on the type of storage device 1000.

[0033] The input / output circuitry 1140 may include multiple sense amplifiers S / A 1141 and multiple write drivers W / D 1142. During a read operation, the multiple sense amplifiers S / A 1141 can read data from memory cells connected to selected word lines. During a write operation, the multiple write drivers W / D 1142 can store data to memory cells connected to selected word lines.

[0034] Word line (WL) voltage generator 1150 can receive internal power from control logic 1160 and generate word line voltages for reading or writing data. Word line voltages can be supplied to selected word lines based on addresses from line decoder 1120.

[0035] Control logic 1160 can use commands CMD, address ADDR, and control signals CTRL provided from memory controller 1200 to control operations such as read and / or write to memory device 1100. Address ADDR may include a row address for selecting a word line and a column address for selecting a memory cell.

[0036] Figure 3 This illustrates an example embodiment. Figure 2 The circuit diagram of the memory cell array 1110 of the shown memory device 1100. (Refer to...) Figure 3 The storage cell array 1110 may include a plurality of storage cells (e.g., MC1 to MC2). In an example embodiment, each storage cell may be a static random access memory cell.

[0037] The memory cell array 1110 can be connected to the row decoder 1120 and / or the word line voltage generator 1150 via the first word line WL1 to the m-th word line WLm. The memory cell array 1110 can be connected to the column decoder 1130 via the first bit line to the z-th bit line (BL1 to BLz, BLB1 to BLBz). For example, BLB1 to BLBz can have voltage levels complementary to BL1 to BLz. For example, in some example embodiments, when BL1 is high, BLB1 can be low.

[0038] Each memory cell in the memory cell array 1110 may include a latch circuit (LAT) containing an inverter, and transmission gates PG and PGB. For example, the first memory cell MC1 may be connected to a first word line WL1, and first bit lines BL1 and BLB1. The first word line WL1 may be connected to the gates of the first transmission gate PG and the second transmission gate PGB. The first bit lines BL1 and BLB1 may be connected to the drain or source of the first transmission gate PG and the second transmission gate PGB.

[0039] Figure 4 This illustrates the relationship between the example embodiment and Figure 3 The memory cell array 1110 includes word lines connected to memory cells, and a word line driver WD connected to word line WL according to an example embodiment. See also... Figure 2 and Figure 4 The memory cell array 1110 may include multiple memory cells 1110_1 to 1110_m. For example, the multiple memory cells 1110_1 to 1110_m are memory cells connected to a bit line BL. Memory cell 1110_1 is the memory cell farthest from the column decoder 1130 or the input / output circuit 1140. Memory cell 1110_m is the memory cell closest to the column decoder 1130 or the input / output circuit 1140. Memory cell 1110_k is the memory cell located between memory cells 1110_1 and memory cells 1110_m.

[0040] Multiple memory cells 1110_1 to 1110_m can be connected to multiple word lines WL1 to WLm respectively. Each word line among the multiple word lines WL1 to WLm can send the word line voltage to the transmission gate of the memory cell connected to the corresponding word line (e.g., Figure 3 (PG or PGB in the text).

[0041] The word line voltage generator 1150 may include multiple word line drivers WD1 to WDm. The output terminals of the multiple word line drivers WD1 to WDm can be connected to multiple word lines WL1 to Wlm, respectively. The input terminals of the multiple word line drivers WD1 to WDm can be connected to multiple complementary word lines WLB1 to WLBm, respectively.

[0042] The line decoder 1120 can be based on Figure 2 The row address RA included in the address ADDR is used to select a word line. For example, the row decoder 1120 can provide a word line drive signal to one of the complementary word lines WLB1 to WLBm selected based on the row address RA. The word line driver connected to the selected complementary word line can invert the word line drive signal based on the power supply voltage and output the inverted word line drive signal to the selected word line.

[0043] The column decoder 1130 can be based on Figure 2 The column address CA included in the address ADDR is used to select one or more bit lines. During a write operation, the write driver W / D 1142 corresponding to the selected bit lines BL and BLB can send data to the selected bit lines BL and BLB. During a read operation, the sense amplifier S / A 1141 corresponding to the selected bit lines BL and BLB can detect the voltage of the selected bit lines BL and BLB.

[0044] Figure 5 This illustrates an example embodiment. Figure 4 The diagram shows the word line voltage generator 1150. (Refer to...) Figure 4 and Figure 5 The word line voltage generator 1150 may include auxiliary circuitry to prevent read interference. For example, the auxiliary circuitry may include word line undervoltage drive circuits (WLUD) 1150_1 to 1150_m. Word line undervoltage drive circuits 1150_1 to 1150_m may be connected to multiple word lines WL1 to Wlm, respectively.

[0045] With improvements in manufacturing processes or reductions in operating voltage, read interference may occur when writing to a memory cell during a read operation or when writing to a memory cell that is not the target of the write operation during a write operation. Word line undervoltage drive circuits 1150_1 to 1150_m can mitigate read interference by reducing the voltage level of the selected word line.

[0046] As the manufacturing process improves, the resistance of the bit line BL may increase. Therefore, the interference margin of a memory cell (i.e., the probability that no read interference occurs on each word line) can have a variable value. For example, the interference margin of a memory cell may increase with the distance from that memory cell to the column decoder 1130 or the input / output circuit 1140. In other words, the interference margin of a memory cell farther from the column decoder 1130 or the input / output circuit 1140 may be higher than the interference margin of a memory cell closer to the column decoder 1130 or the input / output circuit 1140.

[0047] Read interference can be improved by reducing the word line voltage level using word line undervoltage drive circuits 1150_1 to 1150_m. However, since the interference margin may differ for each word line, unnecessary drops in word line voltage may occur depending on the word line's location when the word line voltage is reduced equally across all word lines.

[0048] In the example embodiment, word line undervoltage drive circuits 1150_1 to 1150_m can perform word line undervoltage drive operations based on the interference margin of the selected word line. For example, word line undervoltage drive circuits 1150_1 to 1150_m can perform different word line undervoltage drive operations based on the row address RA of the word line selected from multiple word lines WL1 to WLm.

[0049] According to an example embodiment, word line undervoltage drive circuits 1150_1 to 1150_m can sequentially increase the width of the voltage drop across the selected word line based on the distance from the selected word line to the column decoder 1130 or the input / output circuit 1140. For example, in the example embodiment, word line undervoltage drive circuit 1150_1 may have the maximum resistance. Word line undervoltage drive circuit 1150_2 may have a smaller resistance than word line undervoltage drive circuit 1150_1. Word line undervoltage drive circuit 1150_k may have a smaller resistance than word line undervoltage drive circuit 1150_2. Word line undervoltage drive circuit 1150_k+1 may have a smaller resistance than word line undervoltage drive circuit 1150_k. Word line undervoltage drive circuit 1150_m may have a smaller resistance than word line undervoltage drive circuit 1150_k+1. Word line undervoltage drive circuit 1150_m may have the minimum resistance.

[0050] When the first word line WL1 is selected, the word line undervoltage drive circuit 1150_1 can set the first word line voltage VWL1 to the first word line voltage. When the second word line WL2 is selected, the word line undervoltage drive circuit 1150_2 can set the second word line voltage VWL2 to the second word line voltage. When the k-th word line WLk is selected, the word line undervoltage drive circuit 1150_k can set the k-th word line WLk to the third word line voltage VWL3 to the third word line voltage. When the (k+1)-th word line WLk+1 is selected, the word line undervoltage drive circuit 1150_k+1 can set the (k+1)-th word line WLk+1 to the fourth word line voltage VWL4 to the fourth word line voltage. When the m-th word line WLm is selected, the word line undervoltage drive circuit 1150_m can set the m-th word line WLm to the fifth word line voltage VWL5 to the fifth word line voltage.

[0051] The first word line WL1, furthest from the column decoder 1130 or input / output circuit 1140, can be set to the first word line voltage VWL1, i.e., the highest word line voltage among word line voltages VWL1 to VWL5. The second word line voltage VWL2 can be set lower than the first word line voltage VWL1. The third word line voltage VWL3 can be set lower than the second word line voltage VWL2. The fourth word line voltage VWL4 can be set lower than the third word line voltage VWL3. The fifth word line voltage VWL5 can be set lower than the fourth word line voltage VWL4. The m-th word line WLm, closest to the column decoder 1130 or input / output circuit 1140, can be set to the fifth word line voltage VWL5, i.e., the lowest word line voltage among word line voltages VWL1 to VWL5.

[0052] According to an example embodiment, for each group, word line undervoltage drive circuits 1150_1 to 1150_m may have the same resistance. For example, a first undervoltage drive group may include at least one word line undervoltage drive circuit including word line undervoltage drive circuit 1150_1. The at least one word line undervoltage drive circuit included in the first undervoltage drive group may have the largest resistance. A second undervoltage drive group may include at least one word line undervoltage drive circuit including word line undervoltage drive circuit 1150_k. The at least one word line undervoltage drive circuit included in the second undervoltage drive group may have a smaller resistance than that of the first undervoltage drive group. A third undervoltage drive group may include at least one word line undervoltage drive circuit including word line undervoltage drive circuit 1150_m. The at least one word line undervoltage drive circuit included in the third undervoltage drive group may have a smaller resistance than that of the second undervoltage drive group.

[0053] The number of word line undervoltage drive circuits included in one undervoltage drive group may differ from the number included in another undervoltage drive group. For example, a first undervoltage drive group may include word line undervoltage drive circuits 1150_1 and 1150_2, and a second undervoltage drive group may include word line undervoltage drive circuit 1150_k. In some example embodiments, the first undervoltage drive group may include a maximum number of word line undervoltage drive circuits. In some example embodiments, the second undervoltage drive group may include a maximum number of word line undervoltage drive circuits. In some example embodiments, the third undervoltage drive group may include a maximum number of word line undervoltage drive circuits.

[0054] The first undervoltage drive group, the second undervoltage drive group, and the third undervoltage drive group are exemplary, and the word line undervoltage drive circuits 1150_1 to 1150_m can be divided into at least two or more undervoltage drive groups. For example, the word line undervoltage drive circuits 1150_1 to 1150_m can be divided into two undervoltage drive groups. As another example, the word line undervoltage drive circuits 1150_1 to 1150_m can be divided into four or more undervoltage drive groups.

[0055] Figure 6 It shows Figure 5 A diagram of an example embodiment of the undervoltage drive circuit. Refer to... Figure 5 and Figure 6 The first undervoltage drive circuit 1150_a may be included in the first undervoltage drive group UDGa and may be connected to the first word line Wla. The second undervoltage drive circuit 1150_b may be included in the second undervoltage drive group UDGb and may be connected to the second word line WLb. The second word line WLb may be closer to the column decoder 1130 or the input / output circuit 1140 than the first word line WLa.

[0056] The first undervoltage drive circuit 1150_a may include a first transistor PMa driven by a bias voltage Vbias. The second undervoltage drive circuit 1150_b may include a second transistor PMb driven by a bias voltage Vbias. In some example embodiments, the capacitance of the first transistor PMa may be configured to be greater than the capacitance of the second transistor PMb.

[0057] When driven with the same bias voltage Vbias, the first transistor PMa can have a greater resistance than the second transistor PMb. Therefore, the first word line voltage VWLa can be configured to be higher than the second word line voltage VWLb.

[0058] Figure 7 It shows Figure 5 A diagram of an example embodiment of the undervoltage drive circuit. Refer to... Figure 5 and Figure 7 The first undervoltage drive circuit 1150_a may be included in the first undervoltage drive group UDGa and connected to the first word line WLa. The second undervoltage drive circuit 1150_b may be included in the second undervoltage drive group UDGb and connected to the second word line WLb. The second word line WLb may be closer to the column decoder 1130 or the input / output circuit 1140 than the first word line WLa.

[0059] The first undervoltage drive circuit 1150_a may include a transistor PM driven by a bias voltage Vbias and a first undervoltage drive resistor URa. The second undervoltage drive circuit 1150_b may include a transistor PM driven by a bias voltage Vbias and a second undervoltage drive resistor URb. The resistance value of the first undervoltage drive resistor URa may be configured to be greater than the resistance value of the second undervoltage drive resistor URb.

[0060] When driven by the same bias voltage Vbias, the first undervoltage drive resistor URa can have a greater voltage distribution effect than the second undervoltage drive resistor URb. Therefore, the first word line voltage VWLa can be formed to be higher than the second word line voltage VWLb.

[0061] Figure 9 It shows Figure 5 A diagram of an example embodiment of an undervoltage drive circuit. Refer to... Figure 5 and Figure 8 The first undervoltage drive circuit 1150_a may be included in the first undervoltage drive group UDGa and may be connected to the first word line WLa. The second undervoltage drive circuit 1150_b may be included in the second undervoltage drive group UDGb and may be connected to the second word line WLb. The second word line WLb may be closer to the column decoder 1130 or the input / output circuit 1140 than the first word line WLa.

[0062] The first undervoltage drive circuit 1150_a may be driven by a bias voltage Vbias and may include a plurality of transistors PM connected in series. The second undervoltage drive circuit 1150_b may include at least one transistor PM driven by the bias voltage Vbias. The first undervoltage drive circuit 1150_a may have more transistors PM connected in series than the second undervoltage drive circuit 1150_b. In an example embodiment, the second undervoltage drive circuit 1150_b may include a plurality of transistors PM connected in series and driven by the bias voltage Vbias, wherein the number of transistors PM in the second undervoltage drive circuit 1150_b is less than the number of transistors PM in the first undervoltage drive circuit 1150_a.

[0063] When driven by the same bias voltage Vbias, the first undervoltage drive circuit 1150_a can have a greater resistance than the second undervoltage drive circuit 1150_b. Therefore, the first word line voltage VWLa can be configured to be higher than the second word line voltage VWLb.

[0064] Figure 9 It shows Figure 5 A diagram of an example embodiment of the undervoltage drive circuit. Refer to... Figure 5 and Figure 9The first undervoltage drive circuit 1150_a may be included in the first undervoltage drive group UDGa and may be connected to the first word line WLa. The second undervoltage drive circuit 1150_b may be included in the second undervoltage drive group UDGb and may be connected to the second word line WLb. The second word line WLb may be closer to the column decoder 1130 or the input / output circuit 1140 than the first word line WLa.

[0065] The first undervoltage drive circuit 1150_a may include at least one transistor PM driven by a bias voltage Vbias. The second undervoltage drive circuit 1150_b may be driven by the bias voltage Vbias and may include a plurality of transistors PM connected in parallel. The second undervoltage drive circuit 1150_b may have more transistors PM connected in parallel than the first undervoltage drive circuit 1150_a. In an example embodiment, the first undervoltage drive circuit 1150_a may include a plurality of transistors PM connected in parallel and driven by the bias voltage Vbias, wherein the number of transistors PM in the first undervoltage drive circuit 1150_a is less than the number of transistors PM in the second undervoltage drive circuit 1150_b.

[0066] When driven by the same bias voltage Vbias, the first undervoltage drive circuit 1150_a can have a greater resistance than the second undervoltage drive circuit 1150_b. Therefore, the first word line voltage VWLa can be configured to be higher than the second word line voltage VWLb.

[0067] Figure 10 It shows Figure 4 A diagram of an example embodiment of the word line voltage generator 1150. (Refer to...) Figure 4 and Figure 10 The word line voltage generator 1150 may include auxiliary circuitry to prevent read interference. For example, the auxiliary circuitry may include word line undervoltage drive circuits WLUD1 to WLUDm. The word line undervoltage drive circuits WLUD1 to WLUDm may be connected to multiple word lines WL1 to WLm, respectively. The word line undervoltage drive circuits WLUD1 to WLUDm may have resistors of the same size.

[0068] Word line drivers WD1 to WDm can be connected to the grid ground terminal (hereinafter referred to as the grid ground terminal VSS_MESH). The first part of the word line undervoltage drive circuits WLUD1 to WLUDm can be directly connected to the grid ground terminal VSS_MESH. The second part of the word line undervoltage drive circuits WLUD1 to WLUDm can be connected to the grid ground terminal VSS_MESH via a resistor.

[0069] For example, such as Figure 10As shown in the example embodiment, the third word line undervoltage drive circuit WLUD3 to the m-th word line undervoltage drive circuit WLUDm can be directly connected to the grid ground terminal VSS_MESH. Therefore, the third word line WL3 to the m-th word line WLm can have the same word line voltage level when selected.

[0070] like Figure 10 As shown in the example embodiment, the second word line undervoltage drive circuit WLUD2 can be connected to the grid ground terminal VSS_MESH via the second metal resistor RM2. Therefore, the second word line WL2 can have a higher word line voltage level than the third word line WL3 when selected.

[0071] like Figure 10 As shown in the example embodiment, the first word line undervoltage drive circuit WLUD1 can be connected to the grid ground terminal VSS_MESH via a first metal resistor RM1 and a second metal resistor RM2 connected in series. Therefore, the first word line WL1 can have a higher word line voltage level than the second word line WL2 when selected.

[0072] Therefore, word lines located within a specific distance of the column decoder 1130 or the input / output circuit 1140 can be set to the same word line voltage level when selected. Word lines located outside the specific distance of the column decoder 1130 or the input / output circuit 1140 can be set to a higher word line voltage level when selected than word lines located within the specific distance.

[0073] In some example embodiments, the first metal resistor RM1 and the second metal resistor RM2 may have the same resistance value. Therefore, as the word line distance from the column decoder 1130 or the input / output circuit 1140 increases, the word line voltage level may increase sequentially.

[0074] In some example embodiments, the first metal resistor RM1 and the second metal resistor RM2 may have different resistance values. Therefore, as the word line distance from the column decoder 1130 or the input / output circuit 1140 increases, the word line voltage level may increase in response to the difference in resistance values ​​of the first metal resistor RM1 and the second metal resistor RM2.

[0075] Figure 11 This illustrates an example embodiment. Figure 10 A layout diagram of the word line voltage generator 1150. (Refer to...) Figure 10 and Figure 11 The word line voltage generator 1150 can be connected to the grid ground terminal VSS_MESH via a through-hole contact. Figure 11 In the diagram, solid lines can represent layers M1 or M3. Dashed lines can represent layers M2 or M4.

[0076] Storage devices (e.g., Figure 2 The memory device 1100 in the semiconductor chip can use via contacts to connect different metal layers. The via contact process can be performed according to the following steps: First, an interlayer insulating layer can be formed. An insulating layer can be formed between the metal layers to prevent electrical interference. Next, a via can be formed. A small hole can be formed in the insulating layer to create a via. Next, metal can be deposited. The via can be filled with metal to electrically connect the via contacts. For example, tungsten (W) or copper (Cu) can be used as the metal. Next, a planarization CMP operation can be performed. After filling with metal, the surface can be planarized and prepared for the next process step.

[0077] Word line drivers WD1 to WDm can be connected to the grid ground terminal VSS_MESH via the first metal wire ML1. The third word line undervoltage drive circuit WLUD3 to the m-th word line undervoltage drive circuit WLUDm can be connected to the grid ground terminal VSS_MESH via the second metal wire ML2.

[0078] With improvements in manufacturing processes, long metal wires can possess a resistive component. By omitting the via contact portion, a portion of the second metal wire ML2 can be left unconnected to the grid ground terminal VSS_MESH. A specific length of the second metal wire ML2 that is not connected to the grid ground terminal VSS_MESH can possess a resistive component. Therefore, the first metal resistor RM1 and the second metal resistor RM2 can be implemented using a portion of the second metal wire ML2.

[0079] The third word line undervoltage drive circuit WLUD3 to the m-th word line undervoltage drive circuit WLUDm can be directly connected to the grid ground terminal VSS_MESH. Therefore, the third word line WL3 to the m-th word line WLm can have the same word line voltage level when selected.

[0080] The second word line undervoltage drive circuit WLUD2 can be connected to the grid ground terminal VSS_MESH via the second metal resistor RM2. Therefore, the second word line WL2 can have a higher word line voltage level than the third word line WL3 when selected.

[0081] The first word line undervoltage drive circuit WLUD1 can be connected to the grid ground terminal VSS_MESH via a first metal resistor RM1 and a second metal resistor RM2 connected in series. Therefore, the first word line WL1 can have a higher word line voltage level than the second word line WL2 when selected.

[0082] According to this disclosure, errors in storage devices during read or write operations can be prevented in an energy-efficient manner.

[0083] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. A storage device, comprising: A storage cell array, comprising multiple storage cells; The line decoder is configured to select one word line from a plurality of word lines connected to the plurality of memory cells based on the address received from the memory controller. as well as A word line voltage generator is configured to provide word line voltage to the selected word line. The word line voltage generator includes: Multiple word line drivers, each corresponding to one of the multiple word lines; and Multiple word line undervoltage drive circuits, each corresponding to one of the multiple word lines, reduce the word line voltage level output by the multiple word line drivers to different voltage levels based on the address.

2. The storage device according to claim 1, further comprising: Input / output circuitry is configured to either input data into the memory cell array or output data from the memory cell array. The plurality of word lines include a first word line furthest from the input / output circuit and a second word line located between the first word line and the input / output circuit. The plurality of word line undervoltage drive circuits include: The first undervoltage driving circuit is configured to: reduce the first word line voltage level of the first word line to a first voltage level when the first word line is selected; and The second undervoltage driving circuit is configured to: when the second word line is selected, reduce the second word line voltage level of the second word line to a second voltage level, wherein the second voltage level is greater than the first voltage level.

3. The storage device according to claim 2, wherein, The first undervoltage drive circuit includes a first transistor having a first capacitor, the first transistor being connected between the first word line and a ground terminal, and being configured to be driven by a bias voltage; and The second undervoltage drive circuit includes a second transistor with a second capacitor smaller than the first capacitor. The second transistor is connected between the second word line and the ground terminal and is configured to be driven by the bias voltage.

4. The storage device according to claim 2, wherein, The first undervoltage drive circuit includes a first transistor, which is connected in series with a first resistor between the first word line and the ground terminal, and is driven based on a bias voltage. and The second undervoltage drive circuit includes a second transistor connected in series with a second resistor between the second word line and the ground terminal, and is driven based on the bias voltage. The second resistor has a second resistance value, which is less than the first resistance value of the first resistor.

5. The storage device according to claim 2, wherein, The first undervoltage drive circuit includes a plurality of transistors connected in series between the first word line and the ground terminal, and the first undervoltage drive circuit is configured to drive based on a bias voltage. The second undervoltage drive circuit includes at least one transistor connected in series between the second word line and the ground terminal, and the second undervoltage drive circuit is configured to drive based on the bias voltage. The number of transistors included in the first undervoltage driving circuit is greater than the number of at least one transistor included in the second undervoltage driving circuit.

6. The storage device according to claim 2, wherein, The second undervoltage drive circuit includes a plurality of transistors connected in parallel between the second word line and the ground terminal, and the second undervoltage drive circuit is configured to drive based on a bias voltage. The first undervoltage drive circuit includes at least one transistor connected in parallel between the first word line and the ground terminal, and the first undervoltage drive circuit is configured to drive based on the bias voltage. The number of transistors included in the second undervoltage driving circuit is greater than the number of transistors included in the first undervoltage driving circuit.

7. The storage device according to claim 1, wherein, The plurality of word line drivers are configured to connect to a grid ground terminal connected in a grid pattern, and A portion of the plurality of word line undervoltage drive circuits is configured to be connected to the grid ground terminal.

8. The storage device according to claim 7, wherein, One of the multiple word line undervoltage drive circuits is configured to be connected to the grid ground terminal via a first resistor.

9. The storage device according to claim 8, wherein, Another word line undervoltage drive circuit in the plurality of word line undervoltage drive circuits is configured to be connected to the grid ground terminal via a first resistor and a second resistor connected in series.

10. A storage device comprising: A storage cell array, comprising a first storage cell and a second storage cell; The line decoder is configured to select one word line from the first word line connected to the first memory cell and the second word line connected to the second memory cell, based on the address received from the memory controller. The first word line driver is configured to provide a word line voltage to the first word line when the first word line is selected; The second word line driver is configured to provide the word line voltage to the second word line when the second word line is selected; The first word line undervoltage drive circuit is configured to: reduce the voltage level of the first word line to a first voltage level when the first word line is selected; as well as The second word line undervoltage drive circuit is configured to: when the second word line is selected, reduce the voltage level of the second word line to a second voltage level, wherein the second voltage level is greater than the first voltage level.

11. The storage device of claim 10, further comprising: Input / output circuitry is configured to either input data into the memory cell array or output data from the memory cell array. The first word line is farther from the input / output circuit than the second word line.

12. The storage device according to claim 10, wherein, The second word line undervoltage drive circuit is directly connected to the grid ground terminal, which is connected in a grid pattern, and The first word line undervoltage drive circuit is connected to the grid ground terminal via a specific resistor.

13. The storage device according to claim 12, wherein, The specific resistor is configured to be implemented via a portion of the metal wire that forms the grid grounding terminal.

14. The storage device according to claim 10, wherein, The first word line undervoltage drive circuit is configured to form a first resistance between the first word line and the ground terminal, and The second word line undervoltage drive circuit is configured to form a second resistance between the second word line and the ground terminal, the second resistance being smaller than the first resistance.

15. The storage device according to claim 10, wherein, The first word line undervoltage drive circuit includes a first transistor located between the first word line and a ground terminal, and the first transistor has a first capacitor and is configured to be driven by a bias voltage; and The second word line undervoltage drive circuit includes a second transistor located between the second word line and the ground terminal, and the second transistor has a second capacitance smaller than the first capacitance and is configured to be driven by the bias voltage.

16. A storage device comprising: A storage cell array, comprising multiple storage cells; The line decoder is configured to select one word line from a plurality of word lines connected to the plurality of memory cells based on the address received from the memory controller. as well as A word line voltage generator is configured to provide different word line voltage levels to selected word lines based on the address.

17. The storage device according to claim 16, wherein, The plurality of word lines include a first word line connected to a first memory cell and a second word line connected to a second memory cell, and The word line voltage generator includes: The first word line driver is configured to provide a word line voltage to the first word line when the first word line is selected; The second word line driver is configured to provide the word line voltage to the second word line when the second word line is selected; The first word line undervoltage drive circuit is configured to: reduce the voltage level of the word line voltage of the first word line to a first voltage level when the first word line is selected; and The second word line undervoltage drive circuit is configured to: when the second word line is selected, reduce the voltage level of the word line voltage of the second word line to a second voltage level, wherein the second voltage level is greater than the first voltage level.

18. The storage device of claim 17, further comprising: The input / output circuitry is configured to either input data into the memory cell array or output data from the memory cell array. The first word line is farther from the input / output circuit than the second word line.

19. The storage device according to claim 17, wherein, The second word line undervoltage drive circuit is configured to be directly connected to the grid ground terminal connected in a grid pattern, and The first word line undervoltage drive circuit is configured to be connected to the grid ground terminal via a specific resistor.

20. The storage device according to claim 19, wherein, The specific resistor is configured to be implemented via a portion of the metal wire that forms the grid grounding terminal.

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