Memory cell and method of forming the same

Abstract

A memory cell and its formation method are disclosed. The memory cell includes: a substrate; a first memory structure and a second memory structure located on the substrate; a first drain region, a second drain region, and a common source region located within the substrate; a first bit line plug and a second bit line plug located on the substrate; both the first and second memory structures include: a word line gate and word line gate sidewalls; the projection of the bottom surface of the word line gate toward the substrate is within the projection range of the top surface of the word line gate toward the substrate, and the sidewall of the word line gate away from the common source region is recessed toward the direction closer to the common source region. By reducing the size of the bottom region of the word line gate, more formation space is provided for the word line gate sidewalls toward the direction closer to the word line gate, thereby increasing the thickness of the word line gate sidewalls located on the sidewalls of the bottom region of the word line gate. Without requiring changes to the word line gate sidewall process, the breakdown resistance of the word line gate sidewalls is improved, thereby increasing the breakdown voltage between the bit line plugs in the device structure and reducing leakage problems.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a memory cell and a method for forming the same. Background Technology

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: analog circuits, digital circuits, and mixed-signal circuits. Among these, memory is an important type of digital circuit. Within memory, flash memory has seen particularly rapid development in recent years. The main characteristics of flash memory are its ability to retain stored information for extended periods without power, along with advantages such as high integration density, fast storage speed, and ease of erasing and rewriting. Therefore, it has been widely used in microcomputers, automation control, and many other fields.

[0003] However, existing storage units still have many problems. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a memory cell and a method for forming the same, so as to reduce leakage current in the device structure.

[0005] To address the aforementioned problems, the present invention provides a memory cell comprising: a substrate; a first memory structure and a second memory structure located on the substrate; a first drain region, a second drain region, and a common source region located within the substrate, wherein the first drain region and the common source region are located on opposite sides of the first memory structure, the second drain region and the common source region are located on opposite sides of the second memory structure, and the common source region is located between the first memory structure and the second memory structure; a first bit line plug and a second bit line plug located on the substrate, wherein the first bit line plug is electrically connected to the first drain region, and the second bit line plug is electrically connected to the second drain region; wherein both the first memory structure and the second memory structure include: a word line grid located on the substrate, and a word line grid sidewall covering the sidewall of the word line grid away from the common source region; the projection of the bottom surface of the word line grid toward the substrate is within the projection range of the top surface of the word line grid toward the substrate, and the sidewall of the word line grid away from the common source region is recessed toward the direction close to the common source region.

[0006] Optionally, it further includes: an erase gate located on the substrate and between the first memory structure and the second memory structure; the erase gate is located on the common source region.

[0007] Optionally, both the first memory structure and the second memory structure further include: a floating gate located on the substrate, and a control gate located on the floating gate; the word line gate is located on the side of the floating gate and the control gate away from the common source region.

[0008] Optionally, it may also include a control gate dielectric layer located between the floating gate and the control gate.

[0009] Optionally, the control gate dielectric layer has a multilayer structure; the control gate dielectric layer includes: a first oxide layer, a nitride layer located on the first oxide layer, and a second oxide layer located on the nitride layer.

[0010] Optionally, the word line grid sidewall has a multi-layer structure.

[0011] Optionally, the material of the word line grid sidewalls includes silicon nitride and silicon oxide.

[0012] Optionally, it may also include: a metal contact layer located on the first drain region, the common source region and the second drain region.

[0013] Accordingly, the present invention also provides a method for forming a memory cell, comprising: providing a substrate; forming a first memory structure and a second memory structure on the substrate; forming a first drain region, a second drain region, and a common source region within the substrate, wherein the first drain region and the common source region are located on both sides of the first memory structure, the second drain region and the common source region are located on both sides of the second memory structure, and the common source region is located between the first memory structure and the second memory structure; forming a first bit line plug and a second bit line plug on the substrate, wherein the first bit line plug is electrically connected to the first drain region, and the second bit line plug is electrically connected to the second drain region; wherein forming the first memory structure and the second memory structure each comprises: forming a word line grid on the substrate, and a word line grid sidewall covering the sidewall of the word line grid away from the common source region; the projection of the bottom surface of the word line grid toward the substrate is located within the projection range of the top surface of the word line grid toward the substrate, and the sidewall of the word line grid away from the common source region is recessed toward the direction close to the common source region.

[0014] Optionally, the method for forming the word line grid on the substrate includes: forming a word line grid material layer on the substrate; performing a patterned etching process on the word line grid material layer to form an initial word line grid; and performing a side-pushing process on the sidewall of the initial word line grid away from the common source region to form the word line grid.

[0015] Optionally, the method for forming the initial word grid includes: forming a mask layer on the word grid material layer, the mask layer exposing a portion of the top surface of the word grid material layer; etching the word grid material layer using the mask layer as a mask until penetrating the word grid material layer to form the initial word grid.

[0016] Optionally, the process for side-pushing the sidewalls of the initial word grid includes a dry etching process.

[0017] Optionally, it further includes: forming an erase gate on the substrate, the erase gate being located between the first memory structure and the second memory structure, and the erase gate being located on the common source region.

[0018] Optionally, forming the first memory structure and the second memory structure further includes: forming a floating gate on the substrate; forming a control gate on the floating gate; and the word line gate being located on the side of the floating gate and the control gate away from the common source region.

[0019] Optionally, it may also include forming a control gate dielectric layer between the floating gate and the control gate.

[0020] Optionally, the control gate dielectric layer has a multilayer structure; the control gate dielectric layer includes: a first oxide layer, a nitride layer located on the first oxide layer, and a second oxide layer located on the nitride layer.

[0021] Optionally, the word line grid sidewall has a multi-layer structure.

[0022] Optionally, after forming the first drain region, the common source region, and the second drain region, the method further includes forming a metal contact layer on the first drain region, the common source region, and the second drain region.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] In the storage cell of the present invention, the projection of the bottom surface of the word line gate toward the substrate is located within the projection range of the top surface of the word line gate toward the substrate, and the sidewall of the word line gate away from the erase gate is recessed toward the erase gate. By reducing the size of the bottom region of the word line gate, more forming space is provided for the sidewall of the word line gate in the direction toward the word line gate, thereby increasing the thickness of the sidewall of the word line gate located on the sidewall of the bottom region of the word line gate, rather than increasing the thickness of the sidewall of the word line gate in the direction away from the word line gate. Without making any changes to the process related to the sidewall of the word line gate, the breakdown resistance of the sidewall of the word line gate is improved, thereby improving the breakdown voltage between the bit line plugs in the device structure and reducing leakage problems.

[0025] In the method for forming a memory cell according to the present invention, the projection of the bottom surface of the word line gate toward the substrate is located within the projection range of the top surface of the word line gate toward the substrate, and the sidewall of the word line gate away from the erase gate is recessed toward the direction closer to the erase gate. By reducing the size of the bottom region of the word line gate, more forming space is provided for the sidewall of the word line gate in the direction closer to the word line gate, thereby increasing the thickness of the sidewall of the word line gate located on the sidewall of the bottom region of the word line gate, rather than increasing the thickness of the sidewall of the word line gate in the direction away from the word line gate. Without making any changes to the process related to the sidewall of the word line gate, the breakdown resistance of the sidewall of the word line gate is improved, thereby improving the breakdown voltage between the bit line plugs in the device structure and reducing leakage problems. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a storage unit structure;

[0027] Figures 2 to 17 This is a schematic diagram of the structure of each step in the method for forming a storage unit in an embodiment of the present invention. Detailed Implementation

[0028] As described in the background section, existing storage units still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic diagram of a storage unit.

[0030] Please refer to Figure 1A memory cell includes: a substrate 100; a first memory structure T1 and a second memory structure T2 located on the substrate 100; an erase gate 101 located on the substrate 100 and between the first memory structure T1 and the second memory structure T2; a first drain region 102, a second drain region 103, and a common source region 104 located within the substrate 100, wherein the first drain region 102 and the common source region 104 are located on both sides of the first memory structure T1, the second drain region 103 and the common source region 104 are located on both sides of the second memory structure T2, and the common source region 104 is located between the first memory structure T1 and the second memory structure T2; and the erase gate 101... 01 is located on the common source region 104; a first bit line plug 105 and a second bit line plug 106 are located on the substrate 100, the first bit line plug 105 is electrically connected to the first drain region 102, and the second bit line plug 106 is electrically connected to the second drain region 103; wherein, the first memory structure T1 and the second memory structure T2 each include: a floating gate 107 located on the substrate 100, a control gate 108 located on the floating gate 107, a word line grid 109 located on the side of the floating gate 107 and the control gate 108 away from the erase gate 101, and a word line grid sidewall 110 covering the sidewall of the word line grid 109 away from the erase gate 101.

[0031] In this embodiment, leakage is likely to occur between the first bit line plug 105 and the second bit line plug 106. This is because the thickness of the word line grid sidewall 110 at the bottom region of the word line grid 109 is insufficient, causing the current loaded on the first bit line plug 105 to flow through the word line grid sidewall 110 of the first memory structure T1 to the word line grid 109, and then the current flows through the word line grid sidewall 110 of the second memory structure T2 to the second bit line plug 106.

[0032] However, due to limitations in the process architecture, the word line gate sidewall 110 cannot be directly thickened in the direction away from the word line gate 109. If the word line gate sidewall 110 is simply thickened, it will seriously affect process stability and device compatibility.

[0033] Based on this, the present invention provides a memory cell and a method for forming the same. The projection of the bottom surface of the word line gate toward the substrate is located within the projection range of the top surface of the word line gate toward the substrate, and the sidewall of the word line gate away from the erase gate is recessed toward the direction closer to the erase gate. By reducing the size of the bottom region of the word line gate, more forming space is provided for the sidewall of the word line gate in the direction closer to the word line gate, thereby increasing the thickness of the sidewall of the word line gate located on the sidewall of the bottom region of the word line gate, rather than increasing the thickness of the sidewall of the word line gate in the direction away from the word line gate. Without making any changes to the process related to the sidewall of the word line gate, the breakdown resistance of the sidewall of the word line gate is improved, thereby improving the breakdown voltage between the bit line plugs in the device structure and reducing leakage problems.

[0034] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 2 to 17 This is a schematic diagram of the structure of the storage unit and its formation method in an embodiment of the present invention.

[0036] Please refer to Figure 2 Substrate 200 is provided.

[0037] In this embodiment, the substrate 200 is made of silicon.

[0038] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0039] In other embodiments, the substrate may also be a silicon substrate on an insulator or a germanium substrate on an insulator.

[0040] After providing the substrate 200, a first memory structure and a second memory structure are formed on the substrate 200; a first drain region, a second drain region, and a common source region are formed within the substrate 200. For details of the formation process, please refer to [reference needed]. Figures 3 to 16 .

[0041] Please refer to Figure 3 A floating gate structure material layer 201 is formed on the substrate 200; a control gate structure material layer 202 is formed on the floating gate structure material layer 201.

[0042] In this embodiment, the floating gate structure material layer 201 is used to provide material for the subsequent formation of the floating gate structure; the control gate structure material layer 202 is used to provide material for the subsequent formation of the control gate structure.

[0043] In this embodiment, the floating gate structure material layer 201 includes: a floating gate dielectric material layer, and a floating gate material layer (not shown) located on the floating gate dielectric material layer.

[0044] In this embodiment, the material of the floating gate dielectric material layer is silicon oxide.

[0045] In this embodiment, the floating gate material layer is made of polycrystalline silicon.

[0046] In this embodiment, the control gate structure material layer 202 includes: a control gate dielectric material layer, and a control gate material layer (not shown) located on the control gate dielectric material layer.

[0047] In this embodiment, the control gate dielectric material layer has a multilayer structure; the control gate dielectric material layer includes: a first oxide material layer, a nitride material layer located on the first oxide material layer, and a second oxide material layer located on the nitride material layer.

[0048] In this embodiment, the control gate material layer is made of polycrystalline silicon.

[0049] Please refer to Figure 4 A first mask layer 203 is formed on the control gate structure material layer 202, and the first mask layer 203 has a mask opening 204 that exposes a portion of the top surface of the control gate structure material layer 202.

[0050] In this embodiment, the material of the first mask layer 203 needs to be different from the materials of the floating gate dielectric material layer and the control gate dielectric material layer; that is, the material of the first mask layer 203 can be silicon nitride.

[0051] Please refer to Figure 5 A first sidewall 205 is formed on the sidewall of the mask opening 204.

[0052] In this embodiment, the first sidewall 205 is used to define the position and size of the subsequently formed floating grid structure and the control grid structure.

[0053] Please refer to Figure 6 Using the first mask layer 203 and the first sidewall 205 as masks, the control gate structure material layer 202 and the floating gate structure material layer 201 are etched until the surface of the substrate 200 is exposed, forming the initial control gate structure 206 and the initial floating gate structure 207.

[0054] In this embodiment, etching the control gate structure material layer 202 specifically includes: etching the control gate material layer, the first oxide material layer, the nitride material layer, and the second oxide material layer; etching the floating gate structure material layer 201 specifically includes: etching the floating gate material layer and the floating gate dielectric material layer.

[0055] Please refer to Figure 7 After forming the initial control gate structure 206 and the initial floating gate structure 207, the substrate 200 is subjected to ion implantation using the first mask layer 203 and the first sidewall 205 as masks, thereby forming the common source region 208 within the substrate 200.

[0056] In this embodiment, the ions in the common source region 208 can be N-type ions or P-type ions.

[0057] Please continue to refer to this. Figure 7 In this embodiment, after the common source region 208 is formed, the common source region 208 is metallized so that a portion of the common source region 208 and the metal layer form a metal contact layer (not shown) after heat treatment, thereby reducing the contact resistance of the common source layer.

[0058] Please refer to Figure 8 After the initial control gate structure 206 and the initial floating gate structure 207 are formed, an erase gate dielectric layer 209 is formed on the sidewalls of the initial control gate structure 206 and the initial floating gate structure 207, as well as on the exposed surface of the substrate 200.

[0059] In this embodiment, the material of the erase gate dielectric layer 209 is silicon oxide.

[0060] Please refer to Figure 9 After the erase gate dielectric layer 209 is formed, an erase gate 210 is formed on the erase gate dielectric layer 209.

[0061] In this embodiment, the erase gate 210 is located on the common source region 208.

[0062] In this embodiment, the erase gate 210 is made of polycrystalline silicon.

[0063] Please refer to Figure 10 After the erase gate 210 is formed, the first mask layer 203 is removed; using the first sidewall 205 as a mask, the initial control gate structure 206 and the initial floating gate structure 207 are etched until the surface of the substrate 200 is exposed, thereby forming the control gate structure 211 and the floating gate structure 212.

[0064] In this embodiment, the floating gate structure 212 includes: a floating gate dielectric layer and a floating gate (not shown) located on the floating gate dielectric layer; the control gate structure 211 includes: a control gate dielectric layer and a control gate (not shown) located on the control gate dielectric layer. The control gate dielectric layer is a multilayer structure, comprising: a first oxide layer, a nitride layer located on the first oxide layer, and a second oxide layer located on the nitride layer.

[0065] Please refer to Figure 11 After the control gate structure 211 and the floating gate structure 212 are formed, a second sidewall 213 is formed on the control gate structure 211, the floating gate structure 212 and the sidewall of the first sidewall 205 away from the common source region 208.

[0066] In this embodiment, the second sidewall 213 is used to electrically isolate the subsequently formed word line grid from the control grid structure 211 and the floating grid structure 212, respectively.

[0067] Please refer to Figure 12 After the second sidewall 213 is formed, a word line gate dielectric material layer 214 is formed on the substrate 200; and a word line gate material layer 215 is formed on the word line gate dielectric material layer 214.

[0068] In this embodiment, the word line gate dielectric material layer 214 provides material for the subsequent formation of the word line gate dielectric layer, and the word line gate material layer 215 provides material for the subsequent formation of the word line gate.

[0069] In this embodiment, the word line gate dielectric material layer 214 is made of silicon oxide.

[0070] In this embodiment, the word line gate material layer 215 is made of polycrystalline silicon.

[0071] Please refer to Figure 13 The word line grid material layer 215 is patterned and etched to form the initial word line grid 216.

[0072] In this embodiment, the method for forming the initial word grid 216 includes: forming a mask layer (not shown) on the word grid material layer 215, the mask layer exposing a portion of the top surface of the word grid material layer 215; etching the word grid material layer 215 using the mask layer as a mask until penetrating the word grid material layer 215 to form the initial word grid 216.

[0073] In this embodiment, the method of etching the word line gate material layer 215 with the mask layer as a mask until penetrating the word line gate material layer 215 includes: etching the word line gate material layer 215 with the mask layer as a mask until the top surface of the word line gate dielectric material layer 214 is exposed.

[0074] Please refer to Figure 14 In forming the initial word line gate 216, ion implantation is performed into the substrate 200 using the initial word line gate 216 as a mask to form the first drain region 217 and the second drain region 218.

[0075] In this embodiment, the ions in the first drain region 217 and the second drain region 218 have the same electrical type as the ions in the common source region 208, that is, the ions in the first drain region 217 and the second drain region 218 can be N-type ions or P-type ions.

[0076] Please refer to Figure 15 After the first drain region 217 and the second drain region 218 are formed, the initial word line grid 216 is side-pushed away from the common source region 208 to form the word line grid 219.

[0077] In this embodiment, after the side-pushing process, the projection of the bottom surface of the word line grid 219 toward the substrate 200 is located within the projection range of the top surface of the word line grid 219 toward the substrate 200, and the sidewall of the word line grid 219 away from the common source region 208 is recessed toward the direction close to the common source region 208.

[0078] In this embodiment, the sidewall of the initial word line gate 216 is side-pushing processed using a dry etching process. By adjusting parameters such as the bias voltage and gas concentration in the dry etching process, the sidewall of the initial word line gate 216 can be side-pushing processed.

[0079] It should be noted that the dry etching process used in the side-pushing process needs to have a high etching selectivity, that is, it can only etch the initial word line gate 216, while minimizing the etching damage to the word line gate dielectric material layer 214.

[0080] Please refer to Figure 16 After the word grid 219 is formed, a word grid sidewall 220 is formed, which covers the sidewall of the word grid 219 away from the common source region 208.

[0081] Since the projection of the bottom surface of the word line gate 219 toward the substrate 200 is within the projection range of the top surface of the word line gate 219 toward the substrate 200, and the sidewall of the word line gate 219 away from the erase gate 210 is recessed toward the erase gate 210, by reducing the size of the bottom region of the word line gate 219, more forming space is provided for the word line gate sidewall 220 in the direction toward the word line gate 219, thereby increasing the thickness of the word line gate sidewall 220 located on the sidewall of the bottom region of the word line gate 219, rather than increasing the thickness of the word line gate sidewall 220 in the direction away from the word line gate 219. Without making any changes to the related processes of the word line gate sidewall 220, the breakdown resistance of the word line gate sidewall 220 is improved, thereby improving the breakdown voltage between the bit line plugs of the device structure (i.e., the first bit plug and the second bit plug formed subsequently) and reducing leakage problems.

[0082] In this embodiment, the word line grid sidewall 220 has a multi-layer structure; the material of the word line grid sidewall 220 includes silicon nitride and silicon oxide.

[0083] Thus, the first memory structure T1 and the second memory structure T2 are formed. Both the first memory structure T1 and the second memory structure T2 include: a word line gate 219 located on the substrate 200, and a word line gate sidewall 220 covering the sidewall of the word line gate 219 away from the common source region 208; a floating gate located on the substrate 200, and a control gate located on the floating gate; the word line gate 219 is located on the side of the floating gate and the control gate away from the common source region 208.

[0084] In this embodiment, the erase gate 210 is located between the first storage structure T1 and the second storage structure T2.

[0085] Please refer to Figure 17 After forming the word line grid sidewall 220, a first bit line plug 221 and a second bit line plug 222 are formed on the substrate 200. The first bit line plug 221 is electrically connected to the first drain area 217, and the second bit line plug 222 is electrically connected to the second drain area 218.

[0086] Please continue to refer to this. Figure 17In this embodiment, before forming the first bit line plug 221 and the second bit line plug 222, the word line gate dielectric material layer 214 located on the first drain region 217 and the second drain region 218 is etched to form the word line gate dielectric layer 223; the first drain region 217 and the second drain region 218 are metallized so that a portion of the first drain region 217 and the second drain region 218 and the metal layer form a metal contact layer (not shown) after heat treatment, so as to reduce the contact resistance of the first drain region 217 and the second drain region 218.

[0087] Accordingly, the present invention also provides a storage unit, please refer to the following: Figure 17 The system includes: a substrate 200; a first memory structure T1 and a second memory structure T2 located on the substrate 200; a first drain region 217, a second drain region 218, and a common source region 208 located within the substrate 200, wherein the first drain region 217 and the common source region 208 are located on both sides of the first memory structure T1, the second drain region 218 and the common source region 208 are located on both sides of the second memory structure T2, and the common source region 208 is located between the first memory structure T1 and the second memory structure T2; and a first bit line plug 221 and a second bit line plug 222 located on the substrate 200, wherein the first bit line plug 221... The first drain region 217 is electrically connected, and the second bit line plug 222 is electrically connected to the second drain region 218; wherein, both the first memory structure T1 and the second memory structure T2 include: a word line gate 219 located on the substrate 200, and a word line gate sidewall 220 covering the sidewall of the word line gate 219 away from the common source region 208; the projection of the bottom surface of the word line gate 219 toward the substrate 200 is located within the projection range of the top surface of the word line gate 219 toward the substrate 200, and the sidewall of the word line gate 219 away from the common source region 208 is recessed toward the direction close to the common source region 208.

[0088] The projection of the bottom surface of the word line gate 219 toward the substrate 200 is located within the projection range of the top surface of the word line gate 219 toward the substrate 200. The sidewall of the word line gate 219 away from the erase gate 210 is recessed toward the erase gate 210. By reducing the size of the bottom region of the word line gate 219, more forming space is provided for the word line gate sidewall 220 in the direction toward the word line gate 219, thereby increasing the thickness of the word line gate sidewall 220 located on the sidewall of the bottom region of the word line gate 219, rather than increasing the thickness of the word line gate sidewall 220 in the direction away from the word line gate 219. This improves the breakdown resistance of the word line gate sidewall 220 without requiring changes to the related processes, thereby increasing the breakdown voltage between bit line plugs in the device structure and reducing leakage problems.

[0089] In this embodiment, it further includes: an erase gate 210 located on the substrate 200 and between the first memory structure T1 and the second memory structure T2; the erase gate 210 is located on the common source region 208.

[0090] In this embodiment, both the first memory structure T1 and the second memory structure T2 further include: a floating gate located on the substrate 200 and a control gate located on the floating gate; the word line gate 219 is located on the side of the floating gate and the control gate away from the common source region 208.

[0091] In this embodiment, a control gate dielectric layer located between the floating gate and the control gate is also included.

[0092] In this embodiment, the control gate dielectric layer has a multilayer structure; the control gate dielectric layer includes: a first oxide layer, a nitride layer located on the first oxide layer, and a second oxide layer located on the nitride layer.

[0093] In this embodiment, the word line grid sidewall 220 has a multi-layer structure.

[0094] In this embodiment, the material of the word line grid sidewall 220 includes silicon nitride and silicon oxide.

[0095] In this embodiment, it further includes a metal contact layer located on the first drain region 217, the common source region 208 and the second drain region 218.

[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A storage unit, characterized in that, include: Substrate; A first storage structure and a second storage structure located on the substrate; A first drain region, a second drain region, and a common source region are located within the substrate. The first drain region and the common source region are located on both sides of the first memory structure, the second drain region and the common source region are located on both sides of the second memory structure, and the common source region is located between the first memory structure and the second memory structure. A first bit line plug and a second bit line plug are located on the substrate, the first bit line plug being electrically connected to the first drain region, and the second bit line plug being electrically connected to the second drain region; wherein, both the first memory structure and the second memory structure include: a word line grid located on the substrate, and a word line grid sidewall covering the sidewall of the word line grid away from the common source region; The projection of the bottom surface of the word line gate toward the substrate is within the projection range of the top surface of the word line gate toward the substrate, and the sidewall of the word line gate away from the common source region is recessed toward the direction close to the common source region.

2. The storage unit as claimed in claim 1, characterized in that, Also includes: An erase gate located on the substrate and between the first memory structure and the second memory structure; The erase gate is located on the common source region.

3. The storage unit as described in claim 1, characterized in that, Both the first memory structure and the second memory structure further include: a floating gate located on the substrate, and a control gate located on the floating gate; the word line gate is located on the side of the floating gate and the control gate away from the common source region.

4. The storage unit as described in claim 3, characterized in that, Also includes: A control gate dielectric layer located between the floating gate and the control gate.

5. The storage unit as described in claim 4, characterized in that, The control gate dielectric layer has a multilayer structure; the control gate dielectric layer includes: a first oxide layer, a nitride layer located on the first oxide layer, and a second oxide layer located on the nitride layer.

6. The storage unit as claimed in claim 1, characterized in that, The sidewalls of the character line grid have a multi-layered structure.

7. The storage unit as claimed in claim 6, characterized in that, The materials of the word grid sidewalls include silicon nitride and silicon oxide.

8. The storage unit as claimed in claim 1, characterized in that, Also includes: A metal contact layer located on the first drain region, the common source region, and the second drain region.

9. A method for forming a storage cell, characterized in that, include: Provide substrate; A first memory structure and a second memory structure are formed on the substrate; A first drain region, a second drain region, and a common source region are formed in the substrate. The first drain region and the common source region are located on both sides of the first memory structure, the second drain region and the common source region are located on both sides of the second memory structure, and the common source region is located between the first memory structure and the second memory structure. A first bit line plug and a second bit line plug are formed on the substrate. The first bit line plug is electrically connected to the first drain region, and the second bit line plug is electrically connected to the second drain region. The formation of the first memory structure and the second memory structure both include: forming a word line grid on the substrate, and a word line grid sidewall covering the sidewall of the word line grid away from the common source region. The projection of the bottom surface of the word line gate toward the substrate is within the projection range of the top surface of the word line gate toward the substrate, and the sidewall of the word line gate away from the common source region is recessed toward the direction close to the common source region.

10. The method for forming a memory cell as described in claim 9, characterized in that, The method of forming the word line grid on the substrate includes: forming a word line grid material layer on the substrate; performing a patterned etching process on the word line grid material layer to form an initial word line grid; and performing a side-pushing process on the sidewall of the initial word line grid away from the common source region to form the word line grid.

11. The method for forming a memory cell as described in claim 10, characterized in that, The method for forming the initial word grid includes: forming a mask layer on the word grid material layer, the mask layer exposing a portion of the top surface of the word grid material layer; etching the word grid material layer using the mask layer as a mask until penetrating the word grid material layer to form the initial word grid.

12. The method for forming a memory cell as described in claim 10, characterized in that, The process for side-pushing the sidewalls of the initial word line grid includes a dry etching process.

13. The method for forming a memory cell as described in claim 9, characterized in that, Also includes: An erase gate is formed on the substrate, the erase gate being located between the first memory structure and the second memory structure, and the erase gate being located on the common source region.

14. The method for forming a memory cell as described in claim 9, characterized in that, Forming the first memory structure and the second memory structure further includes: forming a floating gate on the substrate; forming a control gate on the floating gate; and the word line gate being located on the side of the floating gate and the control gate away from the common source region.

15. The method for forming a memory cell as described in claim 14, characterized in that, Also includes: A control gate dielectric layer is formed between the floating gate and the control gate.

16. The method for forming a memory cell as described in claim 15, characterized in that, The control gate dielectric layer has a multilayer structure; the control gate dielectric layer includes: a first oxide layer, a nitride layer located on the first oxide layer, and a second oxide layer located on the nitride layer.

17. The method for forming a memory cell as described in claim 9, characterized in that, The sidewalls of the character line grid have a multi-layered structure.

18. The method for forming a memory cell as described in claim 9, characterized in that, After forming the first drain region, the common source region, and the second drain region, the method further includes forming a metal contact layer on the first drain region, the common source region, and the second drain region.

Images