Memory device and method of making the same, memory system

Abstract

This disclosure provides a memory device, a method for fabricating the same, and a memory system. The semiconductor device includes: a channel layer, a first dielectric layer, and a gate layer stacked in a first direction; a bit line extending through the gate layer, the first dielectric layer, and the channel layer along the first direction; the channel layer being coupled to the bit line; a second dielectric layer located between the gate layer and the bit line; a first electrode layer and a second electrode layer located on opposite sides of the first dielectric layer in the first direction, the first electrode layer and the second electrode layer at least partially overlapping in the first direction; wherein the second electrode layer is coupled to the side of the channel layer away from the bit line.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory device and a method for manufacturing the same, as well as a memory system. Background Technology

[0002] Memory devices are storage equipment used to preserve information in modern information technology. Some semiconductor memories, including both non-volatile and volatile memories, have gradually become widely used products in the storage market due to their high storage density, controllable production costs, suitable read / write speeds, and retention characteristics. However, as people's requirements for storage devices continue to increase, there is still much room for improvement in storage devices and their manufacturing methods. Summary of the Invention

[0003] According to some aspects of embodiments of this disclosure, a memory device is provided, comprising: a channel layer, a first dielectric layer, and a gate layer stacked in a first direction; a bit line extending through the gate layer, the first dielectric layer, and the channel layer along the first direction; the channel layer being coupled to the bit line; a second dielectric layer located between the gate layer and the bit line; a first electrode layer and a second electrode layer located on opposite sides of the first dielectric layer in the first direction, the first electrode layer and the second electrode layer at least partially overlapping in the first direction; wherein the second electrode layer is coupled to the side of the channel layer away from the bit line.

[0004] In some embodiments, the second dielectric layer, the gate layer, and the channel layer extend along a second direction; the second direction intersects the first direction; the second dielectric layer surrounds the bit line, the gate layer surrounds the second dielectric layer, and the channel layer surrounds the bit line.

[0005] In some embodiments, the second electrode layer extends along the second direction and surrounds the channel layer.

[0006] In some embodiments, the memory device further includes: a third dielectric layer located between the first electrode layer and the gate layer; the first electrode layer and the gate layer are electrically isolated at least through the third dielectric layer; the second dielectric layer, the gate layer, the third dielectric layer, and the first electrode layer extend on a first plane, the first plane intersecting the first direction.

[0007] In some embodiments, the channel layer and the second electrode layer extend on a second plane, which intersects the first direction.

[0008] In some embodiments, the first dielectric layer extends between the first electrode layer and the second electrode layer along a second direction intersecting the first direction; the first electrode layer, the first dielectric layer, and the second electrode layer at least partially overlap in the first direction.

[0009] In some embodiments, the first electrode layer is located away from the bit line relative to the second electrode layer in the second direction.

[0010] In some embodiments, the portion of the gate layer surrounding the bit line has a first dimension in the second direction; the portion of the channel layer surrounding the bit line has a second dimension in the second direction; the first dimension is smaller than the second dimension.

[0011] In some embodiments, the bit line, the gate layer, and the third dielectric layer extend into the first electrode layer along a second direction, and the first electrode layer surrounds a portion of the gate layer on its side in the second direction; a portion of the gate layer overlaps with a portion of the first electrode layer in a third direction; the third direction intersects the second direction, and the plane formed by the third direction and the second direction intersects the first direction.

[0012] In some embodiments, the side of the first electrode layer in the second direction includes: a straight edge extending along the third direction and an arc-shaped edge; the arc-shaped edge is located between two adjacent straight edges in the third direction, and the two ends of the arc-shaped edge are respectively connected to the two straight edges; the arc-shaped edge surrounds a portion of the gate layer, and a notch between the two ends of the arc-shaped edge exposes the gate layer.

[0013] In some embodiments, a plurality of bit lines are disposed opposite to each other on both sides of the first electrode layer in the second direction, and the plurality of bit lines include a first bit line and a second bit line, wherein the first bit line and the second bit line are not aligned in the second direction.

[0014] In some embodiments, the memory device further includes: word lines located on both sides of the first electrode layer in the second direction; the word lines extending in a third direction and coupled to a plurality of the gate layers; the word lines being coupled to a portion of the gate layer exposed on the side of the first electrode layer.

[0015] In some embodiments, the memory device further includes: a fourth dielectric layer extending along the third direction and located between the first electrode layer and the word line; and a gate layer located between two adjacent fourth dielectric layers in the third direction.

[0016] In some embodiments, the material comprising the channel layer includes an amorphous oxide semiconductor material.

[0017] In some embodiments, the memory device includes: a transistor, including at least the gate layer, the first dielectric layer, and the channel layer; a plurality of the transistors are stacked in a first direction, and a bit line passes through the plurality of the gate layers, the plurality of the first dielectric layers, and the plurality of the channel layers along the first direction, and the bit line is coupled to the plurality of the channel layers.

[0018] According to some aspects of embodiments of this disclosure, a method for fabricating a storage device is provided, comprising: forming at least one stacked structure, the stacked structure comprising: a first dielectric material layer, a second dielectric material layer, a first dielectric layer, and a first conductive material layer stacked in a first direction; etching the first conductive material layer along a second direction to form a first gap extending along a third direction, the first gap exposing the first dielectric layer; the third direction intersecting the second direction, and a plane formed by the third direction and the second direction intersecting the first direction; forming a third dielectric material extending along the third direction within the first gap. The stack includes a first conductive material layer and a word line extending along the third direction; the third dielectric material layer is located between the first conductive material layer and the word line; an opening is formed through the stacked structure along the first direction; a portion of the first conductive material layer is removed through the opening to form a first electrode layer; a gate layer is formed on a first plane where the first conductive material layer is located, and the gate layer is coupled to the word line; a second electrode layer and a channel layer are formed on a second plane where the second dielectric material layer is located through the opening, and the channel layer is coupled to the second electrode layer; a bit line is formed in the opening, and the bit line is coupled to the channel layer.

[0019] In some embodiments, the method of forming the first void includes: etching the stacked structure to form a first trench through the stacked structure; the first trench extending along the third direction; and using the first trench to etch the first conductive material layer to form the first void.

[0020] In some embodiments, the method of forming the third dielectric material layer and the word line includes: filling the first void with dielectric material, etching away a portion of the dielectric material to form the third dielectric material layer, and forming the word line in the space released by removing the portion of the dielectric material.

[0021] In some embodiments, the manufacturing method further includes forming an isolation structure in the first trench.

[0022] In some embodiments, the method of forming the first electrode layer includes: etching a portion of the first conductive material layer through the opening to form a first cavity; the first cavity surrounds the opening, the first cavity communicates with the opening, and the bottom of the first cavity exposes the first dielectric layer; the remaining first conductive material layer forms the first electrode layer.

[0023] In some embodiments, the method of forming the gate layer includes: forming a third dielectric layer on a sidewall in the first cavity; etching away a portion of the third dielectric layer and a portion of the third dielectric material layer to form a second cavity exposing the word line; the sidewall of the second cavity is provided by the remaining third dielectric layer and the word line; forming the gate layer and the second dielectric layer on the sidewall of the second cavity; the gate layer surrounding the second dielectric layer.

[0024] In some embodiments, forming the second electrode layer and the channel layer includes: etching the second dielectric material layer through the opening to form a third cavity; exposing the first dielectric material layer in the third cavity; filling the third cavity with a conductive material and removing a portion of the conductive material to form the second electrode layer; forming the channel layer in the space of the third cavity released by removing a portion of the conductive material; the second electrode layer surrounding the channel layer and being coupled to the channel layer.

[0025] In some embodiments, the method of forming the bit line includes: etching away residual material in the opening, the residual material comprising at least the constituent material of the channel layer; and forming the bit line in the opening.

[0026] In some embodiments, the material comprising the channel layer includes an amorphous oxide semiconductor material.

[0027] According to some aspects of embodiments of the present disclosure, a memory system is provided, including: the memory device, and a memory controller coupled to the memory device and configured to control the memory device.

[0028] This disclosure provides a memory device comprising: a channel layer, a first dielectric layer, and a gate layer stacked in a first direction, including a bit line penetrating the gate layer, the first dielectric layer, and the channel layer along the first direction, the channel layer being coupled to the bit line; a second dielectric layer existing between the gate layer and the bit line, the second dielectric layer isolating the gate layer and the bit line; wherein at least the gate layer and the channel layer constitute a transistor, multiple gate layers and multiple channel layers are stacked in the first direction, the bit line penetrating the multiple gate layers and multiple channel layers in the first direction, the bit line being coupled to the multiple channel layers, thereby realizing the stacked arrangement of transistors in the first direction and coupling with the bit line, increasing the transistor integration density; the memory device further includes a first electrode layer and a second electrode layer, respectively located on opposite sides of the first dielectric layer in the first direction, the first electrode layer and the second electrode layer at least partially overlapping in the first direction to form a capacitor structure, the second electrode layer being coupled to the side of the channel layer away from the bit line; the capacitor structure is stacked in the first direction to increase the device integration density, and the selection and access of the capacitor structure coupled to the transistor can be realized by selecting and turning on the transistor. Attached Figure Description

[0029] Figure 1 This is a schematic diagram illustrating a storage array according to an exemplary embodiment;

[0030] Figures 2 to 6 This is a schematic diagram of a storage device according to an embodiment of the present disclosure;

[0031] Figure 7 This is a schematic flowchart illustrating a method for manufacturing a storage device according to an embodiment of the present disclosure;

[0032] Figures 8 to 23 This is a schematic diagram illustrating the fabrication of a storage device according to an embodiment of the present disclosure;

[0033] Figure 24 and Figure 25 This is a schematic diagram of an exemplary system according to an embodiment of the present disclosure. Detailed Implementation

[0034] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0035] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0040] Some storage devices, such as Dynamic Random Access Memory (DRAM), may include a storage array and peripheral circuitry. The peripheral circuitry can control the storage array and operate it to perform read, write, or refresh operations. The storage devices provided in the embodiments of this disclosure may be storage devices or part of a storage device. The storage device may be DRAM, or at least a portion of a DRAM storage device, or the storage device may include DRAM. The DRAM includes the storage devices of this disclosure and is applicable to DDR4 memory specifications, DDR5 memory specifications, double data rate synchronous dynamic random access memory, and LPDDR5 memory specifications, low power double data rate synchronous dynamic random access memory.

[0041] In DRAM, memory arrays can be arranged in rows and columns, allowing memory cells to be addressed by specifying their rows and columns. A memory array includes multiple word lines corresponding to rows and multiple bit lines corresponding to columns. The word lines and bit lines intersect; selecting the memory cell at the intersection of the selected word line and bit line selects it for read, write, or refresh operations. Figure 1As exemplified, the memory array may include multiple word lines WLn, WLn+1, WLn-1, and WLn-2, ​​and multiple bit lines BLn, BLn+1, BLn-1, and BLn-2, ​​with the word lines and bit lines intersecting. Memory cells within the memory array may include capacitors and transistors; a memory cell may include one transistor and one capacitor. The word lines may also be conductive structures such as gate layers, serving as the gates of transistors. One controlled terminal (source) of the transistor is coupled to one electrode of the capacitor, and the other controlled terminal (drain) of the transistor is coupled to the bit line. The other electrode of the capacitor may be grounded or have an additional voltage (such as Vcc / 2) applied to it. Figure 1 As shown, the memory cell array is arranged in an x-column, y-row configuration. The rows and columns can be perpendicular or not. The z-direction is either vertical or the thickness direction of the device, and can be the first direction in this embodiment. The xoy plane intersects with or is perpendicular to the z-direction, and the x-direction can be the second direction in this embodiment. The y-direction can be a third direction in this embodiment. The extension direction of word lines or rows can be parallel to the y-direction or at an angle to it. The extension direction of bit lines or columns can be parallel to the x-direction or at an angle to it. The orthographic projection of the word line onto the xoy plane is perpendicular to the orthographic projection of the bit line onto the xoy plane, or they may not be perpendicular but have an angle between them.

[0042] In some embodiments, during read or write operations, a word line selection signal can be used to select the corresponding word line, and a column selection signal can be used to select the corresponding bit line. Simultaneous selection of the word line and bit line allows location of the selected memory cell. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, thereby enabling read, write, or refresh operations on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures.

[0043] In some embodiments, a capacitor represents a logical 1 or 0 by the amount of charge stored within it, or by the voltage difference across its terminals. A voltage signal on the word line is applied to the gate to control the transistor's on or off state, thus selecting or deselecting the capacitor. This allows data stored in the capacitor to be read via the bit line, or data to be written to the capacitor for storage via the bit line.

[0044] In some embodiments, the DRAM memory device or DRAM memory apparatus further includes... Figure 1Peripheral circuitry coupled to the memory array. Exemplary examples of peripheral circuitry may include, but are not limited to: a sensing amplifier circuit, a row decoding circuit, a column decoding circuit, and a voltage generation circuit. The sensing amplifier circuit is coupled to bit lines and can be configured to capture weak voltage fluctuations on the bit lines and locally reconstruct the capacitor voltage of the memory cell based on the voltage fluctuations. The sensing amplifier circuit may include a latch to latch the reconstructed capacitor voltage value, thereby transferring the information stored in the memory cell from the capacitor to the amplifier circuit. The sensing amplifier circuit may include a differential sensing amplifier circuit coupled to two bit lines, operating using a selected bit line and a complementary bit line used as a reference line to detect and amplify the voltage difference between a pair of bit lines. The row decoding circuit is configured to address the memory array and apply an operating voltage to the word lines. The column decoding circuit is configured to column address the memory array, apply a bit line voltage, or receive a bit line voltage. The voltage generation circuit generates the required high and low voltages for each device.

[0045] In some embodiments, the peripheral circuit may include a CMOS structure or CMOS circuit, including digital or analog circuits composed of transistors, for controlling the memory array or powering the memory array. Increasing the device integration of the peripheral circuit is beneficial to increasing the overall integration of the memory device, and improving the stability of the peripheral circuit devices is beneficial to improving the operational stability of the memory device.

[0046] In some embodiments, multiple storage units can Figure 1 The example illustrates an array arrangement on the xoy plane. Specific transistors can be arrayed on an xoy plane, and capacitor structures can be arranged on the plane containing the transistors. Capacitors can also be arranged on a plane above or below the transistor plane. Word lines and bit lines extend and intersect on the xoy plane, facilitating memory cell addressing. However, due to limitations in the arrangement of word lines and bit lines on the same film layer or plane, the transistor array and capacitor array require a large device area. According to some aspects of embodiments of this disclosure, a memory device is provided that allows bit lines and word lines to be arranged on intersecting or perpendicular planes, enabling transistor stacking in the device thickness direction, reducing the horizontal device area occupied by the memory device, and increasing device integration density.

[0047] In some embodiments, Figure 2 as well as Figure 3 A schematic diagram of storage device 10 is provided; for example... Figure 3 A three-dimensional schematic diagram of a storage device 10 is provided. Figure 2 It can be Figure 3 A schematic cross-sectional view of the storage device 10 at AA' on the xoz plane. (Refer to...) Figure 2 As shown, the storage device 10 may include:

[0048] A channel layer 111, a first dielectric layer 112, and a gate layer 113 are stacked in a first direction (z direction); a bit line 101 extends through the gate layer 113, the first dielectric layer 112, and the channel layer 111 along the z direction; the channel layer 111 is coupled to the bit line 101; a second dielectric layer 121 is located between the gate layer 113 and the bit line 101; it also includes a first electrode layer 131 and a second electrode layer 132, the first electrode layer 131 and the second electrode layer 132 are respectively located on opposite sides of the first dielectric layer 112 in the z direction, and the first electrode layer 131 and the second electrode layer 132 at least partially overlap in the z direction; wherein the second electrode layer 132 is coupled to the side of the channel layer 111 away from the bit line 101.

[0049] Reference Figure 2 As shown, a channel layer 111, a first dielectric layer 112, and a gate layer 113 can form a stacked structure 100 in the z direction; the stacked structure 100 also includes other film layer structures, such as a first electrode layer 131 that is insulated from and spaced apart from the gate layer 113, a second electrode layer 132 coupled to the channel layer 111, and a second dielectric layer 121 located between the gate layer 113 and the bit line 101. Figure 2 The memory device 10 may include multiple stacked structures 100 in the z-direction, with adjacent stacked structures 100 isolated by a dielectric material. The memory device 10 may include transistors 110, each transistor 110 including at least: a channel layer 111, a first dielectric layer 112, and a gate layer 113 in one of the stacked structures 100. Specifically, it may include a portion of the first dielectric layer 112 overlapping the gate layer 113 and the channel layer 111. The gate layer 113 serves as the control gate of the transistor 110, and the first dielectric layer 112 serves as the gate dielectric layer. The gate layer 113 is configured to apply different voltages to control the conduction and shutdown of the transistor 110. Corresponding to the stacked arrangement of multiple stacked structures 100, the memory device 10 may include multiple transistors 110 stacked in the z-direction, or an array of multiple stacked transistors 110. Figure 2 The three-layer transistor 110 stacked in the z-direction shown is merely an example; stacks of more transistor 110 layers are possible, and the number and arrangement of each transistor 110 layer are not limited. Bit lines 101 extend along the z-direction, penetrating the stacked structure 100 and the transistor 110. Bit lines 101 can directly contact and couple with the channel layer 111. Bit lines 101 can be isolated from the gate layer 113 through a second dielectric layer 121 to reduce leakage current. The second dielectric layer 121 is located between the gate layer 113 and the bit line 101. Bit lines 101 can penetrate multiple stacked structures 100 in the z-direction and can couple with multiple channel layers 111.

[0050] Reference Figure 2 As shown, the first electrode layer 131 and the second electrode layer 132 can be located on the upper and lower sides of the first dielectric layer 112 in the z-direction, respectively, and are electrically isolated by the first dielectric layer 112. The first electrode layer 131 and the second electrode layer 132 have overlapping regions in the z-direction to form a capacitor structure, that is, the orthographic projection of the first electrode layer 131 in the z-direction and the orthographic projection of the second electrode layer 132 in the z-direction at least partially overlap. The first dielectric layer 112 can serve as the capacitor dielectric of the capacitor structure, and the second electrode layer 132 is coupled to the side of the channel layer 111 away from the bit line 101. The size of the first electrode layer 131 in the x-direction can be equal to or unequal to the size of the second electrode layer 132 in the x-direction, and one side of the first electrode layer 131 in the x-direction can be aligned or misaligned with one side of the second electrode layer 132 in the x-direction. The first dielectric layer 112 can serve as the gate dielectric layer of the transistor 110 and also as the capacitor dielectric of the capacitor structure, which is beneficial to improving the device integration density.

[0051] In some specific embodiments, Figure 2 The transistor 110 and capacitor structure illustrated herein can constitute a memory cell, such as a DRAM memory cell. The capacitor structure can be replaced with other memory structures, including but not limited to phase-change memory structures, resistive-change memory structures, or magnetic-change memory structures. For example, bit line 101 is coupled to multiple stacked channel layers 111 in the z-direction. The end of a channel layer 111 away from bit line 101 is coupled to a second electrode layer 132. A corresponding channel layer 111 can be selected by selecting gate layer 113 and bit line 101, i.e., selecting a transistor 110 whose gate layer 113 is coupled to both bit line 101. Applying a conduction voltage to gate layer 113 turns on the corresponding channel layer 111, thus selecting the second electrode layer 132 coupled to that channel layer 111. The first electrode layer 131 can be grounded or have other voltages (such as Vcc / 2) applied, thereby accessing the corresponding capacitor structure. Read, write, or refresh operations can be performed on the selected memory cell.

[0052] In some embodiments, refer to Figure 3 As shown, to facilitate the explanation of the planar structure of each film layer, a partial cross-sectional view of a portion of the device structure is provided. Figure 3 Step structures do not actually exist. Figure 2 The topmost structure in the example includes a gate layer 113 and a second dielectric layer 121. Figure 3 The corresponding top-level structure is shown below. Figure 2 The example of the bottom or intermediate layer structure includes the channel layer 111 and the second electrode layer 132. Figure 3 The corresponding intermediate layer cross-section is shown in the middle section; Figure 3The illustrated structure does not limit the number of film layers stacked in the stacked structure 100 of this disclosure embodiment. To increase the integration density of the memory device 10 in the horizontal direction, such as the x-direction and / or y-direction, multiple transistors 110 can be arranged on the xoy plane to form a transistor array 110. The multilayer transistor array 110 is stacked in the z-direction, and the bit line 101 is coupled to the multilayer transistors 110 in the z-direction, specifically coupled to the multilayer channel layer 111. The multiple transistors 110 coupled to a bit line 101 and the coupled capacitor structure can be referred to as a memory cell string, and the memory device 10 may include an array of memory cell strings. For example, refer to Figure 3 As shown, multiple strings of memory cells are arranged along the y-direction to form columns. Two columns of memory cells are used as an example; however, this embodiment may include more columns of memory cells, which can form a memory array. The memory device 10 also includes an isolation structure 141 extending along the y-direction. The isolation structure 141 may be located on both sides of the memory device 10 in the x-direction. At least a portion of the memory cell strings or memory array may be located between two adjacent isolation structures 141. The isolation structure 141 is used to support the memory array or to insulate and isolate multiple memory arrays. Multiple bit lines 101 may be arranged in columns along the y-direction, with multiple columns of bit lines 101 between the isolation structures 141. The bit lines 101 in adjacent columns are staggered, and the bit lines 101 in adjacent columns are not aligned in the x-direction to reduce device area and increase device integration.

[0053] In some embodiments, refer to Figure 2 and Figure 3 As shown, the second dielectric layer 121, gate layer 113, and channel layer 111 extend along the x-direction; the x-direction intersects the z-direction; the second dielectric layer 121 surrounds the bit line 101, the gate layer 113 surrounds the second dielectric layer 121, and the channel layer 111 surrounds the bit line 101. The second dielectric layer 121, gate layer 113, and channel layer 111 may extend parallel to the xoy plane; the second dielectric layer 121 and gate layer 113 may be located in the same film layer or the same plane, above the first dielectric layer 112, and the channel layer 111 is located in a film layer or plane below the first dielectric layer 112. The gate layer 113 surrounding the bit line 101, the annular first dielectric layer 112, and the annular channel layer 111 provided in this embodiment are located in planes with different film layer heights, which can realize the stacking of multilayer transistors 110 in the z-direction and their coupling by the bit line 101, and improve the integration density of the device.

[0054] In some embodiments, the memory device 10 further includes: a third dielectric layer 122 located between the first electrode layer 131 and the gate layer 113; the first electrode layer 131 and the gate layer 113 are electrically isolated at least by the third dielectric layer 122; the third dielectric layer 122 may partially surround the gate layer 113 in a lateral direction perpendicular to the z-direction, and a portion of the gate layer 113 may be exposed from the third dielectric layer 122 for conduction; the second dielectric layer 121, the gate layer 113, the third dielectric layer 122, and the first electrode layer 131 may be located in the same film layer; the second dielectric layer 121, the gate layer 113, the third dielectric layer 122, and the first electrode layer 131 extend on a first plane, the first plane intersects the z-direction, the first plane is parallel to the xoy plane, and is located above the first dielectric layer 112.

[0055] In some embodiments, the second electrode layer 132 extends along the x-direction and surrounds the channel layer 111. In some embodiments, the channel layer 111 and the second electrode layer 132 may be located in the same film layer, the channel layer 111 and the second electrode layer 132 extend on a second plane, the second plane intersects the z-direction, the second plane is parallel to the xoy plane, and is located below the first dielectric layer 112.

[0056] In some embodiments, bit line 101 extends along the z-direction, and the cross-sectional shape of bit line 101 in the xoy plane may include: a circle, an ellipse, or other regular or irregular arcs; it may also include a rectangle, a triangle, or other regular or irregular polygons; or it may include regular or irregular shapes composed of arcs and straight lines. Figure 3 The circles or ovals shown are for illustrative purposes only. (See also...) Figure 3 As shown, to increase the integration density of the device, a channel layer 111, which surrounds the bit line 101 laterally and is contacted and coupled to the bit line 101, and a second electrode layer 132, which surrounds the channel layer 111 and is contacted and coupled to the channel layer 111, can be formed on the same film layer parallel to the xoy plane. A first dielectric layer 112 is formed on the film layer containing the second electrode layer 132 and the channel layer 111. On the first dielectric layer 112, on the same film layer parallel to the xoy plane, there are: a second dielectric layer 121 surrounding the bit line 101 in a transverse direction perpendicular to the z direction, a gate layer 113 surrounding the second dielectric layer 121, and a third dielectric layer 122 surrounding a portion of the gate layer 113. A portion of the gate layer 113 can leak out from the third dielectric layer 122 to contact a conductive structure, such as being coupled to the word line 133. A first electrode layer 131 can surround a portion of the gate layer 113 and the third dielectric layer 122 in a transverse direction perpendicular to the z direction. The third dielectric layer 122 is located between the first electrode layer 131 and the gate layer 113 for isolation.

[0057] Reference Figure 3As shown, in order to increase the area of ​​the first electrode layer 131 and thus increase the overlap area of ​​the first electrode layer 131 and the second electrode layer 132 in the z direction, thereby increasing the effective capacitance area of ​​the capacitor structure, the bit line 101, the second dielectric layer 121, the gate layer 113, and the third dielectric layer 122 can be embedded in the first electrode layer 131; or after forming the bit line 101, the second dielectric layer 121, the gate layer 113, the third dielectric layer 122, and other film layer structures, the remaining area on the same film layer surface can be used to form the first electrode layer 131, which can make the first electrode layer 131 have an irregular shape.

[0058] In some embodiments, refer to Figure 3 As shown, a conductive structure extending along the y-direction can be provided to connect multiple annular gate layers 113 arranged along the y-direction, such as two word lines 133 extending along the y-direction. The gate layer 113 is exposed from an annular third dielectric layer 122 with an opening and coupled to the word line 133. Bit line 101, second dielectric layer 121, gate layer 113, and third dielectric layer 122 are formed in the region between the two word lines 133. A fourth dielectric layer 123 extending along the y-direction is formed on the inner side of the two word lines 133. A first electrode layer 131 is provided in the remaining region between the two word lines 133 to increase the area of ​​the first electrode layer 131. The shape of the first electrode layer 131 may include an irregular pattern composed of arcs and straight lines. The fourth dielectric layer 123 may be made of the same material as the third dielectric layer 122 and may not have a physical boundary when in contact, such as including silicon oxide.

[0059] For example, the materials used to form the first dielectric layer 112, the second dielectric layer 121, the third dielectric layer 122, and the fourth dielectric layer 123 may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide; the constituent materials may be the same or different. The materials used to form the bit line 101, the gate layer 113, the word line 133, the first electrode layer 131, and the second electrode layer 132 may include conductive materials such as tungsten, copper, aluminum, chromium, nickel, titanium, cobalt, gold, silver, and platinum; the constituent materials may be the same or different.

[0060] The channel layer 111 may include a semiconductor material, which may include any semiconductor material within the art, including but not limited to: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art; for example, single-crystal silicon, polycrystalline silicon, germanium, silicon carbide, etc. Alternatively, it may include amorphous oxide semiconductor materials, including but not limited to IGZO materials. IGZO materials may be composed of oxides of elements such as indium, gallium, and zinc, exhibiting superior semiconductor properties. The addition of indium and gallium can improve the electron mobility of the semiconductor material, achieving lower operating voltage and lower power consumption compared to traditional semiconductor materials such as silicon; the introduction of zinc helps improve the stability of the semiconductor material. IGZO materials can be used to deposit and fabricate the channel layer 111. The film thickness, crystal form, and film morphology of the channel layer 111 can be controlled by controlling the deposition process parameters, improving the fabrication yield of the channel layer 111 while simplifying the fabrication process.

[0061] In some embodiments, refer to Figure 2 As shown, the first dielectric layer 112 extends between the first electrode layer 131 and the second electrode layer 132 along the x direction, which intersects the z direction; the first electrode layer 131, the first dielectric layer 112 and the second electrode layer 132 at least partially overlap in the z direction. The first dielectric layer 112 can serve as the gate dielectric layer of the transistor 110 to electrically isolate the gate layer 113 and the channel layer 111 in the z-direction. The first dielectric layer 112 can also serve as the capacitor dielectric of the capacitor structure. The first dielectric layer 112 can cover the entire area of ​​the channel layer 111 and can support the entire area of ​​the gate layer 113, providing better electrical isolation between the gate layer 113 and the channel layer 111 and reducing leakage current between them. The first dielectric layer 112 can extend between the first electrode layer 131 and the second electrode layer 132, extending only between the overlapping areas of the first electrode layer 131 and the second electrode layer 132, or the first electrode layer 131 can serve as a continuous film layer covering the entire second electrode layer 132 and the channel layer 111. Figure 4 As shown, the first dielectric layer 112 extends between the planes between BB' and CC'. The first dielectric layer 112 may include a high dielectric constant material such as hafnium oxide. For example, the first dielectric layer 112 covers the film layer containing the second electrode layer 132 and the channel layer 111. The film layer containing the second electrode layer 132, the gate layer 113, and the word line 133 is located on the first dielectric layer 112.

[0062] In some embodiments, refer to Figure 2As shown, the first electrode layer 131 is farther away from the bit line 101 in the x-direction relative to the second electrode layer 132. For example, taking the first end of the first electrode layer 131 near the bit line 101 and the first end of the second electrode layer 132 near the bit line 101 as references, the first end of the second electrode layer 132 is coupled to the channel layer 111; the first end of the first electrode layer 131 is farther away from the bit line 101 in the x-direction relative to the first end of the second electrode layer 132. The first end of the first electrode layer 131 is closer to the first end of the gate layer 113 in the x-direction, and is farther away from the channel layer 111 in the x-direction relative to the first end of the second electrode layer 132. Figure 2 The side of the first electrode layer 131 near the bit line 101 shown may be aligned or not aligned with the side of the second electrode layer 132 near the bit line 101; if the side of the first electrode layer 131 near the bit line 101 is not aligned with the side of the second electrode layer 132 near the bit line 101, the side of the first electrode layer 131 near the bit line 101 is farther away from the bit line 101 or farther away from the channel layer 111 than the second electrode layer 132.

[0063] In some embodiments, refer to Figure 2 As shown, the portion of the gate layer surrounding the bit line 101 has a first dimension D1 in the x-direction; the portion of the channel layer 111 surrounding the bit line 101 has a second dimension D2 in the x-direction; the first dimension D1 is smaller than the second dimension D2. The gate layer 113 may cover the entire region or a portion of the channel layer 111 in the z-direction, such as... Figure 2 The width D2 of the channel layer 111 in the x direction shown in the example is greater than the width D1 of the gate layer 113 (excluding the word line 133 extending along the y direction) in the x direction; this reduces leakage caused by the channel layer 111 being too short; the width D2 of the annular channel layer 111 in the x direction does not include the inner ring dimension of the annular channel layer 111.

[0064] In some embodiments, refer to Figure 2 and Figure 3 As shown, the width D3 of the annular second electrode layer 132 along the x-direction can be less than or equal to the width D2 of the annular channel layer 111; the width D3 of the second electrode layer 132 does not include the inner ring dimension. In some other embodiments, Figure 4 It can be Figure 3 Another schematic diagram of the cross-section of the intermediate storage device 10 at AA', see reference. Figure 4 As shown, the width D3 of the second electrode layer 132 can be greater than the width D2 of the channel layer 111.

[0065] In some embodiments, Figure 5 as well as Figure 6 Show respectively Figure 4 A cross-sectional schematic diagram of the storage device 10 at BB' and CC' in the xoy plane; Figure 5 and Figure 6 The cross-sectional views shown belong to the upper and lower film structures of the first dielectric layer 112.

[0066] In some embodiments, refer to Figure 5 As shown, bit line 101, gate layer 113, and third dielectric layer 122 extend into first electrode layer 131 along the x-direction. The first electrode layer 131 surrounds a portion of the gate layer 113 on its side in the x-direction. A portion of the gate layer 113 overlaps with a portion of the first electrode layer 131 in the y-direction. The y-direction intersects the x-direction, and the plane formed by the y-direction and x-direction intersects and is perpendicular to the z-direction. Bit line 101, gate layer 113, second dielectric layer 121, and third dielectric layer 122 are embedded in the first electrode layer 131. The first electrode layer 131 surrounds a portion of the bit line 101, gate layer 113, second dielectric layer 121, and third dielectric layer 122, but not completely. A portion of the gate layer 113 is exposed from the third dielectric layer 122 and also from the first electrode layer 131, for coupling with the bit line 101 on one side of the first electrode layer 131 in the x-direction. Bit line 101, ring gate layer 113, ring second dielectric layer 121 and ring third dielectric layer 122 with opening may be located in the edge region of the first electrode layer 131 and partially surrounded by the side of the first electrode layer 131. The side of the first electrode layer 131 has a notch 1313 instead of completely surrounding the gate layer 113 and other film layer structures.

[0067] In some embodiments, the shape of the first electrode layer 131 may include a shape formed by connecting arcs and straight lines, such as a shape left after two opposite sides of a rectangle are penetrated by circular openings. Figure 5 An enlarged schematic diagram of a portion of the first electrode layer 131 is also shown. (Refer to...) Figure 5 As shown, the first electrode layer 131 includes a straight edge 1311 extending along the y direction and an arc-shaped edge 1312 on its side in the x direction. The arc-shaped edge 1312 is located between two adjacent straight edges 1311 in the y direction, and its two ends are connected to the two straight edges 1311 respectively. The arc-shaped edge 1312 surrounds a portion of the gate layer 113, and the gap 1313 between the two ends of the arc-shaped edge 1312 exposes the gate layer 113.

[0068] In some embodiments, refer to Figure 5 As shown, the memory device 10 further includes: word lines 133 located on both sides of the first electrode layer 131 in the x direction; word lines 133 extending in the y direction and coupled to a plurality of gate layers 113; word lines 133 and the exposed portions of gate layers 113 on the side of the first electrode layer 131 are coupled.

[0069] In some embodiments, refer to Figure 5As shown, the memory device 10 further includes: a fourth dielectric layer 123 extending along the y direction and located between the first electrode layer 131 and the word line 133, for electrically isolating the first electrode layer 131 and the word line 133; and a gate layer 113 located between two adjacent fourth dielectric layers 123 in the y direction.

[0070] For example, word lines 133 extending along the y-direction can be provided to connect multiple annular gate layers 113 arranged along the y-direction, such as two word lines 133 extending along the y-direction. The gate layer 113 is exposed from an annular third dielectric layer 122 with an opening, and the gate layer 113 is also exposed from the side of the first electrode layer 131. The gate layer 113 is coupled to the word line 133. Bit line 101, second dielectric layer 121, gate layer 113, and third dielectric layer 122 are formed in the region between the two word lines 133. A fourth dielectric layer 123 extending along the y-direction is provided on the inner side of the two word lines 133. The remaining region between the two word lines 133 is provided with a first electrode layer 131 to increase the area of ​​the first electrode layer 131. The shape of the first electrode layer 131 may include an arc shape and an irregular pattern composed of straight lines. The fourth dielectric layer 123 may be made of the same material as the third dielectric layer 122 and may not have a physical boundary when in contact, such as including silicon oxide. The word line 133 and the gate layer 113 may be made of the same or different materials.

[0071] For example, bit line 101 is coupled to multiple stacked channel layers 111 in the z-direction, and the end of channel layer 111 away from bit line 101 is coupled to second electrode layer 132; word line 133 is coupled to multiple gate layers 113 in the y-direction; the corresponding channel layer 111 can be selected by selecting word line 133 and bit line 101, that is, the transistors 110 whose gate layers 113 are all coupled to bit line 101 can be selected. Applying a conduction voltage to the corresponding gate layer 113 through word line 133 can select the second electrode layer 132 coupled to the channel layer 111. The first electrode layer 131 can be grounded or other voltages (such as Vcc / 2) can be applied to it, thereby accessing the corresponding capacitor structure; read, write or refresh operations can be performed on the selected memory cell.

[0072] In some embodiments, refer to Figure 5 and Figure 6As shown, multiple bit lines 101 are arranged opposite each other on both sides of the first electrode layer 131 in the x-direction. The multiple bit lines 101 include a first bit line 101a and a second bit line 101b, which are not aligned in the x-direction. Based on the circular, elliptical, or other arc-shaped cross-section of the bit lines 101, the bit lines 101 can be staggered; for example, multiple bit lines 101 can be arranged in columns along the y-direction, with multiple columns of bit lines 101 between the isolation structures 141; the bit lines 101 in adjacent columns are staggered, and the bit lines 101 in adjacent columns are not aligned in the x-direction to reduce the device area occupied and increase the device integration density. Figure 6 An enlarged schematic diagram of any two bit lines 101 is also shown. For example, a first bit line 101a and a second bit line 101b that are located in different columns and are adjacent to each other are shown. The first bit line 101a and the second bit line 101b are not aligned in the x-direction. The straight-line distance D4 between the first bit line 101a and the second bit line 101b is greater than the perpendicular distance D5 between the first bit line 101a and the second bit line 101b in the x-direction. The straight-line distance D4 between the first bit line 101a and the second bit line 101b can be the distance between the centers of the two bit lines 101.

[0073] In some embodiments, refer to Figure 6 As shown, the second electrode layer 132 and the channel layer 111 can be embedded in the fifth dielectric layer 124. The fifth dielectric layer 124 provides electrical isolation between the second electrode layers 132, reducing leakage current. The fifth dielectric layer 124 can be made of a different material than the first dielectric layer 112 and the second dielectric layer 121 to improve etching selectivity. For example, the first dielectric layer 112 may include a high dielectric material such as hafnium oxide, the second dielectric layer 121, the third dielectric layer 122 and the fourth dielectric layer 123 may include silicon oxide, and the fifth dielectric layer 124 may include silicon nitride.

[0074] In some embodiments, the channel layer 111 is composed of: amorphous oxide semiconductor materials; including but not limited to IGZO materials. IGZO materials may include oxides of elements such as indium, gallium, and zinc, and have superior semiconductor properties.

[0075] In some embodiments, refer to Figure 2 and Figure 4 As shown, the memory device 10 includes: a transistor 110, which includes at least a gate layer 113, a first dielectric layer 112 and a channel layer 111; a plurality of transistors 110 are stacked in the z direction, and a bit line 101 passes through the plurality of gate layers 113, the plurality of first dielectric layers 112 and the plurality of channel layers 111 along the z direction, and the bit line 101 is coupled to the plurality of channel layers 111.

[0076] Reference Figure 2 and Figure 4As shown, the memory device 10 may include multiple stacked structures 100 arranged in the z-direction, and adjacent stacked structures 100 may be isolated by a dielectric material. Each stacked structure 100 may include at least: a channel layer 111, a second electrode layer 132 coupled to the channel layer 111; a first dielectric layer 112 located above the channel layer 111 and the second electrode layer 132; a gate layer 113 and a first electrode layer 131 located above the first dielectric layer 112; and a third dielectric layer 122 located between the gate layer 113 and the second electrode layer 132. The stacked structure 100 also includes a second dielectric layer 121 located between a bit line 101 and the gate layer 113. The bit line 101 may penetrate multiple stacked structures 100. In the stacked structure 100, a transistor 110 may include a channel layer 111, a first dielectric layer 112, and a gate layer 113, specifically including a portion of the first dielectric layer 112 overlapping the gate layer 113 and the channel layer 111.

[0077] The gate layer 113 serves as the control gate of the transistor 110, and the first dielectric layer 112 serves as the gate dielectric layer. The control gate is configured to apply different voltages to control the transistor 110 to turn on and off. The capacitor structure may include a first electrode layer 131, a second electrode layer 132, and a first dielectric layer 112, specifically including a portion of the first dielectric layer 112 that overlaps with the first electrode layer 131 and the second electrode layer 132. The transistor 110 and the capacitor structure can constitute a memory cell, such as a DRAM memory cell. The capacitor structure can be replaced with other memory structures, including but not limited to phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures.

[0078] In some embodiments, multiple transistors 110 can be arranged on the xoy plane to form a transistor array 110. The multilayer transistor array 110 is stacked in the z direction, and the bit line 101 is coupled to the multilayer transistors 110 in the z direction, specifically coupled to the multilayer channel layer 111. The multiple transistors 110 coupled to a bit line 101 and the coupled capacitor structure can be referred to as a memory cell string. The memory device 10 may include an array of memory cell strings.

[0079] The embodiments disclosed herein can realize the stacking of transistors in the z-direction and their coupling with bit lines, thereby increasing the transistor integration density. The components of the capacitor structure and the components of the transistor are disposed in the same film layer. For example, the first electrode layer 131 and the gate layer 113 can be located in the same film layer, and the second electrode layer 132 and the channel layer 111 can be located in the same film layer. Furthermore, the capacitor dielectric of the capacitor structure and the gate dielectric layer of the transistor can share the same dielectric layer, such as the first dielectric layer 112. This enables the storage cells to be stacked in the z-direction, reducing the thickness of the storage cells in the z-direction and facilitating the increase of integration density.

[0080] According to some aspects of embodiments of this disclosure, Figure 7A method for manufacturing a storage device 10 is provided, comprising: forming at least one stacked structure, the stacked structure comprising: a first dielectric material layer, a second dielectric material layer, a first dielectric layer and a first conductive material layer stacked in a first direction;

[0081] The first conductive material layer is etched along the second direction to form a first gap extending along the third direction, the first gap exposing the first dielectric layer; the third direction intersects the second direction, and the plane formed by the third direction and the second direction intersects the first direction;

[0082] A third dielectric material layer extending along the third direction and a word line extending along the third direction are formed within the first gap; the third dielectric material layer is located between the first conductive material layer and the word line;

[0083] An opening is formed that penetrates the stacked structure along the first direction;

[0084] A portion of the first conductive material layer is removed through the opening to form a first electrode layer, and a gate layer is formed on the first plane where the first conductive material layer is located. The gate layer is coupled to the word line.

[0085] A second electrode layer and a channel layer are formed on the second plane where the second dielectric material layer is located through the opening, and the channel layer is coupled to the second electrode layer;

[0086] Bit lines are formed in the openings, and the bit lines are coupled to the channel layer.

[0087] Reference Figure 8 As shown, Figure 8The diagram also shows a schematic cross-section of AA' in the xoz plane; at least one stacked structure 1000 can be formed, the stacked structure 1000 including: a first dielectric material layer 102, a second dielectric material layer 103, a first dielectric layer 112, and a first conductive material layer 104 stacked in the z direction; the formation process of the stacked structure 1000 may include, but is not limited to, deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). Multiple stacked structures 1000 can be formed, adjacent stacked structures 1000 are isolated by a dielectric material or a first dielectric material layer 102, the multiple stacked structures 1000 can be formed on a substrate, or on a semiconductor layer, or on a semiconductor layer of a substrate, the substrate or semiconductor layer can be thinned or removed from the back side. The first dielectric layer 102, the second dielectric layer 103, and the first dielectric layer 112 may comprise different dielectric materials to exhibit different etching selectivity for different etchants, thereby reducing over-etching damage to the film layers that need to be retained during the etching process. For example, the first dielectric layer 102 may comprise silicon oxide; the second dielectric layer 103 may comprise silicon nitride or silicon oxynitride; and the first dielectric layer 112 may comprise a high-dielectric material such as aluminum oxide or hafnium oxide. The first conductive layer 104 may include, but is not limited to, tungsten as an example.

[0088] The edges of the stacked structure 1000 are etched to etch the edges of the first conductive material layer 104, forming a first gap 12 extending in the y direction. The first gap 12 may be located between the first dielectric layer 112 and the first dielectric material layer 102, which is part of another stacked structure 1000. If there are multiple stacked structures 1000, the first conductive material layer 104 of each stacked structure 1000 is etched to form a first gap 12 in each stacked structure 1000, and the first gap 12 exposes the first dielectric layer 112.

[0089] In some embodiments, the stacked structure 1000 is a large-sized film layer structure extending on the surface of a wafer or substrate. After the device fabrication is completed, the wafer is diced to form independent memory devices 10, or the stacked structure 1000 needs to be further divided to form memory devices 10 with different memory regions or memory subarrays. Different memory regions and memory subarrays can be connected via... Figure 3The isolation structure 141 shown in the example isolates storage subarrays between two isolation structures 141, which can serve as banks or blocks of storage devices 10. This division is only for illustrative purposes and is not intended to limit the scope of the entire storage array. Figure 3 The number of isolation structures 141 is not limited to the specific way and arrangement of forming storage units or storage structures in the area between the isolation structures 141.

[0090] In some embodiments, the method of forming the first gap 12 includes: referring to Figure 9 As shown, the etched stacked structure 1000 is used to form a first trench 11 penetrating the stacked structure 1000; the first trench extends along the y-direction; refer to Figure 10 As shown, the first conductive material layer 104 is etched using the first trench 11 to form the first void 12.

[0091] Figure 8 as well as Figure 9 The system may include multiple stacked structures 1000. A first trench 11 may be located in the middle region of the stacked structures 1000. The first trench 11 may divide the stacked structure 1000 into multiple sub-stacked structures 1000. The first trench 11 may have two sub-stacked structures on each side in the x-direction. Figure 9 The schematic diagram of other sub-stacked structures is omitted. The etching process for forming the first trench 11 may include, but is not limited to, dry etching, wet etching, or a combination thereof, such as plasma dry etching that can be used to form the first trench 11 through multiple stacked structures 1000. Figure 10 In this process, dry gas etching or wet etching can be used to selectively etch the first conductive material layer 104 exposed from the sidewall of the first trench 11. The first conductive material layer 104 is then side-cut in the x-direction to form a first void 12. The first void 12 is located between two vertically disposed film layers, exposing the first dielectric layer 112 beneath the first conductive material layer 104. The first dielectric layer 112 and other materials have a low etching rate or are essentially not etched. (For illustrative purposes, the fabrication method described in this disclosure is illustrated.) Figure 10 The partial cross-sectional view of multiple stacked structures 1000 does not represent the formation of a stepped structure. The first conductive material layer 104 of other stacked structures 1000 is also etched to form the first gap 12. The following figures show a cross-sectional view of one of the multiple stacked structures 1000, which will not be described in detail.

[0092] Reference Figures 11 to 14 As shown, a third dielectric material layer 152 is formed in the first gap 12, and a word line 133 extending in the y direction is formed. The third dielectric material layer 152 is located between the first conductive material layer 104 and the word line 133 to provide electrical isolation. Figure 14 As exemplified, the third dielectric material layer 152 and word line 133 can fill the first void 12.

[0093] In some embodiments, the method of forming the third dielectric material layer 152 and the word line 133 includes:

[0094] Reference Figure 11 As shown, the first gap is filled with dielectric material 151, which can fill the internal space of the first gap 12; see reference. Figure 12 As shown, etching removes a portion of the dielectric material 151 to form a third dielectric material layer 152 extending along the y-direction, at which point a portion of the space in the first gap 12 can be released; see reference. Figure 14 As shown, word lines 133 are formed in the space released by removing part of the dielectric material 151. (Refer to...) Figure 13 As shown, conductive material 134 can fill the first gap 12, and some conductive material 134 can be deposited in the first trench 11. Etching removes the conductive material 134 in the first trench 11, leaving the conductive material in the first gap 12 to form word lines 133.

[0095] In some embodiments, the manufacturing method further includes: referring to Figure 14 As shown, a first trench 11 is filled with a dielectric material to form an isolation structure 141 in the first trench 11. The process for forming the isolation structure 141 may include deposition or spin-coating of the dielectric material.

[0096] In some embodiments, refer to Figure 15 As shown, the stacked structure 1000 is etched to form an opening 13 penetrating the stacked structure 1000 along the z-direction. The opening 13 can penetrate multiple stacked structures 1000. The opening 13 is formed in the region between two word lines 133. The opening 13 penetrates the etched first conductive material layer 104, but does not penetrate the third dielectric material layer 152 or the word lines 133. The opening 13 exposes film structures at different film layer heights or on different planes. New film structures can be formed by etching and filling materials on different planes based on the opening 13. Different stacked structures 1000 can be fabricated simultaneously. (Refer to...) Figures 16 to 18 As shown, a portion of the first conductive material layer 104 is removed through the opening 13 to form the first electrode layer 131. A gate layer 113 is formed on the first plane where the first conductive material layer 104 is located. The gate layer 113 is coupled to the word line 133. The first plane is a plane on the first dielectric layer 112, which may be parallel to the xoy plane.

[0097] In some embodiments, the method of forming the first electrode layer 131 includes:

[0098] Reference Figure 16As shown, a portion of the first conductive material layer 104 is etched through the opening 13 to form a first cavity 14; the first cavity 14 surrounds the opening 13 and is connected to the opening 13; the bottom of the first cavity 14 exposes the first dielectric layer 112; the remaining first conductive material layer 104 forms the first electrode layer 131. Through the opening 13, the first conductive material layer 104 is side-cut using gas etching or wet etching to form an annular first cavity 14 extending outward from the opening 13. The etching process of the first cavity 14 can stop at the third dielectric material layer 152, or in other embodiments, the third dielectric material layer 152 can be over-etched, penetrating or not penetrating the third dielectric material layer 152. The remaining first conductive material layer 104 forms the first electrode layer 131. The area of ​​the first electrode layer 131 with the first cavity 14 exposes the first dielectric layer 112, which is a film layer under the first electrode layer 131. The first electrode layer 131 has an irregular shape and may include a pattern composed of arcs and straight lines. Figure 16 This is a partial cross-sectional view of a stacked structure 1000. For other stacked structures 1000, the first conductive material layer 104 can be etched simultaneously, and the first electrode layer 131 can be formed simultaneously.

[0099] In some embodiments, the method of forming the gate layer 113 includes:

[0100] Reference Figure 17 As shown, in Figure 16 A third dielectric layer 122 is formed on the sidewall of the first cavity 14. At this time, the side edge of the word line 133 in the x direction is also isolated by the third dielectric material layer 152 and the third dielectric layer 122. Part of the third dielectric layer 122 and the third dielectric material layer 152 are etched away to form a second cavity 15 that exposes the word line 133. That is, the third dielectric layer 122 and the strip-shaped third dielectric material layer 152 are etched in the x direction until the word line 133 is exposed. The sidewall of the second cavity 15 is provided by the remaining third dielectric layer 122 and the word line 133. The remaining third dielectric layer 122 is an annular shape with an opening that exposes the word line 133. The bottom of the second cavity 15 exposes the first dielectric layer 112 under the first electrode layer 131.

[0101] Reference Figure 18 As shown, a gate layer 113 and a second dielectric layer 121 are formed on the sidewall of the second cavity 15; the gate layer 113 surrounds the second dielectric layer 121; the second dielectric layer 121 is an annular film layer surrounding the opening 13 in a transverse direction perpendicular to the z direction, and the gate layer 113 is an annular film layer surrounding the second dielectric layer 121. Figure 17 The third dielectric material layer 152 is etched along the x-direction and penetrated to expose the word line 133, forming Figure 3 , Figure 5 as well as Figure 18 The fourth dielectric layer 123 is shown in the example.

[0102] In some embodiments, a gate layer 113 is formed by filling the second cavity 15 with conductive material, a portion of the gate layer 113 is etched using the opening 13, and a second dielectric layer 121 is formed in the annular cavity region released after etching the gate layer 113, with the gate layer 113 surrounding the second dielectric layer 121. In some embodiments, conductive material may be formed on the sidewalls of the opening 13 when forming the gate layer 113, and the conductive material on the sidewalls of the opening 13 may be removed when etching the gate layer 113; or the opening 13 may be etched along the z-direction to remove the conductive material inside the opening 13, so as to maintain the inner diameter of the opening 13 and reduce the blockage of the opening 13.

[0103] Reference Figures 19 to 22 The diagram shows a partial cross-sectional view of the stacked structure 1000 in the plane containing the second dielectric material layer 103. A second electrode layer 132 and a channel layer 111 are formed in the second plane containing the second dielectric material layer 103 of the stacked structure 1000 through the opening 13. The channel layer 111 is coupled to the second electrode layer 132. The second electrode layer 132 and the channel layer 111 can be formed simultaneously in the second dielectric material layer 103 of other stacked structures 1000.

[0104] In some embodiments, the second dielectric material layer 103 can be side-cut using gas etching or wet etching through the opening 13 to form an annular third cavity 16 extending outward from the opening 13. The first dielectric material layer 102 is located below the second dielectric material layer 103, and the second dielectric layer 103 is located below the first dielectric layer 112. The first dielectric material layer 102 may include silicon oxide, and the second dielectric layer 103 may include silicon nitride or silicon oxynitride to reduce over-etching damage to the first dielectric material layer 102 during the formation of the third cavity 16. A second electrode layer 132 and a channel layer 111 are formed in the third cavity 16. Exemplarily, forming the second electrode layer and the channel layer 111 includes:

[0105] Reference Figure 19 As shown, the second dielectric material layer 103 is etched through the opening 13 to form a third cavity 16; the third cavity 16 exposes the first dielectric material layer 102 beneath the second dielectric material layer 103; the etching to form the third cavity 16 may stop at the isolation structure 141 or may not expose the isolation structure 141, and multiple third cavities 16 are isolated by the second dielectric material layer 103, the remaining second dielectric layer 103 may be formed as shown in the figure. Figure 6 , Figure 20 The fifth dielectric layer 124 shown has an irregular shape;

[0106] Reference Figure 20 As shown, the third cavity 16 is filled with conductive material; refer to Figure 21 As shown, a portion of the conductive material is removed to form the second electrode layer 132; refer to Figure 22 As shown, a channel layer 111 is formed in the space of the third cavity 16 where some conductive material has been removed and released; a second electrode layer 132 surrounds the channel layer 111 and is coupled to the channel layer 111. Figure 20 The conductive material can fill the space of the third cavity 16. Figure 21 The conductive material is etched to retain the conductive material located on the sidewall of the third cavity 16 to form an annular second electrode layer 132; at least a portion of the third cavity 16 is filled with semiconductor material to form Figure 22 111 annular channel layer; Figure 22 Semiconductor material can be used to fill the entire third cavity 16, or to fill only part of the third cavity 16. When bit line 101 is formed in the opening 13, bit line 101 can fill the remaining third cavity 16.

[0107] In some embodiments, when the third cavity 16 is filled with conductive material, conductive material may be formed on the sidewall of the opening 13, which can... Figure 21 When removing part of the conductive material in the third cavity 16, the conductive material inside the opening 13 is also removed; or the opening 13 is etched along the z-direction to remove the conductive material inside the opening 13 in order to maintain the inner diameter of the opening 13.

[0108] In some embodiments, processes such as atomic deposition can be used in... Figure 19 Formed on the side wall of the third cavity 16 Figure 21 The second electrode layer 132 shown is formed within the remaining third cavity 16. Figure 22 The channel layer 111 is shown.

[0109] In some embodiments, refer to Figure 23 As shown, conductive material is filled into the opening 13 to form bit line 101, which can be directly coupled to the channel layer 111.

[0110] In some embodiments, the method of forming bit line 101 includes: etching removal Figure 22 The residual material in the opening 13 includes at least the constituent material of the channel layer 111; refer to Figure 23 As shown, bit line 101 is formed in opening 13.

[0111] In formation Figure 22 When the channel layer 111 is shown, semiconductor material may form on the sidewalls of the opening 13. The opening 13 can be etched along the z-direction to remove the semiconductor material in the opening 13, thereby maintaining the inner diameter of the opening 13 and ensuring good morphology and dimensions of the bit line 101, reducing contact failure between the bit line 101 and the channel layer 111. Other residual materials may also exist inside the opening 13, such as... Figure 18When the gate layer 113 and the second dielectric layer 121 are formed in the second cavity 15 using the opening 13, there may be residual conductive and dielectric materials inside the opening 13; when the second electrode layer 132 is formed in the third cavity 16 using the opening 13, there may be residual conductive materials; the inside of the opening 13 is etched and cleaned to remove the residual materials in the opening 13. The residual materials may include semiconductor materials, conductive materials and dielectric materials. Bit lines 101 are formed in the opening 13 after etching and cleaning to reduce contact failure between the bit lines 101 and the channel layer 111.

[0112] In some embodiments, the constituent materials of the channel layer 111 include: amorphous oxide semiconductor materials; including but not limited to IGZO materials. IGZO materials may include oxides of elements such as indium, gallium, and zinc, and have superior semiconductor properties. The addition of indium and gallium can improve the electron mobility of semiconductor materials, achieving lower operating voltage and lower power consumption compared to traditional semiconductor materials such as silicon; the introduction of zinc helps to improve the stability of semiconductor materials; IGZO materials can be used to deposit and fabricate the channel layer 111, and the film thickness, crystal form, and film morphology of the channel layer 111 can be controlled by controlling the deposition process parameters, improving the filling uniformity of the channel layer 111 in the third cavity 16, reducing void defects, and reducing contact failure between the channel layer 111 and the second electrode layer 132.

[0113] According to some aspects of embodiments of the present disclosure, a memory system 202 is provided, comprising: Figures 2 to 4 as well as Figure 23 The storage device 10 shown, and the storage controller 206, are coupled to and configured to control the storage device 10. The storage device 10 may also include peripheral circuitry; the peripheral circuitry may be coupled to bit line 101 and word line 133; the peripheral circuitry may include, but is not limited to: sensing amplification circuitry, row decoding circuitry, column decoding circuitry, voltage generation circuitry, etc. Figure 24 A memory system 202 is provided, comprising a memory device 204 and a memory controller 206 coupled thereto. The memory controller 206 controls the memory device 204, which includes... Figures 2 to 4 as well as Figure 23 The storage device 10 described herein is a storage device 204 or at least a portion thereof.

[0114] Reference Figure 24As shown, this disclosure provides a system 200 including a host 208. The system 200 may be a mobile phone, graphics processing device, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 24 As shown, system 200 may include host 208 and memory system 202, the memory system 202 having one or more memory devices 204 and memory controller 206. Host 208 may be a processor (e.g., central processing unit (CPU)) or system-on-a-chip (SoC) (e.g., application processor (AP)). Host 208 may be configured to send data to or receive data from memory device 204, memory device 204 may include... Figures 2 to 4 as well as Figure 23 The aforementioned storage device 10.

[0115] According to some embodiments, a memory controller 206 is coupled to the memory device 204 and the host 208, and is configured to control the memory device 204 to perform read, write, or refresh operations. The memory controller 206 can manage data stored in the memory device 204 and communicate with the host 208. The memory device 204 includes DRAM, or a package structure formed by stacking multiple DRAMs, which can be applied to HBM or HMC package structures.

[0116] In some specific examples, the HBM packaging structure may include multiple DRAM chips vertically stacked on a logic chip, with electrical interconnections between the logic chip and the multiple DRAM chips via through-silicon vias (TSVs). The multiple DRAM chips and the logic chip can form a memory system. The logic chip may include, but is not limited to, components such as control logic, interface control modules, and SRAM caches. The logic chip may be configured as a memory controller 206. Figures 2 to 4 as well as Figure 23The storage device 10 shown can be configured as a memory device 204 or a DRAM chip; the HBM package structure may also include processor chips such as GPUs, CPUs, or SOC chips, and the processor may integrate a memory controller to control data transfer of the DRAM chips. For example, a processor such as a GPU is coupled to a logic chip, and data interaction occurs between the logic chip and the DRAM. In other specific examples, the HMC (Hybrid Memory Cube) package structure may include multiple DRAM chips vertically stacked on a logic chip, with the logic chip and the multiple DRAM chips interconnected via TSVs. The multiple DRAM chips and the logic chip can form a memory system, and the logic chip may include, but is not limited to, components such as control logic, interface control modules, and SRAM caches, and the logic chip may integrate a memory controller.

[0117] In some specific examples, the memory system 202 can be used in conjunction with a solid-state drive (SSD) to improve read and write speeds. Many high-end SSD products choose to embed DRAM to enhance performance and improve random read / write speeds. For example, during file writing, especially small file writing, small files are processed by DRAM before being stored in flash memory, making the SSD storage more efficient and faster. Flash memory includes non-volatile memory, including but not limited to 2D NAND memory or 3D NAND memory. In some specific examples, the memory system 202 can be used as a cache device in a graphics processing device (GPU), which may include, but is not limited to, a graphics graphics card.

[0118] In other embodiments, reference is made to Figure 25 As shown, system 200 may consist only of host 208 and a memory device 204 coupled thereto. The controller for the memory device 204 may be located inside host 208, such as a memory controller integrated within a central processing unit (CPU), or a southbridge or northbridge chip integrated into the motherboard of system 200. Memory device 204 may include, but is not limited to: DDR4 memory, DDR5 memory (Double Data Rate Synchronous Dynamic Random Access Memory), and LPDDR5 memory (Low Power Double Data Rate Synchronous Dynamic Random Access Memory). Memory device 204 may include... Figures 2 to 4 as well as Figure 23 The example storage device 10.

[0119] In some embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the components shown or discussed may be directly or indirectly coupled to each other. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0120] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A storage device, characterized in that, include: A channel layer, a first dielectric layer, and a gate layer are stacked in a first direction; The bit line extends through the gate layer, the first dielectric layer, and the channel layer along the first direction; The channel layer is coupled to the bit line; The second dielectric layer is located between the gate layer and the bit line; The first electrode layer and the second electrode layer are located on opposite sides of the first dielectric layer in the first direction, and the first electrode layer and the second electrode layer overlap at least partially in the first direction; wherein the second electrode layer is coupled to the side of the channel layer away from the bit line.

2. The storage device according to claim 1, characterized in that, The second dielectric layer, the gate layer, and the channel layer extend along a second direction; the second direction intersects the first direction; the second dielectric layer surrounds the bit line, the gate layer surrounds the second dielectric layer, and the channel layer surrounds the bit line.

3. The storage device according to claim 2, characterized in that, The second electrode layer extends along the second direction and surrounds the channel layer.

4. The storage device according to claim 1, characterized in that, The storage device further includes: A third dielectric layer is located between the first electrode layer and the gate layer; the first electrode layer and the gate layer are electrically isolated at least through the third dielectric layer. The second dielectric layer, the gate layer, the third dielectric layer, and the first electrode layer extend on a first plane, which intersects with the first direction.

5. The storage device according to claim 1, characterized in that, The channel layer and the second electrode layer extend on a second plane, which intersects with the first direction.

6. The storage device according to claim 1, characterized in that, The first dielectric layer extends between the first electrode layer and the second electrode layer along a second direction intersecting the first direction; the first electrode layer, the first dielectric layer, and the second electrode layer at least partially overlap in the first direction.

7. The storage device according to claim 6, characterized in that, The first electrode layer is located away from the bit line relative to the second electrode layer in the second direction.

8. The storage device according to claim 2, characterized in that, The portion of the gate layer surrounding the bit line has a first dimension in the second direction; the portion of the channel layer surrounding the bit line has a second dimension in the second direction. The first dimension is smaller than the second dimension.

9. The storage device according to claim 4, characterized in that, The bit line, the gate layer, and the third dielectric layer extend into the first electrode layer along a second direction, and the first electrode layer surrounds a portion of the gate layer on its side in the second direction; a portion of the gate layer overlaps with a portion of the first electrode layer in a third direction. The third direction intersects with the second direction, and the plane formed by the third direction and the second direction intersects with the first direction.

10. The storage device according to claim 9, characterized in that, The first electrode layer on the side in the second direction includes: A straight edge extending along the third direction, and an arc-shaped edge; the arc-shaped edge is located between two adjacent straight edges along the third direction, and the two ends of the arc-shaped edge are respectively connected to the two straight edges; The arc-shaped edge surrounds a portion of the gate layer, and the gap between the two ends of the arc-shaped edge exposes the gate layer.

11. The storage device according to claim 9, characterized in that, The plurality of bit lines are disposed opposite to each other on both sides of the first electrode layer in the second direction. The plurality of bit lines include a first bit line and a second bit line, and the first bit line and the second bit line are not aligned in the second direction.

12. The storage device according to claim 9, characterized in that, The storage device further includes: Word lines are located on both sides of the first electrode layer in the second direction; the word lines extend along a third direction and are coupled to a plurality of gate layers; the word lines are coupled to the exposed portion of the gate layer on the side of the first electrode layer.

13. The storage device according to claim 12, characterized in that, The storage device further includes: The fourth dielectric layer extends along the third direction and is located between the first electrode layer and the word line; the gate layer is located between two adjacent fourth dielectric layers in the third direction.

14. The storage device according to claim 1, characterized in that, The channel layer is composed of amorphous oxide semiconductor materials.

15. The storage device according to claim 1, characterized in that, The storage device includes: A transistor includes at least the gate layer, the first dielectric layer, and the channel layer; a plurality of the transistors are stacked in a first direction, and a bit line passes through the plurality of the gate layers, the plurality of the first dielectric layers, and the plurality of the channel layers along the first direction, and the bit line is coupled to the plurality of the channel layers.

16. A method for manufacturing a storage device, characterized in that, include: At least one stacked structure is formed, the stacked structure comprising: a first dielectric material layer, a second dielectric material layer, a first dielectric layer, and a first conductive material layer stacked in a first direction; The first conductive material layer is etched along the second direction to form a first gap extending along the third direction, the first gap exposing the first dielectric layer; the third direction intersects the second direction, and the plane formed by the third direction and the second direction intersects the first direction; A third dielectric material layer extending along the third direction and a word line extending along the third direction are formed within the first gap; the third dielectric material layer is located between the first conductive material layer and the word line; An opening is formed that penetrates the stacked structure along the first direction; A portion of the first conductive material layer is removed through the opening to form a first electrode layer, and a gate layer is formed on the first plane where the first conductive material layer is located. The gate layer is coupled to the word line. A second electrode layer and a channel layer are formed on the second plane where the second dielectric material layer is located through the opening, and the channel layer is coupled to the second electrode layer; Bit lines are formed in the openings, and the bit lines are coupled to the channel layer.

17. The manufacturing method according to claim 16, characterized in that, The method for forming the first gap includes: The stacked structure is etched to form a first trench penetrating the stacked structure; the first trench extends along the third direction. The first conductive material layer is etched using the first trench to form the first void.

18. The manufacturing method according to claim 17, characterized in that, The method of forming the third dielectric material layer and the word line includes: The first void is filled with a dielectric material, and a portion of the dielectric material is etched away to form the third dielectric material layer. The word lines are formed in the space released by removing a portion of the dielectric material.

19. The manufacturing method according to claim 18, characterized in that, The manufacturing method further includes: An isolation structure is formed in the first trench.

20. The manufacturing method according to claim 16, characterized in that, The method for forming the first electrode layer includes: A portion of the first conductive material layer is etched through the opening to form a first cavity; the first cavity surrounds the opening and is connected to the opening, and the bottom of the first cavity exposes the first dielectric layer; the remaining first conductive material layer forms the first electrode layer.

21. The manufacturing method according to claim 20, characterized in that, The method of forming the gate layer includes: A third dielectric layer is formed on the sidewall of the first cavity; Etching removes a portion of the third dielectric layer and a portion of the third dielectric material layer to form a second cavity exposing the word lines; the sidewalls of the second cavity are provided by the remaining third dielectric layer and the word lines; The gate layer and the second dielectric layer are formed on the sidewall of the second cavity; the gate layer surrounds the second dielectric layer.

22. The manufacturing method according to claim 16, characterized in that, Forming the second electrode layer and the channel layer includes: The second dielectric material layer is etched through the opening to form a third cavity; the third cavity exposes the first dielectric material layer. The third cavity is filled with conductive material, and a portion of the conductive material is removed to form a second electrode layer. The channel layer is formed in the space of the third cavity released by removing part of the conductive material; the second electrode layer surrounds the channel layer and is coupled to the channel layer.

23. The manufacturing method according to claim 22, characterized in that, The method for forming the bit line includes: Etching removes residual material from the opening, the residual material comprising at least the constituent material of the channel layer; The bit line is formed in the opening.

24. The manufacturing method according to claim 22, characterized in that, The channel layer is composed of amorphous oxide semiconductor materials.

25. A memory system, characterized in that, include: The storage device according to any one of claims 1 to 14, and A memory controller is coupled to the memory device and configured to control the memory device.

Images