Semiconductor device testing method and apparatus, electronic device, storage medium

Abstract

The present disclosure relates to the technical field of semiconductor testing, and provides a semiconductor device testing method and device, electronic equipment and storage medium. The method comprises: determining a criterion limit value of dynamic part average testing, comprising: obtaining semiconductor device samples based on a preset sampling method; performing continuous reliability testing on the semiconductor device samples; obtaining the criterion limit value of the dynamic part average testing based on semiconductor device samples that fail to pass the continuous reliability testing; and performing continuous reliability testing and dynamic part average testing on semiconductor devices based on the criterion limit value to obtain a testing result. The present disclosure not only realizes that continuous reliability testing and dynamic part average testing of semiconductor devices can be completed simultaneously through one testing process without damaging logic, optimizes the testing process, improves testing efficiency, but also makes testing conditions more stringent and makes the final screened semiconductor devices have higher quality and stronger reliability.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor testing technology, and in particular to a semiconductor device testing method and apparatus, electronic equipment, and storage medium. Background Technology

[0002] In existing technologies, when performing functional testing on semiconductor components, Automatic Test Equipment (ATE) typically includes Part Average Testing (PAT) and Ongoing Reliability Testing (ORT) functions. PAT is a method used in ATE to improve component quality and reliability, incorporating more stringent test ranges based on varying manufacturing capabilities. PAT is categorized into static PAT and dynamic PAT (DPAT). DPAT is typically used in the Final Test (FT) stage, applying PAT to data in real time. When testing semiconductor components, the ORT function determines that the component has passed the test if it is a good product and its coordinates are contained in a pre-defined coordinate library.

[0003] However, existing ATE systems can only perform DPAT and ORT functions separately; that is, they can only complete either the DPAT or ORT function individually. If both DPAT and ORT functions need to be performed together, an additional entire testing procedure is required. Summary of the Invention

[0004] This disclosure aims to address at least one of the problems existing in the prior art by providing a semiconductor device testing method and apparatus, electronic device, and storage medium.

[0005] One aspect of this disclosure provides a method for testing semiconductor devices, comprising:

[0006] Determining the criterion limit for dynamic component average testing includes: obtaining semiconductor device samples based on a preset sampling method; performing continuous reliability testing on the semiconductor device samples; and obtaining the criterion limit for dynamic component average testing based on semiconductor device samples that fail the continuous reliability test.

[0007] Based on the criterion limits, continuous reliability testing and dynamic component averaging testing are performed on semiconductor devices to obtain test results.

[0008] Optionally, based on criterion limits, continuous reliability testing and dynamic component averaging testing are performed on semiconductor devices, including:

[0009] Perform continuous reliability testing on semiconductor devices;

[0010] Based on the criterion limit, dynamic component averaging tests are performed on semiconductor devices that fail the continuous reliability test.

[0011] Optionally, before performing continuous reliability testing on semiconductor device samples or semiconductor devices, the testing methods may also include:

[0012] Perform routine electrical performance tests on semiconductor device samples or semiconductor devices;

[0013] Continuous reliability testing is performed on semiconductor device samples or semiconductor devices that have passed routine electrical performance tests.

[0014] Optionally, the testing methods also include:

[0015] The semiconductor devices corresponding to the test results of each stage of testing are categorized and stored.

[0016] Optionally, determining the criterion limits for dynamic part averaging tests may also include:

[0017] Based on a preset number of semiconductor device samples that failed the continuous reliability test, the criterion limit for dynamic component average testing is determined.

[0018] Optionally, determining the criterion limits for dynamic part averaging tests may also include:

[0019] Based on the preset sampling frequency and total number of samples, determine the number of thresholds for periodically updating the criterion limit;

[0020] For each threshold number of semiconductor devices that pass the dynamic component average test, a new semiconductor device sample is collected based on the sampling frequency and the total number of samples, and the criterion limit is updated periodically based on the new semiconductor device sample.

[0021] Optionally, determining the criterion limits for dynamic part averaging tests may also include:

[0022] For each semiconductor device that passes the dynamic component average test, a new semiconductor device sample is collected to update the criterion limit in real time based on the new semiconductor device sample.

[0023] Another aspect of this disclosure provides a semiconductor device testing apparatus, comprising:

[0024] The determination module is used to determine the criterion limit for dynamic component average testing, including: obtaining semiconductor device samples based on a preset sampling method; performing continuous reliability testing on the semiconductor device samples; and obtaining the criterion limit for dynamic component average testing based on semiconductor device samples that fail the continuous reliability test.

[0025] The test module is used to perform continuous reliability testing and dynamic component averaging testing on semiconductor devices based on criterion limits, and obtain test results.

[0026] Another aspect of this disclosure provides an electronic device comprising:

[0027] At least one processor; and,

[0028] A memory that is communicatively connected to at least one processor; wherein,

[0029] The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform the semiconductor device testing method described above.

[0030] Another aspect of this disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the semiconductor device testing method described above.

[0031] Compared with the prior art, this disclosure not only enables the simultaneous completion of continuous reliability testing and dynamic component averaging testing of semiconductor devices through a single testing process without disrupting the logic, thus optimizing the testing process and improving testing efficiency, but also makes the testing conditions more stringent, resulting in higher quality and stronger reliability of the final selected semiconductor devices. Attached Figure Description

[0032] One or more embodiments are illustrated by way of example with the corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0033] Figure 1 A flowchart illustrating a semiconductor device testing method provided in one embodiment of this disclosure;

[0034] Figure 2 A flowchart of a semiconductor device testing method provided for another embodiment of this disclosure;

[0035] Figure 3 A flowchart of a semiconductor device testing method provided for another embodiment of this disclosure;

[0036] Figure 4 A schematic diagram of a semiconductor device testing apparatus provided for another embodiment of this disclosure;

[0037] Figure 5 A schematic diagram of the structure of an electronic device provided in another embodiment of this disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and with various variations and modifications based on the following embodiments. The division of the various embodiments below is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0039] One embodiment of this disclosure relates to a semiconductor device testing method, the process of which is as follows: Figure 1 As shown, it includes:

[0040] Step 101: Determine the criterion limit for the dynamic part average test.

[0041] Specifically, step 101 includes: obtaining semiconductor device samples based on a preset sampling method; performing continuous reliability testing on the semiconductor device samples; and obtaining the criterion limit for dynamic component average testing based on the semiconductor device samples that failed the continuous reliability test.

[0042] When performing continuous reliability testing on semiconductor device samples, if the coordinates of the semiconductor device sample are in a preset coordinate library, the semiconductor device is determined to have passed the continuous reliability test; if the coordinates of the semiconductor device sample are not in the preset coordinate library, the semiconductor device is determined to have failed the continuous reliability test.

[0043] For example, when obtaining the criterion limit for dynamic component average testing based on semiconductor device samples that failed the continuous reliability test, the criterion limit for dynamic component average testing can be calculated using existing DPAT algorithms, such as methods that calculate the criterion limit using the mean and standard deviation or methods that calculate the criterion limit using the median and interquartile range, based on the test data of the semiconductor device samples that failed the continuous reliability test. This criterion limit includes an upper criterion limit and a lower criterion limit.

[0044] For example, determining the criterion limit for dynamic part average testing, i.e., step 101 further includes:

[0045] Based on a preset number of semiconductor device samples that failed the continuous reliability test, the criterion limit for dynamic component average testing is determined.

[0046] Specifically, the preset quantity can be 200, meaning that a person skilled in the art can use the DPAT algorithm to calculate the criterion limit for the average test of dynamic components based on the test data of 200 semiconductor device samples that failed the continuous reliability test.

[0047] It should be noted that this embodiment does not limit the specific value of the preset quantity. In addition to 200, the preset quantity can also be 100, 300, 400, etc., and those skilled in the art can choose according to actual needs.

[0048] By determining the criterion limit for dynamic component average testing based on a preset number of semiconductor device samples that failed the continuous reliability test, the determined criterion limit can be made more scientific and reasonable, making subsequent dynamic component average testing more rigorous, thereby screening out semiconductor devices with higher quality and stronger reliability.

[0049] Step 102: Based on the criterion limit, perform continuous reliability testing and dynamic component averaging testing on the semiconductor device to obtain the test results.

[0050] Specifically, this step can first perform continuous reliability testing on the semiconductor device, and then perform dynamic component averaging testing on the semiconductor device based on the criterion limit determined in step 101, and obtain the corresponding test results respectively.

[0051] For example, based on criterion limits, performing continuous reliability testing and dynamic component averaging testing on semiconductor devices, i.e., step 102 may include:

[0052] Perform continuous reliability testing on semiconductor devices; based on criterion limits, perform dynamic component averaging testing on semiconductor devices that fail the continuous reliability test.

[0053] In other words, step 102 can first perform a continuous reliability test on the semiconductor device to determine whether the coordinates of the semiconductor device are in the preset coordinate library. If they are, the corresponding semiconductor device is determined to have passed the continuous reliability test; if not, the corresponding semiconductor device is determined to have failed the continuous reliability test. Based on the criterion limit determined in step 101, a dynamic component averaging test is performed on the semiconductor device that has failed the continuous reliability test to obtain the corresponding test result.

[0054] By first performing continuous reliability testing on semiconductor devices, and then conducting dynamic component averaging testing on semiconductor devices that fail the continuous reliability testing based on criterion limits, the testing process for semiconductor devices can be further optimized and the testing efficiency of semiconductor devices can be improved.

[0055] Compared with the prior art, the embodiments of this disclosure first determine the criterion limit for dynamic component averaging (DSME) testing, and then perform continuous reliability testing and DSME testing on semiconductor devices based on the criterion limit to obtain test results. Furthermore, when determining the criterion limit for DSME testing, semiconductor device samples are first obtained based on a preset sampling method, and then continuous reliability testing is performed on the semiconductor device samples. The criterion limit for DSME testing is obtained based on the semiconductor device samples that fail the continuous reliability test. This not only enables the simultaneous completion of continuous reliability testing and DSME testing of semiconductor devices in a single testing process without disrupting the logic, thus optimizing the testing process and improving testing efficiency, but also makes the testing conditions more stringent, resulting in higher quality and stronger reliability of the finally selected semiconductor devices.

[0056] For example, before performing continuous reliability testing on semiconductor device samples or semiconductor devices, the testing method may further include:

[0057] Perform routine electrical performance tests on semiconductor device samples or semiconductor devices; perform continuous reliability tests on semiconductor device samples or semiconductor devices that pass the routine electrical performance tests.

[0058] For example, in step 101, the semiconductor device samples can be subjected to routine electrical performance testing before undergoing continuous reliability testing, and then the continuous reliability testing can be performed on the semiconductor device samples that pass the routine electrical performance testing. Alternatively, in step 102, the semiconductor devices can be subjected to routine electrical performance testing before undergoing continuous reliability testing, and then the continuous reliability testing can be performed on the semiconductor devices that pass the routine electrical performance testing.

[0059] Conventional electrical performance testing includes, but is not limited to, Unclamped Inductive Switching (UIS) testing, DVDS testing, and Final Test (FT). UIS testing essentially simulates the extreme electrothermal stress encountered by semiconductor devices in system applications, revealing their energy tolerance. DVDS testing detects a semiconductor device's ability to dissipate internal heat, revealing its junction temperature dissipation to ambient temperature. FT testing is performed on the packaged semiconductor chip after wafer packaging to ensure the performance and quality of the finished product.

[0060] By conducting routine electrical performance tests on semiconductor device samples or devices before performing continuous reliability tests, and then conducting continuous reliability tests on those samples or devices that have passed the routine electrical performance tests, more rigorous testing can be performed on the semiconductor device samples or devices, thereby further improving the quality and reliability of the finally selected semiconductor devices.

[0061] For example, the testing method also includes:

[0062] The semiconductor devices corresponding to the test results of each stage of testing are categorized and stored.

[0063] Specifically, in step 101, if conventional electrical performance testing is performed on the semiconductor device samples before continuous reliability testing, then semiconductor device samples that fail the conventional electrical performance testing can be stored in the corresponding fail bin. Continuous reliability testing is performed on semiconductor device samples that pass the conventional electrical performance testing, and the semiconductor device samples that pass the continuous reliability testing are stored in the corresponding ORT bin. Semiconductor device samples that fail the continuous reliability testing are stored in a pre-set sample bin, thereby obtaining the criterion limit for dynamic component average testing based on the semiconductor device samples in the sample bin.

[0064] In step 102, if a conventional electrical performance test is performed on the semiconductor device before the continuous reliability test, the semiconductor devices that fail the conventional electrical performance test can be stored in the corresponding fail bin. The semiconductor devices that pass the conventional electrical performance test are then subjected to a continuous reliability test, and the semiconductor devices that pass the continuous reliability test are stored in the corresponding ORT bin. Based on the criterion limit determined in step 101, the semiconductor devices that fail the continuous reliability test are subjected to a dynamic component averaging test, and the semiconductor devices that pass the dynamic component averaging test are stored in the corresponding pass bin. The semiconductor devices that fail the dynamic component averaging test are stored in the DPAT fail bin.

[0065] By classifying and storing the semiconductor devices corresponding to the test results of each stage of testing, the test results of each stage become clearer and easier to understand. This also saves the subsequent process of selecting materials according to the test results, further optimizing the testing process and improving testing efficiency.

[0066] For example, determining the criterion limit for dynamic part average testing, i.e., step 101 further includes:

[0067] Based on the preset sampling frequency and total number of samples, determine the number of thresholds for periodically updating the criterion limit;

[0068] For each threshold number of semiconductor devices that pass the dynamic component average test, a new semiconductor device sample is collected based on the sampling frequency and the total number of samples, and the criterion limit is updated periodically based on the new semiconductor device sample.

[0069] Specifically, assuming the preset sampling frequency is n and the preset total number of samples is m, the threshold number for periodically updating the criterion limit can be expressed as m*n. That is, every time the number of semiconductor devices tested by the dynamic component average test in step 102 reaches m*n, a new semiconductor device sample is collected according to the sampling frequency n and the total number of samples m. Based on the new semiconductor device sample, a new criterion limit is obtained, thus realizing the periodic update of the criterion limit.

[0070] It should be noted that when updating the criterion limit periodically based on the new semiconductor device sample, the new criterion limit can be determined solely based on the new semiconductor device sample, or it can be determined based on both the new semiconductor device sample and the previous semiconductor device sample. This implementation does not limit either approach.

[0071] By periodically updating the criterion limits, dynamic adjustments to the criterion limits can be achieved, thereby further improving the quality and reliability of the final selected semiconductor devices.

[0072] For example, determining the criterion limit for dynamic part average testing, i.e., step 101 further includes:

[0073] For each semiconductor device that passes the dynamic component average test, a new semiconductor device sample is collected to update the criterion limit in real time based on the new semiconductor device sample.

[0074] In other words, for each semiconductor device that passes the dynamic component average test in step 102, a new semiconductor device sample is collected, and a new criterion limit is obtained based on the new semiconductor device sample, thereby realizing the real-time update of the criterion limit.

[0075] It should be noted that the number of semiconductor samples used to update the criterion limit in real time can be fixed. In this case, each time a new semiconductor device sample is collected, the earliest semiconductor device sample can be deleted, thereby updating the semiconductor device samples while ensuring that the number of semiconductor device samples remains unchanged, and thus achieving real-time updating of the criterion limit.

[0076] By updating the criterion limits in real time, the criterion limits can be dynamically adjusted in real time, thereby further improving the quality and reliability of the finally selected semiconductor devices.

[0077] To enable those skilled in the art to better understand the above embodiments, a specific example is provided below for illustration.

[0078] This embodiment relates to a semiconductor device testing method, including the following steps:

[0079] First, several semiconductor devices were collected to obtain a semiconductor device sample. Then, as... Figure 2 As shown, routine electrical performance tests are performed on semiconductor device samples, including UIS, DVDS, and FT tests. If a semiconductor device sample fails the routine electrical performance test, the corresponding semiconductor device sample is stored in the corresponding fail bin, such as BIN4. If a semiconductor device sample passes the routine electrical performance test, a continuous reliability test is performed on the corresponding semiconductor device to determine whether the coordinates of the semiconductor device sample are in the preset ORT coordinate library. If the coordinates of the semiconductor device sample are in the preset ORT coordinate library, the corresponding semiconductor device is stored in the corresponding ORT bin, such as BIN6. If the coordinates of the semiconductor device sample are not in the preset ORT coordinate library, the corresponding semiconductor device is stored in a pre-set sample tray, such as BIN2. Repeat. Figure 2 The process shown involves determining the criterion limit for the average test of dynamic components based on the test data obtained from the 200 semiconductor device samples in the aforementioned test process using the DPAT algorithm when the number of semiconductor device samples in the sample tray reaches 200. The DPAT algorithm preferably uses the median and interquartile ranges.

[0080] After obtaining the criterion limits for dynamic component averaging (DPAT), the semiconductor devices to be tested are first subjected to routine electrical performance tests, including UIS, DVDS, and FT tests. If a semiconductor device fails the routine electrical performance test, it is stored in the corresponding fail bin, such as BIN4. If a semiconductor device passes the routine electrical performance test, a continuous reliability test is performed to determine whether its coordinates are in the preset ORT coordinate library. If the coordinates are in the preset ORT coordinate library, it is stored in the corresponding ORT bin, such as BIN6. If the coordinates are not in the preset ORT coordinate library, a dynamic component averaging (DPAT) test is performed based on the criterion limits. If a semiconductor device fails the DPAT test, it is stored in the DPAT fail bin, such as BIN3. If a semiconductor device passes the DPAT test, it is stored in the corresponding pass bin, such as BIN1, thus obtaining the final good product selected from this test.

[0081] Another embodiment of this disclosure relates to a semiconductor device testing apparatus, such as... Figure 4 As shown, it includes:

[0082] The determination module 401 is used to determine the criterion limit for dynamic component average testing, including: obtaining semiconductor device samples based on a preset sampling method; performing continuous reliability testing on the semiconductor device samples; and obtaining the criterion limit for dynamic component average testing based on semiconductor device samples that fail the continuous reliability test.

[0083] Test module 402 is used to perform continuous reliability testing and dynamic component averaging testing on semiconductor devices based on criterion limits to obtain test results.

[0084] For a detailed implementation of the semiconductor device testing apparatus provided in this disclosure, please refer to the semiconductor device testing method provided in this disclosure, which will not be repeated here.

[0085] Compared with the prior art, the present invention first determines the criterion limit for dynamic component average testing through a determination module, and then performs continuous reliability testing and dynamic component average testing on semiconductor devices based on the criterion limit by a testing module to obtain test results. Furthermore, the determination module first obtains semiconductor device samples based on a preset sampling method, and then performs continuous reliability testing on the semiconductor device samples. Based on the semiconductor device samples that fail the continuous reliability test, the criterion limit for dynamic component average testing is obtained. This not only enables the continuous reliability testing and dynamic component average testing of semiconductor devices to be completed simultaneously in a single testing process without disrupting the logic, thus optimizing the testing process and improving testing efficiency, but also makes the testing conditions more stringent, resulting in higher quality and stronger reliability of the finally selected semiconductor devices.

[0086] Another embodiment of this disclosure relates to an electronic device, such as Figure 5 As shown, it includes:

[0087] At least one processor 501; and,

[0088] Memory 502 is communicatively connected to at least one processor 501; wherein,

[0089] The memory 502 stores instructions that can be executed by at least one processor 501, which enables the at least one processor 501 to perform the semiconductor device testing method described in the above embodiments.

[0090] The memory and processor are connected via a bus, which can include any number of interconnecting buses and bridges, connecting various circuits of one or more processors and memories. The bus can also connect various other circuits, such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and will not be described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over the wireless medium via an antenna, which further receives data and transmits it to the processor.

[0091] The processor manages the bus and general processing, and also provides various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory is used to store data used by the processor during operation.

[0092] Another embodiment of this disclosure relates to a computer-readable storage medium storing a computer program that, when executed by a processor, implements the semiconductor device testing method described in the above embodiments.

[0093] That is, those skilled in the art will understand that all or part of the steps in the methods described in the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0094] Those skilled in the art will understand that the above embodiments are specific implementations of this disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this disclosure.

Claims

1. A method for testing semiconductor devices, characterized in that, The testing method includes: Determining the criterion limit for dynamic component average testing includes: obtaining semiconductor device samples based on a preset sampling method; performing continuous reliability testing on the semiconductor device samples; and obtaining the criterion limit for dynamic component average testing based on semiconductor device samples that fail the continuous reliability testing. Based on the aforementioned criterion limit, continuous reliability testing and dynamic component averaging testing are performed on the semiconductor device to obtain the test results; The continuous reliability testing and dynamic component averaging testing of semiconductor devices based on the aforementioned criterion limit include: The semiconductor device is subjected to continuous reliability testing; Based on the aforementioned criterion limit, a dynamic component averaging test is performed on semiconductor devices that fail the continuous reliability test.

2. The test method according to claim 1, characterized in that, Before performing continuous reliability testing on the semiconductor device sample or the semiconductor device, the testing method further includes: Perform routine electrical performance tests on the semiconductor device sample or the semiconductor device; The continuous reliability test is performed on the semiconductor device samples or semiconductor devices that have passed the conventional electrical performance test.

3. The test method according to claim 1 or 2, characterized in that, The testing method also includes: The semiconductor devices corresponding to the test results of each stage of testing are categorized and stored.

4. The test method according to claim 1 or 2, characterized in that, The criterion limit for determining the average test value of dynamic parts specifically includes: The criterion limit for the dynamic component average test is determined based on a preset number of semiconductor device samples that fail the continuous reliability test.

5. The test method according to claim 1 or 2, characterized in that, The criterion limit for determining the average test value of dynamic parts specifically includes: Based on the preset sampling frequency and total number of samples, determine the number of thresholds for periodically updating the criterion limit; For each semiconductor device that passes the average test of the dynamic components for the specified threshold number of tests, a new semiconductor device sample is collected based on the sampling frequency and the total number of samples, so as to periodically update the criterion limit based on the new semiconductor device sample.

6. The test method according to claim 1 or 2, characterized in that, The criterion limit for determining the average test value of dynamic parts specifically includes: For each semiconductor device that passes the average test of the dynamic components, a new semiconductor device sample is collected to update the criterion limit in real time based on the new semiconductor device sample.

7. A semiconductor device testing apparatus, characterized in that, The testing apparatus includes: The determination module is used to determine the criterion limit for dynamic component average testing, including: obtaining semiconductor device samples based on a preset sampling method; performing continuous reliability testing on the semiconductor device samples; and obtaining the criterion limit for dynamic component average testing based on semiconductor device samples that fail the continuous reliability testing. The testing module is used to perform continuous reliability testing and dynamic component averaging testing on semiconductor devices based on the criterion limit, and obtain test results; The continuous reliability testing and dynamic component averaging testing of semiconductor devices based on the aforementioned criterion limit include: The semiconductor device is subjected to continuous reliability testing; Based on the aforementioned criterion limit, a dynamic component averaging test is performed on semiconductor devices that fail the continuous reliability test.

8. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the semiconductor device testing method according to any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the semiconductor device testing method according to any one of claims 1 to 6.

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