64-bit adder for realizing radix-4 Booth multiplier and its implementation method

Abstract

Embodiments of the present application provide a 64-bit adder for implementing a radix-4 Booth multiplier, and an implementation method, an operation circuit, and a chip thereof. The adder includes: a circuit for determining the bits corresponding to the 0th-63th bits of 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights, and compressing the partial products on the 0th-63th bits respectively to output two groups of 64-bit data; a carry adder with a carry chain, including: N carry modules, each carry module corresponding to multiple bits of the two 64-bit groups of data, a preprocessing unit for each carry module, for preprocessing multiple bits in the corresponding two 64-bit groups of data; a carry calculation unit, for generating a carry output for each bit corresponding to the nth carry module and an inter-stage carry parameter of the nth carry module; and a summation module electrically connected to the N carry modules to process the two 64-bit groups of data and obtain a corresponding summation result.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of circuits, and more particularly to a 64-bit adder for implementing a radix-4 Booth multiplier, an implementation method thereof, an operation circuit, and a chip. Background Art

[0002] Radix-4 Booth multipliers are commonly used in digital circuit design. For example, they are often used in complex logic chips such as central processing units (CPUs) and graphics processing units (GPUs). They are also commonly used in integrated design chips such as microcontroller units (MCUs) and field programmable gate arrays (FPGAs). Generally, multiplication can be divided into three steps: generating partial products, compressing the partial products into two row vectors, and finally adding the two row vectors. Radix-4 Booth encoding is often used to generate partial products, which can reduce the number of partial products in the multiplier by half.

[0003] Therefore, how to obtain the final calculation result based on the partial product in radix-4-Booth coding and thus improve the overall performance of the radix-4-Booth coding multiplier has become a technical problem that needs to be solved urgently. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a 64-bit adder for implementing a radix-4 Booth multiplier, and an implementation method, a computing circuit, and a chip thereof, to overcome all or part of the above technical deficiencies.

[0005] In a first aspect, an embodiment of the present application provides a 64-bit adder for implementing a radix-4 Booth multiplier, comprising:

[0006] The multi-way carry-save adder is used to determine the corresponding bits of 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights at bits 0-63, and compress the partial products at bits 0-63 respectively to output two groups of 64-bit data, wherein the number of carry-save adders used for compression at bits 0-63 is the sum of the number of partial products at the corresponding bits and the number of sign bits minus 2;

[0007] A carry adder with a carry chain, configured to add and sum the two groups of 64-bit data, the carry adder with a carry chain comprising:

[0008] N carry modules, each carry module corresponding to multiple bits of the two 64-bit groups of data, wherein the nth carry module is connected to the n-1th carry module to receive the inter-stage carry parameter output by the n-1th carry module, the multiplicand and the multiplier are 32-bit binary numbers, N is an integer less than or equal to 7, and n is an integer greater than 1 and less than or equal to N; each carry module includes a preprocessing unit and a plurality of carry calculation units, and one carry calculation unit corresponds to one bit of the two 64-bit groups of data; wherein the partial product is used to represent the product of the i+1th bit, the ith bit, and the i-1th bit of the multiplier and the multiplicand based on radix-4 Booth multiplication; i is an integer greater than or equal to 0 and less than or equal to 31;

[0009] The n-th carry module includes a preprocessing unit for preprocessing a plurality of bits in the corresponding two groups of 64-bit data;

[0010] The nth carry module comprises a plurality of carry calculation units, configured to perform calculations based on the preprocessing result and the inter-stage carry parameter of the n-1th carry module to generate a carry output for each bit corresponding to the nth carry module and the inter-stage carry parameter of the nth carry module;

[0011] A summation module is electrically connected to the N carry modules and is used to process the two 64-bit groups of data when the sign bit selection control signal of the two 64-bit groups of data is a valid bit, wherein the processing includes: inverting the highest bit of the partial product of the two 64-bit groups of data, adding 1 to the highest bit of the first partial product, and adding 1 bit before the highest bit of all partial products, and the bit number is 1; and performing an operation based on each bit in the two 64-bit groups of data after processing and the corresponding carry output to obtain a corresponding summation result; wherein the sign bit selection control signal is used to indicate that the partial product is a negative multiple of the multiplicand.

[0012] In a second aspect, the present application provides a method for implementing a 64-bit adder for implementing a radix-4 Booth multiplier, comprising:

[0013] Receive 16 sets of 32-bit partial products with radix-4 Booth multiplication carry weights; the partial products are used to represent the products of the i+1th bit, the ith bit, and the i-1th bit of the multiplier and the multiplicand based on radix-4 Booth multiplication; i is an integer greater than or equal to 0 and less than or equal to 31;

[0014] Determine the corresponding bits of 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights at bits 0-63, compress the partial products at bits 0-63 respectively, and output two groups of 64-bit data; the number of carry-save adders used for compression at bits 0-63 of the multi-way carry-save adder is the sum of the number of partial products at the corresponding bits and the number of sign bits minus 2;

[0015] Dividing the two compressed 64-bit data groups into N data groups in descending order of bit positions, each data group including multiple bits from the two 64-bit data groups, where N is an integer less than or equal to 7; wherein the partial product is used to represent the product of the i+1th bit, the ith bit, and the i-1th bit of the multiplier and the multiplicand based on radix-4 Booth multiplication; and i is an integer greater than or equal to 0 and less than or equal to 31;

[0016] Preprocessing the multiple bits contained in each data group;

[0017] Calculating carry outputs of multiple bits contained in each data group, wherein for an nth data group among the N data groups, performing an operation based on the preprocessing result of the nth data group and the inter-stage carry parameter of the (n-1)th data group to generate a carry output for each bit corresponding to the nth data group and an inter-stage carry parameter of the nth carry module, where n is an integer greater than 1 and less than or equal to N;

[0018] When the sign bit selection control signal of the two 64-bit data groups is a valid bit, processing the partial products of the two 64-bit data groups, the processing comprising: inverting the highest bit of the partial products in the two 64-bit data groups, adding 1 to the highest bit of the first partial product, and adding 1 bit before the highest bit of all partial products, where the bit number is 1; wherein the sign bit selection control signal is used to indicate that the partial product is a multiplication of the multiplicand by a negative multiple;

[0019] An operation is performed based on each bit in the two groups of 64-bit data after processing and the corresponding carry output to obtain a corresponding summation result.

[0020] In a third aspect, the present application provides an arithmetic circuit, which includes an adder provided according to any embodiment of the first aspect.

[0021] In a fourth aspect, the present application provides a chip, which includes an arithmetic circuit provided according to any embodiment of the second aspect. The embodiment of the present application provides a 64-bit adder for implementing a radix-4 Booth multiplier and its implementation method, arithmetic circuit and chip. Since the multi-way carry-save adder is used to determine the bits corresponding to the 0th to 63rd bits of 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights, and compresses the partial products on the 0th to 63rd bits respectively, and outputs two groups of 64-bit data; a carry adder with a carry chain is used to add and sum the two groups of 64-bit data, and the carry adder with a carry chain includes N carry modules, each carry module corresponds to multiple bits in the two groups of 64-bit data, and each carry module includes a preprocessing unit and multiple carry calculation units, the nth carry module includes a preprocessing unit for preprocessing multiple bits in the corresponding two groups of 64-bit data, and the nth carry module includes multiple The carry calculation unit is used to perform calculations based on the preprocessing result and the inter-stage carry parameter of the n-1th carry module to generate the carry output of each bit corresponding to the n-th carry module and the inter-stage carry parameter of the n-th carry module. This allows each carry calculation unit in the n-th carry module to directly use the preprocessing result and the inter-stage carry parameter output by the n-1th carry module to parallelly calculate the carry output of each corresponding bit when the inter-stage carry parameter output by the n-1th carry module is obtained. This basically achieves the parallel calculation of the carry output of each bit in the partial product for use in the summation operation, thereby shortening the duration of the entire calculation process and improving the calculation speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Hereinafter, some specific embodiments of the present application will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0023] Figure 1 A schematic diagram illustrating the principle of a 64-bit adder for implementing a radix-4 Booth multiplier for summing 16 groups of 16-bit data, provided in an embodiment of the present application;

[0024] Figure 2 A schematic diagram of the structure of a carry adder with a carry chain in a 64-bit adder for implementing a radix-4 Booth multiplier provided in an embodiment of the present application;

[0025] Figure 3A circuit diagram of a first pre-processing unit in a carry module of a carry adder with a carry chain in a 64-bit adder for implementing a radix-4 Booth multiplier provided in an embodiment of the present application;

[0026] Figure 4 A circuit diagram of a second pre-processing unit in a carry module of a carry adder with a carry chain in a 64-bit adder for implementing a radix-4 Booth multiplier provided in an embodiment of the present application;

[0027] Figure 5 A schematic flowchart of a method for implementing a 64-bit adder for implementing a radix-4 Booth multiplier provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The specific implementation of the embodiment of the present invention is further described below with reference to the accompanying drawings of the embodiment of the present invention.

[0029] Example 1

[0030] Figure 1 A 64-bit addition method for implementing a radix-4 Booth multiplier is provided in an embodiment of the present application.

[0031] Schematic diagram of the principle of the device for summing 16 groups of 16-bit data. Each data is a partial product, which is used to represent the product of the i+1th bit, the ith bit and the i-1th bit of the multiplier and the multiplicand based on the radix-4 Booth multiplication; i is an integer greater than or equal to 0 and less than or equal to 31. Specifically, the multi-way carry-save adder is used to determine the corresponding bit positions of the 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights on the 0th to 63rd bits. Since the carry weights of the 16 groups of partial products are different, they are ranked according to the carry weights to form the following: Figure 1 The staggered arrangement shown. The multiple carry-save adders compress the partial products on bits 0-63 respectively and output two sets of 64-bit data. The number of carry-save adders used for compression on bits 0-63 is the sum of the number of partial products on the corresponding bits and the number of sign bits minus 2.

[0032] The embodiment of the present application provides a 64-bit addition method for implementing a radix-4 Booth multiplier.

[0033] The multi-way carry-save adder in the device is used to implement 8-2 data compression on 16 groups of 16-bit data and output two groups of 64-bit data. The number of carry-save adders corresponding to each bit of the 64-bit adder is the sum of the number of partial products of the corresponding bit and the number of sign bits minus 2. For example, the number of carry-save adders corresponding to bits 14-18 is 7, the number of carry-save adders corresponding to bit 15 is 6, the number of carry-save adders corresponding to bit 16 is 8, the number of carry-save adders corresponding to bit 17 is 7, and the number of carry-save adders corresponding to bit 18 is 9.

[0034] Figure 2 This is a schematic diagram of the structure of a carry adder with a carry chain in a 64-bit adder for implementing a radix-4 Booth multiplier provided in an embodiment of the present application. The carry adder with a carry chain in this embodiment can be an independent hardware circuit structure or a basic circuit unit structure of other devices such as a chip or microprocessor. Figure 2 As shown, the carry adder with a carry chain in a 64-bit adder for implementing a radix-4 Booth multiplier provided in an embodiment of the present application includes N carry modules 10, where N is an integer less than or equal to 7. Each carry module corresponds to multiple bits in two sets of 64-bit data, where the two sets of 64-bit data are 16-bit binary numbers. For example, a carry module can correspond to two bits, three bits, or more bits in the two sets of 64-bit data. It should be understood that the number of bits in the two sets of 64-bit data corresponding to each of the N carry modules 10 can be the same or different. The partial product is used to represent the product of the i+1th bit, the ith bit, and the i-1th bit of the multiplier and the multiplicand based on radix-4 Booth multiplication; i is an integer greater than or equal to 0 and less than or equal to 31.

[0035] The nth carry module is connected to the n-1th carry module to receive the inter-stage carry parameter output by the n-1th carry module, thereby calculating the inter-stage carry parameter of the nth carry module and the carry output of each bit corresponding to the nth carry module based on the inter-stage carry parameter output by the n-1th carry module. Wherein, n is an integer greater than 1 and less than or equal to N.

[0036] Each carry module includes a pre-processing unit and multiple carry calculation units, and one carry calculation unit corresponds to one bit of the two groups of 64-bit data.

[0037] In this embodiment, the preprocessing unit included in the n-th carry module is used to preprocess multiple bits in the corresponding two groups of 64-bit data.

[0038] Optionally, in one implementation of the present application, the preprocessing result includes: an intra-group carry generation signal and an intra-group carry propagation signal. The preprocessing unit included in the nth carry module is specifically configured to: operate on each bit in the corresponding two groups of 64-bit data to generate a carry generation signal and a carry propagation signal corresponding to each bit; and generate an intra-group carry generation signal and an intra-group carry propagation signal for each bit based on the carry generation signal and carry propagation signal of at least one corresponding bit.

[0039] Specifically, a logical AND operation is performed on each bit in the two corresponding 64-bit data sets to generate a carry generation signal for each bit. The carry generation signal is the result of the logical AND operation of the corresponding bit in the two 64-bit data sets. A logical OR operation is performed on each bit in the two corresponding 64-bit data sets to generate a carry propagate signal for each bit. The carry propagate signal is the result of the logical OR operation of the corresponding bit in the two 64-bit data sets. To facilitate the overall layout during circuit implementation, in the embodiments of the present application, the result of performing a logical NOT operation on the carry generation signal for each bit is sometimes referred to as the carry generation signal. Similarly, the result of performing a logical NOT operation on the carry propagate signal for each bit is referred to as the carry propagate signal.

[0040] After obtaining the carry generation signal and carry propagation signal for each bit corresponding to the nth carry module, the preprocessing unit included in the nth carry module can also perform a logical OR operation on the carry generation signals of multiple adjacent bits to generate an intra-group carry generation signal. The preprocessing unit included in the nth carry module can also perform a logical AND operation on the carry propagation signals of multiple adjacent bits to generate an intra-group carry propagation signal. To facilitate the overall layout during circuit implementation, in the embodiments of the present application, the result of performing a logical NOT operation on the intra-group carry generation signal is sometimes referred to as the intra-group carry generation signal. Similarly, the result of performing a logical NOT operation on the intra-group carry propagation signal is referred to as the intra-group carry propagation signal.

[0041] For example, for the first addend A and the second addend B The carry of the i-th bit generates a signal , the carry propagation signal of the i-th bit As mentioned above, in order to facilitate the overall layout of the circuit implementation, the carry generation signal and carry propagation signal of the i-th bit are sometimes expressed as or The carry signal from the jth bit to the ith bit is generated +…+ Intra-group carry propagation signal from the j-th bit to the i-th bit … As mentioned above, in order to facilitate the overall layout of the circuit implementation, the intra-group carry generation signal and carry propagation signal from the j-th bit to the i-th bit can sometimes also be expressed as and .

[0042] also, ,and, ,in, k is any bit between the jth bit and the ith bit in order from low to high.

[0043] In this embodiment, the nth carry module includes multiple carry calculation units, which are used to perform operations based on the preprocessing results and the inter-stage carry parameters of the n-1th carry module to generate the carry output of each bit corresponding to the nth carry module and the inter-stage carry parameters of the nth carry module.

[0044] Optionally, in one embodiment of the present application, each carry calculation unit included in the nth carry module is specifically used to perform operations based on the intra-group carry generation signal and intra-group carry propagation signal of the corresponding bit and the inter-stage carry parameter of the n-1th carry module to generate the carry output of the corresponding bit.

[0045] For the highest bit among the multiple bits corresponding to the nth carry module, the carry calculation unit corresponding to the highest bit is also used to use the carry parameter obtained in the calculation of the carry output of the highest bit corresponding to the nth carry module as the inter-stage carry parameter of the nth carry module.

[0046] The carry parameter is an intermediate quantity obtained during the calculation of the carry output of each bit, and there is a preset relationship between the carry parameter and the carry output. The carry output of each bit can be obtained by calculating the carry parameter of the bit and the carry propagation signal of the bit. Specifically, the carry output of each bit is the logical AND operation result of the carry parameter of the bit and the carry propagation signal of the bit. For example, if the carry output of the i-th bit is , the carry propagation signal of the i-th bit is P i , the carry parameter of the i-th bit is , then the default relationship is: .

[0047] If the highest bit among the multiple bits corresponding to the n-1th carry module is bits, then the multiple carry calculation units in the n-1th carry module calculate the Carry output of bits Get the carry parameter , as the n-1th inter-stage carry parameter. If the output result of the preprocessing unit of the nth carry module includes the intra-group carry generation signal and generate signals for carry within the group , then the carry output of the i-th bit is In addition, due to ,therefore, Also holds true.

[0048] because and It can be obtained by the preprocessing unit. Therefore, the carry calculation unit corresponding to the i-th bit in the n-th carry module obtains the inter-level carry parameter of the n-1-th carry module. When the nth carry module is used, the carry output or carry parameter of the i-th bit can be obtained through simple logical operations. In addition, because the preprocessing unit in the n-th carry module can preprocess the multiple bits corresponding to the n-th carry module to obtain the corresponding multiple intra-group carry generation signals and intra-group carry propagation signals, the multiple carry calculation units in the n-th carry module can calculate the carry output of each bit in parallel based on the corresponding intra-group carry generation signals and intra-group carry propagation signals, thereby improving the efficiency of carry calculation.

[0049] It should be understood that in order to facilitate the overall layout of the circuit implementation, the carry parameter and carry output Sometimes also expressed as and .

[0050] In an embodiment of the present application, since the preprocessing unit included in the nth carry module preprocesses multiple bits in the corresponding two groups of 64-bit data, the multiple carry calculation units included in the nth carry module are used to perform operations based on the preprocessing results and the inter-level carry parameters of the n-1th carry module to generate the carry output of each bit corresponding to the nth carry module and the inter-level carry parameters of the nth carry module. This allows each carry calculation unit in the nth carry module to directly use the preprocessing results and the inter-level carry parameters output by the n-1th carry module to parallel calculate the carry output of each corresponding bit when the inter-level carry parameters output by the n-1th carry module are obtained, thereby basically realizing the parallel calculation of the carry output of each bit in the 16-bit binary data.

[0051] In addition, if Figure 2As shown, the multi-way carry-save adder in the 64-bit adder for implementing a radix-4 Booth multiplier also includes a summation module, which is electrically connected to the N carry modules and is used to process the two 64-bit data groups when the sign bit selection control signal of the two 64-bit data groups is a valid bit. The processing includes: inverting the highest bit of all partial products of the multiplicand and the multiplier, adding 1 to the highest bit of the first partial product, and adding 1 bit before the highest bit of all partial products, where the bit number is 1; and performing an operation based on each bit in the two processed 64-bit data groups and the corresponding carry output to obtain a corresponding summation result. The sign bit selection control signal is used to indicate that the partial product is a negative multiple of the multiplicand.

[0052] For example, for the i-th bit in the first addend A and the second addend B, the sum of the i-th bit can be obtained according to the following summation formula. The formula is:

[0053]

[0054] in, It is the carry output of the i-1th bit in the first addend A and the second addend A.

[0055] In this embodiment, since the carry output of each bit in the 16-bit binary data is basically calculated in parallel, the sum result of each bit in the 16-bit binary data can be calculated basically in parallel, thereby shortening the duration of the entire calculation process and improving the calculation speed.

[0056] Optionally, in one embodiment of the present application, the number of bits in the two groups of 64-bit data corresponding to the nth carry module is equal to or greater than the number of bits in the two groups of 64-bit data corresponding to the (n-1)th carry module.

[0057] Because the calculation of the carry output for each bit corresponding to the nth carry module depends on the inter-stage carry parameter of the n-1th carry module, the carry operation time of each carry calculation unit in the nth carry module has a certain logical delay relative to the carry operation time of each carry calculation unit in the n-1th carry module. By ensuring that the number of bits in the two 64-bit data groups corresponding to the nth carry module is equal to or greater than the number of bits in the two 64-bit data groups corresponding to the n-1th carry module, this logical delay can be fully utilized to calculate the intra-group carry generation signal and the intra-group carry propagation signal, avoiding the situation where the nth carry module waits for the inter-stage carry parameter of the n-1th carry module during calculation, which helps further reduce the time consumed by calculation.

[0058] Optionally, in one embodiment of the present application, N is equal to 7, the first carry module corresponds to the 0th to 3rd bits of the two groups of 64-bit data, the second carry module corresponds to the 4th to 7th bits of the two groups of 64-bit data, the third carry module corresponds to the 8th to 15th bits of the two groups of 64-bit data, the fourth carry module corresponds to the 16th to 31st bits of the two groups of 64-bit data, the fifth carry module corresponds to the 32nd to 48th bits of the two groups of 64-bit data, the sixth carry module corresponds to the 49th to 58th bits of the two groups of 64-bit data, and the seventh carry module corresponds to the 50th to 63rd bits of the two groups of 64-bit data. Thus, the layout of the adder is more concentrated, the area is smaller, and it is conducive to the overall structural layout.

[0059] It should be understood that in this embodiment, the number N of carry modules may be 2, 4, or more, and the specific bits corresponding to each carry module may be set as needed, which is not limited in this embodiment.

[0060] Example 2

[0061] Based on the 64-bit adder for realizing the radix-4 Booth multiplier provided in the first embodiment, this embodiment further provides Figure 2 The diagram shows the structure of a carry module in a multi-way carry-save adder in a 64-bit adder for implementing a radix-4 Booth multiplier. It should be understood that this carry module can be any of the N carry modules in the first embodiment. For ease of description, this carry module will be referred to as the nth carry module below. In this embodiment, the preprocessing units included in the nth carry module include at least one first preprocessing unit and at least one second preprocessing unit arranged alternately.

[0062] In this embodiment, the first preprocessing unit is used to perform operations on the i-th bit and the i-1-th bit in the corresponding two groups of 64-bit data to generate a first preprocessing result, where the first preprocessing result indicates the logical OR operation result of the carry generation signals of the i-th bit and the i-1-th bit, where i is an odd number.

[0063] Optionally, in a specific implementation of the present application, Figure 3As shown, the first preprocessing unit includes: a first AND gate 201, a second AND gate 202, and a first NOR gate 203. The first input and the second input of the first AND gate 201 respectively receive the i-th bit, and the output of the first AND gate 201 is connected to the first input of the first NOR gate 203; the first input and the second input of the second AND gate 202 respectively receive the i-1-th bit, and the output of the second AND gate 202 is connected to the second input of the first NOR gate 203. The output of the first NOR gate 203 outputs the first preprocessing result. For example, if the first addend is A and the second addend is B, then the first preprocessing result is ,in, and A carry signal is generated for the i-th bit and a carry signal is generated for the i-1-th bit.

[0064] It should be understood that the first pre-processing unit may also be directly implemented by a structure such as an AND-NOR gate, and this embodiment does not limit this.

[0065] In this embodiment, the second preprocessing unit is used to perform operations on the j-th bit and the j-1-th bit in the corresponding two groups of 64-bit data to generate a second preprocessing result, where the second preprocessing result indicates the logical AND operation result of the carry propagation signals of the j-th bit and the j-1-th bit, where j is an even number.

[0066] Optionally, in a specific implementation of the present application, Figure 4 As shown, the second pre-processing unit includes: a first OR gate 301, a second OR gate 302 and a first NAND gate 303. The first input and the second input of the first OR gate 301 respectively receive the j-th bit, and the output of the first OR gate 301 is connected to the first input of the first NAND gate; the first input and the second input of the second OR gate 302 respectively receive the j-1-th bit, and the output of the second OR gate 302 is connected to the second input of the first NAND gate 303. The output of the first NAND gate 303 outputs the second pre-processing result. For example, if the first addend is A and the second addend is B, then the first pre-processing result is ,in, and is the carry propagation signal of the j-th bit and the carry propagation signal of the j-1-th bit.

[0067] It should be understood that the second pre-processing unit may also be directly implemented by a structure such as an OR-NAND gate, and this embodiment does not limit this.

[0068] Correspondingly, the nth carry module includes multiple carry calculation units, which are used to obtain the carry output of the corresponding bit based on at least one first preprocessing result and at least one second preprocessing result and the inter-stage carry parameter of the (n-1)th carry module.

[0069] Optionally, in one embodiment of the present application, the preprocessing unit included in the nth carry module further includes a third preprocessing unit and a fourth preprocessing unit, wherein the third preprocessing unit respectively operates on at least two adjacent first preprocessing results output by at least one first preprocessing unit and at least two adjacent second preprocessing results output by at least one second preprocessing unit to generate corresponding third preprocessing results and fourth preprocessing results, wherein the third preprocessing result indicates a carry parameter between corresponding adjacent multiple bits, and the fourth preprocessing result indicates a logical AND operation result of carry propagation signals of corresponding adjacent multiple bits. The nth carry module includes multiple carry calculation units for obtaining a carry output for the corresponding bit based on the third preprocessing result and the fourth preprocessing result and the inter-stage carry parameter of the (n-1)th carry module.

[0070] For example, the third preprocessing unit processes the first preprocessing result and And the second preprocessing result Perform the operation to generate the carry parameter GON_7_4= indicating the carry between the 4th bit and the 7th bit. The fourth preprocessing unit performs the second preprocessing based on the result of and the second preprocessing result Perform the operation to generate the logical OR operation result of the carry generation signal indicating the 3rd bit to the 6th bit, that is, an intra-group carry propagation signal (ie, PAN_6_3). The corresponding carry calculation unit can obtain the carry output of the 7th bit based on the third preprocessing result GON_7_4 and the fourth preprocessing result PAN_6_3 and the inter-stage carry parameter of the (n-1)th carry module.

[0071] Optionally, in one embodiment of the present application, the multiple carry calculation units included in the nth carry module include a first carry calculation unit corresponding to the i-th bit, and the first carry calculation unit includes a third OR gate, a third AND gate, and a second NOR gate;

[0072] A first input terminal of a third OR gate is connected to an output terminal of the corresponding second pre-processing unit, a second input terminal of the third OR gate is connected to an inter-stage carry parameter output by the (n-1)th carry module, an output terminal of the third OR gate is connected to a first input terminal of a third AND gate, a second input terminal of the third AND gate is connected to an output terminal of the corresponding first pre-processing unit, and an output terminal of the third AND gate outputs the carry parameter of the i-th bit;

[0073] The output end of the third AND gate is connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the carry propagation signal of the i-th bit, and the output end of the second NOR gate is connected to the summing module to output the carry output of the i-th bit to the summing module.

[0074] Optionally, in an embodiment of the present application, the multiple carry calculation units further include a second carry calculation unit corresponding to the j-th bit, and the second carry calculation unit includes a fourth OR gate and a second NAND gate.

[0075] The first input end of the fourth OR gate is connected to the output end of the corresponding second preprocessing unit, the second input end of the fourth OR gate is connected to the inter-stage carry parameter output by the n-1th carry module or the carry parameter of the j-1th bit, the output end of the fourth OR gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate receives the carry generation signal corresponding to the jth bit, and the output end of the second NAND gate is connected to the summation module to output the carry output of the jth bit to the summation module.

[0076] In this embodiment, since the first preprocessing unit, the second preprocessing unit, the third preprocessing unit and the fourth preprocessing unit in each carry module preprocess multiple bits in the two groups of 64-bit data corresponding to each carry module, each carry module includes multiple carry calculation units. This allows each carry module to obtain the inter-stage carry parameter output by the previous carry module. The multiple carry calculation units in each carry module can directly use the preprocessing result and the inter-stage carry parameter output by the previous carry module to parallel calculate the carry output of each corresponding bit, thereby basically realizing the parallel calculation of the carry output of each bit in the 16-bit binary data.

[0077] In the present application, the first carry module corresponds to the 0th to 3rd bits of the two groups of 64-bit data, the second carry module corresponds to the 4th to 7th bits of the two groups of 64-bit data, the third carry module corresponds to the 8th to 15th bits of the two groups of 64-bit data, the fourth carry module corresponds to the 16th to 23rd bits of the two groups of 64-bit data, and the fifth carry module corresponds to the 24th to 31st bits of the two groups of 64-bit data.

[0078] In addition, by regularly arranging the first preprocessing unit, the second preprocessing unit, the third preprocessing unit, the fourth preprocessing unit, the first carry calculation unit, and the second carry calculation unit, the computing speed of the 64-bit adder for implementing the radix-4 Booth multiplier can be improved while reducing the occupied area of ​​the 64-bit adder for implementing the radix-4 Booth multiplier, and the wiring is made more concentrated, which is conducive to the overall structured layout.

[0079] It should be noted that this application is used to illustrate a specific example of a carry chain of multiple carry-save adders in a 64-bit adder for implementing a radix-4 Booth multiplier provided in this embodiment. Depending on actual needs, the number of carry modules can be 2, 4, or more, and the specific bits corresponding to each carry module can be set as needed. This embodiment does not limit this.

[0080] Example 3

[0081] Based on the 64-bit adder for implementing a radix-4 Booth multiplier provided in the above embodiment, an embodiment of the present application provides a method for implementing a 64-bit adder for implementing a radix-4 Booth multiplier. Figure 5 Flowchart of a method for implementing a 64-bit adder for implementing a radix-4 Booth multiplier provided in an embodiment of the present application. Figure 5 As shown, the implementation method of the 64-bit adder for implementing the radix-4 Booth multiplier includes:

[0082] S501. Receive 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights; the partial products are used to represent the product of the i+1th bit, the ith bit, and the i-1th bit of the multiplier and the multiplicand based on radix-4 Booth multiplication; i is an integer greater than or equal to 0 and less than or equal to 31;

[0083] S502: Determine the corresponding bits of 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights at bits 0-63, compress the partial products at bits 0-63 respectively, and output two groups of 64-bit data; the number of carry-save adders used for compression at bits 0-63 of the multi-way carry-save adders is the sum of the number of partial products at the corresponding bits and the number of sign bits minus 2;

[0084] S503. Divide the two compressed 64-bit data groups into N data groups in order of bit from low to high, each data group including multiple bits from the two 64-bit data groups, where N is an integer less than or equal to 7; wherein the partial product is used to represent the product of the i+1th bit, the ith bit, and the i-1th bit of the multiplier and the multiplicand based on radix-4 Booth multiplication; and i is an integer greater than or equal to 0 and less than or equal to 31.

[0085] S504, preprocessing the multiple bits included in each data group;

[0086] S505. Calculate carry outputs for multiple bits included in each data group, wherein for an nth data group among the N data groups, perform an operation based on the preprocessing result of the nth data group and the inter-stage carry parameter of the (n-1)th data group to generate a carry output for each bit corresponding to the nth data group and an inter-stage carry parameter of the nth carry module, where n is an integer greater than 1 and less than or equal to N.

[0087] S506. When the sign bit selection control signal of the two 64-bit data sets is a valid bit, the two 64-bit data sets are processed, the processing comprising: inverting the highest bit of all partial products of the multiplicand and the multiplier, adding 1 to the highest bit of the first partial product, and adding one bit number before the highest bit of all partial products, where the bit number number is 1; wherein the sign bit selection control signal is used to indicate that the partial product is a negative multiple of the multiplicand;

[0088] S507 , performing an operation based on each bit in the two groups of 64-bit data after processing and the corresponding carry output to obtain a corresponding summation result.

[0089] The implementation method of the 64-bit adder for implementing a radix-4 Booth multiplier provided in the embodiment of the present application is used to implement the 64-bit adder for implementing a radix-4 Booth multiplier in the aforementioned device embodiment, and has the beneficial effects of the corresponding device embodiment, which will not be repeated here.

[0090] Example 4

[0091] The embodiment of the present application provides an arithmetic circuit, which includes a 64-bit adder for implementing a radix-4 Booth multiplier according to any one of the aforementioned embodiments 1 and 2. The principle and effect thereof are similar and will not be described in detail here.

[0092] Example 5

[0093] The embodiment of the present application provides a chip, which includes the arithmetic circuit provided according to the aforementioned embodiment 4. The principles and effects thereof are similar and will not be described in detail here.

[0094] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0095] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A 64-bit adder for implementing a radix-4 Booth multiplier, characterized in that The 64-bit adder for implementing a base-4 Booth multiplier comprises: a multi-way carry-save adder, configured to determine corresponding bits of 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights at bits 0-63, and to compress the partial products at bits 0-63 respectively, outputting two groups of 64-bit data, wherein the number of carry-save adders used for compression at bits 0-63 is the sum of the number of partial products at the corresponding bits and the number of sign bits minus 2; A carry adder with a carry chain, configured to add and sum the two groups of 64-bit data, the carry adder with a carry chain comprising: N carry modules, each carry module corresponding to multiple bits of the two 64-bit data groups, wherein the nth carry module is connected to the n-1th carry module to receive the inter-stage carry parameter output by the n-1th carry module, the multiplicand and the multiplier are 32-bit binary numbers, N is an integer less than or equal to 7, and n is an integer greater than 1 and less than or equal to N; each carry module includes a preprocessing unit and a plurality of carry calculation units, and one carry calculation unit corresponds to one bit of the two 64-bit data groups; wherein the partial product is used to represent the product of the i+1th bit, the ith bit, and the i-1th bit of the multiplier and the multiplicand based on base 4 Booth multiplication; i is an integer greater than or equal to 0 and less than or equal to 31; The n-th carry module includes a preprocessing unit for preprocessing a plurality of bits in the corresponding two groups of 64-bit data; The nth carry module comprises a plurality of carry calculation units, configured to perform calculations based on the preprocessing result and the inter-stage carry parameter of the n-1th carry module to generate a carry output for each bit corresponding to the nth carry module and the inter-stage carry parameter of the nth carry module; A summation module is electrically connected to the N carry modules and is used to process the two groups of 64-bit data when the sign bit selection control signal of the two groups of 64-bit data is a valid bit, wherein the processing includes: inverting the highest bit of the partial products of the two groups of 64-bit data, adding 1 to the highest bit of the first partial product, and adding 1 bit before the highest bit of all partial products, where the bit number is 1; and performing an operation based on each bit in the two groups of 64-bit data after processing and the corresponding carry output to obtain a corresponding summation result; wherein the sign bit selection control signal is used to indicate that the partial product is a multiplicand multiplied by a negative multiple.

2. The 64-bit adder for implementing a radix-4 Booth multiplier according to claim 1, wherein: N is equal to 7, the first carry module corresponds to the 0th to 3rd bits of the two groups of 64-bit data, the second carry module corresponds to the 4th to 7th bits of the two groups of 64-bit data, the third carry module corresponds to the 8th to 15th bits of the two groups of 64-bit data, the fourth carry module corresponds to the 16th to 31st bits of the two groups of 64-bit data, the fifth carry module corresponds to the 32nd to 48th bits of the two groups of 64-bit data, the sixth carry module corresponds to the 49th to 58th bits of the two groups of 64-bit data, and the seventh carry module corresponds to the 50th to 63rd bits of the two groups of 64-bit data.

3. The 64-bit adder for implementing a radix-4 Booth multiplier according to claim 2, wherein: The preprocessing results include: an intra-group carry generation signal and an intra-group carry propagation signal; The nth carry module includes a preprocessing unit, specifically configured to: operate on each bit in the corresponding two groups of 64-bit data to generate a carry generation signal and a carry propagation signal corresponding to each bit; and generate an intra-group carry generation signal and an intra-group carry propagation signal for each bit based on the carry generation signal and the carry propagation signal of the corresponding at least one bit; Each carry calculation unit included in the nth carry module is specifically used to perform calculations based on the intra-group carry generation signal and intra-group carry propagation signal of the corresponding bit and the inter-stage carry parameter of the n-1th carry module to generate a carry output of the corresponding bit.

4. The 64-bit adder for implementing a radix-4 Booth multiplier according to claim 3, wherein: The carry calculation unit of the highest bit corresponding to the nth carry module is also used to use the carry parameter obtained in the calculation of the carry output of the highest bit among the multiple bits corresponding to the nth carry module as the inter-stage carry parameter of the nth carry module, wherein the carry output of the highest bit is obtained by calculating the carry parameter of the highest bit and the carry propagation signal of the highest bit.

5. The 64-bit adder for implementing a radix-4 Booth multiplier according to claim 4, wherein: The preprocessing unit included in the n-th carry module includes at least one first preprocessing unit and at least one second preprocessing unit that are alternately arranged; The first preprocessing unit is configured to perform an operation on the i-th bit and the i-1-th bit in the corresponding two groups of 64-bit data to generate a first preprocessing result, where the first preprocessing result indicates a logical OR operation result of the carry generation signals of the i-th bit and the i-1-th bit, where i is an odd number; The second preprocessing unit is configured to perform an operation on the j-th bit and the j-1-th bit in the corresponding two groups of 64-bit data to generate a second preprocessing result, where the second preprocessing result indicates a logical AND operation result of the carry propagation signals of the j-th bit and the j-1-th bit, where j is an even number; The nth carry module includes multiple carry calculation units, which are used to obtain the carry output of the corresponding bit based on the first preprocessing result, the second preprocessing result and the inter-stage carry parameter of the (n-1)th carry module.

6. The 64-bit adder for implementing a radix-4 Booth multiplier according to claim 5, wherein: The multiple carry calculation units included in the nth carry module include a first carry calculation unit corresponding to the i-th bit, and the first carry calculation unit includes a third OR gate, a third AND gate, and a second NOR gate; A first input end of the third OR gate is connected to an output end of the corresponding second preprocessing unit or fourth preprocessing unit, a second input end of the third OR gate is connected to an inter-stage carry parameter output by the (n-1)th carry module, an output end of the third OR gate is connected to a first input end of the third AND gate, a second input end of the third AND gate is connected to an output end of the corresponding first preprocessing unit or third preprocessing unit, and an output end of the third AND gate outputs the carry parameter of the i-th bit; The output end of the third AND gate is connected to the first input end of the second NOR gate, the second input end of the second NOR gate receives the carry propagation signal of the i-th bit, and the output end of the second NOR gate is connected to the summation module to output the carry output of the i-th bit to the summation module.

7. The 64-bit adder for implementing a radix-4 Booth multiplier according to claim 6, wherein: The multiple carry calculation units include a second carry calculation unit corresponding to the j-th bit, and the second carry calculation unit includes a fourth OR gate and a second NAND gate; The first input end of the fourth OR gate is connected to the output end of the corresponding second preprocessing unit, the second input end of the fourth OR gate is connected to the inter-stage carry parameter output by the n-1th carry module or the carry parameter of the j-1th bit, the output end of the fourth OR gate is connected to the first input end of the second NAND gate, the second input end of the second NAND gate receives the carry generation signal corresponding to the jth bit, and the output end of the second NAND gate is connected to the summation module to output the carry output of the jth bit to the summation module.

8. A method for implementing a 64-bit adder for implementing a radix-4 Booth multiplier, characterized in that: include: Receive 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights; the partial products are used to represent the product of the i+1th bit, the ith bit, and the i-1th bit of the multiplier and the multiplicand based on radix-4 Booth multiplication; i is an integer greater than or equal to 0 and less than or equal to 31; Determine the corresponding bits of 16 groups of 32-bit partial products with radix-4 Booth multiplication carry weights on bits 0-63, compress the partial products on bits 0-63 respectively, and output two groups of 64-bit data; The number of carry-save adders used for compression on bits 0-63 of the multi-way carry-save adder is the sum of the number of partial products on the corresponding bit positions and the number of sign bits minus 2; Dividing the two compressed 64-bit data groups into N data groups in order of bits from low to high, each data group including multiple bits from the two 64-bit data groups, where N is an integer less than or equal to 7; Preprocessing the multiple bits contained in each data group; Calculating carry outputs of multiple bits contained in each data group, wherein for an nth data group among the N data groups, performing an operation based on the preprocessing result of the nth data group and the inter-stage carry parameter of the (n-1)th data group to generate a carry output for each bit corresponding to the nth data group and an inter-stage carry parameter of the nth carry module, where n is an integer greater than 1 and less than or equal to N; When the sign bit selection control signal of the two 64-bit data groups is a valid bit, processing the partial product of the two 64-bit data groups, the processing comprising: inverting the most significant bit of the partial product of the two 64-bit data groups, adding 1 to the most significant bit of the first partial product, and adding 1 bit before the most significant bit of all partial products, wherein the bit number is 1; wherein the sign bit selection control signal is used to indicate that the partial product is a multiplication of a multiplicand by a negative multiple; An operation is performed based on each bit in the two groups of 64-bit data after processing and the corresponding carry output to obtain a corresponding summation result.

9. An arithmetic circuit, characterized in that: The arithmetic circuit includes a 64-bit adder for realizing a radix-4 Booth multiplier according to any one of claims 1 to 7.

10. A chip, characterized in that: The chip includes the arithmetic circuit according to claim 9.

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