Storage system and method for operating the same

Abstract

The present invention discloses a storage system and an operation method thereof. The DDR5 DIMM in the system includes a first sub-channel; the first sub-channel includes a first group of data buffers and a first group of DRAM chips; the first group of data buffers (DB) is used to obtain first data and a first ECC code at a first rate through a first group of data buses, and is further used to store the first data and the first ECC code to the first group of DRAM chips at a second rate through a second group of data buses. The first group of data buffers includes a plurality of data buffers, the first group of DRAM chips includes a plurality of DRAM chip groups, the first group of data buses includes a plurality of host-side data buses, and the second group of data buses includes a plurality of storage-side data buses; the host-side data buses, the data buffers, the storage-side data buses, and the DRAM chip groups are in one-to-one correspondence. The present invention supports the chipkill ECC function, and has a small amount of chip usage, low cost, and low power consumption.

Description

Technical Field

[0001] The present invention belongs to the technical field of memories, and more particularly, relates to a storage system and an operation method thereof. Background Art

[0002] DDR5 is the abbreviation of the fifth generation of DDR SDRAM. The current Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) standard is applicable to DDR5 memories and provides a channel that can support Dual-in-line Memory Module (DIMM) devices, with a maximum rate of 3200 MHz or 6400 MT / s, and records data on both the rising and falling edges of the clock.

[0003] The term chipkill traditionally refers to the ability to correct multiple-bit errors in memory, where multiple-bit errors are the bus width of the memory device. For example, for a 4- or 8-bit wide SDRAM, a system that supports the chipkill function will be able to correct 4- or 8-bit wide errors in the memory device. Therefore, in a system that supports chipkill, a chip failure of the entire SDRAM organized in a ×4 or ×8 configuration will not cause the system to fail.

[0004] The goal of the DDR5 memory standard is to at least double the maximum rate of DDR4 to reach 6400 MT / s, or even 8400 MI / s, while ensuring high reliability and reducing costs and power consumption. However, the existing DDR4 / DDR5 hybrid DIMM does not have the chipkill function, error detection occupies a large storage overhead, and the number of chips that need to be activated for a single access is relatively large, resulting in the inability to meet the requirements of reliability, cost, and power consumption. Summary of the Invention

[0005] In view of the above deficiencies or improvement requirements of the prior art, the present invention provides a storage system and an operation method thereof, which have a bandwidth twice that of ordinary DDR5 DIMMs, support the chipkill ECC (Error Correcting Code) function, and have a small number of chips used, low costs, and low power consumption.

[0006] To achieve the above object, according to one aspect of the present invention, there is provided a DDR5 DIMM, including a first sub-channel; the first sub-channel includes a first group of data buffers and a first group of DRAM chips; the first group of data buffers is used to obtain first data and a first ECC code at a first rate through a first group of data buses, and is further used to store the first data and the first ECC code to the first group of DRAM chips at a second rate through a second group of data buses; the first group of data buffers includes a plurality of data buffers, the first group of DRAM chips includes a plurality of DRAM chip groups, the first group of data buses includes a plurality of host-side data buses, and the second group of data buses includes a plurality of storage-side data buses; the host-side data buses, the data buffers, the storage-side data buses, and the DRAM chip groups are in one-to-one correspondence.

[0007] In some embodiments, the first data includes a first part and a second part, and the first ECC code includes first ECC data and second ECC data; the first group of data buffers is used to obtain the first part and the first ECC data at the rising edge of the clock, and is further used to obtain the second part and the second ECC data at the falling edge of the clock; both the first part and the second part include a plurality of consecutive nibble data.

[0008] In some embodiments, all the DRAM chips in the first group are ×4 DRAM chips, and the lengths of both the first ECC data and the second ECC data are nibbles; each of the plurality of data buffers is used to obtain 2 nibble data in the first part or the first ECC data at the rising edge of the clock, and is further used to obtain 2 nibble data in the second part or the second ECC data at the falling edge of the clock, and is further used to store the 2 nibble data in the first part and the 2 nibble data in the second part obtained to the corresponding DRAM chip group, or store the obtained first ECC data and second ECC data to the corresponding DRAM chip group.

[0009] In some embodiments, each DRAM chip in the DRAM chip group stores 1 nibble data, or each DRAM chip in the DRAM chip group stores the first ECC data or the second ECC data.

[0010] In some embodiments, all the DRAM chips in the first group are ×8 DRAM chips, and the lengths of both the first ECC data and the second ECC data are one byte; each of the plurality of data buffers is used to obtain 2 nibble data in the first part or the first ECC data at the rising edge of the clock, and is further used to obtain 2 nibble data in the second part or the second ECC data at the falling edge of the clock, and is further used to store the 2 nibble data in the first part and the 2 nibble data in the second part obtained to the corresponding DRAM chip group, or store the obtained first ECC data and second ECC data to the corresponding DRAM chip group.

[0011] In some embodiments, two half-byte data in the first part are stored in one DRAM chip of the corresponding DRAM chip group, and two half-byte data in the second part are stored in another DRAM chip of the corresponding DRAM chip group; the first ECC data is stored in one DRAM chip of the corresponding DRAM chip group, and the second ECC data is stored in another DRAM chip of the corresponding DRAM chip group.

[0012] In some embodiments, the first sub-channel further includes a clock latch driver, the DDR5 DIMM further includes a second sub-channel having the same structure as the first sub-channel, and the clock latch driver is shared by the first sub-channel and the second sub-channel.

[0013] According to another aspect of the present invention, a storage system is provided, including a CPU, a memory controller, and the above-mentioned DDR5 DIMM.

[0014] According to still another aspect of the present invention, an operation method of a storage system is provided. The storage system includes a memory controller and a DDR5 DIMM. The operation method includes: determining whether the DDR5 DIMM supports the chipkill function; when the DDR5 DIMM supports the chipkill function, further determining whether the DDR5 DIMM is a ×4 DIMM; when the DDR5 DIMM is a ×4 DIMM, combining four consecutive data bits received into a half-byte data having the same data width as that of the DRAM, and performing RS(18, 16) code in the space of GF(2 4 ) to support the chipkill correction algorithm for 16 consecutive half-byte data, and generating two ECC data with a length of half-byte; when the DDR5 DIMM is a ×8 DIMM, combining two consecutive data half-bytes into a byte data having the same data width as that of the DRAM, and performing RS(10, 8) code in the space of GF(2 8 ) to support the chipkill correction algorithm for eight consecutive byte data, and generating two ECC data with a length of one byte.

[0015] In some embodiments, when the DDR5 DIMM is a ×4 DIMM, the 16 consecutive half-byte data and the two ECC data with a length of half-byte are respectively written into 18 ×4 DRAM chips; when the DDR5 DIMM is a ×8 DIMM, the eight consecutive byte data and the two ECC data with a length of one byte are respectively written into 10 ×8 DRAM chips.

[0016] Generally speaking, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects: It supports ×4 and ×8 configurations, allowing ×4 DDR4 / DDR5 DRAM chips and ×8 DDR4 / DDR5 DRAM chips to be used in high-end servers with chipkill reliability. In the ×4 DIMM configuration, the data bus width of each DRAM chip is 4 bits. Each access to each channel will activate 18 DRAM chips, including 16 data chips and 2 chips for reliability detection, with a relatively low storage overhead. By selecting a suitable ECC module for encoding and storing two ECC symbols in 2 4-bit DRAM chips, the chipkill error detection function can be achieved; in the ×8 DIMM configuration, the data bus width of each DRAM chip is 8 bits. Each access to each channel only needs to activate 10 DRAM chips. By selecting a suitable ECC module for encoding and storing two ECC symbols in 2 8-bit DRAM chips, the chipkill error detection function can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a computer system with D5-LRDIMM;

[0018] Figure 2 is a computer system with D5-HBDIMM;

[0019] Figure 3 is a schematic diagram of a sub-channel structure of D5-HBDIMM according to an embodiment of the present invention;

[0020] Figure 4 is when the MC writes data into the ×4 configuration Figure 3 schematic diagram of the sub-channel of the D5-HBDIMM shown;

[0021] Figure 5 is when the MC writes data into the ×8 configuration Figure 3 schematic diagram of the sub-channel of the D5-HBDIMM shown;

[0022] Figure 6 is a schematic diagram of the structure of Reed-Solomon code;

[0023] Figure 7 is a schematic diagram of the process of implementing chipkill in D5-HBDIMM according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary in nature and not restrictive.

[0025] The DDR host-to-memory module interface is 64-bit data plus 16-bit error correction code (ECC). This is a dual-channel system where the 64-bit data bus is divided into two sub-channels, each sub-channel containing 32-bit data and 8-bit ECC, and the sub-channel also includes a command / address interface.

[0026] Figure 1 There is a computer system 900, which includes a central processing unit (CPU) 910, a memory controller (MC) 920, and a DDR5 load-reduced DIMM (DDR5 Load Reduced DIMM, DDR5 LRDIMM or D5-LRDIMM) that meets the JEDEC standard. The D5-LRDIMM includes two sub-channels. Figure 1 Figure 1 shows one of the sub-channels 100 of the D5-LRDIMM. As Figure 1 shown, the sub-channel 100 includes five ×4 DRAM chip groups 141-145 (which together contain 20 ×4 DRAM chips), as well as five data buffers (DB) 111-115 and a registering clock driver (RCD) 130. Among them, the RCD 130 is shared by two sub-channels (the other sub-channel Figure 1 is not shown), the command / address bus 120 connects the MC 920 and the RCD 130, the first set of data buses 101-105 are between the external host interface of the sub-channel 100 and the DB 111-115, and the second set of data buses 121-125 are between the DB 111-115 and the ×4 DRAM chip groups 141-145. The two sets of data buses have the same data rate.

[0027] Define the DDR5 High Bandwidth DIMM (DDR5 HBDIMM or D5-HBDIMM) as a DDR5 DIMM with double speed, which uses slower but interleaved DDR4 DRAM chips or DDR5 DRAM chips. That is to say, low-cost DDR4 DRAM chips or DDR5 DRAM chips can be used to provide twice the bandwidth of a conventional DDR5-DIMM. For a ×4 DIMM, the number of DRAM chips on the two columns of the DIMM can be 36 and 40 respectively, and for a ×8 DIMM, the number of DRAM chips on the two columns of the DIMM can be 18 and 20 respectively.

[0028] Figure 2 A computer system 930 is given, which includes a CPU 940, an MC 950, and a D5-HBDIMM that meets the JEDEC standard. The D5-HBDIMM includes two sub-channels. Figure 2 One of the sub-channels 200 of the D5-HBDIMM is given. As Figure 2 shown, the sub-channel 200 includes 5 DRAM chip groups 241-245 (which contain a total of 20 or 18 DRAM chips), 5 High Bandwidth Data Buffers (HBDBs) 211-215, and a High Bandwidth Clock Latch Driver (HBRCD) 230. Among them, the HBRCD 230 is shared by the two sub-channels, the command / address bus 220 connects the MC 950 and the HBRCD 230, the first set of data buses 201-205 is between the external host interface of the sub-channel 200 and the HBDBs 211-215, and the second set of data buses 221-225 is between the HBDBs 211-215 and the DRAM chips 241-245. The second set of data buses 221-225 runs at half the data rate of the first set of data buses 201-205. For example, the data rate of the first set of data buses 201-205 is 6400MT / s, and the data rate of the second set of data buses 221-225 is 3200MT / s.

[0029] Figure 3 is a schematic diagram of the structure of a sub-channel (the first sub-channel) of the D5-HBDIMM according to an embodiment of the present invention. As Figure 3 shown, the first sub-channel 300 includes a first set of data buffers, a clock latch driver, and a first set of DRAM chips. In some embodiments, the first set of data buffers includes 5 High Bandwidth Data Buffers (HBDBs) 311-315, the clock latch driver includes a High Bandwidth Clock Latch Driver (HBRCD) 330, and the first set of DRAM chips includes 5 DRAM chip groups 341-345, which contain 20 ×8 DRAMs or 18 ×4 DRAM chips. The D5-HBDIMM also includes a second sub-channel ( Figure 3(not shown in the figure), the second sub-channel may have the same structure as the first sub-channel. Correspondingly, for example, the second sub-channel includes a second set of data buffers, a clock latch driver, and a second set of DRAM chips. Among them, the clock latch driver is shared by the first sub-channel and the second sub-channel. For the detailed situation of the second sub-channel, reference can be made to the first sub-channel, which will not be elaborated here.

[0030] The command / address bus 320 is connected to the MC ( Figure 3 (not shown in the figure) and the high-bandwidth clock latch driver 330. The first set of data buses 301 - 305 are between the external host interface and the high-bandwidth data buffers 311 - 315 of the first sub-channel 300. The second set of data buses 321 - 325 are between the high-bandwidth data buffers 311 - 315 and the DRAM chipset 341 - 345. The second set of data buses 321 - 325 operate at half the data rate of the first set of data buses 301 - 305. For example, if the data rate of the first set of data buses 301 - 305 is 6400 MT / s, then the data rate of the second set of data buses 321 - 325 is 3200 MT / s.

[0031] It should be understood that the storage system (or computer system) may include a CPU, an MC, and a D5-HBDIMM having the above-mentioned first sub-channel and second sub-channel. Among them, DIMM (Dual In-line Memory Module) is a module that contains multiple random access memory (RAM) chips on a small circuit board and stores the programs and data that the CPU needs to execute. The CPU manages and reads / writes the DIMM through the MC. The RCD is used for signal conditioning and mediates between the host and the DRAM.

[0032] Figure 4 It is the MC that writes data into the ×4 configuration of the Figure 3 Schematic diagram of the sub-channel of the D5-HBDIMM shown in the figure. As Figure 4As shown, the first sub-channel 300 includes five ×4 DRAM chip groups 341-345, specifically including the first ×4 DRAM chip group 341, the second ×4 DRAM chip group 342, the third ×4 DRAM chip group 343, the fourth ×4 DRAM chip group 344, and the fifth ×4 DRAM chip group 345. Each of the first to fourth ×4 DRAM chip groups 341-344 contains four ×4 DRAM chips, and the fifth ×4 DRAM chip group 345 contains two ×4 DRAM chips. The ×4 DRAM chip groups 341-345 altogether contain 18 ×4 DRAM chips. The first set of data buses 301-305 specifically includes the first host-side data bus 301, the second host-side data bus 302, the third host-side data bus 303, the fourth host-side data bus 304, and the fifth host-side data bus 305. The second set of data buses 321-325 specifically includes the first storage-side data bus 321, the second storage-side data bus 322, the third storage-side data bus 323, the fourth storage-side data bus 324, and the fifth storage-side data bus 325.

[0033] The first host-side data bus 301 connects the external host interface and the first high-bandwidth data buffer 311, and the first storage-side data bus 321 connects the first high-bandwidth data buffer 311 and the first ×4 DRAM chip group 341; the second host-side data bus 302 connects the external host interface and the second high-bandwidth data buffer 312, and the second storage-side data bus 322 connects the second high-bandwidth data buffer 312 and the second ×4 DRAM chip group 342; the third host-side data bus 303 connects the external host interface and the third high-bandwidth data buffer 313, and the third storage-side data bus 323 connects the third high-bandwidth data buffer 313 and the third ×4 DRAM chip group 343; the fourth host-side data bus 304 connects the external host interface and the fourth high-bandwidth data buffer 314, and the fourth storage-side data bus 324 connects the fourth high-bandwidth data buffer 314 and the fourth ×4 DRAM chip group 344; the fifth host-side data bus 305 connects the external host interface and the fifth high-bandwidth data buffer 315, and the fifth storage-side data bus 325 connects the fifth high-bandwidth data buffer 315 and the fifth ×4 DRAM chip group 345.

[0034] In a ×4 DIMM, the 64-bit data bus and 8-bit ECC are divided into two sub-channels, with 32 bits of data and 4 bits of ECC on each clock edge of each sub-channel. In an embodiment of the present invention, four consecutive bits on the data bus are defined as a nibble. On the rising edge of the clock, the external host interface of the first sub-channel 300 has 8 nibbles of data (N0, N1, …, N7) and one ECC nibble (ECC0); on the falling edge of the clock, the external host interface of the first sub-channel 300 has 8 data nibbles (N8, N9, ..., N15) and one ECC nibble (ECC1).

[0035] Taking the first high-bandwidth data buffer 311 as an example, at a rate of 6400MT / s, it acquires the data nibbles N0 and N1 from the first host-side data bus 301 on the rising edge of the clock DCK, and acquires the data nibbles N8 and N9 from the first host-side data bus 301 on the falling edge of the clock DCK, and after a fixed delay time Tpdm, it sends N0, N1, N8, and N9 together to 4 ×4 DRAM chips within the first ×4 DRAM chipset 341 at a rate of 3200MT / s, and each DRAM chip receives one data nibble. In some embodiments, Tpdm is between 1.1ns + tck / 4 and 1.62ns + tck / 4, where tck is the period of the clock DCK.

[0036] Similarly, the second high-bandwidth data buffer 312 acquires the nibble data N2 and N3 on the rising edge of the clock DCK, acquires the nibble data N10 and N11 on the falling edge of the clock DCK, and after a fixed delay time Tpdm, it sends N2, N3, N10, and N11 together to 4 ×4 DRAM chips within the second ×4 DRAM chipset 342, and each DRAM chip receives one data nibble. The third high-bandwidth data buffer 313 acquires the nibble data N4 and N5 on the rising edge of the clock DCK, acquires the nibble data N12 and N13 on the falling edge of the clock DCK, and after a fixed delay time Tpdm, it sends N4, N5, N12, and N13 together to 4 ×4 DRAM chips within the third ×4 DRAM chipset 343, and each DRAM chip receives one data nibble. The fourth high-bandwidth data buffer 314 acquires the nibble data N6 and N7 on the rising edge of the clock DCK, acquires the nibble data N14 and N15 on the falling edge of the clock DCK, and after a fixed delay time Tpdm, it sends N6, N7, N14, and N15 together to 4 ×4 DRAM chips within the fourth ×4 DRAM chipset 344, and each DRAM chip receives one nibble of data.

[0037] In an embodiment of the present invention, each nibble is defined as an ECC symbol. The MC generates Reed-Solomon (RS) codes for 16 consecutive data nibbles in a Galois Field (GF) to support the chipkill correction algorithm, generating two ECC nibbles. Specifically, for 16 consecutive nibble data, RS(18, 16) codes are generated in the GF(2 4 ) space to support the chipkill correction algorithm, and two ECC nibbles, ECC0 and ECC1, are generated.

[0038] The fifth high-bandwidth data buffer 315 obtains the nibble ECC0 from the fifth host-side data bus 305 at the rising edge of the clock DCK and obtains the nibble ECC1 from the fifth host-side data bus 305 at the falling edge of the clock DCK at a rate of 6400 MT / s. After a fixed delay time Tpdm, ECC0 and ECC1 are sent together to two ×4 DRAM chips within the fifth ×4 DRAM chipset 345 through the fifth storage-side data bus 325 at a rate of 3200 MT / s, and each DRAM chip receives one nibble ECC.

[0039] In some embodiments, the 18 ×4 DRAM chips within the chipset 341-345 are DDR4 DRAM chips. In some embodiments, the 18 ×4 DRAM chips within the DRAM chipset 341-345 are DDR5 DRAM chips.

[0040] In a ×4 DIMM configuration, the data bus width of each DRAM chip is 4 bits, and 18 DRAM chips are activated for each access of each channel. Since there are 16 data chips and 2 chips providing chipkill reliability in each channel, the error detection only incurs a 12.5% storage overhead. Compared with the prior art, the storage overhead generated by the error detection of the present invention is reduced by 12.5%, the number of DRAM chips is reduced, and chipkill reliability is provided.

[0041] Figure 5 It is a schematic diagram of a sub-channel of the D5-HBDIMM in the ×8 configuration where the MC writes data. As Figure 3 shown. Figure 5As shown, the first sub-channel 300 includes five ×8 DRAM chip groups 341-345, specifically including the first ×8 DRAM chip group 341, the second ×8 DRAM chip group 342, the third ×8 DRAM chip group 343, the fourth ×8 DRAM chip group 344, and the fifth ×8 DRAM chip group 345. Each of the first to fifth ×8 DRAM chip groups 341-345 contains four ×8 DRAM chips, and the ×8 DRAM chip groups 341-345 in total contain 20 ×8 DRAM chips.

[0042] In the ×8 DIMM, the 64-bit data bus and 16-bit ECC are divided into two sub-channels, and there are 32 bits of data and 8 bits of ECC at each clock edge of each sub-channel. At the rising edge of the clock, the external host interface connecting the first sub-channel 300 has 8 nibble data (N0, N1, …, N7) and one byte of ECC (ECC0). At the falling edge of the clock, the external host interface connecting the first sub-channel 300 has 8 nibble data (N8, N9, …, N15) and one byte of ECC (ECC1).

[0043] Taking the first high-bandwidth data buffer 311 as an example, at a rate of 6400MT / s, it obtains nibble data N0 and N1 from the first host-side data bus 301 at the rising edge of the clock DCK, and obtains nibble data N8 and N9 from the first host-side data bus 301 at the falling edge of the clock DCK. After a fixed delay time Tpdm, it sends N0 and N1 together to one ×8 DRAM chip within the first ×8 DRAM chip group 341 and sends N8 and N9 together to another ×8 DRAM chip within the first ×8 DRAM chip group 341 at a rate of 3200MT / s through the first storage-side data bus 321.

[0044] Similarly, the second highest bandwidth data buffer 312 acquires nibble data N2 and N3 at the rising edge of the clock DCK, acquires nibble data N10 and N11 at the falling edge of the clock DCK, and after a fixed delay time Tpdm, sends N2 and N3 together to an ×8 DRAM chip within the second ×8 DRAM chipset 342, and sends N10 and N11 together to another ×8 DRAM chip within the second ×8 DRAM chipset 342. The third highest bandwidth data buffer 313 acquires nibble data N4 and N5 at the rising edge of the clock DCK, acquires nibble data N12 and N13 at the falling edge of the clock DCK, and after a fixed delay time Tpdm, sends N4 and N5 together to an ×8 DRAM chip within the third ×8 DRAM chipset 343, and sends N12 and N13 together to another ×8 DRAM chip within the third ×8 DRAM chipset 343. The fourth highest bandwidth data buffer 314 acquires nibble data N6 and N7 at the rising edge of the clock DCK, acquires nibble data N14 and N15 at the falling edge of the clock DCK, and after a fixed delay time Tpdm, sends N6 and N7 together to an ×8 DRAM chip within the fourth ×8 DRAM chipset 344, and sends N14 and N15 together to another ×8 DRAM chip within the fourth ×8 DRAM chipset 344.

[0045] In an embodiment of the present invention, each byte is defined as an ECC symbol. The MC generates Reed-Solomon codes for 8 consecutive data bytes in the GF space to support the chipkill correction algorithm and generates two ECC bytes. Specifically, for 8 consecutive data bytes, RS(10, 8) codes are generated in the GF(2 8 ) space to support the chipkill correction algorithm, and two ECC bytes ECC0 and ECC1 are generated.

[0046] The fifth highest bandwidth data buffer 315 acquires one byte of ECC0 from the fifth host-side data bus 305 at the rising edge of the clock DCK at a rate of 6400 MT / s, acquires one byte of ECC1 from the fifth host-side data bus 305 at the falling edge of the clock DCK, and after a fixed delay time Tpdm, sends ECC0 and ECC1 together to 2 ×8 DRAM chips within the fifth ×8 DRAM chipset 345 at a rate of 3200 MT / s through the fifth memory-side data bus 325, and each DRAM chip receives one byte of ECC.

[0047] In some embodiments, the ×8 DRAM chipset 341-345 consists of 20 ×8 DDR4 DRAM chips. In some embodiments, the ×8 DRAM chipset 341-345 consists of 20 ×8 DDR5 DRAM chips.

[0048] In the ×8 DIMM configuration, the data bus width of each DRAM chip is 8 bits. For each access of each channel, only 10 DRAM chips need to be activated. By selecting a suitable ECC module for encoding and storing two ECC data in two ×8 DRAM chips respectively, the chipkill function can be achieved. Therefore, compared with the prior art, the present invention has chipkill reliability and lower power consumption.

[0049] Figure 6 It is a schematic structural diagram of a Reed-Solomon code, which includes: k original data symbols of m bits and 2t parity check symbols of m bits. n = k + 2t represents the total number of code symbols, and t represents the number of error symbols that can be corrected. In the ×4 D5-HBDIMM, m = 4, k = 16, t = 1, n = 18. In the ×8 D5-HBDIMM, m = 8, k = 8, t = 1, n = 10. Therefore, any single DRAM chip failure in the D5-HBDIMM of the embodiments of the present invention can be corrected, thereby realizing the chipkill function.

[0050] In some embodiments, in the ×4 D5-HBDIMM, two half-bytes of ECC0 and ECC1 can use the following encoding method to generate 2 4-bit parity check symbols:

[0051] ECC0 = N0 + N1 + … + N15;

[0052] ECC1 = α[1]*N0 + α[2]*N1 + … α

[16] *N15.

[0053] Where α[] is the corresponding Galois field over GF(2 4 )

[0054] In some embodiments, in the ×8 D5-HBDIMM, two bytes of ECC0 and ECC1 can use the following encoding method to generate 2 8-bit parity check symbols:

[0055] ECC0 = {N1, N0} + {N3, N2} + … + {N15, N14};

[0056] ECC1 = alpha[1]*{N1, N0} + alpha[2]*{N3, N2} + … + alpha[8]*{N15, N14}.

[0057] Among them, alpha[] is the corresponding Galois field over GF(2 8 ).

[0058] Figure 7 is a schematic flowchart of implementing chipkill in D5-HBDIMM according to an embodiment of the present invention. As Figure 7 shown, the method for implementing chipkill in D5-HBDIMM specifically includes the following steps:

[0059] Step S1: Initialize D5-HBDIMM;

[0060] Step S2: Read the configuration of D5-HBDIMM;

[0061] Step S3: According to the read configuration of D5-HBDIMM, determine whether D5-HBDIMM supports the chipkill function;

[0062] Step S4-1: When D5-HBDIMM supports the chipkill function, further determine whether D5-HBDIMM is a ×4 DIMM;

[0063] Step S4-2: When D5-HBDIMM does not support the chipkill function, use Hamming ECC encoding, the memory controller prepares to access the DIMM, and enter Step S6;

[0064] Step S5-1: When D5-HBDIMM is a ×4 DIMM, combine 4 consecutive data bits received into a nibble data with the same data width as that of DRAM, generate RS(18, 16) code in the GF(2 4 ) space to support the chipkill correction algorithm, generate two nibble ECCs, the memory controller prepares to access the DIMM, and enter Step S6;

[0065] Step S5-2: When D5-HBDIMM is not a ×4 DIMM, combine two consecutive data nibbles into a byte data with the same data width as that of DRAM, generate RS(10, 8) code in the GF(2 8 ) space to support the chipkill correction algorithm, generate two ECCs with a length of one byte, the memory controller prepares to access the DIMM, and enter Step S6;

[0066] Step S6: The memory controller accesses D5-HBDIMM.

[0067] Among them, when D5-HBDIMM supports the chipkill function, step S6 further includes the following steps:

[0068] Transmit the first data to the first sub-channel of the D5-HBDIMM at a first rate, where the first sub-channel includes a first group of data buffers and a first group of DRAM chips;

[0069] Transmit the second data to the second sub-channel of the D5-HBDIMM at a first rate, where the second sub-channel includes a second group of data buffers and a second group of DRAM chips;

[0070] The first group of data buffers and the second group of data buffers receive the first data and the second data respectively, and store the first data and the second data to the first group of DRAM chips and the second group of DRAM chips respectively at a second rate; each of the first group of DRAM chips and the second group of DRAM chips includes a plurality of DRAM chip groups.

[0071] Transmit the first ECC code to the first sub-channel of the D5-HBDIMM at a first rate;

[0072] Transmit the second ECC code to the second sub-channel of the D5-HBDIMM at a first rate;

[0073] The first group of data buffers and the second group of data buffers receive the first ECC code and the second ECC code respectively, and store the first ECC code and the second ECC code to the first group of DRAM chips and the second group of DRAM chips respectively at a second rate.

[0074] As mentioned above, the second sub-channel has the same structure as the first sub-channel. Taking the first sub-channel as an example, the above process of receiving and storing data will be described in detail below. The second sub-channel has the same process as the first sub-channel and will not be elaborated here.

[0075] Specifically, the first group of data buffers obtains the first data and the first ECC code from multiple host-side data buses at a first rate, and stores the first data and the first ECC code to multiple DRAM chip groups from multiple storage-side data buses at a second rate; among them, the host-side data buses, data buffers, storage-side data buses, and DRAM chip groups are in one-to-one correspondence.

[0076] In some embodiments, the first data includes a first part and a second part, and the first ECC code includes first ECC data and second ECC data. The first sub-channel obtains the first part of the first data and the first ECC data from a plurality of host-side data buses at the rising edge of the clock, and obtains the second part of the first data and the second ECC data from the plurality of host-side data buses at the falling edge of the clock. In some embodiments, after obtaining the first data and the first ECC code, the first sub-channel has a fixed delay time Tpdm, and then stores the first data and the first ECC code to a plurality of DRAM chip sets from the plurality of storage-side data buses at a second rate. In some embodiments, Tpdm is between 1.1 ns + tck / 4 and 1.62 ns + tck / 4, where tck is the period of the clock DCK.

[0077] In some embodiments, the second rate is half of the first rate. For example, the first rate is 6400 MT / s and the second rate is 3200 MT / s.

[0078] In some embodiments, D5-HBDIMM is a ×4 DIMM, the DRAM chip is a ×4 DRAM chip. Among the plurality of DRAM chip sets included in the first group of DRAM chips, one DRAM chip set has 2 DRAM chips, and the other DRAM chip sets each have 4 DRAM chips. The first ECC code is stored in the group where the 2 DRAM chips are located. In some embodiments, the first data includes a plurality of nibble data, the lengths of the first ECC data and the second ECC data are each a nibble, and the plurality of nibble data, the first ECC data, and the second ECC data are respectively stored in the DRAM chips of the first group of DRAM chips. That is to say, each of the nibble data, the first ECC data, and the second ECC data occupies one DRAM chip. In some embodiments, the first data includes 16 nibble data, the first group of DRAM chips includes 18 DRAM chips, and the 16 nibble data, the first ECC data, and the second ECC data are respectively stored in the 18 DRAM chips of the first group of DRAM chips. That is to say, each access to the sub-channel needs to activate 18 DRAM chips.

[0079] In some embodiments, the D5-HBDIMM is an ×8 DIMM, the DRAM chips are ×8 DRAM chips, and each of the multiple DRAM chip groups included in the first group of DRAM chips has 4 DRAM chips. The first ECC code is stored in one of the groups of DRAM chips. In some embodiments, the first data includes multiple nibble data, the lengths of the first ECC data and the second ECC data are each one byte, and every two of the multiple nibble data, the first ECC data, and the second ECC data are respectively stored in the DRAM chips of the first group of DRAM chips. That is to say, every two of the nibble data, the first ECC data, and the second ECC data each occupy one DRAM chip. In some embodiments, the first data includes 16 nibble data, the first group of DRAM chips includes 20 DRAM chips, and every two of the 16 nibble data, the first ECC data, and the second ECC data are respectively stored in 10 DRAM chips of the first group of DRAM chips.

[0080] That is to say, compared with the ×4 DIMM, each sub-channel of the ×8 DIMM has two more DRAM chips, but only 10 of them need to be activated each time the sub-channel is accessed. By generating a suitable ECC code and storing the data of the ECC code in two ×8 DRAM chips, chipkill error detection can be achieved, with high reliability. At the same time, since fewer chips are activated each time of access, the power consumption can be significantly reduced.

[0081] The above method can execute the chipkill algorithm according to the needs of the computer system user, further determine whether the D5-HBDIMM has the required number of ECC chips to perform the chipkill algorithm on the DRAM chips, and can switch between the chipkill algorithm and the Hamming ECC, being suitable for more application scenarios.

[0082] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.

[0083] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of this application, "a plurality of" means two or more unless specifically defined otherwise.

[0084] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more (two or more) executable instructions for implementing a specific logical function or process. And the scope of the preferred embodiments of this application includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in a reverse order according to the involved functions, rather than in the order shown or discussed.

[0085] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatuses, or devices.

[0086] It should be understood that various parts of this application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the method in the above embodiments can be completed by a program instructing relevant hardware. This program can be stored in a computer-readable storage medium. When this program is executed, it includes one or a combination of the steps of the method embodiments.

[0087] In addition, each functional unit in various embodiments of this application can be integrated into one processing module, or each unit can exist physically alone, or two or more units can be integrated into one module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the above integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. This storage medium can be a read-only memory, a magnetic disk, an optical disc, etc.

[0088] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various changes or substitutions thereof, and these should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A DDR5 DIMM, characterized in that, it includes a first sub-channel; the first sub-channel includes a first group of data buffers and a first group of DRAM chips; the first group of data buffers is used to obtain first data and a first ECC code at a first rate through a first group of data buses, the first data includes a first part and a second part, the first ECC code includes first ECC data and second ECC data, and the first ECC data and the second ECC data are generated by generating a Reed-Solomon code for the first data in the GF space; the first group of data buffers is used to obtain the first part and the first ECC data at the rising edge of the clock, and obtain the second part and the second ECC data at the falling edge of the clock, and both the first part and the second part include a continuous plurality of nibble data; the first group of data buffers is further used to store the first data and the first ECC code to the first group of DRAM chips at a second rate through a second group of data buses; the first group of data buffers includes a plurality of data buffers, the first group of DRAM chips includes a plurality of DRAM chip groups, the first group of data buses includes a plurality of host-side data buses, and the second group of data buses includes a plurality of storage-side data buses; the host-side data buses, the data buffers, the storage-side data buses, and the DRAM chip groups correspond one by one; the first ECC data and the second ECC data are respectively stored in different DRAM chips of a DRAM chip group.

2. The DDR5 DIMM according to claim 1, characterized in that, all of the first group of DRAM chips are ×4 DRAM chips, and the lengths of both the first ECC data and the second ECC data are nibbles; each of the plurality of data buffers is used to obtain 2 nibble data in the first part or the first ECC data at the rising edge of the clock, and is further used to obtain 2 nibble data in the second part or the second ECC data at the falling edge of the clock, and is further used to store the 2 nibble data in the first part and the 2 nibble data in the second part obtained to the corresponding DRAM chip group, or store the obtained first ECC data and second ECC data to the corresponding DRAM chip group.

3. The DDR5 DIMM according to claim 2, characterized in that, each DRAM chip in the DRAM chip group stores 1 nibble data, or each DRAM chip in the DRAM chip group stores the first ECC data or the second ECC data.

4. The DDR5 DIMM according to claim 1, characterized in that, The first group of DRAM chips are all ×8 DRAM chips, and the lengths of the first ECC data and the second ECC data are both one byte; each of the multiple data buffers is used to obtain 2 half-byte data or the first ECC data in the first part at the rising edge of the clock, and is also used to obtain 2 half-byte data or the second ECC data in the second part at the falling edge of the clock, and is further used to store the obtained 2 half-byte data in the first part and the 2 half-byte data in the second part into the corresponding DRAM chip group, or store the obtained first ECC data and second ECC data into the corresponding DRAM chip group.

5. The DDR5 DIMM according to claim 4, wherein, The 2 half-byte data in the first part are stored in one DRAM chip of the corresponding DRAM chip group, and the 2 half-byte data in the second part are stored in another DRAM chip of the corresponding DRAM chip group; the first ECC data are stored in one DRAM chip of the corresponding DRAM chip group, and the second ECC data are stored in another DRAM chip of the corresponding DRAM chip group.

6. The DDR5 DIMM according to any one of claims 1 to 5, wherein, The first sub-channel further includes a clock latch driver, the DDR5 DIMM further includes a second sub-channel, the second sub-channel has the same structure as the first sub-channel, and the clock latch driver is shared by the first sub-channel and the second sub-channel.

7. A storage system, wherein, comprises a CPU, a memory controller and the DDR5 DIMM according to any one of claims 1 to 6.

8. An operation method of a storage system, the storage system comprising a memory controller and a DDR5 DIMM, wherein, The operation method includes: Determine whether the DDR5 DIMM supports the chipkill function; When the DDR5 DIMM supports the chipkill function, further determine whether the DDR5 DIMM is a ×4 DIMM; When the DDR5 DIMM is a ×4 DIMM, combine the received 4 consecutive data bits into a nibble data with the same data width as that of the DRAM, and perform the RS(18,16) code in the GF(2 4 ) space on 16 consecutive nibble data and generate 2 ECC data with the length of a nibble to support the chipkill correction algorithm; When the DDR5 DIMM is a ×8 DIMM, two consecutive data half-bytes are combined into one byte of data with the same data width as that of the DRAM, and RS(10,8) codes in the GF(2 8 ) space are performed on 8 consecutive bytes of data and 2 bytes-long ECC data are generated to support the chipkill correction algorithm.

9. The operation method of the storage system according to claim 8, wherein, When the DDR5 DIMM is a ×4 DIMM, write the 16 consecutive half-byte data and the 2 half-byte-length ECC data into 18 ×4 DRAM chips respectively; when the DDR5 DIMM is a ×8 DIMM, write the 8 consecutive byte data and the 2 one-byte-length ECC data into 10 ×8 DRAM chips respectively.

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