Semiconductor structure and method of manufacturing the same, method of manufacturing a transistor device

Abstract

The application provides a semiconductor structure, a preparation method thereof and a preparation method of a transistor device. By forming a tensile stress material layer in the window, the diffusion of the metal in the metal layer in the substrate is limited to the right below the window under the action of the tensile stress material layer, the range of the lateral diffusion of the metal is reduced, and the metal is prevented from diffusing to the peripheral components. For example, in the preparation process of the transistor device, the problem that the metal in the metal silicide layer in the source-drain region laterally diffuses to the gate structure is avoided, and the device performance of the formed semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, as well as a method for fabricating transistor devices. Background Technology

[0002] In the field of semiconductor technology, metal silicide layers are widely used in various semiconductor devices. For example, in transistor devices, metal silicides are commonly used to reduce the contact resistance between the source / drain regions and conductive plugs. Currently, metal silicide layers are typically formed by the reaction of metal and silicon. However, with the development of semiconductor technology, semiconductor integrated circuits are trending towards higher integration levels, making it easy for metal silicide layers to diffuse and affect other components during and after fabrication. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor structure to solve the problem that metal in a metal silicide layer can easily diffuse into surrounding components.

[0004] To address the aforementioned technical problems, the present invention provides a method for fabricating a semiconductor structure, comprising: providing a substrate and forming a dielectric layer on the substrate, wherein a window is formed in the dielectric layer and the window exposes the substrate; forming a metal layer, wherein the metal layer at least covers the substrate exposed within the window; filling the window with a tensile stress material layer; and performing an annealing process to react the metal in the metal layer with the silicon in the substrate to form a metal silicide layer in the substrate.

[0005] Optionally, the side boundary of the metal silicide layer does not extend beyond the side boundary of the window.

[0006] Optionally, the thickness of the metal silicide layer decreases sequentially from the center of the window to the edge of the window.

[0007] Optionally, the cross-sectional shape of the metal silicide layer in the thickness direction is triangular.

[0008] Optionally, the tensile stress material layer may be made of silicon nitride.

[0009] Optionally, a doped region is also formed in the substrate, the doped region is exposed by an opening in the dielectric layer, and the metal silicide layer is formed on the doped region.

[0010] Optionally, the metal layer may be nitrided prior to the formation of the tensile stress material layer.

[0011] Optionally, a metal nitride layer may be formed on the metal layer prior to the formation of the tensile stress material layer.

[0012] Optionally, after performing the annealing process, the process further includes: sequentially removing the tensile stress material layer and the metal layer that has not reacted with the substrate, and forming a conductive plug in the window.

[0013] The present invention also provides a method for fabricating a transistor device, comprising: forming a gate structure on a substrate; forming source / drain regions in the substrate on the side of the gate structure; and performing the semiconductor structure fabrication method described above to form a metal silicide layer on the source / drain regions.

[0014] The present invention also provides a semiconductor structure comprising: a dielectric layer formed on a substrate, wherein an opening is formed in the dielectric layer; and a metal silicide layer formed on the substrate exposed within the opening, wherein the side boundary of the metal silicide layer does not extend beyond the side boundary of the opening.

[0015] Optionally, the thickness of the metal silicide layer decreases sequentially from the center of the window to the edge of the window.

[0016] Optionally, the cross-sectional shape of the metal silicide layer in the vertical direction is triangular.

[0017] Optionally, the semiconductor structure further includes a metal nitride layer and a conductive plug, wherein the metal nitride layer is located on the metal silicide layer and the conductive plug is located on the metal nitride layer.

[0018] In the semiconductor structure and its fabrication method provided by this invention, by forming a tensile stress material layer within the window, the diffusion tendency of the metal in the metal layer within the substrate is largely confined to directly below the window under the action of the tensile stress material layer on the substrate, reducing the range of lateral metal diffusion and thus preventing the diffused metal from affecting surrounding components. For example, in the fabrication of transistor devices, this avoids the problem of lateral diffusion of metal in the metal silicide layer in the source / drain region to the gate structure, which is beneficial to improving the device performance of the formed semiconductor structure. Furthermore, regarding the formed semiconductor structure, since the metal silicide layer is confined to the area within the window and does not extend beyond the window, the diffusion of metal within the metal silicide layer to surrounding components and the resulting adverse effects are avoided. Attached Figure Description

[0019] Figure 1 This is a schematic flowchart of a method for preparing a semiconductor structure according to an embodiment of the present invention.

[0020] Figures 2-6 This is a schematic diagram of the semiconductor structure in one embodiment of the present invention during its fabrication process.

[0021] Figure 7 This is a schematic diagram of the structure of a transistor device according to an embodiment of the present invention.

[0022] The accompanying figure is labeled as follows:

[0023] 10 / 100-substrate;

[0024] 20 / 200 - Dielectric layer;

[0025] 200a - Window opening;

[0026] 300 - Metal layer;

[0027] 400 - Tensile stress material layer;

[0028] 50 / 500 - Metal silicide layer;

[0029] 61-Metal nitride layer;

[0030] 62-Conductive plug;

[0031] 70-gate structure;

[0032] 81 - First doped region;

[0033] 82 - Second doped region. Detailed Implementation

[0034] The core concept of this invention is to provide a method for preparing a semiconductor structure. This method can effectively improve the problem of large-scale metal diffusion during and after the preparation of the metal silicide layer, which is beneficial to improving the device performance of the formed semiconductor structure.

[0035] For details, please refer to [link / reference]. Figure 1 As shown, the method for preparing the semiconductor structure provided by the present invention may include the following steps.

[0036] S100, a substrate is provided, and a dielectric layer is formed on the substrate, wherein a window is formed in the dielectric layer, the window exposing the substrate.

[0037] S200, forming a metal layer that at least covers the substrate exposed within the opening.

[0038] S300, a layer of tensile stress-filling material is placed inside the window.

[0039] S400, an annealing process is performed to react the metal in the metal layer with the silicon in the substrate to form a metal silicide layer in the substrate.

[0040] The following combination Figures 2-6 The semiconductor structure and its preparation method proposed in this invention will be further described in detail with reference to specific embodiments, wherein... Figures 2-6This is a schematic diagram of the semiconductor structure in one embodiment of the present invention during its fabrication process. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, used only to facilitate and clarify the illustration of the embodiments of the present invention. It should be understood that relative terms such as "above," "below," "top," "bottom," and "over" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described, for example, as being "above" another element would now be below that element.

[0041] In step S100, please refer to the following for details. Figure 2 As shown, a substrate 100 is provided, and a dielectric layer 200 is formed on the substrate 100. A window 200a is formed in the dielectric layer 200, and the window 200a exposes the substrate 100. In this embodiment, the bottom of the window 200a further extends into the substrate 100.

[0042] Furthermore, a doped region (not shown in the figure) may be formed in the substrate 100, and the window 200a in the dielectric layer 200 exposes at least a portion of the doped region.

[0043] In step 200, please refer to the following for details. Figure 3 As shown, a metal layer 300 is formed, which at least covers the substrate 100 exposed within the opening. The metal layer 300 can be formed using a deposition process, and it also covers the sidewalls of the opening 200a. That is, the metal layer 300 covers both the sidewalls and the bottom of the opening 200a. Furthermore, the material of the metal layer 300 may include, for example, cobalt.

[0044] In step S300, please refer to the following for details. Figure 4 As shown, a tensile stress material layer 400 is filled within the window 200a. The tensile stress material layer 400 can apply tensile stress to the substrate 100, thereby limiting the diffusion tendency of the metal in the metal layer 300 within the substrate to the maximum extent directly below the window 200a. In a specific example, the material of the tensile stress material layer 400 may include, for example, silicon nitride.

[0045] In this embodiment, the tensile stress material layer 400 fills the window 200a so that the tensile stress material layer 400 can apply a large tensile stress to the substrate 100 in the area corresponding to the window 200a, thereby improving the restraining effect on the metal diffusion trend.

[0046] Alternatively, the metal layer 300 may be nitrided before the tensile stress material layer 400 is formed. Or, a metal nitride layer may be formed on the metal layer 300 before the tensile stress material layer 400 is formed, followed by filling the tensile stress material layer 400 onto the metal nitride layer.

[0047] In step S400, please refer to the following for details. Figure 5 As shown, an annealing process is performed to react the metal in the metal layer 300 with the silicon in the substrate 100 to form a metal silicide layer 500 in the substrate 100. In this embodiment, the metal silicide layer 500 is formed on a doped region within the substrate 100.

[0048] It should be noted that during the annealing process, the metal diffuses within the substrate 10 and reacts with the silicon in the substrate to form a metal silicide layer 500 of a certain thickness. However, under the action of the tensile stress material layer 400, the diffusion trend of the metal within the substrate is maximally restricted to directly below the opening, reducing the range of lateral metal diffusion and thus preventing the metal from diffusing beyond a large area and affecting other components. For example, in a transistor device, a metal silicide layer can be formed in the source and drain regions. If, during the fabrication of the metal silicide layer, the metal undergoes a large-scale lateral diffusion and reaches the gate structure, it will cause a large leakage current problem in the formed transistor device, affecting device performance. The fabrication method provided in this embodiment can effectively improve the problem of metal diffusion to the gate structure.

[0049] Continue to refer to Figure 5 As shown, the side boundary of the metal silicide layer 500 does not extend beyond the side boundary of the window, that is, the lateral width of the metal silicide layer 500 is less than or equal to the lateral width of the window 200a. In this embodiment, the tensile stress material layer 400 fills the window 200a, and the stress intensity of the tensile stress material layer 400 on the substrate 100 decreases sequentially from the center to the edge of the window, thereby causing the metal in the metal layer 300 to diffuse mainly towards the central region of the window, and consequently causing the thickness of the formed metal silicide layer 500 to decrease sequentially from the center to the edge of the window. At this time, the cross-sectional shape of the formed metal silicide layer 500 in the thickness direction is, for example, triangular or triangular-like.

[0050] For further details, please refer to [link / reference]. Figure 6As shown, the method for fabricating the semiconductor structure further includes: sequentially removing the tensile stress material layer and the metal layer that has not reacted with the substrate, at which point the metal silicide layer 500 is exposed in the window 200a. Further, a conductive plug (not shown) can be formed in the window 200a, and the conductive plug is connected to the metal silicide layer 500. In this embodiment, a doped region is formed within the substrate 100, and the metal silicide layer 500 is formed within the doped region. The conductive plug is then connected to the doped region through the metal silicide layer 500, reducing the contact resistance between the conductive plug and the doped region. Furthermore, before forming the conductive plug, a metal nitride layer can be formed on the inner surface of the window, and the conductive plug is formed on the metal nitride layer.

[0051] Based on the preparation method described above, this embodiment also provides a semiconductor structure. For details, please refer to... Figure 6 As shown, the semiconductor structure includes a dielectric layer 200 formed on a substrate 100, in which an opening 200a is formed. It also includes a metal silicide layer 500 formed on the substrate exposed within the opening 200a. The side boundaries of the metal silicide layer 500 do not extend beyond the side boundaries of the opening 200a; that is, the metal silicide layer 500 is confined directly below the opening 200a and does not extend beyond the area of ​​the opening 200a. This prevents the metal within the metal silicide layer 500 from further laterally diffusing beyond a larger area and affecting other components.

[0052] In a specific example, the thickness of the metal silicide layer 500 decreases sequentially from the center of the window to the edge of the window, and the cross-sectional shape of the metal silicide layer 500 in the vertical direction is, for example, a triangle or a triangular-like shape.

[0053] Furthermore, a doped region (not shown) may be formed in the substrate 100, the doped region being at least partially exposed to the window 200a, and the metal silicide layer 500 being formed on the doped region. The semiconductor structure also includes a conductive plug (not shown), the conductive plug being formed in the window 200a and connecting to the doped region. Specifically, the conductive plug is connected to the doped region through the metal silicide layer 500, which helps to reduce the contact resistance between the conductive plug and the doped region. Alternatively, a metal nitride layer may also be formed on the metal silicide layer 500, and the conductive plug may be disposed on the metal nitride layer.

[0054] In addition, this embodiment also provides a method for fabricating a transistor device, which employs the semiconductor structure fabrication method described above to form a metal silicide layer in the source and drain regions of the transistor device.

[0055] For example, it can be combined Figure 7 As shown, the method for fabricating the transistor device includes: first, forming a gate structure 70 on a substrate 10; then, forming source / drain regions (including a first doped region 81 and a second doped region 82) in the substrate 10 on the side of the gate structure 70; and performing the semiconductor structure fabrication method described above to form a metal silicide layer 50 on the source / drain regions (the metal silicide layer 50 is specifically formed on the first doped region 81).

[0056] Specifically, the second doped region 82 in the source / drain region extends laterally from the end of the gate structure 70 to the side of the gate structure 70, the first doped region 81 is laterally connected to the second doped region 82, and the first doped region 81 is diffused deeper in the substrate relative to the second doped region 82. Furthermore, the doping concentration of the first doped region 81 is higher than the doping concentration of the second doped region 82.

[0057] Furthermore, during the formation of the dielectric layer 20, the dielectric layer 20 covers the gate structure 70 and the source / drain regions, and an opening is formed in the dielectric layer 20. The opening is located above the source / drain regions so that a portion of the source / drain regions is partially exposed to the opening. Specifically, the first doped region 81 in the source / drain regions is at least partially exposed to the opening, so that the metal silicide layer is formed on the first doped region 81.

[0058] Continue to refer to Figure 7 As shown, a metal silicide layer 50 is formed on the first doped region 81, and the metal silicide layer 50 extends to a predetermined depth in the first doped region 81.

[0059] As described above, the method for preparing the metal silicide layer 50 may include: first, forming a metal layer that at least covers the bottom surface of the opening to cover the substrate exposed in the opening; next, filling the opening with a tensile stress material layer, wherein the tensile stress material layer can completely fill the opening; next, performing an annealing process to react the metal in the metal layer with the silicon in the substrate to form the metal silicide layer 50 in the substrate; and then, removing the tensile stress material layer and the unreacted metal layer to release the space of the opening and expose the metal silicide layer 50. The material of the metal layer may include, for example, cobalt, and the material of the formed metal silicide layer 50 may include cobalt silicide.

[0060] In this embodiment, during the fabrication of the metal silicide layer 50, the stress exerted on the substrate by the tensile stress material layer is utilized to limit the metal diffusion tendency in the metal layer. This better confines the metal diffusion area directly below the opening, mitigating the problem of metal lateral diffusion to a large area and approaching the gate structure 70, effectively improving the issue of metal diffusion affecting the gate structure. In a specific example, the thickness of the formed metal silicide layer 50 can be controlled to decrease sequentially from the center to the edge of the opening. The resulting cross-sectional shape of the metal silicide layer 500 in the thickness direction is, for example, triangular or triangular-like.

[0061] Furthermore, the method for fabricating the transistor device further includes: forming a conductive plug 62 in the opening to connect the metal silicide layer 50. In a specific example, before forming the conductive plug 62, a metal nitride layer 61 is formed on the bottom and sidewalls of the opening, respectively covering the metal silicide layer 50. The conductive plug 62 is formed on the metal nitride layer 61 and fills the opening.

[0062] This embodiment also proposes a transistor device. (See reference...) Figure 7 The transistor device includes: a gate structure 70 formed on a substrate 10; and source / drain regions (including a first doped region 81 and a second doped region 82) formed in the substrate on the side of the gate structure. The source / drain regions are located on the side of the gate structure 70, and are typically electrically led out using conductive plugs 62. That is, the conductive plugs 62 are formed above the source / drain regions, and the bottom of the conductive plugs 62 extends into the substrate 10 to electrically connect to the source / drain regions.

[0063] Continue to refer to Figure 7 As shown, the transistor device further includes a metal silicide layer 50, which is located between the source / drain region and the conductive plug 62, and the maximum width of the metal silicide layer 50 is less than or equal to the width of the conductive plug 62. That is, the metal silicide layer 50 is formed on the contact surface of the source / drain region and extends into the source / drain region, and the bottom of the conductive plug 62 extends to the metal silicide layer 50, thereby electrically connecting the conductive plug 62 to the metal silicide layer 50. In this embodiment, the thickness of the metal silicide layer 50 decreases sequentially from the centerline of the conductive plug to its edge; for example, the cross-sectional shape of the metal silicide layer 50 in the vertical direction is triangular. Furthermore, a metal nitride layer 61 may also be disposed between the conductive plug 62 and the metal silicide layer 50.

[0064] Furthermore, the source / drain region includes a first doped region 81 and a second doped region 82. The doping concentration of the first doped region 81 is higher than that of the second doped region 82, and the second doped region 82 is closer to the gate structure 70 and extends below the gate structure 70. The first doped region 81 connects to the second doped region 82 and extends away from the gate structure 70.

[0065] In summary, the semiconductor structure fabrication method provided in this embodiment, by forming a tensile stress material layer within the opening, applies stress to the substrate using this tensile stress material layer. This limits the diffusion of metal in the metal layer within the substrate to the area directly below the opening, reducing the range of lateral metal diffusion and thus preventing the diffused metal from affecting surrounding components. For example, in the fabrication of transistor devices, this avoids the problem of lateral metal diffusion from the metal silicide layer in the source / drain regions to the gate structure.

[0066] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0067] It should also be understood that, unless otherwise specified or indicated, the terms "first," "second," "third," etc., used in the specification are merely for distinguishing individual components, elements, steps, etc., and are not for indicating logical or sequential relationships between individual components, elements, steps, etc. Furthermore, it should be recognized that the singular forms "a" and "an" used herein and in the appended claims include plural bases unless the context clearly indicates the opposite. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And the word "or" should be understood as having the definition of logical "or," not the definition of logical "exclusive or," unless the context clearly indicates the opposite. Furthermore, implementation of the methods and / or devices in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a dielectric layer is formed on the substrate, wherein a window is formed in the dielectric layer, the window exposing the substrate; A metal layer is formed, the metal layer at least covering the substrate exposed within the opening; A layer of tensile stress-filling material is placed inside the window; as well as, An annealing process is performed to react the metal in the metal layer with the silicon in the substrate to form a metal silicide layer in the substrate, wherein the side boundary of the metal silicide layer does not extend beyond the side boundary of the window.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The thickness of the metal silicide layer decreases sequentially from the center of the window to the edge of the window.

3. The method for preparing the semiconductor structure as described in claim 2, characterized in that, The cross-sectional shape of the metal silicide layer in the thickness direction is triangular.

4. The method for preparing the semiconductor structure according to claim 1, characterized in that, The tensile stress material layer is made of silicon nitride.

5. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The substrate also has doped regions formed therein, and the openings in the dielectric layer expose the doped regions, and the metal silicide layer is formed on the doped regions.

6. The method for preparing a semiconductor structure as described in claim 1, characterized in that, The metal layer is nitrided before the tensile stress material layer is formed.

7. The method for preparing a semiconductor structure as described in claim 1, characterized in that, A metal nitride layer is formed on top of the metal layer before the tensile stress material layer is formed.

8. The method for preparing a semiconductor structure according to any one of claims 1-7, characterized in that, After the annealing process, the following are also included: The tensile stress material layer and the metal layer that did not react with the substrate are removed sequentially, and a conductive plug is formed in the window.

9. A method for fabricating a transistor device, characterized in that, include: A gate structure is formed on a substrate; The source / drain regions are formed in the substrate on the side of the gate structure; as well as, Perform the method for fabricating a semiconductor structure as described in any one of claims 1-8 to form a metal silicide layer on the source / drain region.

10. A semiconductor structure, characterized in that, include: A dielectric layer is formed on a substrate, and windows are formed in the dielectric layer; A metal layer covering the substrate exposed within the opening; A metal silicide layer is formed on a substrate exposed within the opening, and the side boundaries of the metal silicide layer do not extend beyond the side boundaries of the opening. A tensile stress material layer is in direct contact with the upper surface of the metal layer away from the metal silicide layer.

11. The semiconductor structure as claimed in claim 10, characterized in that, The thickness of the metal silicide layer decreases sequentially from the center of the window to the edge of the window.

12. The semiconductor structure as claimed in claim 11, characterized in that, The cross-sectional shape of the metal silicide layer in the vertical direction is triangular.

13. The semiconductor structure as described in claim 10, characterized in that, It also includes a metal nitride layer and a conductive plug, wherein the metal nitride layer is located on the metal silicide layer and the conductive plug is located on the metal nitride layer.

Images