Switch capable of reducing parasitic inductance

Abstract

The present invention provides a switch capable of reducing parasitic inductance. The switch capable of reducing parasitic inductance includes a semiconductor element, a first top-layer wire, and a second top-layer wire. The second top-layer wire is used for electrically connecting a power input terminal and a current inflow end of the semiconductor element, and a first part of the first top-layer wire and a second part of the second top-layer wire are arranged adjacent to each other in parallel. When the semiconductor element is turned on, an input current flows out from the power input terminal and is divided into a first current and a second current. The first current and the second current respectively flow through the first part and the second part, and when the first current and the second current respectively flow through the first part and the second part, they are opposite to each other, so as to reduce a first superimposed parasitic inductance between the first top-layer wire and the second top-layer wire.

Description

Technical Field

[0001] The present invention relates to a switch capable of reducing parasitic inductance, and particularly to a switch capable of reducing parasitic inductance for a switching power supply circuit. Background Art

[0002] Figure 1 A circuit schematic diagram showing a typical buck-type switching power supply circuit 10 is presented. The buck-type switching power supply circuit 10 includes a control circuit 1 and a power stage circuit 2. As Figure 1 shown, the power stage circuit 2 includes an upper bridge switch 11, a lower bridge switch 12, and an inductor 13. The upper bridge switch 11 and the lower bridge switch 12 are switched according to an upper bridge signal UG and a lower bridge signal LG respectively, to convert an input voltage Vin into an output voltage Vout; and an inductor current IL is generated, which flows through the inductor 13 via a phase node PH to supply power to a load circuit 3.

[0003] Figure 2A A top view schematic diagram of the upper bridge switch 11 is shown. Figure 2B A cross-sectional schematic diagram of the upper bridge switch 11 taken along Figure 2A section line AA' is shown, and Figure 2C a cross-sectional schematic diagram of the upper bridge switch 11 taken along Figure 2A section line BB' is shown. Please refer to Figure 1 and Figure 2A - Figure 2B simultaneously. When the upper bridge switch 11 is turned on (i.e., the gate 117 of the semiconductor element 110 in the upper bridge switch 11 is electrically connected to a high-level voltage), an input current Iin flows out from a power input terminal 120 and is divided into sub-currents Iin11 and Iin12 as Figure 2B shown, where the sub-current Iin11 of the input current Iin flows from a metal wire 121 through a metal plug 122a and a metal wire 123a to a drain 119, and the sub-current Iin12 of the input current Iin flows from the metal wire 121 through a metal plug 122b and a metal wire 123b to a drain 119'. When the upper bridge switch 11 remains on, referring to Figure 1 and Figure 2C simultaneously, a conduction current Ic1 flows from the drain 119 through a channel formed in a semiconductor layer to a source 118, and then from the source 118 to a metal plug 127a, a metal wire 126, and a metal plug 125; and a conduction current Ic2 flows from the drain 119' through another channel formed in the semiconductor layer to a source 118', and then from the source 118' to a metal plug 127b, a metal wire 126, and a metal plug 125. The conduction currents Ic1 and Ic2 are combined into an inductor current IL, and the inductor current IL finally flows to the phase node PH via a metal wire 124.

[0004] As Figure 2AAs shown, in order to minimize the size of the upper bridge switch 11 to reduce manufacturing costs and improve operating efficiency, the metal wires 121 and 124 are arranged adjacent to each other and as close to each other as possible; however, according to Ampère's circuital law, when the upper bridge switch 11 is conducting, the directions of the input current Iin and the inductive current IL flowing through the parallel metal wires 121 and 124 are the same (viewed from above Figure 2A looking down, both the input current Iin and the inductive current IL flow from right to left, as indicated by the dashed hollow arrows in the figure), and the directions of the parasitic inductances generated by them are the same. After superposition, the slew rate of the upper bridge switch 11 will be limited.

[0005] In view of this, the present invention proposes a switch capable of reducing the parasitic inductance in metal wires. Summary of the Invention

[0006] In one aspect, the present invention provides a switch capable of reducing parasitic inductance, which includes: a semiconductor element for determining to electrically connect a current input end and a current output end therein according to a control voltage to conduct the semiconductor element; a first top wire for electrically connecting a power input end and the current input end; and a second top wire for electrically connecting the power input end and the current input end, wherein the second top wire and the first top wire are formed at the same height, and a first part of the first top wire and a second part of the second top wire are arranged parallel and adjacent to each other; wherein, when the semiconductor element is in a conducting operation, an input current flows out from the power input end and is divided into a first current and a second current; wherein, the first current and the second current respectively flow through the first part and the second part, and when the first current and the second current respectively flow through the first part and the second part, they are in opposite directions to reduce a first superimposed parasitic inductance of the first top wire and the second top wire.

[0007] In one embodiment, the switch capable of reducing parasitic inductance further includes: a third top wire for electrically connecting the current output end and a node; and a fourth top wire for electrically connecting the current output end and the node, wherein the fourth top wire and the third top wire are formed at the same height, and a third part of the third top wire and a fourth part of the fourth top wire are arranged parallel and adjacent to each other; wherein, when the semiconductor element is in the conducting operation, the input current flows out from the current output end and is divided into a third current and a fourth current; wherein, the third current and the fourth current respectively flow through the third part and the fourth part, and when the third current and the fourth current respectively flow through the third part and the fourth part, they are in opposite directions to reduce a second superimposed parasitic inductance of the third top wire and the fourth top wire.

[0008] In one embodiment, the third top wire and the second top wire are formed at the same height, and the third part of the third top wire and the second part of the second top wire are arranged adjacent to each other in parallel; wherein, when the third current and the second current flow through the third part and the second part respectively, they are opposite to each other, so as to reduce a third superimposed parasitic inductance between the third top wire and the second top wire.

[0009] In one embodiment, the switch capable of reducing parasitic inductance is an upper bridge switch in a buck switching power supply circuit.

[0010] In one embodiment, the switch capable of reducing parasitic inductance is a lower bridge switch in a boost switching power supply circuit.

[0011] In one embodiment, the semiconductor device is a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device.

[0012] In one embodiment, the LDMOS device includes: a well region having a first conductivity type, formed in a semiconductor layer; a body region having a second conductivity type, formed in the semiconductor layer, the body region being connected to the well region in a channel direction; a gate formed on the semiconductor layer, a part of the body region being located directly below the gate and connected to the gate to provide an inversion current channel for the semiconductor device during the on operation; and a source and a drain having the first conductivity type, the source and the drain being respectively located in the body region and the well region below different sides outside the gate, and in the channel direction, a drift region is located in the well region between the drain and the body region to serve as a drift current channel for the semiconductor device during the on operation.

[0013] In one embodiment, the first top wire, the second top wire, the third top wire and the fourth top wire are formed at the same height, and the power input terminal and the node are formed at the same height.

[0014] In one embodiment, the semiconductor device includes a first LDMOS device and a second LDMOS device, the first LDMOS device and the second LDMOS device share the same body region and the same body pole, and the first LDMOS device and the second LDMOS device are arranged mirror-symmetrically to each other.

[0015] In one embodiment, when viewed from a top view, the first top wire and the second top wire span respective well regions, the body region, the body pole, a gate, a source and a drain of the first LDMOS device and the second LDMOS device in a channel direction.

[0016] One advantage of the present invention is that the present invention can reduce the parasitic inductance in the metal wire.

[0017] The following will be described in detail through specific embodiments, and it will be easier to understand the purpose, technical content, features and achieved effects of the present invention. Brief Description of the Drawings

[0018] Figure 1 A circuit schematic diagram showing a known buck switching power supply circuit.

[0019] Figure 2A It is a top view schematic diagram of a semiconductor element used as an upper bridge switch in the power stage for a known buck switching power supply circuit.

[0020] Figure 2B Is Figure 2A A cross-sectional schematic diagram of the semiconductor element taken along the cutting line AA'.

[0021] Figure 2C Is Figure 2A A cross-sectional schematic diagram of the semiconductor element taken along the cutting line BB'.

[0022] Figure 3A It is a top view schematic diagram of a switch that can reduce parasitic inductance according to an embodiment of the present invention.

[0023] Figure 3B It is a top view schematic diagram of a switch that can reduce parasitic inductance according to an embodiment of the present invention.

[0024] Figure 3C Is Figure 3A A cross-sectional schematic diagram of the switch that can reduce parasitic inductance taken along the cutting line CC'.

[0025] Figure 3D Is Figure 3A A cross-sectional schematic diagram of the switch that can reduce parasitic inductance taken along the cutting line DD'.

[0026] Figure 3E Is Figure 3A A cross-sectional schematic diagram of the switch that can reduce parasitic inductance taken along the cutting line EE'.

[0027] Figure 3F Is Figure 3A A cross-sectional schematic diagram of the switch that can reduce parasitic inductance taken along the cutting line FF'.

[0028] Figure 4A It is a top view schematic diagram of a switch that can reduce parasitic inductance according to another embodiment of the present invention.

[0029] Figure 4BYes Figure 4A A schematic cross-sectional view of a switch with reduced parasitic inductance taken along the cutting line GG'.

[0030] Figure 4C Yes Figure 4A A schematic cross-sectional view of a switch with reduced parasitic inductance taken along the cutting line HH'.

[0031] Explanation of symbols in the figure

[0032] 1: Control circuit

[0033] 2: Power stage circuit

[0034] 3: Load circuit

[0035] 10: Buck switching power supply circuit

[0036] 11: High-side switch

[0037] 12: Low-side switch

[0038] 13: Inductor

[0039] 21, 31: Switches with reduced parasitic inductance

[0040] 110: Semiconductor component

[0041] 117: Gate

[0042] 118, 118’: Source

[0043] 119, 119’: Drain

[0044] 120: Power input terminal

[0045] 121, 123a, 123b, 124, 126, 223a1, 223a2, 223b1, 223b2, 226a, 226b, 323a2, 323b1: Metal wires

[0046] 122a, 122b, 125, 127a, 127b, 222a1, 222a2, 222b1, 222b2, 225a, 225b, 227a1, 227a2, 227b1, 227b2, 322a2, 322b1, 325a, 325b: Metal plugs

[0047] 210, 310: Semiconductor components

[0048] 211, 311: Substrates

[0049] 211’, 311’: Semiconductor layers

[0050] 211a, 311a: Upper surfaces

[0051] 211b, 311b: Lower surface

[0052] 212, 312: Well region

[0053] 212a, 212b, 312a, 312b: Drift region

[0054] 213a, 213a’, 313a, 313a’: Inversion region

[0055] 214, 214’, 314, 314’: Drift oxide region

[0056] 215, 315: Body region

[0057] 216, 316: Body electrode

[0058] 217, 217’, 317, 317’: Gate

[0059] 218, 218’, 318, 318’: Source

[0060] 219, 219’, 319, 319’: Drain

[0061] 220, 320: Power input terminal

[0062] 221a, 321a: First top layer wire

[0063] 221b, 321b: Second top layer wire

[0064] 224a, 324a: Third top layer wire

[0065] 224b, 324b: Fourth top layer wire

[0066] 2171, 2171’, 3171, 3171’: Dielectric layer

[0067] 2172, 2172’, 3172, 3172’: Conductive layer

[0068] 2173, 2173’, 3173, 3173’: Spacer layer

[0069] 2211: First part

[0070] 2212: Second part

[0071] 2213: Third part

[0072] 2214: Fourth part

[0073] Ic1, Ic2, Ic11, Ic12, Ic21, Ic22, Ic13, Ic31: Conducting current

[0074] Iin: Input current

[0075] Iin1: First current

[0076] Iin2: Second current

[0077] Iin3: Third current

[0078] Iin4: Fourth current

[0079] Iin11, Iin12, Iin13, Iin21, Iin22, Iin23, Iin31, Iin32, Iin41, Iin42: Sub - currents

[0080] IL: Inductor current

[0081] LG: Lower - bridge signal

[0082] LT1, LT2: Laterally - diffused metal - oxide - semiconductor (LDMOS) devices

[0083] PH: Phase node

[0084] UG: Upper - bridge signal

[0085] Vin: Input voltage

[0086] Vout: Output voltage Detailed implementation manners

[0087] Regarding the foregoing and other technical contents, features, and effects of the present invention, they will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. The drawings in the present invention are all schematic, mainly intended to show the process steps and the vertical order relationship between layers. As for the shape, thickness, and width, they are not drawn to scale.

[0088] Figure 3A And Figure 3B is a top - view schematic diagram of switch 21 that can reduce parasitic inductance according to an embodiment of the present invention. Figure 3C is Figure 3A a cross - sectional schematic diagram of switch 21 that can reduce parasitic inductance taken along section line CC'. Figure 3D is Figure 3A a cross - sectional schematic diagram of switch 21 that can reduce parasitic inductance taken along section line DD'. As Figure 3A and Figure 3B shown, and referring to Figure 3C and Figure 3D, the switch 21 capable of reducing parasitic inductance according to the present invention includes a semiconductor element 210, a first top wire 221a, and a second top wire 221b. Please refer to Figure 3A and Figure 3C , the first top wire 221a is used to electrically connect the power input terminal 220 to the current inflow terminal (such as the drains 219 and 219'). Please refer to Figure 3A and Figure 3D , the second top wire 221b is used to electrically connect the power input terminal 220 to the current inflow terminal (such as the drains 219 and 219'). In one embodiment, the second top wire 221b and the first top wire 221a are formed at the same height. In one embodiment, as Figure 3B shown, a first part 2211 of the first top wire 221a (such as but not limited to Figure 3B shown by the upper thick black long dotted line frame in Figure 3B ) and a second part 2212 of the second top wire 221b (such as but not limited to Figure 3B shown by the upper thick black dotted line frame in Figure 3B ) are arranged parallel and adjacent to each other.

[0089] As Figure 3A shown, when the semiconductor element 210 is in the on operation, the input current flows out from the power input terminal 220 and is divided into a first current Iin1 and a second current Iin2. The first current Iin1 and the second current Iin2 respectively flow through the first part 2211 and the second part 2212, and when the first current Iin1 and the second current Iin2 respectively flow through the first part 2211 and the second part 2212, they are opposite to each other. Therefore, the directions of the parasitic inductances generated by them are opposite, and after superposition, they can be roughly offset from each other, thereby reducing the first superimposed parasitic inductance of the first top wire 221a and the second top wire 221b, and further improving the operation conversion rate of the switch 21 capable of reducing parasitic inductance.

[0090] As Figure 3A shown, the switch 21 capable of reducing parasitic inductance according to the present invention further includes a third top wire 224a and a fourth top wire 224b. Figure 3E is Figure 3A a cross-sectional schematic view of the switch 21 capable of reducing parasitic inductance taken along the section line EE'. Please refer to Figure 3A and Figure 3E , the third top wire 224a is used to electrically connect the current outflow terminal (such as the sources 218 and 218') to the node (such as the phase node PH). Figure 3F is Figure 3A a cross-sectional schematic view of the switch 21 capable of reducing parasitic inductance taken along the section line FF'. Please refer to Figure 3A and Figure 3F, the fourth top wire 224b is used to electrically connect the current output terminals (such as source electrodes 218 and 218') to a node (such as phase node PH). In one embodiment, the fourth top wire 224b and the third top wire 224a are formed at the same height. As Figure 3A shown, the third part 2213 of the third top wire 224a (such as but not limited to Figure 3B the lower thick black long dotted line frame shown in Figure 3B ) is arranged adjacent and parallel to the fourth part 2214 of the fourth top wire 224b (such as but not limited to

[0091] the lower thick black dotted line frame shown in Figure 3A ). As Figure 3A shown, the third top wire 224a and the second top wire 221b are formed at the same height. In one embodiment, as Figure 3A shown, the third part 2213 of the third top wire 224a is arranged adjacent and parallel to the second part 2212 of the second top wire 221b. As Figure 3A shown, when the semiconductor element 210 is in the on operation, the third current Iin3 and the second current Iin2 flow through the third part 2213 and the second part 2212 respectively, and are in opposite directions to each other when flowing through the third part 2213 and the second part 2212 respectively, so as to reduce the third superimposed parasitic inductance between the third top wire 224a and the second top wire 221b. In one embodiment, the first top wire 221a, the second top wire 221b, the third top wire 224a and the fourth top wire 224b are formed at the same height, and the power input terminal 220 and a node (such as phase node PH) are formed at the same height. In one embodiment, the switch 21 capable of reducing the parasitic inductance may be the upper bridge switch in a buck switching power supply circuit. In another embodiment, the switch 21 capable of reducing the parasitic inductance may be the lower bridge switch in a boost switching power supply circuit.

[0092] Figure 3B is a top view schematic diagram showing the switch 21 capable of reducing the parasitic inductance according to an embodiment of the present invention. Figure 3BShows the parasitic inductance and its direction generated by the first current Iin1, the second current Iin2, the third current Iin3, and the fourth current Iin4 flowing through the first top wire 221a, the second top wire 221b, the third top wire 224a, and the fourth top wire 224b respectively. As Figure 3B As shown, when the foregoing currents flow through the respective top wires, the parasitic inductance generated can cancel out part of the parasitic inductance with each other. For example, for the two parts of the top wire in each of the following items, the parasitic inductance generated by each of them can more or less cancel each other out:

[0093] 1. The part of the first top wire 221a close to the power input terminal 220 and the part of the second top wire 221b close to the power input terminal 220;

[0094] 2. The part of the first top wire 221a far from the power input terminal 220 and the part of the second top wire 221b far from the power input terminal 220;

[0095] 3. The part of the third top wire 224a close to the phase node PH and the part of the fourth top wire 224b close to the phase node PH;

[0096] 4. The part of the third top wire 224a far from the phase node PH and the part of the fourth top wire 224b far from the phase node PH;

[0097] For the two parts of the top wire in each of the above items, the parasitic inductance generated by them can cancel each other out due to the opposite directions, thereby achieving the effect of reducing the parasitic inductance.

[0098] Please refer to Figure 3C , the switch 21 of the present invention capable of reducing parasitic inductance includes a semiconductor element 210, which is used to determine the current inflow end (such as the drains 219 and 219') and the current outflow end (such as the sources 218 and 218') electrically connected therein according to the control voltage to turn on the semiconductor element 210. As Figure 3CAs shown, the switch 21 capable of reducing parasitic inductance includes a semiconductor element 210. The semiconductor element 210 includes: lateral diffused metal oxide semiconductor (LDMOS) elements LT1 and LT2. The LDMOS element LT1 includes: a well region 212, a drift oxide region 214, a body region 215, a body electrode 216, a gate 217, a source 218, and a drain 219. The LDMOS element LT2 includes: a well region 212, a drift oxide region 214', a body region 215, a body electrode 216, a gate 217', a source 218', and a drain 219'. Among them, when the semiconductor element 210 is fabricated, the LDMOS elements LT1 and LT2 share the body region 215 and the body electrode 216, and the LDMOS elements LT1 and LT2 are arranged mirror-symmetrically with respect to each other to form the semiconductor element 210. Therefore, as Figure 3C shown, the source 218' is mirror-symmetric to the source 218, the gate 217' is mirror-symmetric to the gate 217, and so on.

[0099] In one embodiment, when viewed from a top view, the first top wire 221a, the second top wire 221b, the third top wire 224a, and the fourth top wire 224b span the well regions 212, the body regions 215, the body electrodes 216, the gates 217 and 217', the sources 218 and 218', and the drains 219 and 219' of the LDMOS element LT1 and the LDMOS element LT2 in the channel direction.

[0100] A semiconductor layer 211' is formed on a substrate 211. The semiconductor layer 211' has opposite upper surface 211a and lower surface 211b in the vertical direction (as indicated by the solid arrow direction in Figure 3C , the same below). The substrate 211 is, for example but not limited to, a P-type or N-type semiconductor substrate. The semiconductor layer 211' is formed on the substrate 211, for example, by an epitaxial process step, or a part of the substrate 211 is used as the semiconductor layer 211'. The manner of forming the semiconductor layer 211' is well-known to those skilled in the art and will not be elaborated here.

[0101] Please continue to refer to Figure 3C , the drift oxide regions 214 and 214' are respectively formed on the upper surface 211a and are respectively connected to the upper surface 211a, and are respectively located in the corresponding partial drift regions 212a and 212b (as Figure 3Cdirectly above the areas (as indicated by the dashed boxes in LDMOS components LT1 and LT2), and are respectively connected to the corresponding drift regions 212a and 212b. The drift oxide regions 214 and 214' are, for example but not limited to, local oxidation of silicon (LOCOS) structures as shown in the figure, and can also be shallow trench isolation (STI) structures or chemical vapor deposition (CVD) oxide structures.

[0102] The well region 212 has a first conductivity type, is formed in the semiconductor layer 211', and in the vertical direction, the well region 212 is located below the upper surface 211a and is connected to the upper surface 211a. The well region 212 is formed, for example, by at least one ion implantation process step. The body region 215 has a second conductivity type, is formed in the well region 212, and in the vertical direction, the body region 215 is located below the upper surface 211a and is respectively connected to the upper surface 211a. The body electrode 216 has a second conductivity type and is used as an electrical contact for the body region 215. In the vertical direction, the body electrode 216 is formed below the upper surface 211a and is connected to the corresponding body region 215 in the upper surface 211a. The gates 217' and 217 are respectively formed on the upper surface 211a of the semiconductor layer 211'. In the vertical direction, a part of the body region 215 is located directly below the gates 217' and 217 and is respectively connected to the gates 217' and 217 to respectively provide the inversion regions 213a' and 213a in the on-operation of the corresponding semiconductor components 210. The inversion regions 213a' and 213a are respectively located directly below the corresponding parts of the gates 217' and 217 and are respectively connected to the corresponding gates 217' and 217.

[0103] Please continue to refer to Figure 3C , the source electrodes 218' and 218 and the drain electrodes 219' and 219 have a first conductivity type. In the vertical direction, the source electrodes 218' and 218 and the drain electrodes 219' and 219 are respectively formed below the upper surface 211a and are respectively connected to the upper surface 211a. The source electrodes 218' and 218 and the drain electrodes 219' and 219 are respectively located in the body region 215 below the outside of the corresponding gates 217' and 217 in the channel direction (as indicated by the dashed arrow in the figure, the same below) and in the well region 212 away from the body region 215 side. In the channel direction, the drift regions 212b and 212a are respectively located between the corresponding drain electrodes 219' and 219 and the body region 215, in the well region 212 close to the upper surface 211a, and are used as drift current channels in the on-operation of the LDMOS components LT1 and LT2.

[0104] It should be noted that the so-called inversion regions 213a' and 213a refer to the regions where an inversion layer is formed under the corresponding gates 217' and 217 due to the voltages applied to the corresponding gates 217' and 217 during the conduction operation of the LDMOS elements LT2 and LT1, allowing the conduction current to pass through. These regions are located between the corresponding sources 218' and 218 and the corresponding drift regions 212b and 212a, which are well-known to those skilled in the art and will not be elaborated here. The same applies to other embodiments of the present invention.

[0105] It should be noted that the first conductivity type and the second conductivity type can be P-type or N-type. When the first conductivity type is P-type, the second conductivity type is N-type; when the first conductivity type is N-type, the second conductivity type is P-type.

[0106] It should be noted that the so-called drift current channel refers to the region where the conduction current passes through the semiconductor element 210 in a drifting manner during the conduction operation, which is well-known to those skilled in the art and will not be elaborated here.

[0107] It should be noted that in a preferred embodiment, the gates 217' and 217 respectively include corresponding dielectric layers 2171' and 2171 connected to the upper surface 211a, corresponding conductive layers 2172' and 2172 with conductivity, and corresponding spacer layers 2173' and 2173 with electrical insulation properties. Among them, the dielectric layers 2171' and 2171 are respectively formed on the body regions 215 and are respectively connected to the body regions 215. The conductive layers 2172' and 2172 are respectively used as the electrical contacts of the corresponding gates 217' and 217, are respectively formed on all the corresponding dielectric layers 2171' and 2171, and are respectively connected to the corresponding dielectric layers 2171' and 2171. The spacer layers 2173' and 2173 are respectively formed on both sides of the corresponding conductive layers 2172' and 2172 to serve as the electrical insulation layers on both sides of the corresponding gates 217' and 217. In one embodiment, in the LDMOS elements LT1 and LT2, the sources 218' and 218 and the body electrodes 216 are respectively electrically connected by a silicided metal layer (not shown in the figure).

[0108] In addition, it should be noted that the so-called high-voltage element (which can also be referred to as a semiconductor element as above) refers to an element where, during normal operation, the voltage applied to the drain is higher than a specific voltage, such as 5V, and the channel direction distance (the lengths of the drift regions 212b and 212a) between the body 215 and the corresponding drains 219' and 219 is adjusted according to the operating voltage borne during normal operation, so that it can operate at the aforementioned higher specific voltage. All of these are well-known to those skilled in the art and will not be elaborated here.

[0109] As Figure 3CAs shown, in the portion of the first top layer conductor 221a away from the power input terminal 220, the first current Iin1 is first divided into sub-currents Iin11 and Iin12. Among them, the sub-current Iin11 flows from the first top layer conductor 221a through the metal plug 222a1 and the metal wire 223a1 to the drain 219, while the sub-current Iin12 flows from the first top layer conductor 221a through the metal plug 222a2 and the metal wire 223a2 to the drain 219'. When the semiconductor element 210 remains conducting, referring to Figure 3C , the conducting current Ic11 flows from the drain 219 to the source 218 through the channel formed in the semiconductor layer, and the conducting current Ic12 flows from the drain 219' to the source 218' through another channel formed in the semiconductor layer.

[0110] Please refer to Figure 3D , in Figure 3D the embodiment shown, the semiconductor element 210 of this embodiment is similar to that of Figure 3C , so its detailed description is omitted. As Figure 3D shown, in the portion of the second top layer conductor 221b away from the power input terminal 220, the second current Iin2 is first divided into sub-currents Iin21 and Iin22. Among them, the sub-current Iin21 flows from the second top layer conductor 221b through the metal plug 222b1 and the metal wire 223b1 to the drain 219, while the sub-current Iin22 flows from the second top layer conductor 221b through the metal plug 222b2 and the metal wire 223b2 to the drain 219'. When the semiconductor element 210 remains conducting, referring to Figure 3D , the conducting current Ic21 flows from the drain 219 to the source 218 through the channel formed in the semiconductor layer, and the conducting current Ic22 flows from the drain 219' to the source 218' through another channel formed in the semiconductor layer.

[0111] Please refer to Figure 3E , in Figure 3E the embodiment shown, the semiconductor element 210 of this embodiment is similar to that of Figure 3C , so its detailed description is omitted. After the conducting current Ic11 flows from the drain 219 to the source 218, the sub-current Iin31 flows from the source 218 to the metal plug 227a1, the metal wire 226a, and the metal plug 225a. After the conducting current Ic12 flows from the drain 219' to the source 218', the sub-current Iin32 flows from the source 218' to the metal plug 227a2, the metal wire 226a, and the metal plug 225a. The sub-currents Iin31 and Iin32 are combined into the third current Iin3 at the metal plug 225a, and the third current Iin3 finally flows to the phase node PH through the third top layer conductor 224a.

[0112] Please refer to Figure 3F , inFigure 3F In the illustrated embodiment, the semiconductor element 210 of the present embodiment is similar to Figure 3C the embodiment of [], so its detailed description is omitted. After the conduction current Ic21 flows from the drain 219 to the source 218, the sub-current Iin41 flows from the source 218 to the metal plug 227b1, the metal wire 226b, and the metal plug 225b. After the conduction current Ic22 flows from the drain 219' to the source 218', the sub-current Iin42 flows from the source 218' to the metal plug 227b2, the metal wire 226b, and the metal plug 225b. The sub-currents Iin41 and Iin42 are combined into the fourth current Iin4 at the metal plug 225b, and the fourth current Iin4 finally flows to the phase node PH via the fourth top wire 224b.

[0113] Figure 4A FIG. [] is a top view schematic diagram of a switch 31 that can reduce parasitic inductance according to another embodiment of the present invention. The power input terminal 320, the first top wire 321a, the second top wire 321b, the third top wire 324a, the fourth top wire 324b, and the phase node PH of the present embodiment are similar to Figure 3A the power input terminal 220, the first top wire 221a, the second top wire 221b, the third top wire 224a, the fourth top wire 224b, and the phase node PH of the embodiment of [], so their detailed descriptions are omitted. The difference between the present embodiment and Figure 3A the embodiment of [] is that the present embodiment only includes the metal plugs 322a2, 322b1, 325a, and 325b.

[0114] Figure 4B is Figure 4A a cross-sectional schematic diagram of the switch 31 that can reduce parasitic inductance taken along the section line GG'. Figure 4C is Figure 4A a cross-sectional schematic diagram of the switch 31 that can reduce parasitic inductance taken along the section line HH'. As Figure 4A and Figure 3B shown, and referring to Figure 4B and Figure 4C , the switch 31 that can reduce parasitic inductance of the present invention includes a semiconductor element 310, a first top wire 321a, and a second top wire 321b. Please also refer to Figure 4A and Figure 4B , the first top wire 321a is used to electrically connect the power input terminal 320 to the current inflow end (such as the drain 319'). Please also refer to Figure 4A and Figure 4C , the second top wire 321b is used to electrically connect the power input terminal 320 to the current inflow end (such as the drain 319). In one embodiment, the second top wire 321b and the first top wire 321a are formed at the same height. In one embodiment, as Figure 4AAs shown, a first part of the first top layer wire 321a and a second part of the second top layer wire 321b are arranged adjacent to each other in parallel.

[0115] As Figure 4A shown, when the semiconductor element 310 is in the conducting operation, the input current flows out from the power input terminal 320 and is divided into a first current Iin1 and a second current Iin2. The first current Iin1 and the second current Iin2 respectively flow through the first part and the second part, and when the first current Iin1 and the second current Iin2 respectively flow through the first part and the second part, they are opposite to each other, so as to reduce the first superimposed parasitic inductance of the first top layer wire 321a and the second top layer wire 321b.

[0116] As Figure 4A shown, the switch 31 capable of reducing the parasitic inductance of the present invention further includes a third top layer wire 324a and a fourth top layer wire 324b. Please refer to Figure 4A , the third top layer wire 324a is used for electrically connecting the current output terminal (such as the source electrodes 318 and 318') and the node (such as the phase node PH). Please refer to Figure 4A , the fourth top layer wire 324b is used for electrically connecting the current output terminal (such as the source electrodes 318 and 318') and the node (such as the phase node PH). In an embodiment, the fourth top layer wire 324b and the third top layer wire 324a are formed at the same height. As Figure 4A shown, a third part of the third top layer wire 324a and a fourth part of the fourth top layer wire 324b are arranged adjacent to each other in parallel.

[0117] As Figure 4A shown, when the semiconductor element 310 is in the conducting operation, the input current flows out from the current output terminal (such as the source electrodes 318 and 318') and is divided into a third current Iin3 and a fourth current Iin4. The third current Iin3 and the fourth current Iin4 respectively flow through the third part and the fourth part, and when the third current Iin3 and the fourth current Iin4 respectively flow through the third part and the fourth part, they are opposite to each other, so as to reduce the second superimposed parasitic inductance of the third top layer wire 324a and the fourth top layer wire 324b. In an embodiment, as Figure 4A shown, the third top layer wire 324a and the second top layer wire 321b are formed at the same height. In an embodiment, as Figure 4A shown, a third part of the third top layer wire 324a and a second part of the second top layer wire 321b are arranged adjacent to each other in parallel. As Figure 4AAs shown, when the semiconductor element 310 is in the on operation, the third current Iin3 and the second current Iin2 flow through the third part and the second part respectively, in opposite directions to each other, so as to reduce the third superimposed parasitic inductance of the third top wire 324a and the second top wire 321b. In one embodiment, the first top wire 321a, the second top wire 321b, the third top wire 324a and the fourth top wire 324b are formed at the same height, and the power input terminal 320 and the node (such as the phase node PH) are formed at the same height. In one embodiment, the switch 31 capable of reducing the parasitic inductance may be the upper bridge switch in a buck switching power supply circuit. In another embodiment, the switch 31 capable of reducing the parasitic inductance may be the lower bridge switch in a boost switching power supply circuit.

[0118] Please refer to Figure 4B , the switch 31 capable of reducing the parasitic inductance of the present invention includes a semiconductor element 310, which is used to determine the current inflow end (such as the drain 319 or 319') and the current outflow end (such as the source 318 and 318') connected therein according to the control voltage, so as to turn on the semiconductor element 310. The semiconductor element 310 in this embodiment is similar to Figure 3C the semiconductor element 210, so its detailed description is omitted.

[0119] As Figure 4B shown, in the part of the first top wire 321a far from the power input terminal 320, the first current Iin1 directly enters the metal plug 322a2, and the sub-current Iin13 flows through the metal plug 322a2 and the metal wire 323a2 to the drain 319'. When the semiconductor element 310 remains on, referring to Figure 4B , the on-current Ic13 flows from the drain 319' to the source 318' through the channel formed in the semiconductor layer.

[0120] Please refer to Figure 4C , in Figure 4C the embodiment shown, the semiconductor element 310 in this embodiment is similar to Figure 4B the embodiment, so its detailed description is omitted. As Figure 4C shown, in the part of the second top wire 321b far from the power input terminal 320, the second current Iin2 directly enters the metal plug 322b1, and the sub-current Iin23 flows through the metal plug 322b1 and the metal wire 323b1 to the drain 319. When the semiconductor element 310 remains on, referring to Figure 4C , the on-current Ic31 flows from the drain 319 to the source 318 through the channel formed in the semiconductor layer.

[0121] It should be noted that one of the technical features by which the present invention is superior to the prior art is that: according to the present invention, with Figure 3BTaking the illustrated embodiment as an example, by using two top-layer conductors to transmit current in opposite directions respectively, and making a respective part of the two top-layer conductors adjacent and parallel to each other, the parasitic inductance caused by the current in the two top-layer conductors can be cancelled out due to the opposite directions, thereby achieving the effect of reducing the parasitic inductance.

[0122] The present invention has been described above with reference to the preferred embodiments. However, the above description is only for making those skilled in the art easily understand the content of the present invention, and is not used to limit the scope of the rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. In addition, the various embodiments described are not limited to being applied alone, but can also be combined and applied. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any embodiment of the present invention does not necessarily achieve all the purposes or advantages. Therefore, any item of the claims should not be limited thereto.

Claims

1. A switch capable of reducing parasitic inductance, comprising: A semiconductor element for determining, according to a control voltage, the electrical connection between a current inflow terminal and a current outflow terminal thereof to turn on the semiconductor element; A first top layer wire for electrically connecting a power input terminal and the current inflow terminal; and A second top layer wire for electrically connecting the power input terminal and the current inflow terminal, wherein the second top layer wire and the first top layer wire are formed at the same height, and a first part of the first top layer wire and a second part of the second top layer wire are arranged adjacent to each other in parallel; Wherein, When the semiconductor element is in a conduction operation, an input current flows out from the power input terminal and is divided into a first current and a second current; Wherein, the first current and the second current respectively flow through the first part and the second part, and when the first current and the second current respectively flow through the first part and the second part, they are opposite to each other to reduce a first superimposed parasitic inductance of the first top layer wire and the second top layer wire.

2. The switch capable of reducing parasitic inductance according to claim 1, Wherein, Further comprising: A third top layer wire for electrically connecting the current outflow terminal and a node; and A fourth top layer wire for electrically connecting the current outflow terminal and the node, wherein the fourth top layer wire and the third top layer wire are formed at the same height, and a third part of the third top layer wire and a fourth part of the fourth top layer wire are arranged adjacent to each other in parallel; Wherein, when the semiconductor element is in the conduction operation, a conduction current flows out from the current outflow terminal and is divided into a third current and a fourth current; Wherein, the third current and the fourth current respectively flow through the third part and the fourth part, and when the third current and the fourth current respectively flow through the third part and the fourth part, they are opposite to each other to reduce a second superimposed parasitic inductance of the third top layer wire and the fourth top layer wire.

3. The switch capable of reducing parasitic inductance according to claim 2, Wherein, The third top layer wire and the second top layer wire are formed at the same height, and the third part of the third top layer wire and the second part of the second top layer wire are arranged adjacent to each other in parallel; wherein, when the third current and the second current respectively flow through the third part and the second part, they are opposite to each other to reduce a third superimposed parasitic inductance of the third top layer wire and the second top layer wire.

4. The switch capable of reducing parasitic inductance according to claim 1, Wherein, The switch capable of reducing parasitic inductance is an upper bridge switch in a buck switching power supply circuit.

5. The switch capable of reducing parasitic inductance according to claim 1, Wherein, The switch capable of reducing parasitic inductance is a lower bridge switch in a boost switching power supply circuit.

6. The switch capable of reducing parasitic inductance according to claim 1, Wherein, The semiconductor element is a lateral diffused metal oxide semiconductor element.

7. The switch capable of reducing parasitic inductance according to claim 6, Wherein, The lateral diffused metal oxide semiconductor element includes: A well region having a first conductivity type, formed in a semiconductor layer; A body region, having a second conductivity type, is formed in the semiconductor layer, and the body region is connected to the well region in a channel direction; A gate is formed on the semiconductor layer, and a part of the body region is located directly below the gate and connected to the gate to provide an inversion current channel for the semiconductor device during the on operation; and A source and a drain, having the first conductivity type, the source and the drain are respectively located in the body region and the well region below different outer sides of the gate, and in the channel direction, a drift region is located in the well region between the drain and the body region for serving as a drift current channel for the semiconductor device during the on operation.

8. The switch capable of reducing parasitic inductance according to claim 2, wherein, The first top wire, the second top wire, the third top wire and the fourth top wire are formed at the same height, and the power input terminal and the node are formed at the same height.

9. The switch capable of reducing parasitic inductance according to claim 6, wherein, The semiconductor device includes a first laterally diffused metal oxide semiconductor device and a second laterally diffused metal oxide semiconductor device. The first laterally diffused metal oxide semiconductor device and the second laterally diffused metal oxide semiconductor device share the same body region and the same body pole, and the first laterally diffused metal oxide semiconductor device and the second laterally diffused metal oxide semiconductor device are arranged mirror images of each other.

10. The switch capable of reducing parasitic inductance according to claim 9, wherein, When viewed from a top view, the first part and the second part span a well region, the body region, the body pole, a gate, a source and a drain of the first laterally diffused metal oxide semiconductor device and the second laterally diffused metal oxide semiconductor device respectively in a channel direction.

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