Display device, display substrate and method for manufacturing the same

Abstract

The display device, the display substrate and the manufacturing method thereof belong to the technical field of display, and the display substrate comprises a substrate and a plurality of pixel units arranged on the substrate; the pixel unit comprises a pixel driving circuit; in at least part of the pixel driving circuit, the orthographic projection of the gate of at least two thin film transistors on the substrate at least partially overlaps, so that the occupied area of the thin film transistor can be effectively reduced, the number of thin film transistors arranged in the pixel unit can be increased, and the pixel requirement of the high-PPI display device can be met.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a display device, a display substrate, and a method for preparing the same. Background Technology

[0002] With the development of display technology, people have higher and higher requirements for display devices. For example, display products such as Organic Electroluminescence Display (OLED) and Liquid Crystal Display (LCD) are widely used in near-eye fields such as Virtual Reality (VR) and Augmented Reality (AR) due to their characteristics of being thin, light-emitting, self-emissive, and having fast response speed.

[0003] Due to the unique optical path structure of displays used in near-eye applications, these products often require high resolution (i.e., pixel density unit (PPI)). If the resolution cannot meet the requirements, a "sand-window effect" can easily occur, thus affecting the user experience. Because the pixel driving circuitry of display devices is relatively complex and requires a large layout space, it is difficult to achieve the pixel requirements of high PPI display devices under current technological limitations. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art, and provides a display device, a display substrate and a method for manufacturing the same, which can arrange multiple thin-film transistors in a small layout space and improve the resolution of the display device.

[0005] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a display substrate, including a substrate and a plurality of pixel units disposed on the substrate; the pixel unit includes a pixel driving circuit.

[0006] In at least a portion of the pixel driving circuit, the orthogonal projections of the gates of at least two thin-film transistors onto the substrate at least partially overlap.

[0007] In some embodiments, the thin-film transistor includes an active layer; the active layer includes a source region, a drain region, and a channel region sandwiched between the source region and the drain region; the source region serves as the source of the thin-film transistor, and the drain region serves as the drain of the thin-film transistor.

[0008] In some embodiments, both the source region and the drain region are doped with phosphorus ions.

[0009] In some embodiments, the pixel driving circuit includes a switching transistor, a first reset transistor, a second reset transistor, a driving transistor, and a light-emitting control transistor; the gates of the first reset transistor and the gates of the second reset transistor overlap on the substrate.

[0010] In some embodiments, the display substrate includes a first semiconductor layer and a first conductive layer sequentially disposed on the substrate.

[0011] The active layer of the driving transistor and the active layer of the light-emitting control transistor are located in the first semiconductor layer.

[0012] The gate of the driving transistor and the gate of the light-emitting control transistor are located in the first conductive layer.

[0013] In some embodiments, the display substrate further includes a second semiconductor layer and a second conductive layer disposed sequentially on the side of the first conductive layer opposite to the substrate.

[0014] The active layer of the first reset transistor and the active layer of the switching transistor are located in the second semiconductor layer; the drain region of the active layer of the first reset transistor and the drain region of the active layer of the switching transistor are connected to form an integral structure, and are electrically connected to the gate of the driving transistor through the first connection via.

[0015] The gate of the first reset transistor and the gate of the switching transistor are located in the second conductive layer.

[0016] In some embodiments, the pixel driving circuit further includes a first storage capacitor; the display substrate further includes a third conductive layer and a fourth conductive layer disposed sequentially on the side of the second conductive layer facing away from the substrate.

[0017] The third conductive layer includes a reference signal line, a first electrode of the first storage capacitor, a data line, and a first power signal line. The reference signal line is electrically connected to the source region of the active layer of the first reset transistor through a second connection via. The first electrode of the first storage capacitor is electrically connected to the drain region of the active layer of the first reset transistor through a third connection via, or the first electrode of the first storage capacitor is electrically connected to the drain region of the active layer of the switching transistor through a third connection via. The data line is electrically connected to the source region of the active layer of the switching transistor through a fourth connection via. The first power signal line is electrically connected to the source region of the active layer of the light-emitting control transistor through a fifth connection via.

[0018] The fourth conductive layer includes the second electrode of the first storage capacitor; the second electrode of the first storage capacitor is electrically connected to the drain region of the active layer of the driving transistor through a sixth connection via.

[0019] In some embodiments, the display substrate further includes a third semiconductor layer, a fifth conductive layer, and a sixth conductive layer sequentially disposed on the side of the fourth conductive layer facing away from the substrate; the pixel driving circuit further includes a second storage capacitor;

[0020] The third semiconductor layer includes the active layer of the second reset transistor; the drain region of the active layer of the second reset transistor is electrically connected to the second plate of the first storage capacitor through a seventh connection via.

[0021] The fifth conductive layer includes the gate of the second reset transistor;

[0022] The sixth conductive layer includes a first electrode of the second storage capacitor and an initialization signal line; the first electrode of the second storage capacitor is electrically connected to the second electrode of the first storage capacitor through an eighth connection via; the initialization signal line is electrically connected to the source region of the active layer of the second reset transistor through a ninth connection via.

[0023] In some embodiments, the pixel unit further includes a light-emitting device; the display substrate further includes a seventh conductive layer disposed on the side of the sixth conductive layer opposite to the substrate; the first electrode of the light-emitting device is located on the seventh conductive layer; the first electrode of the light-emitting device is electrically connected to the drain region of the active layer of the driving transistor through a tenth connection via.

[0024] In some embodiments, the pixel driving circuit includes a switching transistor, a first reset transistor, a second reset transistor, a driving transistor, and a light-emitting control transistor; the gate of the driving transistor and the gate of the switching transistor at least partially overlap on the substrate.

[0025] In some embodiments, the active layer is a metal oxide active layer. In a second aspect, this disclosure also provides a method for fabricating a display substrate, comprising: forming a plurality of pixel units on a substrate;

[0026] The formation of a plurality of pixel units on a substrate includes: a pixel driving circuit for forming the pixel units; wherein the orthogonal projections of the gates of at least two thin-film transistors of at least a portion of the pixel driving circuit onto the substrate at least partially overlap.

[0027] In some embodiments, the active layer of the thin-film transistor includes a source region, a drain region, and a channel region sandwiched between the source region and the drain region; the source region serves as the source of the thin-film transistor, and the drain region serves as the drain of the thin-film transistor.

[0028] The method further includes:

[0029] Phosphorus ions are doped into the source and drain regions of the active layer of the thin-film transistor, respectively.

[0030] Thirdly, this disclosure also provides a display device, including a display substrate as described in any one of the first aspects above. Attached Figure Description

[0031] Figure 1 A schematic block diagram of a display substrate provided in an embodiment of this disclosure;

[0032] Figure 2 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present disclosure;

[0033] Figure 3 This is a schematic diagram of the driving timing of the pixel driving circuit provided in an embodiment of the present disclosure;

[0034] Figure 4 A cross-sectional view of a pixel driving circuit provided in an embodiment of this disclosure;

[0035] Figures 5a to 5t This is a schematic diagram of the pixel driving circuit fabrication process provided in the embodiments of this disclosure;

[0036] Figure 6 This is a cross-sectional view of another pixel driving circuit provided in an embodiment of this disclosure. Detailed Implementation

[0037] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of this disclosure are clearly and completely described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0039] It should be noted that in this disclosure, the two structures being "set in the same layer" means that they are formed from the same material layer, so they are in the same layer in terms of stacking relationship, but it does not mean that the distance between them and the substrate is equal, nor does it mean that their other layer structures are completely the same as those between them and the substrate.

[0040] The present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0041] See Figure 1 As shown, it is a schematic block diagram of a display substrate provided in an embodiment of the present disclosure. The display substrate 100 provided in the embodiment of the present disclosure includes a substrate 11 and a plurality of pixel units 12 disposed on the substrate 11. The pixel unit 12 may include a pixel driving circuit 121 and a light-emitting device 122. The pixel driving circuit 121 is used to drive the light-emitting device 122 to emit light.

[0042] It should be noted that in some embodiments, pixel unit 12 may only include pixel driving circuit 121; pixel unit 12 may also only include light-emitting device 122. In practical applications, one pixel driving circuit 121 may drive one or more light-emitting devices 122 in pixel unit 12, and the embodiments disclosed herein do not impose specific limitations.

[0043] For example, the display substrate 100 can be applied to a display panel, such as an active matrix organic light-emitting diode (AMOLED) display panel. The display substrate 100 can be an array substrate, for example, the pixel units 12 can be arranged on the substrate 11 in a preset array.

[0044] For example, the substrate 11 may include, but is not limited to, suitable substrates such as glass substrates, quartz substrates, and plastic substrates.

[0045] The light-emitting device 122 may include, for example, an OLED or a mini LED. The light-emitting device 122 is configured to emit light under the drive current generated by the pixel driving circuit 121. The more pixel units 12 there are per unit area, the higher the image clarity (i.e., the higher the resolution) displayed on the display panel.

[0046] Figure 2 An example of a pixel driving circuit is provided. The pixel driving circuit 121 includes: a switching transistor T1, a first reset transistor T2, a second reset transistor T3, a driving transistor T4, a light-emitting control transistor T5, and a first storage capacitor C. st Second storage capacitor C EL Data line Date, reference signal line Vref, initialization signal line Vinit, first power signal line VDD, and second power signal line VSS.

[0047] The source of switching transistor T1 is electrically connected to the data line Date, and the drain of switching transistor T1 is connected to the first storage capacitor C. st First plate C st1 The drain of the first reset transistor T2 and the gate of the drive transistor T4 are electrically connected, and the gate of the switching transistor T1 is electrically connected to the third scan line S3. Specifically, the switching transistor T1 is configured to turn on when the working level is written to the third scan line S3, transmitting the data voltage signal written by the data line Date to the gate of the drive transistor T4, and transmitting the data voltage signal through the first storage capacitor C. st Store it.

[0048] The source of the first reset transistor T2 is electrically connected to the reference signal line Vref, and the drain of the first reset transistor T2 is connected to the first storage capacitor C. st First plate C st1 The drain of switching transistor T1 and the gate of driving transistor T4 are electrically connected; the gate of first reset transistor T2 is electrically connected to the first scan line S1. The drain of first reset transistor T2 and the first storage capacitor C... st First plate C st1 The connection node between the drain of the switching transistor T1 and the gate of the driving transistor T4 is N1. Specifically, the first reset transistor T2 is configured to turn on when the first scan line S1 writes the working level, and output the first reset signal written by the reference connection signal line Vref to the connection node N1.

[0049] The source of the second reset transistor T3 is electrically connected to the initialization signal line Vinit, and the drain of the second reset transistor T3 is connected to the first storage capacitor C. st The second electrode plate C st2 Second storage capacitor C EL First plate C EL1 The first electrode (i.e., anode) of the light-emitting device 122 is electrically connected to the drain of the driving transistor T4, and the gate of the second reset transistor T3 is electrically connected to the second scan line S2. The drain of the second reset transistor T3 is connected to the first storage capacitor C. st The second electrode plate C st2 The connection node is N2. Specifically, the second reset transistor T3 is configured to turn on when the second scan line S2 is written with the working level, and transmit the second reset signal written by the initialization signal line Vinit to the connection node N2.

[0050] The source of the driving transistor T4 is electrically connected to the drain of the light-emitting control transistor T5; the drain of the driving transistor T4 is connected to the first electrode (i.e., the anode) of the light-emitting device 122 and the first storage capacitor C, respectively. st The second electrode plate C st2 Second storage capacitor C EL First plate C EL1 The drain of the second reset transistor T3 is electrically connected, and the gate of the driving transistor T4 is connected to the drain of the switching transistor T1 and the first storage capacitor C, respectively. st First plate C st1 The drain of the first reset transistor T2 is electrically connected. Specifically, the driving transistor T4 is configured to provide a driving current to the first electrode of the light-emitting device 122 when it is turned on, thereby driving the light-emitting device 122 to emit light.

[0051] The source of the light-emitting control transistor T5 is electrically connected to the first power supply signal line VDD, the drain of the light-emitting control transistor T5 is electrically connected to the source of the driving transistor T4, and the gate of the light-emitting control transistor T5 is electrically connected to the light-emitting control signal line. Specifically, the light-emitting control transistor T5 is configured to transmit the first power supply voltage input to the first power supply signal line VDD to the source of the driving transistor T4 when it is turned on.

[0052] The first electrode (i.e., anode) of the light-emitting device 122 is connected to the drain of the driving transistor T4 and the first storage capacitor C, respectively. st The second electrode plate C st2 Second storage capacitor C EL First plate C EL1 The drain of the second reset transistor T3 is electrically connected, and the second electrode (i.e., the cathode) of the light-emitting device 122 is connected to the second storage capacitor C. EL The second electrode plate C EL2It is electrically connected to the second power signal line VSS.

[0053] For example, the first power signal line VDD is a voltage source that outputs a constant first power supply voltage, which is a positive voltage; while the second power signal line VSS can be a voltage source that outputs a constant second power supply voltage, which is a negative voltage, etc. For example, in some embodiments, the second power signal line VSS is grounded.

[0054] like Figure 3 A schematic diagram illustrating the driving timing of the pixel driving circuit 121 described above is provided. Here, S1 represents the first scan line of the first reset transistor T2, S2 represents the second scan line of the second reset transistor T3, S3 represents the third scan line of the switching transistor T1, and EM represents the light emission control signal line of the light emission control transistor T5.

[0055] For example, such as Figure 3 The driving timing shown is as follows: In the first stage, S1 and S2 are high, S3 is low, and EM is low. At this time, the first reset transistor T2 in the pixel driving circuit 121 receives the first reset signal written by the reference signal line Vref, and the voltage of the N1-connected node is Vref; the second reset transistor T3 in the pixel driving circuit 121 receives the second reset signal written by the initialization signal line Vinit, and the voltage of the N2-connected node is Vinit. In the second stage, S1 is high, S2 is low, S3 is low, and EM is high. At this time, the first reset transistor T2 in the pixel driving circuit 121 continuously receives the first reset signal written by the reference signal line Vref, and the voltage of the N1-connected node remains Vref; since S2 is low, the initialization signal line Vinit and the first storage capacitor C... st The connection between them is interrupted, point N2 is at a low level, and the first storage capacitor C... st The voltage is configured to store the voltage difference between the two connected nodes N1 and N2. In the third stage, S1 is low, S2 is low, S3 is high, and EM is low. At this time, the switching transistor T1 in the pixel driving circuit 121 can realize the connection between the driving transistor T4 and the data line Date, and receive the data voltage signal written by the data line Date. At the same time, it transmits the data voltage signal to the gate of the driving transistor T4. In the fourth stage, S1 is low, S2 is low, S3 is low, and EM is high. At this time, the light-emitting control transistor T5 in the pixel driving circuit 121 receives the first power supply voltage provided by the first power supply signal line VDD and provides driving current to the driving transistor T4. The driving transistor T4 controls the driving current flowing from the first power supply signal line VDD to the light-emitting device 122 according to the voltage stored in the storage capacitor Cst.

[0056] Based on their characteristics, thin-film transistors can be classified into P-type transistors or N-type transistors. This disclosure uses an N-type transistor (e.g., an N-type MOS transistor) as an example to illustrate the technical solution of this disclosure. That is, in the description of this disclosure, the switching transistor T1, the first reset transistor T2, the second reset transistor T3, the driving transistor T4, the light-emitting control transistor T5, etc., can all be N-type transistors. However, it should be understood that the thin-film transistors in the embodiments of this disclosure are not limited to N-type transistors. Those skilled in the art can also use P-type transistors (e.g., P-type MOS transistors) to implement the functions of one or more thin-film transistors in the embodiments of this disclosure according to actual needs.

[0057] The above example only uses the pixel driving circuit 121 as a 5T2C structure (i.e., five thin film transistors and two capacitors). In actual products, the pixel driving circuit 121 can also be a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, etc. This disclosure does not limit this.

[0058] With users' increasing demands for display quality, improving the PPI of display devices is a pressing issue in the display field. To achieve a high PPI, in this embodiment, the gates of at least two thin-film transistors in at least a portion of the pixel driving circuit 121 have their orthogonal projections onto the substrate 11 at least partially overlap. This effectively reduces the area occupied by the thin-film transistors, thereby increasing the number of pixel units 12 per unit area, thus meeting the pixel requirements of high-PPI display devices. The specific structure of the pixel driving circuit 121 can be found in the following description... Figure 4 The cross-sectional view and detailed description of the pixel driving circuit 121 are not described in detail here.

[0059] To make the specific structure of each pixel unit 12 of the display substrate in the embodiments of this disclosure clearer, the following description will take a 5T2C pixel driving circuit as an example for pixel driving circuit 121.

[0060] See Figure 4 As shown, Figure 4 Taking only a cross-sectional view of one pixel driving circuit 121 in the display substrate 100 as an example, other pixel driving circuits in the display substrate 100 may have the same or similar structure as pixel driving circuit 121, and will not be discussed further. Figure 4 It is shown repeatedly in the text. For example... Figure 4 As shown, the pixel driving circuit 121 includes a switching transistor T1, a first reset transistor T2, a second reset transistor T3, a driving transistor T4, a light-emitting control transistor T5, and a first storage capacitor C. st Second storage capacitor C ELData line Date, reference signal line Vref, initialization signal line Vinit, first power signal line VDD, and second power signal line VSS.

[0061] In some embodiments, the thin-film transistor includes an active layer; the active layer may include a source region, a drain region, and a channel region sandwiched between the source region and the drain region; the source region may be used as the source of the thin-film transistor, and the drain region may be used as the drain of the thin-film transistor. Therefore, the source, drain, and active layer of the thin-film transistor are disposed in the same layer. Compared with the method of distributing the source and drain of the thin-film transistor in layers with the active layer, the method of distributing the active layer in the same layer in the embodiments of this disclosure can improve the flatness between the layers of the thin-film transistor, thereby improving the display effect of the display device.

[0062] Taking a thin-film transistor as an example, the active layer of the first reset transistor T2 includes a source region 453, a drain region 451, and a channel region 455.

[0063] The orthogonal projection of the gate of the thin-film transistor onto the substrate 11 can cover the orthogonal projection of the channel region of the active layer of the thin-film transistor onto the substrate 11.

[0064] For example, the active layer of a thin-film transistor can be a metal oxide active layer, such as indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc aluminum oxide (IAZO), etc. For ease of explanation, this specification uses IGZO active layer as an example for illustration, but it does not constitute a limitation of this disclosure.

[0065] Taking an active layer comprising a source region, a drain region, and a channel region as an example, the display substrate 100 includes a first semiconductor layer 41 and a first conductive layer 42 sequentially disposed on a substrate 11. The active layer of the driving transistor T4 and the active layer of the light-emitting control transistor T5 are located on the first semiconductor layer 41. Furthermore, to reduce process complexity (e.g., avoid depositing different active layers in the same layer), improve working efficiency, and reduce the area occupied by the active layer of the thin-film transistor, the active layer of the driving transistor T4 and the active layer of the light-emitting control transistor T5 can be specifically configured as an integral structure connected together. Specifically, as shown... Figure 2 The pixel driving circuit 121 shown has a first semiconductor layer 41 in which the source region 411 of the active layer of the driving transistor T4 and the drain region 412 of the active layer of the light-emitting control transistor T5 are connected as a single structure. This configuration reduces manufacturing complexity, improves efficiency, and also reduces the area occupied by the active layer of the thin-film transistor, thereby reducing the area occupied by the thin-film transistor and increasing the number of pixel units 12 disposed per unit area.

[0066] In addition, in some embodiments, the active layer of the driving transistor T4 and the active layer of the light-emitting control transistor T5 may be respectively provided on the first semiconductor layer 41. That is, the active layer of the driving transistor T4 and the active layer of the light-emitting control transistor T5 contained in the first semiconductor layer 41 are not connected to a single structure. Here, specific settings can be made according to the needs of actual application scenarios, and the embodiments disclosed herein do not impose specific limitations.

[0067] The gate T41 of the driving transistor T4 and the gate T51 of the light-emitting control transistor T5 are located in the first conductive layer 42. Specifically, the gate T41 of the driving transistor T4 and the gate T51 of the light-emitting control transistor T5 can be respectively located at different positions in the first conductive layer 42, such as... Figure 4 The location shown.

[0068] A first gate insulating layer 43 is further disposed between the first semiconductor layer 41 and the first conductive layer 42, and the first gate insulating layer 43 is used to protect the first semiconductor layer 41.

[0069] In some embodiments, after the first gate insulating layer 43 is formed, the first semiconductor layer 41 is doped using the first conductive layer 42 as a mask. The impurities can be N-type or P-type impurities. For example, the first semiconductor layer 41 is heavily doped using the first conductive layer 42 as a mask, and the impurities are N-type impurities (i.e., phosphorus ions). When phosphorus particles are doped in both the source and drain regions, the conductivity of the source and drain regions of the driving transistor T4 and the light-emitting control transistor T5 is improved, that is, the conductivity of the source and drain of the driving transistor T4 and the light-emitting control transistor T5 is improved.

[0070] The display substrate 100 further includes a first insulating layer 44 disposed on the side of the first conductive layer 42 facing away from the substrate 11, which can protect the first conductive layer 42. Here, the material of the first insulating layer 44 is only required to satisfy the insulation between the first conductive layer 42 and the second semiconductor layer 45, and the embodiments disclosed herein do not impose specific limitations.

[0071] The display substrate 100 further includes a second semiconductor layer 45 and a second conductive layer 46 sequentially disposed on the side of the first conductive layer 42 facing away from the substrate 11. Specifically, the second semiconductor layer 45 and the second conductive layer 46 are sequentially disposed on the side of the first insulating layer 44 facing away from the substrate 11. The active layer of the first reset transistor T2 and the active layer of the switching transistor T1 are located on the second semiconductor layer 45. The drain region 451 of the active layer of the first reset transistor T2 and the drain region 452 of the active layer of the switching transistor T1 are connected as a single structure and electrically connected to the gate T41 of the driving transistor T4 through the first connection via 1.

[0072] Here, in order to reduce the difficulty of the process and improve the efficiency, and also to reduce the area occupied by the active layer of the thin-film transistor, it can be specifically configured such that the active layer of the first reset transistor T2 and the active layer of the switching transistor T1 are connected as a single structure. Specifically, as follows: Figure 2 The pixel driving circuit 121 shown has the following configuration: In the second semiconductor layer 45, the drain region 451 of the active layer of the first reset transistor T2 and the drain region 452 of the active layer of the switching transistor T1 are connected as a single structure and electrically connected to the gate T41 of the driving transistor T4 (specifically, they can be electrically connected to the gate T41 of the driving transistor T4 through a first connection via 1). Here, the first connection via 1 penetrates the first insulating layer 44, and its orthogonal projection on the first conductive layer 42 is located at the gate T41 of the driving transistor T4. This configuration reduces process complexity, improves efficiency, and reduces the area occupied by the active layer of the thin-film transistor, thereby reducing the area occupied by the thin-film transistor and increasing the number of pixel units 12 per unit area.

[0073] In some embodiments, the active layer of the first reset transistor T2 and the active layer of the switching transistor T1 may be respectively disposed on the second semiconductor layer 45. That is, the active layer of the first reset transistor T2 and the active layer of the switching transistor T1 contained in the second semiconductor layer 45 are not connected as a single structure. Here, specific settings can be made according to the needs of actual application scenarios, and the embodiments disclosed herein do not impose specific limitations.

[0074] The gate T21 of the first reset transistor T2 and the gate T11 of the switching transistor T1 are located in the second conductive layer 46. Specifically, the gate T21 of the first reset transistor T2 and the gate T11 of the switching transistor T1 can be respectively located at different positions in the second conductive layer 46, such as... Figure 4 The location shown.

[0075] To ensure insulation between the second semiconductor layer 45 and the second conductive layer 46, a second gate insulating layer 47 is provided on the side of the second semiconductor layer 45 facing away from the substrate 11.

[0076] The display substrate 100 further includes a first interlayer insulating layer 48 disposed on the side of the second conductive layer 46 facing away from the substrate 11, which can protect the second conductive layer 46. The first interlayer insulating layer 48 may include, for example, silicon compounds or metal oxides.

[0077] The pixel driving circuit 121 also includes a first storage capacitor C. st The display substrate 100 further includes a third conductive layer 49 and a fourth conductive layer 4010 sequentially disposed on the side of the second conductive layer 46 facing away from the substrate 11. The third conductive layer 49 includes a reference signal line Vref and a first storage capacitor C.st First plate C st1 The data line Date and the first power signal line VDD.

[0078] As shown in Figure 5, the display substrate 100 further includes a second connection via 2, a third connection via 3, and a fourth connection via 4, which penetrate the second gate insulating layer 47 and the first interlayer insulating layer 48. The orthographic projection of the second connection via 2 onto the second semiconductor layer 45 is located in the source region 453 of the active layer of the first reset transistor T2. The orthographic projection of the third connection via 3 onto the second semiconductor layer 45 is located in the drain region 451 of the active layer of the first reset transistor T2; or, the orthographic projection of the third connection via 3 onto the second semiconductor layer 45 is located in the drain region 452 of the active layer of the switching transistor T1; or, a portion of the orthographic projection of the third connection via 3 onto the second semiconductor layer 45 is located in the drain region 451 of the active layer of the first reset transistor T2, and another portion of the orthographic projection of the third connection via 3 onto the second semiconductor layer 45 is located in the drain region 452 of the active layer of the switching transistor T1. The orthographic projection of the fourth connection via 4 onto the second semiconductor layer 45 is located in the source region 454 of the active layer of the switching transistor T1.

[0079] The reference signal line Vref can be electrically connected to the source region 453 of the active layer of the first reset transistor T2 through the second connection via via2; the first storage capacitor C st First plate C st1 The first reset transistor T2 is electrically connected to the drain region 451 of the active layer via the third connection via 3, or the first storage capacitor C st First plate C st1 The third connection via 3 is electrically connected to the drain region 452 of the active layer of the switching transistor T1; the data line Date is electrically connected to the source region 454 of the active layer of the switching transistor T1 through the fourth connection via 4; the first power signal line VDD is electrically connected to the source region 413 of the active layer of the light-emitting control transistor T5 through the fifth connection via 5.

[0080] The display substrate 100 also includes a fifth connection via 5 that penetrates the first interlayer insulating layer 48, the second gate insulating layer 47, the first insulating layer 44, and the first gate insulating layer 43. The orthogonal projection of the fifth connection via 5 on the first semiconductor layer 41 is located in the source region 413 of the active layer of the light-emitting control transistor T5. Specifically, the first power signal line VDD passes through the first interlayer insulating layer 48, the second gate insulating layer 47, the first insulating layer 44, and the first gate insulating layer 43 through the fifth connection via 5 and is electrically connected to the source region 413 of the active layer of the light-emitting control transistor T5.

[0081] The display substrate 100 further includes a second insulating layer 4011 disposed on the side of the third conductive layer 49 facing away from the substrate 11. The second insulating layer 4011 protects the third conductive layer 49. The second insulating layer 4011 may be an insulating layer with the same material as the first insulating layer 44; or, the second insulating layer 4011 may be a first passivation layer PVX1; or, the second insulating layer 4011 may be an insulating layer composed of an insulating layer with the same material as the first insulating layer 44 and the first passivation layer PVX1. It can be set according to the actual application scenario, needs and experience. The embodiments disclosed in this disclosure do not make specific limitations.

[0082] The fourth conductive layer 4010 includes a first storage capacitor C st The second electrode plate C st2 .like Figure 4 As shown, the display substrate 100 also includes a sixth connection via 6 through the second insulating layer 4011, the first interlayer insulating layer 48, the second gate insulating layer 47, the first insulating layer 44, and the first gate insulating layer 43, and a first storage capacitor C. st The second electrode plate C st2 The first storage capacitor C is electrically connected to the drain region 414 of the active layer of the driving transistor T4 via the sixth connection via 6. st The second electrode plate C st2 The sixth connection via 414 passes through the second insulating layer 4011, the first interlayer insulating layer 48, the second gate insulating layer 47, the first insulating layer 44, and the first gate insulating layer 43, and is electrically connected to the drain region 414 of the active layer of the driving transistor T4.

[0083] The display substrate 100 also includes a third insulating layer 4012 disposed on the side of the fourth conductive layer 4010 facing away from the substrate 11. The third insulating layer 4012 protects the fourth conductive layer 4010 (for example, it can be a second passivation layer PVX2).

[0084] The display substrate 100 further includes a third semiconductor layer 4013, a fifth conductive layer 4014, and a sixth conductive layer 4015 sequentially disposed on the side of the fourth conductive layer 4010 facing away from the substrate 11; the pixel driving circuit 121 further includes a second storage capacitor C. EL Specifically, the third semiconductor layer 4013, the fifth conductive layer 4014, and the sixth conductive layer 4015 are sequentially disposed on the side of the third insulating layer 4012 facing away from the substrate 11.

[0085] The display substrate 100 further includes a third gate insulating layer 4016, a second interlayer insulating layer 4017, and a planarization layer 4018. Specifically, to ensure insulation between the third semiconductor layer 4013 and the fifth conductive layer 4014, a third gate insulating layer 4016 is provided on the side of the third semiconductor layer 4013 facing away from the substrate 11. To ensure insulation between the fifth conductive layer 4014 and the sixth conductive layer 4015, a second interlayer insulating layer 4017 is provided on the side of the fifth conductive layer 4014 facing away from the substrate 11. To protect the sixth conductive layer 4015, a planarization layer 4018 is provided on the side of the sixth conductive layer 4015 facing away from the substrate 11.

[0086] The display substrate 100 also includes a seventh connection via 7 that penetrates the third insulating layer 4012. The orthogonal projection of the seventh connection via 7 onto the fourth conductive layer 4010 is located at the first storage capacitor C. st The second electrode plate C st2 The display substrate 100 also includes an eighth connection via 8 that penetrates the second interlayer insulating layer 4017, the third gate insulating layer 4016, and the third insulating layer 4012. The orthogonal projection of the eighth connection via 8 onto the fourth conductive layer 4010 is located at the first storage capacitor C. st The second electrode plate C st2 The display substrate 100 also includes a ninth connection via 9 through the second interlayer insulating layer 4017, the third gate insulating layer 4016, and the third insulating layer 4012. The orthogonal projection of the ninth connection via 9 onto the third semiconductor layer 5013 is located in the source region 4013-2 of the active layer of the second reset transistor T3.

[0087] The third semiconductor layer 4013 includes the active layer of the second reset transistor T3. The drain region 4013-1 of the active layer of the second reset transistor T3 is connected to the first storage capacitor C through the seventh connection via 7. st The second electrode plate C st2 Electrical connection. The fifth conductive layer 4014 includes the gate T31 of the second reset transistor T3, and the orthographic projections of the gate T31 of the second reset transistor T3 and the gate T21 of the first reset transistor T2 on the substrate 11 overlap. The sixth conductive layer 4015 includes the second storage capacitor C. EL First plate C EL1 and the initialization signal line Vinit. Second storage capacitor C. EL First plate C EL1 The first storage capacitor C is connected via the eighth connection via 8. st The second electrode plate C st2 Electrical connection. The initialization signal line Vinit is electrically connected to the source region 4013-2 of the active layer of the second reset transistor T3 through the ninth connection via via9.

[0088] Alternatively, the second storage capacitor C EL First plate C EL1 It can also be electrically connected to the drain region 4013-1 of the active layer of the second reset transistor T3 through the eighth connection via 8.

[0089] The pixel unit 12 also includes a light-emitting device 122; the display substrate 100 also includes a seventh conductive layer 4019 disposed on the side of the sixth conductive layer 4015 facing away from the substrate 11. Specifically, the seventh conductive layer 4019 is disposed on the side of the planarization layer 4018 facing away from the substrate 11. The first electrode AND of the light-emitting device 122 is located on the seventh conductive layer 4019.

[0090] The display substrate 100 further includes a tenth connection via 10 that extends sequentially from the side opposite to the substrate 11 through the first gate insulating layer 43, the first insulating layer 44, the second gate insulating layer 47, the first interlayer insulating layer 48, the second insulating layer 4011, the third insulating layer 4012, the third gate insulating layer 4016, the second interlayer insulating layer 4017, and the planarization layer 4018. The first electrode AND of the light-emitting device 122 is electrically connected to the drain region 414 of the active layer of the driving transistor T4 through the tenth connection via 10.

[0091] like Figure 3 The pixel driving circuit 121 shown includes the first electrode AND of the light-emitting device 122, which is also the anode of the light-emitting device 122. The second electrode (also the cathode) of the light-emitting device 122 and the second storage capacitor C are also shown. EL The second electrode plate C EL2 None of them were in Figure 3 As shown in the figure. The second storage capacitor C... EL The second electrode plate C EL2 The second storage capacitor C is disposed on the side of the planarization layer 4018 opposite to the substrate 11 and its orthogonal projection on the substrate 11. EL First plate C EL1 The orthographic projections of the two objects at least partially overlap.

[0092] It should be noted that the connection vias described in this disclosure (i.e., the first connection vias via1 to the tenth connection vias via10) can be cylindrical or conical vias; if they are conical vias, the diameter of the vias increases from the direction away from the substrate 11. The specific size of the connection vias can be set according to the actual scenario and experience, and this disclosure does not impose specific limitations. Taking the first connection via as an example, the maximum diameter of the first connection via is smaller than the size of the area where the drain region 451 of the active layer of the first reset transistor T2 or the drain region 452 of the active layer of the switching transistor T1 is projected onto the gate T41 of the driving transistor T4.

[0093] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, and the present invention is not limited thereto. Taking the pixel driving circuit 121 as a 5T2C structure as an example, in another exemplary embodiment, the orthogonal projections of the gate of the driving transistor and the gate of the switching transistor on the substrate at least partially overlap, see details below. Figure 6 As shown.

[0094] Figure 6 The principles of setting up each layer and Figure 4 The underlying principle is the same for all layers. The following explanation is based on a specific embodiment:

[0095] The display substrate 100 includes a first semiconductor layer 61, a first gate insulating layer 62, a first conductive layer 63, a first interlayer insulating layer 64, a second conductive layer 65, a first insulating layer 66, a third conductive layer 67, a second gate insulating layer 68, a second semiconductor layer 69, a second insulating layer 610, a fourth conductive layer 611, a second interlayer insulating layer 612, a fifth conductive layer 613, a passivation layer 614, a sixth conductive layer 615, a planarization layer 616, and a seventh conductive layer 617 sequentially disposed on a substrate 11.

[0096] The active layers of the first reset transistor T2 and the switching transistor T1 are located on the first semiconductor layer 61. The gate T21 of the first reset transistor T2 and the gate T11 of the switching transistor T1 are located on the first conductive layer 63. Reference signal line Vref and first storage capacitor C are also present. st First plate C st1 The gate T41 of the driving transistor T4 and the data line Date are located in the second conductive layer 65. The reference signal line Vref is electrically connected to the source region of the active layer of the first reset transistor T2 through a first connection via; the first storage capacitor C... st First plate C st1 The second connection via is electrically connected to the drain region of the active layer of the first reset transistor T2; the gate T41 of the driving transistor T4 is electrically connected to the drain region of the active layer of the first reset transistor T2 through the third connection via, or the gate T41 of the driving transistor T4 is electrically connected to the drain region of the active layer of the switching transistor T1 through the third connection via; the data line Date is electrically connected to the source region of the active layer of the switching transistor T1 through the fourth connection via.

[0097] The drain region 61-1 of the active layer of the first reset transistor T2 and the drain region 61-2 of the active layer of the switching transistor T1 are connected as a single structure.

[0098] The gate T31 of the second reset transistor T3 and the first storage capacitor C st The second electrode plate C st2The gate T51 of the light-emitting control transistor T5 is located in the third conductive layer 67. The active layers of the second reset transistor T3, the driving transistor T4, and the light-emitting control transistor T5 are located in the second semiconductor layer 69.

[0099] The fourth conductive layer 611 includes a first connection electrode, a second connection electrode, a third connection electrode, a fourth connection electrode, and a fifth connection electrode. The first connection electrode is electrically connected to the source region of the active layer of the second reset transistor T3 through a fifth connection via; the second connection electrode is electrically connected to the drain region of the active layer of the second reset transistor T3 through a sixth connection via, and simultaneously connected to the first storage capacitor C through a seventh connection via. st The second electrode plate C st2 Electrical connection; the third connection electrode is connected to the first storage capacitor C through the eighth connection via. st The second electrode plate C st2 Electrical connections: The third connection electrode is electrically connected to the drain region of the active layer of the driving transistor T4 through the ninth connection via; the fourth connection electrode is electrically connected to the source region of the active layer of the driving transistor T4 through the tenth connection via; the fourth connection electrode is electrically connected to the drain region of the active layer of the light-emitting control transistor T5 through the eleventh connection via; and the fifth connection electrode is electrically connected to the source region of the active layer of the light-emitting control transistor T5 through the twelfth connection via.

[0100] The initialization signal line Vinit and the first power signal line VDD are located in the fifth conductive layer 613. Specifically, the initialization signal line Vinit is electrically connected to the first connection electrode through the thirteenth connection via; the first power signal line VDD is electrically connected to the fifth connection electrode through the fourteenth connection via.

[0101] Second storage capacitor C EL First plate C EL1 Located in the sixth conductive layer 615. Second storage capacitor C EL First plate C EL1 Electrically connected to the third connection electrode via the fifteenth connection via.

[0102] The first electrode AND of the light-emitting device 122 is located on the seventh conductive layer 617. The first electrode AND is electrically connected to the third electrode through the sixteenth connection via.

[0103] According to embodiments of this disclosure, a method for fabricating a display substrate is also provided, comprising forming a plurality of pixel units on a substrate. Forming the plurality of pixel units on the substrate includes: a pixel driving circuit for forming the pixel units, wherein the orthogonal projections of the gates of at least two thin-film transistors of at least a portion of the pixel driving circuit onto the substrate at least partially overlap.

[0104] The following example uses the pixel driving circuit 121 as a 5T2C structure. Figure 4 As shown, the pixel driving circuit 121 includes a switching transistor T1, a first reset transistor T2, a second reset transistor T3, a driving transistor T4, and a light-emitting control transistor T5. The gate T21 of the first reset transistor T2 and the gate T31 of the second reset transistor T3 have their orthogonal projections onto the substrate 11 overlap.

[0105] Regarding the aforementioned display substrate 100, this disclosure provides related processes for fabricating the display substrate 100. Specifically, the process for fabricating the pixel driving circuit is as follows, referring to... Figures 5a to 5t As shown:

[0106] S1. A first semiconductor layer 41 is formed on the substrate 11, such as... Figure 5a As shown.

[0107] Specifically, firstly, a semiconductor layer is deposited on the substrate 11; then, photoresist is coated on the side of the semiconductor layer away from the substrate 11 and exposed, developed, etched, and stripped to obtain the first semiconductor layer 41, which is also the active layer of the driving transistor T4 and the active layer of the light-emitting control transistor T5.

[0108] Furthermore, in order to reduce the difficulty of the process (for example, to avoid depositing different active layers in the same layer), improve work efficiency, and reduce the area occupied by the active layer of the thin film transistor, the active layer of the driving transistor T4 and the active layer of the light-emitting control transistor T5 can be connected into a single structure.

[0109] Here, a semiconductor layer is deposited on the substrate 11. The semiconductor layer can be deposited on the substrate 11 by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0110] S2. A first gate insulating layer 43 is formed on the side of the first semiconductor layer 41 facing away from the substrate 11, such as... Figure 5b As shown.

[0111] Specifically, a first gate insulating layer 43 is deposited on the side of the first semiconductor layer 41 that is away from the substrate 11.

[0112] In the embodiments of this disclosure, the deposition preparation methods involved can all adopt the above-described preparation method for depositing the first semiconductor layer 41, and repeated parts will not be described again.

[0113] S4. A first conductive layer 42 is formed on the side of the first gate insulating layer 43 facing away from the substrate 11, such as... Figure 5c As shown.

[0114] Specifically, firstly, a conductive layer is deposited on the side of the first gate insulating layer 43 facing away from the substrate 11; then, photoresist is coated on the side of the conductive layer facing away from the substrate 11, and exposure, development, etching, and stripping processes are performed according to the pre-set channel positions (that is, the channel regions of the active layer of the driving transistor T4 and the active layer of the light-emitting control transistor T5 are respectively on the first gate insulating layer 43 and the second gate insulating layer 47) to obtain the first conductive layer 42, that is, the gate T41 of the driving transistor T4 and the gate T51 of the light-emitting control transistor T5.

[0115] S5. Using the first conductive layer 42 as a mask, the first semiconductor layer 41 is doped.

[0116] For example, using the first conductive layer 42 as a mask, the first semiconductor layer 41 is heavily doped with N-type impurities (i.e., phosphorus ions). When phosphorus particles are doped in both the source and drain regions, the conductivity of the source and drain regions of the driving transistor T4 and the light-emitting control transistor T5 is improved, that is, the conductivity of the source and drain of the driving transistor T4 and the light-emitting control transistor T5 is improved.

[0117] S6. A first insulating layer 44 is deposited on the side of the first conductive layer 42 facing away from the substrate 11, such as... Figure 5d As shown.

[0118] S7. A hole is drilled in the direction opposite to the substrate 11 on the gate T41 of the driving transistor T4; a hole is drilled in the direction opposite to the substrate 11 on the first semiconductor layer 41, such as... Figure 5e As shown.

[0119] As can be seen from the pixel driving circuit 121 described above, the drain region 451 of the active layer of the first reset transistor T2 and the drain region 452 of the active layer of the switching transistor T1 are connected to a single structure and electrically connected to the gate T41 of the driving transistor T4. Therefore, a first connection via 1 penetrating the first insulating layer 44 needs to be formed. Specifically, a first connection via 1 penetrating the first insulating layer 44 is formed in the region where the drain region 451 of the active layer of the first reset transistor T2 or the drain region 452 of the active layer of the switching transistor T1 is projected onto the gate T41 of the driving transistor T4.

[0120] In some embodiments, since the multilayer insulating layers have a considerable depth, it is difficult to perform a drilling process that penetrates multiple insulating layers in one go. Therefore, in order to reduce the difficulty of subsequent multilayer drilling processes, the same connection via can be drilled in batches. Taking the fifth connection via 5 as an example, as can be seen from the pixel driving circuit 121, the fifth connection via 5 penetrates multiple insulating layers, that is, the fifth connection via 5 penetrates the first interlayer insulating layer 48, the second gate insulating layer 47, the first insulating layer 44, and the first gate insulating layer 43. In one scenario, to reduce the difficulty of the drilling process, a sub-connecting via is formed through each insulating layer. For example, after depositing a first gate insulating layer 43, a fifth connecting sub-via via 51 is formed through the first gate insulating layer 43 on the side of the active layer of the light-emitting control transistor T5 facing away from the substrate 11. Subsequently, after depositing a first insulating layer 44, a fifth connecting sub-via via 52 is formed through the first insulating layer 44 on the side of the fifth connecting sub-via facing away from the substrate 11. Similarly, a fifth connecting sub-via via 53 is formed through the second gate insulating layer 47, and a fifth connecting sub-via via 54 is formed through the first interlayer insulating layer 48. The combination of the fifth connecting sub-vias via 51, 52, 53, and 54 forms a fifth connecting via via 55 that penetrates the first interlayer insulating layer 48, the second gate insulating layer 47, the first insulating layer 44, and the first gate insulating layer 43.

[0121] In another scenario, for vias penetrating multiple insulating layers, to reduce the difficulty of the drilling process and the number of drilling operations, thereby improving the manufacturing efficiency of the display panel, the drilling process is performed after depositing two or more insulating layers. The specific drilling process can be referenced from the drilling process performed after each insulating layer deposition described above; repeated parts will not be repeated.

[0122] In this embodiment of the disclosure, the connecting vias penetrating multiple insulating layers include a second connecting via via2, a third connecting via via3, a fourth connecting via via4, a sixth connecting via via6, an eighth connecting via via7, a ninth connecting via via9, and a tenth connecting via via10. The drilling method for these vias can refer to the preparation method of the fifth connecting via via5 described above (including the two cases of forming a penetrating fifth connecting via via5 described above), as follows: Figure 5j As shown.

[0123] S8. A second semiconductor layer 45 is deposited on the side of the first insulating layer 44 facing away from the substrate 11. The drain region 451 of the active layer of the first reset transistor T2 in the second semiconductor layer 45 (or, the drain region 452 of the active layer of the switching transistor T1 in the second semiconductor layer 45) is electrically connected to the gate T41 of the driving transistor T4 in the first conductive layer 42. Figure 5f As shown.

[0124] Here, the active layer of the first reset transistor T2 in the second semiconductor layer 45 and the active layer of the switching transistor T1 in the second semiconductor layer 45 are connected to form an integral structure. Specifically, the drain region 451 of the active layer of the first reset transistor T2 and the drain region 452 of the active layer of the switching transistor T1 are connected to form an integral structure.

[0125] S9. A second gate insulating layer 47 is deposited on the side of the second semiconductor layer 45 facing away from the substrate 11, such as... Figure 5g As shown.

[0126] S10, deposit a second conductive layer 46 on the side of the second gate insulating layer 47 facing away from the substrate 11, such as Figure 5h As shown.

[0127] Specifically, the gate T21 of the first reset transistor T2 and the gate T11 of the switch transistor T1 are deposited on the second gate insulating layer 47 according to the channel region of the active layer of the first reset transistor T2 and the channel region of the active layer of the switch transistor T1, respectively.

[0128] S11. Using the second conductive layer 46 as a mask, the second semiconductor layer 45 is doped.

[0129] Here, the preparation process of doping the second semiconductor layer 45 can be referred to in step S5 above for the heavy doping of the first semiconductor layer 41, and the repeated parts will not be described again.

[0130] S12, deposit a first interlayer insulating layer 48 on the side of the second conductive layer 46 facing away from the substrate 11, such as Figure 5i As shown.

[0131] For example, the first interlayer insulating layer 48 may include, for example, a silicon compound or a metal oxide.

[0132] S13. A hole is drilled in the source region 453 of the active layer of the first reset transistor T2 in the direction away from the substrate 11 to form a second connection via 2 penetrating the first interlayer insulating layer 48 and the second gate insulating layer 47; a hole is drilled in the drain region 451 of the active layer of the first reset transistor T2 in the direction away from the substrate 11 to form a third connection via 3 penetrating the first interlayer insulating layer 48 and the second gate insulating layer 47; or, a hole is drilled in the drain region 452 of the active layer of the switching transistor T1 in the direction away from the substrate 11 to form a third connection via 3 penetrating the first interlayer insulating layer 48 and the second gate insulating layer 47; a hole is drilled in the positive direction of the source region 454 of the active layer of the switching transistor T1 in the direction away from the substrate 11 to form a fourth connection via 4 penetrating the first interlayer insulating layer 48 and the second gate insulating layer 47. Figure 5j As shown.

[0133] S14. A third conductive layer 49 is deposited on the side of the first interlayer insulating layer 48 facing away from the substrate 11, such as... Figure 5k As shown.

[0134] The third conductive layer 49 includes a reference signal line Vref and a first storage capacitor C. st First plate C st1 The system includes a data line (Date), a first power signal line (VDD), and a reference signal line (Vref). The reference signal line (Vref) is electrically connected to the source region 453 of the active layer of the first reset transistor T2 via a second connection via 2. The first storage capacitor C... st First plate C st1 The first reset transistor T2 is electrically connected to the drain region 451 of the active layer via the third connection via 3, or the first storage capacitor C st First plate C st1 The third connection via 3 is electrically connected to the drain region 452 of the active layer of the switching transistor T1; the data line Date is electrically connected to the source region 454 of the active layer of the switching transistor T1 through the fourth connection via 4; the first power signal line VDD is electrically connected to the source region 413 of the active layer of the light-emitting control transistor T5 through the fifth connection via 5.

[0135] S15. A second insulating layer 4011 is deposited on the side of the third conductive layer 49 facing away from the substrate 11, such as... Figure 5l As shown.

[0136] The second insulating layer 4011 may be an insulating layer with the same material as the first insulating layer 44; or it may be the first passivation layer PVX1; or it may be an insulating layer composed of an insulating layer with the same material as the first insulating layer 44 and the first passivation layer PVX1. It can be set according to the actual application scenario, needs and experience. This disclosure embodiment does not make specific limitations.

[0137] S16. A fourth conductive layer 4010 is deposited on the side of the second insulating layer 4011 facing away from the substrate 11, such as... Figure 5m As shown.

[0138] The fourth conductive layer 4010 includes a first storage capacitor C st The second electrode plate C st2 First storage capacitor C st The second electrode plate C st2 The active layer of the driving transistor T4 is electrically connected to the drain region 414 via the sixth connection via 6.

[0139] Here, the sixth connecting via 6 is prepared after the deposition of the second insulating layer 4011 and before the deposition of the fourth conductive layer 4010. For the specific preparation process, please refer to the preparation process of the sixth connecting via 5 above. Repeated parts will not be described again.

[0140] S17. A third insulating layer 4012 is deposited on the side of the fourth conductive layer 4010 facing away from the substrate 11, such as... Figure 5n As shown.

[0141] The third insulating layer 4012 can be the second passivation layer PVX2.

[0142] S18. A hole is drilled in the fourth conductive layer 4010 on the side facing away from the substrate 11 to form a seventh connection via 7 penetrating the third insulating layer 4012. Then, a third semiconductor layer 4013 is deposited on the side of the third insulating layer 4012 facing away from the substrate 11. Figure 5o As shown.

[0143] Specifically, the third semiconductor layer 4013 includes the active layer of the second reset transistor T3. The active layer of the second reset transistor T3 includes a source region 4013-2, a drain region 4013-1, and a channel region 4013-3. The channel region 4013-3 of the active layer of the second reset transistor T3 overlaps with the orthographic projection of the channel region 455 of the active layer of the first reset transistor T2 onto the substrate 11.

[0144] S19. A third gate insulating layer 4016 is deposited on the side of the third semiconductor layer 4013 facing away from the substrate 11, such as... Figure 5p As shown.

[0145] S20. A fifth conductive layer 4014 is deposited on the side of the third gate insulating layer 4016 facing away from the substrate 11, such as... Figure 5q As shown.

[0146] Specifically, the fifth conductive layer 4014 includes the gate T31 of the second reset transistor T3, and the gate T31 of the second reset transistor T3 overlaps with the gate T21 of the first reset transistor T2 on the substrate 11.

[0147] S21. Using the fifth conductive layer 4014 as a mask, the third semiconductor layer 4013 is doped.

[0148] S22. A second interlayer insulating layer 4017 is deposited on the side of the fifth conductive layer 4014 facing away from the substrate 11, as follows: Figure 5r As shown.

[0149] S23, in the first storage capacitor C st The second electrode plate C st2 An eighth connection via 4012 is formed by drilling a hole on the side facing away from the substrate 11, penetrating the second interlayer insulating layer 4017, the third gate insulating layer 4016, and the third insulating layer 4012. A ninth connection via 4013 is formed by drilling a hole on the side facing away from the substrate 11, penetrating the second interlayer insulating layer 4017 and the third gate insulating layer 4016. Then, a sixth conductive layer 4015 is deposited on the side of the second interlayer insulating layer 4017 facing away from the substrate 11, as shown below. Figure 5s As shown.

[0150] The sixth conductive layer 4015 includes a second storage capacitor C. EL First plate C EL1 and the initialization signal line Vinit. Second storage capacitor C. EL First plate C EL1 The first storage capacitor C is connected via the eighth connection via 8. st The second electrode plate C st2 Electrical connection. The initialization signal line Vinit is electrically connected to the source region 4013-2 of the active layer of the second reset transistor T3 through the ninth connection via via9.

[0151] S24. A planarization layer 1018 is deposited on the side of the sixth conductive layer 4015 facing away from the substrate 11, such as... Figure 5t As shown.

[0152] S25. In the direction away from the substrate 11, holes are drilled in batches in the drain region 414 of the active layer of the driving transistor T4 (referring to the drilling method of the fifth connection via 5). Tenth connection vias 10 are formed through multiple tenth connection vias, penetrating the first gate insulating layer 43, the first insulating layer 44, the second gate insulating layer 47, the first interlayer insulating layer 48, the second insulating layer 4011, the third insulating layer 4012, the third gate insulating layer 4016, the second interlayer insulating layer 4017, and the planarization layer 4018. A seventh conductive layer 4019 (including the first electrode AND of the light-emitting device 122) is deposited on the side of the planarization layer 1018 away from the substrate 11. The first electrode AND is electrically connected to the drain region 414 of the active layer of the driving transistor T4 through the tenth connection via 10, as shown below. Figure 4 As shown.

[0153] S26, the second electrode of the light-emitting device 122 is respectively connected to the second storage capacitor C EL The second electrode plate C EL2 The second power signal line VSS is electrically connected and grounded.

[0154] In the above-mentioned method for preparing a display substrate, a pixel driving circuit for a pixel unit is formed on the substrate. In this method, the gates of at least two thin-film transistors of at least a portion of the pixel driving circuit have their orthogonal projections on the substrate at least partially overlapping. That is, the gates with orthogonal projections are disposed on different layers. This stacking arrangement can effectively reduce the area occupied by the thin-film transistors and increase the number of pixel units disposed per unit area, thereby meeting the pixel requirements of high PPI display devices.

[0155] Here, the specific structure of the display substrate in the method of forming pixel units can be found in the structure of the display substrate in the above-described display substrate embodiments, and will not be repeated here.

[0156] In some embodiments, the active layer of a thin-film transistor includes a source region, a drain region, and a channel region sandwiched between the source region and the drain region. The source region serves as the source of the thin-film transistor, and the drain region serves as the drain of the thin-film transistor.

[0157] To improve the conductivity of the source and drain of a thin-film transistor (TFT), the source and drain regions in the active layer of the TFT can be doped to make them conductive, thereby achieving electrical interconnection between the various structures. Specific doping methods include: doping phosphorus ions into the source and drain regions of the active layer of the TFT, for example, performing the doping process in steps S5, S11, and S21.

[0158] In addition, during the doping process, this disclosure may also include doping other impurities, such as P-type impurities (trivalent boron B ions, etc.), in the source and drain regions of the active layer, besides differential N-type impurities (i.e., P ions).

[0159] Here, the doping method of phosphorus ions in the source and drain regions of the active layer of the thin-film transistor can be found in the detailed description of the specific structure of the display substrate described above, and will not be repeated here.

[0160] According to an embodiment of this disclosure, a display device is also provided, including the display substrate described in the above embodiments.

[0161] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, characterized in that, It includes a substrate and a plurality of pixel units disposed on the substrate; the pixel unit includes a pixel driving circuit. In at least a portion of the pixel driving circuit, the orthogonal projections of the gates of at least two thin-film transistors onto the substrate at least partially overlap. The display substrate further includes a third semiconductor layer, a fifth conductive layer and a sixth conductive layer disposed sequentially along a direction away from the substrate. The pixel driving circuit also includes a first storage capacitor, a second reset transistor, and a second storage capacitor; The third semiconductor layer includes the active layer of the second reset transistor; the drain region of the active layer of the second reset transistor is electrically connected to the second plate of the first storage capacitor through a seventh connection via. The fifth conductive layer includes the gate of the second reset transistor; The sixth conductive layer includes a first plate of the second storage capacitor and an initialization signal line; the first plate of the second storage capacitor is electrically connected to the second plate of the first storage capacitor through an eighth connection via; the initialization signal line is electrically connected to the drain region of the active layer of the second reset transistor through a ninth connection via.

2. The display substrate according to claim 1, characterized in that, The thin-film transistor includes an active layer; the active layer includes a source region, a drain region, and a channel region sandwiched between the source region and the drain region; the source region serves as the source of the thin-film transistor, and the drain region serves as the drain of the thin-film transistor.

3. The display substrate according to claim 2, characterized in that, Both the source region and the drain region are doped with phosphorus ions.

4. The display substrate according to claim 2, characterized in that, The pixel driving circuit includes a switching transistor, a first reset transistor, a driving transistor, and a light-emitting control transistor; the gates of the first reset transistor and the gates of the second reset transistor overlap on the substrate.

5. The display substrate according to claim 4, characterized in that, The display substrate includes a first semiconductor layer and a first conductive layer sequentially disposed on the substrate. The active layer of the driving transistor and the active layer of the light-emitting control transistor are located in the first semiconductor layer. The gate of the driving transistor and the gate of the light-emitting control transistor are located in the first conductive layer.

6. The display substrate according to claim 5, characterized in that, The display substrate further includes a second semiconductor layer and a second conductive layer sequentially disposed on the side of the first conductive layer away from the substrate. The active layer of the first reset transistor and the active layer of the switching transistor are located in the second semiconductor layer; the drain region of the active layer of the first reset transistor and the drain region of the active layer of the switching transistor are connected to form an integral structure, and are electrically connected to the gate of the driving transistor through the first connection via. The gate of the first reset transistor and the gate of the switching transistor are located in the second conductive layer.

7. The display substrate according to claim 6, characterized in that, The display substrate further includes a third conductive layer and a fourth conductive layer disposed sequentially on the side of the second conductive layer facing away from the substrate. The third conductive layer includes a reference signal line, a first electrode of the first storage capacitor, a data line, and a first power signal line. The reference signal line is electrically connected to the source region of the active layer of the first reset transistor through a second connection via. The first electrode of the first storage capacitor is electrically connected to the drain region of the active layer of the first reset transistor through a third connection via, or the first electrode of the first storage capacitor is electrically connected to the drain region of the active layer of the switching transistor through a third connection via. The data line is electrically connected to the source region of the active layer of the switching transistor through a fourth connection via. The first power signal line is electrically connected to the source region of the active layer of the light-emitting control transistor through a fifth connection via. The fourth conductive layer includes the second electrode of the first storage capacitor; the second electrode of the first storage capacitor is electrically connected to the drain region of the active layer of the driving transistor through a sixth connection via.

8. The display substrate according to claim 4, characterized in that, The pixel unit further includes a light-emitting device; the display substrate further includes a seventh conductive layer disposed on the side of the sixth conductive layer opposite to the substrate; the first electrode of the light-emitting device is located on the seventh conductive layer; the first electrode of the light-emitting device is electrically connected to the drain region of the active layer of the driving transistor through a tenth connection via.

9. The display substrate according to claim 4, characterized in that, The pixel driving circuit includes a switching transistor, a first reset transistor, a second reset transistor, a driving transistor, and a light-emitting control transistor; the gate of the driving transistor and the gate of the switching transistor at least partially overlap on the substrate.

10. The display substrate according to any one of claims 1 to 9, characterized in that, The active layer is a metal oxide active layer.

11. A method for preparing a display substrate, characterized in that, include: Multiple pixel units are formed on the substrate. The method of forming a plurality of pixel units on a substrate includes: a pixel driving circuit for forming the pixel units; wherein the orthogonal projections of the gates of at least two thin-film transistors of at least a portion of the pixel driving circuit on the substrate at least partially overlap. The pixel driving circuit forming the pixel unit includes: forming a third semiconductor layer on the substrate, forming a fifth conductive layer on the side of the third semiconductor layer facing away from the substrate, and forming a sixth conductive layer on the side of the fifth conductive layer facing away from the substrate; the pixel driving circuit further includes a first storage capacitor, a second reset transistor, and a second storage capacitor; the third semiconductor layer includes the active layer of the second reset transistor; the drain region of the active layer of the second reset transistor is electrically connected to the second plate of the first storage capacitor through a seventh connection via; the fifth conductive layer includes the gate of the second reset transistor; the sixth conductive layer includes the first plate of the second storage capacitor and an initialization signal line; the first plate of the second storage capacitor is electrically connected to the second plate of the first storage capacitor through an eighth connection via; the initialization signal line is electrically connected to the drain region of the active layer of the second reset transistor through a ninth connection via.

12. The method for preparing a display substrate according to claim 11, characterized in that, The active layer of the thin-film transistor includes a source region, a drain region, and a channel region sandwiched between the source region and the drain region; the source region serves as the source of the thin-film transistor, and the drain region serves as the drain of the thin-film transistor. The method further includes: Phosphorus ions are doped into the source and drain regions of the active layer of the thin-film transistor, respectively.

13. A display device, characterized in that, Includes the display substrate as described in any one of claims 1 to 10.

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