A low-latency rate matching method, device, electronic device, and storage medium

Abstract

The present invention provides a low-latency rate matching method, apparatus, electronic device, and storage medium. The method includes: performing data pre-packeting on communication data to obtain packetized communication data; using the initial data in the packetized communication data as the starting data, performing interleaved cyclic processing on the packetized communication data to obtain multiple cyclic extraction data, and realizing rate matching output according to the multiple cyclic extraction data; wherein, the interleaved cycle includes multiple offset cycles. By dividing the communication data into n×n data flow blocks and then completing interleaving through an interleaved cycle including multiple offset cycles, it can enable the communication data after pre-packeting to be input in parallel with n data. After interleaving is completed, n data are output in parallel, greatly reducing the processing latency. Compared with a simple parallel processing algorithm, it can adapt to the rate matching function under a variety of different modulation modes and has higher resource utilization.

Description

Technical Field

[0001] The present invention relates to the field of information processing technologies, and in particular, to a low-latency rate matching method, apparatus, electronic device, and storage medium. Background Art

[0002] With the development of communication technologies, millisecond-level end-to-end latency requirements are proposed for 5G. Ideally, the end-to-end latency of 5G is 1 ms, and the typical end-to-end latency is about 5 - 10 ms. For the 4G network we currently use, the ideal end-to-end latency is about 10 ms, and the typical end-to-end latency of LTE is 50 - 100 ms, which means that 5G needs to reduce the end-to-end latency to one-tenth of that of 4G.

[0003] In such a situation, 5G will face challenges such as large bandwidth and low latency. For the rate matching module, it will face the requirement of a larger amount of data but a lower processing delay. The traditional rate matching algorithm first caches the received data using a memory, then completes interleaving through jump addresses according to the interleaving positions, and then writes to a circular buffer and inserts NULL bits to complete rate matching. Such processing will bring a large processing delay after the amount of data increases.

[0004] Therefore, how to better achieve low-latency rate matching has become an urgent problem in the industry. Summary of the Invention

[0005] The present invention provides a low-latency rate matching method, apparatus, electronic device, and storage medium to solve the defect that a large processing delay will be brought after the amount of data increases when completing rate matching in the prior art, and to achieve low-latency rate matching.

[0006] According to a low-latency rate matching method provided by the present invention, it includes:

[0007] Performing data pre-grouping on communication data to obtain grouped communication data;

[0008] Taking the initial data in the grouped communication data as the starting data, performing interleaving loop processing on the grouped communication data to obtain multiple loop extraction data, and realizing rate matching output according to the multiple loop extraction data;

[0009] Wherein, the interleaving loop includes multiple offset loops.

[0010] According to a low-latency rate matching method provided by the present invention, the step of performing data pre-grouping on communication data to obtain multiple groups of grouped communication data is specifically:

[0011] Divide the communication data into n groups, and then divide each group of the grouped communication data into n data bits to obtain an n×n data stream block, thereby obtaining the grouped communication data;

[0012] Wherein, n is determined according to the latency requirement and resource requirement of the communication data.

[0013] According to a low-latency rate matching method provided by the present invention, the step of performing interleaved cyclic processing on the grouped communication data at a preset interval starting from the initial data in the grouped communication data to obtain multiple cyclic extraction data specifically includes:

[0014] Determine the offset cyclic target number of times and the offset cyclic selected data number in the interleaved cycle according to the preset number of interleaved cycles and the number of groups of the grouped communication data;

[0015] Perform multiple offset cycles according to the offset cyclic selected data number. When the first preset condition is satisfied, complete one interleaved cycle;

[0016] Repeat the interleaved cycle until the second preset condition is satisfied to obtain multiple cyclic extraction data;

[0017] Wherein, the first preset condition refers to that the number of times of performing the offset cycle reaches the offset cyclic target number of times;

[0018] Wherein, the second preset condition refers to that the number of times of the interleaved cycle reaches the preset number of offset cycles.

[0019] According to a low-latency rate matching method provided by the present invention, the step of performing multiple offset cycles according to the offset cyclic selected data number specifically includes:

[0020] Starting from the starting data, extract data every m data bits to obtain the extracted data of the offset cyclic selected data number, complete one offset cycle, and then perform multiple offset cycles;

[0021] Wherein, m is the preset number of interleaved cycles.

[0022] According to a low-latency rate matching method provided by the present invention, after the step of performing interleaved cyclic processing on the grouped communication data to obtain multiple cyclic extraction data, the method further includes:

[0023] After obtaining multiple cyclic extraction data, when there is still a residual data stream block in the grouped communication data, translate the residual data stream block according to the number of shifted bits;

[0024] Wherein, the number of shifted bits is determined according to the total length of the cyclic extraction data.

[0025] A low-latency rate matching method provided by the present invention, the step of implementing rate matching output according to the multiple cyclic decimation data specifically includes:

[0026] Input the multiple cyclic decimation data into a cyclic buffer to cyclically write into the cyclic buffer according to the length of a preset cyclic buffer;

[0027] When reading data from the cyclic buffer, pause data reading when reaching the address corresponding to the NULL bit, and insert the NULL bit by outputting the NULL bit to implement rate matching output.

[0028] The present invention also provides a low-latency rate matching device, including:

[0029] A grouping module for pre-grouping communication data to obtain grouped communication data;

[0030] A matching module for performing interleaved cyclic processing on the grouped communication data starting from the initial data in the grouped communication data to obtain multiple cyclic decimation data, and implementing rate matching output according to the multiple cyclic decimation data;

[0031] Wherein, the interleaved cycle includes multiple offset cycles.

[0032] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of the low-latency rate matching method as described in any one of the above are implemented.

[0033] The present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the low-latency rate matching method as described in any one of the above are implemented.

[0034] A low-latency rate matching method, device, electronic device, and storage medium provided by the present invention divide communication data into n×n data stream blocks, and then complete interleaving through an interleaved cycle including multiple offset cycles. It can implement n data in parallel input after pre-grouping, and n data in parallel output after interleaving is completed, greatly reducing the processing latency. Compared with a simple parallel processing algorithm, it can adapt to the rate matching function under a variety of different modulation methods and has higher resource utilization. Description of the Drawings

[0035] To more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a schematic flowchart of the low-latency rate matching method provided by the present invention;

[0037] Figure 2 It is one of the schematic diagrams of the interleaving cycle provided by the present invention;

[0038] Figure 3 It is another schematic diagram of the interleaving cycle provided by the present invention;

[0039] Figure 4 It is a schematic flowchart of the rate dematching process provided by the present invention;

[0040] Figure 5 It is a schematic structural diagram of the low-latency rate matching device provided by the present invention;

[0041] Figure 6 It is a schematic entity structure diagram of the electronic device provided by the present invention. Specific Embodiments

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0043] The following will describe Figures 1 - 4 the low-latency rate matching method of the present invention

[0044] Figure 1 is a schematic flowchart of the low-latency rate matching method provided by the present invention. As Figure 1 shown, it includes:

[0045] Step S1: Perform data pre-grouping on the communication data to obtain grouped communication data;

[0046] Specifically, the data pre-grouping described in the embodiments of the present invention is as follows: First, the communication data is divided into n groups, and the number of n is set according to the requirements for the latency of the communication data and the requirements for the communication data resources. When the latency requirement is lower, n is larger; when the resource consumption is lower, n is smaller. The specific value of n can be input in advance.

[0047] The data is written into different groups in sequence. Each group of data contains n data bits. Only one data is written each time. After writing, it returns to the first group and continues to write data until all data is written, obtaining grouped communication data.

[0048] Step S2: Taking the initial data in the grouped communication data as the starting data, performing an interleaved loop process on the grouped communication data to obtain multiple loop extraction data, and realizing rate matching output according to the multiple loop extraction data;

[0049] Among them, the interleaved loop includes multiple offset loops.

[0050] Specifically, the initial data described in the embodiments of the present invention may specifically refer to the first data stream block of the first group in the grouped communication data, or may be any specified data stream block in the grouped communication data.

[0051] The specific process of performing an interleaved loop process on the grouped communication data in the embodiments of the present invention is as follows: First, determine the number of interleaved loops, and then execute the interleaved loop according to this number. Each interleaved loop consists of multiple offset loops. The number of data stream blocks selected each time for the offset loop is specifically loop_r = floor(n * n / m)+1, where n is the number of groups of the grouped communication data, and m is the preset number of interleaved loops.

[0052] After determining the number of data stream blocks selected each time for the offset loop, calculate the number of offset loops included in each interleaved loop as m / loop_r according to it, and only read the data once for each offset loop.

[0053] Perform an interleaved loop process according to the number of data stream blocks selected each time for the above offset loop and the number of offset loops included in each interleaved loop to obtain multiple loop extraction data, and input the multiple loop extraction data into a cyclic buffer to cyclically write into the cyclic buffer according to the length of the preset cyclic buffer;

[0054] When reading data from the cyclic buffer, pause data reading when reading the address corresponding to the NULL bit, and insert the NULL bit by the way of outputting the NULL bit to realize rate matching output.

[0055] In the embodiments of the present invention, the communication data is segmented into n×n data stream blocks, and then interleaving is completed through an interleaved loop including multiple offset loops. It can realize that the communication data after pre-grouping is input in parallel with n data. After interleaving, n data are output in parallel, greatly reducing the processing delay. And compared with a simple parallel processing algorithm, it can adapt to the rate matching function under a variety of different modulation methods and has higher resource utilization.

[0056] Based on the above embodiments, the step of pre-grouping communication data to obtain multiple groups of grouped communication data is specifically as follows:

[0057] Divide the communication data into n groups, and then divide each group of the grouped communication data into n data bits to obtain a data stream block of n×n, thereby obtaining the grouped communication data;

[0058] Wherein, n is determined according to the delay requirement and resource requirement of the communication data.

[0059] Specifically, first divide the communication data into n groups. The number of n is set according to the delay requirement of the communication data and the requirement of the communication data resources. The lower the delay requirement, the larger n is, and the lower the resource consumption, the smaller n is. The specific value of n can be input in advance.

[0060] The data is written into different groups in sequence. Each group of data contains n data bits. Only one data is written each time. After writing, return to the first group and continue writing data until all data is written to obtain the grouped communication data.

[0061] In the embodiment of the present invention, the communication data is first grouped to facilitate subsequent interleaving processing.

[0062] Based on the above embodiments, the step of performing interleaved loop processing on the grouped communication data according to the initial data in the grouped communication data as the starting data at a preset interval to obtain multiple loop extraction data specifically includes:

[0063] Determine the target number of offset loops and the number of data selected for offset loops in the interleaved loop according to the preset number of interleaved loops and the number of groups of the grouped communication data;

[0064] Perform multiple offset loops according to the number of data selected for offset loops. When the first preset condition is met, one interleaved loop is completed;

[0065] Repeat the interleaved loop until the second preset condition is met to obtain multiple loop extraction data;

[0066] Wherein, the first preset condition refers to that the number of times of performing the offset loop reaches the target number of offset loops;

[0067] Wherein, the second preset condition refers to that the number of times of the interleaved loop reaches the preset number of offset loops.

[0068] The step of performing multiple offset loops according to the number of data selected for offset loops specifically includes:

[0069] Starting from the initial data, data extraction is performed every m data bits to obtain the extracted data with the number of data selected in an offset cycle, completing one offset cycle, and then performing multiple offset cycles;

[0070] where m is the preset interleaving cycle number.

[0071] Specifically, in the embodiments of the present invention, each interleaving cycle consists of multiple offset cycles, and the number of data stream blocks selected each time in the offset cycle is specifically loop_r = floor(n*n / m)+1, where n is the number of groups of packet communication data and m is the preset interleaving cycle number.

[0072] After determining the number of data stream blocks selected each time in the offset cycle, the number of offset cycles included in each interleaving cycle is calculated as m / loop_r according to it, and data is read only once in each offset cycle.

[0073] In the embodiments of the present invention, the number of data stream blocks selected each time in the offset cycle refers to the number of data stream blocks captured in one offset cycle.

[0074] The preset interleaving cycle number described in the embodiments of the present invention is determined according to the modulation level, and the values are 1 / 2 / 4 / 6 / 8, or it can also be set by itself according to requirements.

[0075] Figure 2 is one of the schematic diagrams of the interleaving cycle provided by the present invention, Figure 3 is the second schematic diagram of the interleaving cycle provided by the present invention, as Figure 2 and Figure 3 shown, the data read from each pre-group is numbered 1, 2, 3... n*n in sequence. Starting from 1, data is extracted at an interval of m, Figure 2 The positions of the first three data selected in the described selection are S1 = 1; S2 = n+2; S3 = 2*n+3; and so on. It should satisfy S1+m-1 = S2; S2+m-1 = S3; and so on until the completion of this data extraction, a total of loop_r data. When the second offset cycle is selected, starting from n+1, data is extracted at an interval of m, Figure 3The first three selected data positions described this time are S1 = n + 1; S2 = 2*n + 2; S3 = 3*n + 3, and so on. It should satisfy S1 + m - 1 = S2; S2 + m - 1 = S3; and so on until the completion of this data extraction, with a total of loop_r data. After that, during each interleaving loop, the data output loop is controlled by the loop connection shift module to ensure the data connection in the case of non-integer multiples during each interleaving. The number of shifted bits is mod(E / m,n), where E is the total length of the input data, and mod() represents the modulo n of the data E / m. This can ensure that the data after pre-grouping is input in parallel with n data, and the data after passing through the adaptive interleaving module is also output in parallel with n, greatly reducing the processing delay.

[0076] Based on the above embodiments, after the step of performing interleaving loop processing on the packet communication data to obtain a plurality of loop extraction data, the method further includes:

[0077] After obtaining a plurality of loop extraction data, in the case where there are still residual data stream blocks in the packet communication data, shift the residual data stream blocks according to the number of shifted bits;

[0078] Wherein, the number of shifted bits is determined according to the total length of the loop extraction data.

[0079] Specifically, during subsequent interleaving loops, if it is detected that after the completion of the interleaving loop, there are still residual data stream blocks in the packet communication data that have not been extracted, shift them according to the number of shifted bits so that they can be extracted in the next interleaving loop.

[0080] The specific number of shifted bits is mod(E / m,n), where E is the total length of the loop extraction data, and mod() represents the modulo n of the data E / m.

[0081] The embodiments of the present invention can ensure that the data after pre-grouping is input in parallel with n data, and the data after passing through the adaptive interleaving module is also output in parallel with n, greatly reducing the processing delay.

[0082] Based on the above embodiments, the step of implementing rate matching output according to the plurality of loop extraction data specifically includes:

[0083] Input the plurality of loop extraction data into a loop buffer to be cyclically written into the loop buffer according to the length of the preset loop buffer;

[0084] When reading data from the loop buffer, pause data reading when reading the address corresponding to the NULL bit, and insert NULL bits by outputting NULL bits to achieve rate matching output.

[0085] Specifically, after obtaining multiple loop-extracted data, it passes through a loop buffer writing module, and the data is cyclically written into the cache according to the set loop buffer length. Finally, it is output through a rate matching output module. This module does not require cache space. Instead, when reading data from the loop buffer, it pauses data reading when reading the address corresponding to the NULL bit, and inserts the NULL bit by outputting the NULL bit.

[0086] Compared with the traditional method, this module can reduce the processing delay by n times, and compared with the simple parallel processing algorithm, the resource consumption is reduced by 5 times.

[0087] Figure 4 It is a schematic diagram of the rate dematching process provided by the present invention. As Figure 4 shown, it includes a data preprocessing part, an adaptive interleaving part, a buffer writing part, and a rate matching output part; data pre-grouping, which first divides the data into n groups. The number of n is set according to the delay requirement and resource requirement. The lower the delay requirement, the larger n is, and the lower the resource consumption, the smaller n is. The received data is sequentially written into different groups, and only one data is written each time. After writing, it returns to group 1 to continue writing data until all data is written.

[0088] Adaptive interleaving: The data enters the adaptive interleaving module. According to the data modulation method, the value of the interleaving cycle number m is the same as the modulation level, and the values are 1 / 2 / 4 / 6 / 8, which is controlled by the interleaving cycle controller. Each interleaving cycle consists of multiple offset cycles. n data are read from each path of the data pre-grouping. The number of selectable data is loop_r = floor(n * n / m) + 1. The offset cycle controller selects the initial data address as 1, and the next data address is the previous data address plus m. The number of times of each offset cycle is m / loop_r, and this process is controlled by the loop offset controller. Each offset cycle reads data only once. After that, during each interleaving cycle, the loop connection shift module controls the data output cycle to ensure data connection in the case of non-integer multiples. The number of its shift bits is mod(E / m, n), where E is the total length of the input data, and mod() represents the modulus of data E / m divided by n. This can ensure that the data after pre-grouping is input in parallel with n data, and the data after passing through the adaptive interleaving module is also output in parallel with n data, greatly reducing the processing delay.

[0089] Loop buffer writing: The data then passes through the loop buffer writing module, and the data is cyclically written into the cache according to the set loop buffer length.

[0090] The rate matching output is finally output through the rate matching output module. This module does not require a cache space. Instead, when reading data from the cyclic buffer, it pauses data reading when reading the address corresponding to the NULL bit, and inserts NULL bits in the way of outputting NULL bits.

[0091] The low-latency rate matching device provided by the present invention will be described below. The low-latency rate matching method described below can be correspondingly referred to the low-latency rate matching method described above.

[0092] Figure 5 It is a schematic structural diagram of the low-latency rate matching device provided by the present invention. As Figure 5 shown, it includes: a grouping module 510 and a matching module 520; wherein, the grouping module 510 is used to perform data pre-grouping on communication data to obtain grouped communication data; wherein, the matching module 520 is used to use the initial data in the grouped communication data as the starting data, perform interleaved cyclic processing on the grouped communication data to obtain multiple cyclic extraction data, and implement rate matching output according to the multiple cyclic extraction data; wherein, the interleaved cycle includes multiple offset cycles.

[0093] The device provided by the embodiment of the present invention is used to execute the above-mentioned method embodiments. For the specific process and detailed content, please refer to the above embodiments, and will not be elaborated here.

[0094] In the embodiment of the present invention, the communication data is segmented into data stream blocks of n×n, and then interleaving is completed through an interleaved cycle including multiple offset cycles. It can realize that the communication data after pre-grouping is input in parallel with n data. After interleaving is completed, n data are output in parallel, which greatly reduces the processing latency. Compared with the simple parallel processing algorithm, it can adapt to the rate matching function under a variety of different modulation methods and has higher resource utilization.

[0095] Figure 6 It is a schematic structural diagram of the electronic device entity provided by the present invention. As Figure 6As shown in the figure, the electronic device may include: a processor 610, a communications interface 620, a memory 630, and a communication bus 640. Among them, the processor 610, the communications interface 620, and the memory 630 complete mutual communication through the communication bus 640. The processor 610 may call logic instructions in the memory 630 to execute a low-latency rate matching method, which includes: performing data pre-packeting on communication data to obtain packetized communication data; using the initial data in the packetized communication data as the starting data, performing interleaved cyclic processing on the packetized communication data to obtain a plurality of cyclic extraction data, and implementing rate matching output according to the plurality of cyclic extraction data; wherein, the interleaved cycle includes multiple offset cycles.

[0096] In addition, when the logic instructions in the above-mentioned memory 630 are implemented in the form of software functional units and sold or used as independent products, they may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, may be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0097] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the low-latency rate matching method provided by the above-mentioned various methods. The method includes: performing data pre-packeting on communication data to obtain packetized communication data; using the initial data in the packetized communication data as the starting data, performing interleaved cyclic processing on the packetized communication data to obtain a plurality of cyclic extraction data, and implementing rate matching output according to the plurality of cyclic extraction data; wherein, the interleaved cycle includes multiple offset cycles.

[0098] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it is configured to execute the low-latency rate matching method provided in the above-mentioned embodiments. The method includes: performing data pre-packeting on communication data to obtain packetized communication data; using the initial data in the packetized communication data as the starting data, performing interleaved cyclic processing on the packetized communication data to obtain a plurality of cyclic extraction data, and realizing rate matching output according to the plurality of cyclic extraction data; wherein, the interleaved cycle includes multiple offset cycles.

[0099] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative labor.

[0100] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course also by hardware. Based on this understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disc, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A low-latency rate matching method, characterized in that It includes: Performing data pre-grouping on communication data to obtain grouped communication data; Using the initial data in the grouped communication data as the starting data, performing interleaved cyclic processing on the grouped communication data to obtain multiple cyclic extraction data, and implementing rate matching output according to the multiple cyclic extraction data; Among them, the interleaved cycle includes multiple offset cycles; Among them, the step of performing data pre-grouping on communication data to obtain multiple groups of grouped communication data is specifically: Dividing the communication data into n groups, and then dividing each group of grouped communication data into n data bits to obtain an n×n data stream block, thereby obtaining the grouped communication data; Among them, n is determined according to the delay requirement and resource requirement of the communication data; Among them, the step of performing interleaved cyclic processing on the grouped communication data according to the initial data in the grouped communication data as the starting data at a preset interval to obtain multiple cyclic extraction data specifically includes: Determining the target number of offset cycles and the number of data bits selected for offset cycles in the interleaved cycle according to the preset number of interleaved cycles and the number of groups of the grouped communication data; Performing multiple offset cycles according to the number of data bits selected for offset cycles, and when the first preset condition is met, completing one interleaved cycle; Repeating the execution of the interleaved cycle until the second preset condition is met to obtain multiple cyclic extraction data; Among them, the first preset condition means that the number of times of performing the offset cycle reaches the target number of offset cycles; Among them, the second preset condition means that the number of times of the interleaved cycle reaches the preset number of offset cycles.

2. The low-latency rate matching method according to claim 1, wherein The step of performing multiple offset cycles according to the number of data bits selected for offset cycles specifically includes: Starting from the starting data, extracting data every m data bits to obtain the number of extracted data bits selected for the offset cycle, completing one offset cycle, and then performing multiple offset cycles; Among them, m is the preset number of interleaved cycles.

3. The low-latency rate matching method according to claim 1, characterized in that After the step of performing interleaved cyclic processing on the grouped communication data to obtain multiple cyclic extraction data, the method further includes: After obtaining multiple cyclic extraction data, when there are still residual data stream blocks in the grouped communication data, translating the residual data stream blocks according to the number of shifted bits; Among them, the number of shifted bits is determined according to the total length of the cyclic extraction data.

4. The low-latency rate matching method according to claim 1, wherein The step of implementing rate matching output according to the multiple cyclic extraction data specifically includes: Inputting the multiple cyclic extraction data into a cyclic buffer to cyclically write into the cyclic buffer according to the length of the preset cyclic buffer; When reading data from the cyclic buffer, inserting NULL bits by pausing data reading when the address corresponding to the NULL bit is read and outputting the NULL bit to implement rate matching output.

5. A low-latency rate matching device, characterized in that It includes: A grouping module for performing data pre-grouping on communication data to obtain grouped communication data; A matching module for using the initial data in the grouped communication data as the starting data, performing interleaved cyclic processing on the grouped communication data to obtain multiple cyclic extraction data, and implementing rate matching output according to the multiple cyclic extraction data; Among them, the interleaved cycle includes multiple offset cycles; Wherein, the device is further configured to: Divide the communication data into n groups, and then divide each group of the grouped communication data into n data bits to obtain an n×n data stream block, thereby obtaining grouped communication data; Wherein, n is determined according to the latency requirement and resource requirement of the communication data; Wherein, the step of performing interleaved cyclic processing on the grouped communication data at a preset interval with the initial data in the grouped communication data as the starting data to obtain multiple cyclic extraction data specifically includes: Determine the target number of offset cycles and the number of data selected for offset cycles in the interleaved cycle according to the preset number of interleaved cycles and the number of groups of the grouped communication data; Perform multiple offset cycles according to the number of data selected for offset cycles, and when a first preset condition is satisfied, complete one interleaved cycle; Repeat the interleaved cycle until a second preset condition is satisfied to obtain multiple cyclic extraction data; Wherein, the first preset condition refers to that the number of offset cycles reaches the target number of offset cycles; Wherein, the second preset condition refers to that the number of interleaved cycles reaches the preset number of offset cycles.

6. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, the steps of the low-latency rate matching method according to any one of claims 1 to 4 are implemented.

7. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the low-latency rate matching method according to any one of claims 1 to 4 are implemented.

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