Packaged circuit board and circuit board packaging method

Abstract

The packaged circuit board and circuit board packaging method provided in the embodiments of the present application include: a multi-layer circuit board, a plurality of first components are arranged on the front and / or back of the multi-layer circuit board, wherein for any layer of the circuit board, M internal conductive structures and N side wall conductive structures are arranged on the circuit board, the N side wall conductive structures are located on the side wall of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, the internal conductive structure is used to connect the plurality of second components with the plurality of first components, and M and N are integers greater than or equal to 1 respectively. There are at least two layers of circuit boards in the multi-layer circuit board with conductive holes arranged therebetween, and the conductive holes are used to connect at least two layers of circuit boards. Among them, by designing a graded side conductive structure on the circuit board, the components can be graded and mounted on the side of the circuit board, thereby increasing the number of side components mounted.

Description

Technical Field

[0001] The embodiments of the present application relate to circuit board manufacturing technology, and more particularly to a packaged circuit board and a circuit board packaging method. Background Art

[0002] With the development of multifunctionality and high performance of terminal electronic products, new requirements are put forward for the network structure design of the circuit board of its core functional components, such as the requirement for the overall area and volume of the circuit board to be gradually reduced, and the number of conductive structures per unit area or volume to be increased. In the circuit board packaging process of electronic products, the main functional components are generally packaged on the front and back sides, but the front and back packaging areas of the circuit board can no longer meet its application requirements.

[0003] At present, in the prior art of packaging circuit boards, a through half-hole packaging structure is usually provided on the side of the circuit board so that components can be packaged on the side of the circuit board, thereby expanding the component packaging area of ​​the circuit board.

[0004] However, due to the half-hole packaging structure provided in the side packaging area in the prior art, there is a problem of limited number of packaged components when packaging components. Summary of the invention

[0005] The embodiments of the present application provide a packaged circuit board and a circuit board packaging method to improve the problem of limited number of components packaged on the side of the circuit board.

[0006] In a first aspect, an embodiment of the present application provides a packaged circuit board, comprising: a multi-layer circuit board, on the front and / or back of the multi-layer circuit board are arranged a plurality of first components, wherein:

[0007] For any layer of the circuit board, M internal conductive structures and N side wall conductive structures are arranged on the circuit board, the N side wall conductive structures are located on the side walls of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, the internal conductive structure is used to connect the plurality of second components with the plurality of first components, and M and N are integers greater than or equal to 1 respectively;

[0008] There are at least two layers of circuit boards in the multi-layer circuit board, and a conducting hole is arranged between them. The conducting hole is used to make the at least two layers of circuit boards communicate with each other.

[0009] In a possible design, for any internal conductive structure, the internal conductive structure is connected to at least one of the plurality of first components;

[0010] For any sidewall conductive structure, the sidewall conductive structure is connected to at least one of the M internal conductive structures.

[0011] In a possible design, a second component is disposed on a sidewall conductive structure, and the second component is connected to the sidewall conductive structure.

[0012] In a possible design, for any layer of a circuit board, the circuit board includes a plurality of circuit units, and the M internal conductive structures and the N sidewall conductive structures are respectively located on sides of the plurality of circuit units.

[0013] In a possible design, the conductive via includes at least two internal conductive structures, and the at least two internal conductive structures are located on at least two adjacent layers of circuit boards, and the at least two internal conductive structures are connected.

[0014] In a second aspect, an embodiment of the present application provides a circuit board packaging method, comprising:

[0015] For any layer of a multi-layer circuit board, M internal conductive structures are formed inside the circuit board, and N side wall conductive structures are formed on the side wall of the circuit board; a plurality of first components are arranged on the front and / or back surface of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, and the internal conductive structures are used to connect the plurality of second components with the plurality of first components, and M and N are integers greater than or equal to 1 respectively;

[0016] A via hole is formed between at least two layers of the multi-layer circuit board, and the via hole is used to connect the at least two layers of the circuit board.

[0017] In a possible design, M internal conductive structures are formed inside the circuit board, and N sidewall conductive structures are formed on the sidewalls of the circuit board, including:

[0018] Forming M laser blind holes inside the circuit board, and electroplating and filling the M laser blind holes to form the M internal conductive structures;

[0019] N laser blind holes are formed on the side wall of the circuit board, and the N laser blind holes are filled with electroplating, and the side wall of the circuit board is cut away to form the N side wall conductive structures.

[0020] In a possible design, the N laser blind holes are filled with electroplating, and the sidewalls of the circuit board are cut away to form the N sidewall conductive structures, including:

[0021] Filling the N laser blind holes with electroplating to obtain N electroplated conductive structures;

[0022] Determining a sidewall cut line, wherein the sidewall cut line intersects the N electroplated via structures;

[0023] The side wall of the circuit board is cut along the side wall cutting line to form the N side wall conductive structures, and the cutting process is used to cut off a part of the N electroplated conductive structures to expose the conductors inside the N electroplated conductive structures.

[0024] In a possible design, the circuit board includes a plurality of circuit units; M laser blind holes are formed inside the circuit board, including:

[0025] Determine a first target circuit unit among the plurality of circuit units, wherein the first target circuit unit is located at a center position of the circuit board;

[0026] The M laser blind holes are formed at preset positions in the first target circuit unit, and the preset positions are located at sides of the first target circuit unit.

[0027] In a possible design, the circuit board includes a plurality of circuit units; and N laser blind holes are formed on the side wall of the circuit board, including:

[0028] Determine a second target circuit unit among the plurality of circuit units, wherein the second target circuit unit is located at an edge position of the circuit board;

[0029] The N laser blind holes are formed at preset positions in the second target circuit unit, and the preset positions are located at sides of the second target circuit unit.

[0030] In a third aspect, an embodiment of the present application provides a circuit board packaging device, including:

[0031] A processing module, for forming M internal conductive structures inside any layer of a multi-layer circuit board, and forming N side wall conductive structures on the side wall of the circuit board; a plurality of first components are arranged on the front and / or back of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, and the internal conductive structures are used to connect the plurality of second components with the plurality of first components, wherein M and N are integers greater than or equal to 1 respectively;

[0032] The conducting module is used to form a conducting hole between at least two layers of the multi-layer circuit board, and the conducting hole is used to connect the at least two layers of the circuit board.

[0033] In one possible design, the processing module is used to:

[0034] Forming M laser blind holes inside the circuit board, and electroplating and filling the M laser blind holes to form the M internal conductive structures;

[0035] N laser blind holes are formed on the side wall of the circuit board, and the N laser blind holes are filled with electroplating, and the side wall of the circuit board is cut away to form the N side wall conductive structures.

[0036] In one possible design, the processing module is used to:

[0037] Filling the N laser blind holes with electroplating to obtain N electroplated conductive structures;

[0038] Determining a sidewall cut line, wherein the sidewall cut line intersects the N electroplated via structures;

[0039] The side wall of the circuit board is cut along the side wall cutting line to form the N side wall conductive structures, and the cutting process is used to cut off a part of the N electroplated conductive structures to expose the conductors inside the N electroplated conductive structures.

[0040] In one possible design, the processing module is used to:

[0041] Determine a first target circuit unit among the plurality of circuit units, wherein the first target circuit unit is located at a center position of the circuit board;

[0042] The M laser blind holes are formed at preset positions in the first target circuit unit, and the preset positions are located at sides of the first target circuit unit.

[0043] In one possible design, the processing module is used to:

[0044] Determine a second target circuit unit among the plurality of circuit units, wherein the second target circuit unit is located at an edge position of the circuit board;

[0045] The N laser blind holes are formed at preset positions in the second target circuit unit, and the preset positions are located at sides of the second target circuit unit.

[0046] In a fourth aspect, an embodiment of the present application provides a circuit board packaging device, including:

[0047] Memory, used to store programs;

[0048] A processor is used to execute the program stored in the memory. When the program is executed, the processor is used to execute the method described in the first aspect and any one of the various possible designs of the first aspect.

[0049] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect and any one of the various possible designs of the first aspect.

[0050] In a sixth aspect, an embodiment of the present application provides a computer program product, comprising: a computer program, the computer program being stored in a readable storage medium, at least one processor of an electronic device being able to read the computer program from the readable storage medium, and the at least one processor executing the computer program so that the electronic device executes the method described in the first aspect above and any one of the various possible designs of the first aspect.

[0051] The packaged circuit board and circuit board packaging method provided in the embodiments of the present application include: a multi-layer circuit board, a plurality of first components are arranged on the front and / or back of the multi-layer circuit board, wherein for any layer of the circuit board, M internal conductive structures and N side wall conductive structures are arranged on the circuit board, the N side wall conductive structures are located on the side wall of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, the internal conductive structure is used to connect the plurality of second components with the plurality of first components, and M and N are integers greater than or equal to 1 respectively. There are at least two layers of circuit boards in the multi-layer circuit board with conductive holes arranged therebetween, and the conductive holes are used to connect at least two layers of circuit boards. Among them, by designing a graded side conductive structure on the circuit board, the graded packaged components are arranged on the side of the circuit board, thereby increasing the number of side components packaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0053] Figure 1 A schematic diagram of a multi-layer circuit board provided by an embodiment of the present invention;

[0054] Figure 2 A schematic diagram of the entire board design of each layer of the packaged circuit board provided in an embodiment of the present invention;

[0055] Figure 3 A schematic diagram of a cross section of a circuit board provided by an embodiment of the present invention;

[0056] Figure 4 Process of the circuit board packaging method provided in the embodiment of the present application Figure 1 ;

[0057] Figure 5 A schematic diagram of a circuit board interlayer via provided in an embodiment of the present application;

[0058] Figure 6 Process of circuit board packaging method provided for implementation of this application Figure 2 ;

[0059] Figure 7 A schematic diagram of a cross-section of a circuit board side wall provided in an embodiment of the present application;

[0060] Figure 8 A schematic diagram of the packaging position of the circuit board side wall provided in an embodiment of the present application;

[0061] Fig. 9 A schematic diagram of the structure of a circuit board packaging device provided in an embodiment of the present application;

[0062] Fig.10 A schematic diagram of the hardware structure of the circuit board packaging device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0064] Figure 1 A schematic diagram of a multi-layer circuit board provided by an embodiment of the present invention, Figure 2 A schematic diagram of the entire board design of each layer of the packaged circuit board provided in an embodiment of the present invention, Figure 3 A schematic diagram of a cross section of a circuit board provided in an embodiment of the present invention.

[0065] In this embodiment, a 12-layer circuit board is taken as an example to introduce a multi-layer circuit board. Figure 1 As shown, a 12-layer circuit board 10 has a plurality of first components 104 disposed on the front side 101 and / or the back side 102 of the 12-layer circuit board, and a plurality of second components 105 disposed on the side 103 of the circuit board. The 12-layer circuit board 10 is composed of signal layers 106 and insulation layers 107 placed alternately.

[0066] When designing the conduction structure of each layer of a multi-layer circuit board, Figure 2As shown, each layer of the circuit board is composed of a circuit board panel unit 20. The circuit board panel unit includes a plurality of circuit board finished product design units 201, and each circuit board finished product design unit 201 includes a plurality of internal conductive structures 202 and a plurality of side wall conductive structure positions 203.

[0067] For any layer of the circuit board, M internal conductive structures 202 and N sidewall conductive structures 203 are arranged on the circuit board, the N sidewall conductive structures 203 are located on the sidewalls of the circuit board, a plurality of second components 105 are arranged on the N sidewall conductive structures 203, and the internal conductive structures 202 are used to connect the plurality of second components 105 with the plurality of first components 104. M and N are integers greater than or equal to 1, respectively.

[0068] For any one of the internal conductive structures 202, the internal conductive structure 202 is connected to at least one of the plurality of first components 104. For any one of the sidewall conductive structures 203, the sidewall conductive structure 203 is connected to at least one of the M internal conductive structures 202. Among them, a second component 105 is disposed on a sidewall conductive structure 203, and the second component 105 is connected to the sidewall conductive structure 203. For any one layer of the circuit board, the circuit board includes a plurality of circuit board finished product design units 201, and the M internal conductive structures 202 and the N sidewall conductive structures 203 are respectively located on the sides of the plurality of circuit units.

[0069] In this embodiment, only an exemplary introduction is given to the circuit board panel units 20 that constitute each layer of the circuit board, the number of the circuit board finished design units 201, and the position of the board side wall conductive structure 203. The panel units 20 that constitute each layer of the circuit board, the number of the finished design units 201, the side wall conductive structure 203, and the position of the side wall conductive structure 203 are not limited, and the specific settings can be set according to specific needs. In the process of making each layer of the circuit board, the specific implementation method of designing the side wall conductive connection structure according to the number of side wall conductive pads and the number of circuit connections can refer to any one of the conductive connection structures designed in the prior art, and this embodiment will not be repeated.

[0070] like Figure 3 As shown, multiple vias 301 located in the circuit board and a side packaging position 302 located on the side of the circuit board can be seen. The side packaging position is used to indicate the position where the second component 105 is packaged on the side of the circuit board.

[0071] There are at least two layers of circuit boards in the multi-layer circuit board, and a via hole 301 is provided between them. The via hole 301 is used to make the at least two layers of circuit boards connected.

[0072] In this embodiment, only the number and specific positions of the via holes 301 and the side packaging positions 302 in the cross-sectional view of the circuit board are introduced as examples, and the number and specific positions of the via holes 301 and the side packaging positions 302 are not limited. The specific settings of the number 302 and specific positions of the via holes 301 and the side packaging positions can be set according to actual needs.

[0073] The via hole 301 includes at least two internal conductive structures 202 , the at least two internal conductive structures 202 are located on at least two adjacent layers of the circuit board, and the at least two internal conductive structures 202 are connected.

[0074] The embodiment of the present application provides a packaged circuit board, including: a multi-layer circuit board, a plurality of first components are arranged on the front and / or back of the multi-layer circuit board, wherein for any layer of the circuit board, M internal conductive structures and N side wall conductive structures are arranged on the circuit board, the N side wall conductive structures are located on the side wall of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, the internal conductive structure is used to connect the plurality of second components with the plurality of first components, and M and N are integers greater than or equal to 1 respectively. There are at least two layers of circuit boards in the multi-layer circuit board with conductive holes, and the conductive holes are used to connect at least two layers of circuit boards. Among them, by designing a graded side conductive structure on the circuit board, the side of the circuit board can be graded to package components, thereby increasing the number of side components packaged.

[0075] Based on the introduction of the packaged circuit board proposed in this application, Figure 4 , Figure 5 The specific packaging method of the packaging circuit board proposed in this application is introduced in detail. Figure 4 Process of the circuit board packaging method provided in the embodiment of the present application Figure 1 , Figure 5 A schematic diagram of a circuit board interlayer via provided in an embodiment of the present application.

[0076] like Figure 4 As shown, the method includes:

[0077] S401. For any layer of a multi-layer circuit board, M internal conductive structures are formed inside the circuit board, and N side wall conductive structures are formed on the side wall of the circuit board. A plurality of first components are arranged on the front and / or back of the circuit board, and a plurality of second components are arranged on the N side wall conductive structures. The internal conductive structures are used to connect the plurality of second components with the plurality of first components, and M and N are integers greater than or equal to 1, respectively.

[0078] In this embodiment, in order to enable the multi-layer circuit board to achieve the required functions, for any layer of the multi-layer circuit board, M internal conductive structures are formed inside the circuit board, and N side wall conductive structures are formed on the side wall of the circuit board, where M and N are integers greater than or equal to 1 respectively.

[0079] Wherein, a plurality of first components are arranged on the front and / or back of the circuit board, and a plurality of second components are arranged on the N sidewall conductive structures. By arranging the internal conductive structure inside the circuit board, the first components located on the front and / or back of the circuit board and the second components located on the side of the circuit board are connected.

[0080] In this embodiment, the conductive structure of the circuit board is only exemplarily introduced, and the conductive structure of the circuit board is not limited. The setting of the conductive structure of the circuit board can be adjusted according to actual needs.

[0081] S402, forming a via hole between at least two layers of the multi-layer circuit board, wherein the via hole is used to connect the at least two layers of the circuit board.

[0082] In order to achieve inter-layer conduction of the multi-layer circuit board to ensure that the multi-layer circuit board can work normally, a conducting hole is formed between at least two layers of the multi-layer circuit board.

[0083] like Figure 5 As shown, the circuit board is composed of signal layers 106 and insulating layers 107 alternately. There are two via holes in the figure, namely two-layer via hole 501 and four-layer via hole 502. If conduction is to be achieved between two signal layers, a via hole is set between the two layers. The via hole is a metal hole that achieves inter-layer conduction.

[0084] In this embodiment, the via holes are merely introduced as an example, and no limitation is imposed on the positions, number of conductive layers and conductive media of the via holes. The specific settings of the positions, number of conductive layers and conductive media of the via holes in the circuit board can be set according to actual needs.

[0085] The circuit board packaging method provided in the embodiment of the present application includes: for any layer of circuit boards in a multi-layer circuit board, M internal conductive structures are formed inside the circuit board, and N side wall conductive structures are formed on the side walls of the circuit board. A plurality of first components are arranged on the front and / or back of the circuit board, and a plurality of second components are arranged on the N side wall conductive structures. The internal conductive structures are used to connect the plurality of second components with the plurality of first components, and M and N are integers greater than or equal to 1. A conductive hole is formed between at least two layers of the multi-layer circuit board, and the conductive hole is used to connect at least two layers of the circuit board. Among them, by arranging a packaging structure for hierarchically packaged components on the side, the number of components that can be packaged on the side is greatly increased.

[0086] Based on the above embodiments, the circuit board packaging method provided by the present application is further introduced in combination with a specific embodiment. Figures 6 to 8 Make an introduction, Figure 6 Process of circuit board packaging method provided for implementation of this application Figure 2 , Figure 7 A schematic diagram of a side wall section of a circuit board provided in an embodiment of the present application, Figure 8 A schematic diagram of the circuit board side wall packaging position provided in an embodiment of the present application.

[0087] like Figure 6 As shown, the method includes:

[0088] S601. For any layer of a multi-layer circuit board, the circuit board includes a plurality of circuit units.

[0089] In the design process of a multi-layer circuit board, any layer of the multi-layer circuit board is composed of a plurality of circuit units, wherein the circuit unit may be, for example, a circuit board finished product design unit.

[0090] In this embodiment, the design and composition of a single-layer board in a multi-layer circuit board are only exemplarily introduced, and the design and composition of the single-layer board are not limited. The design and composition of the single-layer board in a multi-layer circuit board can be set according to actual needs.

[0091] S602 . Determine a first target circuit unit among multiple circuit units, where the first target circuit unit is located at a center position of a circuit board.

[0092] In order to clarify the component packaging position of each circuit unit in the multiple circuit units of each single-layer circuit board in the multi-layer circuit board, the first target circuit unit of the circuit board must be determined first. The first target circuit unit is located at the center of the circuit board.

[0093] In this embodiment, the first target circuit unit is merely introduced as an example, and is not intended to be limiting. The first target circuit unit may be specifically set according to actual requirements.

[0094] S603 , forming M laser blind holes at preset positions in the first target circuit unit, where the preset positions are located at sides of the first target circuit unit.

[0095] In this embodiment, the preset position is used to indicate the position where each layer of the circuit board needs to be connected. The preset position is located at the side of the first target circuit unit.

[0096] In order to achieve conduction between circuit board layers at a preset position of the circuit board, M laser blind vias need to be formed at a preset position of the first target circuit unit. The specific number of laser blind vias can be set according to specific requirements.

[0097] S604 , filling the M laser blind vias with electroplating to form M internal conductive structures.

[0098] Based on step S603 , on the basis of forming M laser blind vias at preset positions in the first target circuit unit, M internal conducting structures are formed by electroplating the M laser blind vias.

[0099] In this embodiment, the formation of the internal conductive structure is merely described as an example, and the formation of the internal conductive structure is not limited. The specific formation of the internal conductive structure can be set according to requirements.

[0100] S605 . Determine a second target circuit unit among the multiple circuit units, where the second target circuit unit is located at an edge of the circuit board.

[0101] In this embodiment, a second target circuit unit is determined among a plurality of circuit units of each layer of the circuit board, wherein the second target circuit unit is used to indicate an edge position of the circuit board.

[0102] One point that needs to be emphasized is that this edge position is used for side packaging components.

[0103] S606 , forming N laser blind holes at preset positions in the second target circuit unit, where the preset positions are located at sides of the second target circuit unit.

[0104] The preset position in the second target circuit unit is located at the side of the second target circuit unit. In order to realize the side-level packaging of components on the circuit board, N laser blind holes are formed at the preset position of the second target circuit unit.

[0105] In this embodiment, only an exemplary introduction is given to setting the laser blind holes at the preset positions of the second target circuit unit. The number and specific positions of the laser blind holes at the preset positions of the second target circuit unit can be set according to actual needs.

[0106] In a possible implementation, laser blind holes are fabricated at different levels according to the grading requirements of the sidewall conductive structure.

[0107] S607 , performing electroplating filling on the N laser blind vias to obtain N electroplated conductive structures.

[0108] Based on step S606, N laser blind holes are set at preset positions on the second target circuit unit. Next, in order to achieve side conduction in the second target circuit unit, the N laser blind holes located in the second target circuit unit need to be electroplated and filled, so that N electroplated conductive structures are obtained after the electroplating and filling process.

[0109] Next, a specific example is used to explain in detail. Figure 7 As shown, there are interlayer board via holes 301 and side package via holes 702 in the circuit board. The electroplated via structure can be, for example, the side package via holes 702.

[0110] S608 , determining a sidewall cutting line, where the sidewall cutting line intersects with the N electroplated conductive structures.

[0111] Based on step S607, after N electroplated conductive structures are set at the preset position of the second target circuit unit, it is necessary to determine the side wall cutting line of the circuit board. The side wall cutting line in the circuit board is located at the edge position of the preset position in the second target circuit unit, and the side wall cutting line intersects with the N electroplated conductive unit structures in the second target circuit unit.

[0112] Corresponds to Figure 7 In the example, the sidewall cut-off line 703 intersects with the sidewall conductive structure in the circuit board.

[0113] S609, performing a cutting process on the side wall of the circuit board along the side wall cutting line to form N side wall conductive structures, wherein the cutting process is used to cut off a portion of the N electroplated conductive structures to expose the conductors inside the N electroplated conductive structures.

[0114] After the sidewall cutting line is determined based on step S608, the sidewall of the circuit board is cut along the sidewall cutting line. The cutting process is mainly used to cut off a part of the N electroplated via structures so that the conductors inside the N electroplated via structures are exposed.

[0115] Corresponds to Figure 7In the embodiment, the side wall package via hole in the circuit board is cut along the side wall cutting line 703. After the cutting operation is completed, the conductor inside the electroplated via structure at the side wall package position is exposed, thereby obtaining the side package position 704.

[0116] At the same time, since laser blind holes are made at different levels according to the hierarchical requirements of the side wall conductive structure, after these laser blind holes are electroplated and filled, hierarchical conductive units will appear on the side wall of the circuit board.

[0117] After the sidewall conductive structure of the hierarchical design is cut away, a plurality of hierarchical packaging positions are obtained on the side of the circuit board.

[0118] like Figure 8 As shown, the schematic diagram of the circuit board side wall packaging position includes different side wall packaging units, for example, a 1-layer hierarchical packaging unit 802 and a 2-layer hierarchical packaging unit 803. The 2-layer hierarchical packaging unit 803 realizes the conduction of two layers of the circuit board. Correspondingly, at least one component can be packaged on the packaging unit in the figure.

[0119] In this embodiment, the sidewall graded packaging unit is merely introduced as an example, and the specific implementation of the sidewall graded packaging unit is not limited. The specific implementation of the sidewall graded packaging unit can be set according to actual needs.

[0120] S610: Form a via hole between at least two layers of the multi-layer circuit board, where the via hole is used to connect the at least two layers of the circuit board.

[0121] The implementation of step S610 is similar to that of step S402 and will not be described in detail here.

[0122] The circuit board packaging method provided by the embodiment of the present application includes: for any layer of a circuit board in a multi-layer circuit board, the circuit board includes a plurality of circuit units. A first target circuit unit is determined among the plurality of circuit units, and the first target circuit unit is located at the center of the circuit board. M laser blind holes are formed at a preset position in the first target circuit unit, and the preset position is located at the side of the first target circuit unit. The M laser blind holes are electroplated and filled to form M internal conductive structures. A second target circuit unit is determined among the plurality of circuit units, and the second target circuit unit is located at the edge of the circuit board. N laser blind holes are formed at a preset position in the second target circuit unit, and the preset position is located at the side of the second target circuit unit. The N laser blind holes are electroplated and filled to obtain N electroplated conductive structures. A side wall resection line is determined, and the side wall resection line intersects with the N electroplated conductive structures. The side wall of the circuit board is resected along the side wall resection line to form N side wall conductive structures, and the resection process is used to resect a part of the N electroplated conductive structures so that the conductors inside the N electroplated conductive structures are exposed. A via hole is formed between at least two layers of the multi-layer circuit board, and the via hole is used to connect at least two layers of the circuit board. The number of side mounted components is significantly increased by opening a graded packaging unit on the side of the circuit board.

[0123] Fig. 9 This is a schematic diagram of the structure of the circuit board packaging device provided in the embodiment of the present application. Fig. 9 As shown, the device 90 includes: a processing module 901 and a conducting module 902 .

[0124] The processing module 901 is used for forming M internal conductive structures inside any layer of a multi-layer circuit board, and forming N side wall conductive structures on the side wall of the circuit board; a plurality of first components are arranged on the front and / or back of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, and the internal conductive structures are used to connect the plurality of second components with the plurality of first components, and the M and the N are integers greater than or equal to 1 respectively;

[0125] The conducting module 902 is used to form a conducting hole between at least two layers of the multi-layer circuit board, and the conducting hole is used to connect the at least two layers of the circuit board.

[0126] In one possible design, the processing module 901 is used to:

[0127] Forming M laser blind holes inside the circuit board, and electroplating and filling the M laser blind holes to form the N internal conductive structures;

[0128] N laser blind holes are formed on the side wall of the circuit board, and the N laser blind holes are filled with electroplating, and the side wall of the circuit board is cut away to form the N side wall conductive structures.

[0129] In one possible design, the processing module 901 is used to:

[0130] Filling the N laser blind holes with electroplating to obtain N electroplated conductive structures;

[0131] Determining a sidewall cut line, wherein the sidewall cut line intersects the N electroplated via structures;

[0132] The side wall of the circuit board is cut along the side wall cutting line to form the N side wall conductive structures, and the cutting process is used to cut off a part of the N electroplated conductive structures to expose the conductors inside the N electroplated conductive structures.

[0133] In one possible design, the processing module 901 is used to:

[0134] Determine a first target circuit unit among the plurality of circuit units, wherein the first target circuit unit is located at a center position of the circuit board;

[0135] The M laser blind holes are formed at preset positions in the first target circuit unit, and the preset positions are located at sides of the first target circuit unit.

[0136] In one possible design, the processing module 901 is used to:

[0137] Determine a second target circuit unit among the plurality of circuit units, wherein the second target circuit unit is located at an edge position of the circuit board;

[0138] The N laser blind holes are formed at preset positions in the second target circuit unit, and the preset positions are located at sides of the second target circuit unit.

[0139] The device provided in this embodiment can be used to execute the technical solution of the above method embodiment. Its implementation principle and technical effect are similar, and this embodiment will not be repeated here.

[0140] Fig.10 A schematic diagram of the hardware structure of the circuit board packaging device provided in the embodiment of the present application is shown in FIG. Fig.10 As shown, the circuit board packaging device 100 of this embodiment includes: a processor 1001 and a memory 1002;

[0141] Memory 1002, used for storing computer-executable instructions;

[0142] The processor 1001 is used to execute the computer-executable instructions stored in the memory to implement the various steps performed by the circuit board packaging method in the above embodiment. For details, please refer to the relevant description in the above method embodiment.

[0143] Optionally, the memory 1002 may be independent or integrated with the processor 1001 .

[0144] When the memory 1002 is independently provided, the circuit board packaging device further includes a bus 1003 for connecting the memory 1002 and the processor 1001 .

[0145] An embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the circuit board packaging method executed by the above circuit board packaging device is implemented.

[0146] An embodiment of the present application also provides a computer program product, which includes: a computer program, which is stored in a readable storage medium, and at least one processor of an electronic device can read the computer program from the readable storage medium, and at least one processor executes the computer program so that the electronic device executes the solution provided by any of the above embodiments.

[0147] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0148] The above-mentioned integrated module implemented in the form of a software function module can be stored in a computer-readable storage medium. The above-mentioned software function module is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application.

[0149] It should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented by a hardware processor or implemented by a combination of hardware and software modules in the processor.

[0150] The memory may include a high-speed RAM memory, and may also include a non-volatile storage NVM, such as at least one disk memory, and may also be a USB flash drive, a mobile hard disk, a read-only memory, a magnetic disk or an optical disk, etc.

[0151] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0152] The above storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0153] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A packaged circuit board, characterized in that: include: A multi-layer circuit board, wherein a plurality of first components are arranged on the front and / or back surface of the multi-layer circuit board, wherein: For any layer of the circuit board, M internal conductive structures and N side wall conductive structures are arranged on the circuit board, the N side wall conductive structures are located on the side wall of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, the internal conductive structure is used to connect the plurality of second components with the plurality of first components, and the M and N are integers greater than or equal to 1 respectively; wherein the M internal conductive structures are formed by forming M laser blind holes inside the circuit board and electroplating and filling the M laser blind holes; the N side wall conductive structures are formed by forming N laser blind holes on the side wall of the circuit board, electroplating and filling the N laser blind holes, and cutting off the side wall of the circuit board; The N side wall conductive structures are specifically formed by: performing electroplating filling on the N laser blind holes to obtain N electroplated conductive structures, determining a side wall cutting line, the side wall cutting line intersecting with the N electroplated conductive structures, and performing a cutting process on the side wall of the circuit board along the side wall cutting line; wherein the cutting process is used to cut off a part of the N electroplated conductive structures so that the conductors inside the N electroplated conductive structures are exposed to obtain a side graded packaging position; the side graded packaging position is used to indicate the position where the second component is packaged on the side of the circuit board; There are at least two layers of circuit boards in the multi-layer circuit board, and a conducting hole is provided between them, and the conducting hole is used to make the at least two layers of circuit boards connected; For any one of the internal conductive structures, the internal conductive structure is connected to at least one of the plurality of first components; for any one of the sidewall conductive structures, the sidewall conductive structure is connected to at least one of the M internal conductive structures.

2. The packaged circuit board according to claim 1, characterized in that: A second component is disposed on a sidewall conductive structure, and the second component is connected to the sidewall conductive structure.

3. The packaged circuit board according to claim 1, characterized in that: For any layer of the circuit board, the circuit board includes a plurality of circuit units, and the M internal conductive structures and the N sidewall conductive structures are respectively located on the sides of the plurality of circuit units.

4. The packaged circuit board according to claim 1, characterized in that: The conductive hole includes at least two internal conductive structures, and the at least two internal conductive structures are located on at least two adjacent layers of circuit boards, and the at least two internal conductive structures are connected.

5. A circuit board packaging method, characterized in that: include: For any layer of a multi-layer circuit board, M internal conductive structures are formed inside the circuit board, and N side wall conductive structures are formed on the side wall of the circuit board; a plurality of first components are arranged on the front and / or back of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, and the internal conductive structures are used to connect the plurality of second components with the plurality of first components, and M and N are integers greater than or equal to 1 respectively; wherein any one of the internal conductive structures is connected to at least one of the plurality of first components, and any one of the side wall conductive structures is connected to at least one of the M internal conductive structures; A via hole is formed between at least two layers of the multi-layer circuit board, wherein the via hole is used to connect the at least two layers of the circuit board; M internal conductive structures are formed inside the circuit board, and N sidewall conductive structures are formed on the sidewalls of the circuit board, including: M laser blind holes are formed inside the circuit board, and the M laser blind holes are filled with electroplating to form the M internal conductive structures; N laser blind holes are formed on the side wall of the circuit board, and the N laser blind holes are filled with electroplating, and the side wall of the circuit board is cut to form the N side wall conductive structures; The N laser blind holes are electroplated and filled, and the side walls of the circuit board are cut away to form the N side wall conductive structures, including: Perform electroplating filling on the N laser blind holes to obtain N electroplated conductive structures; determine a side wall resection line, wherein the side wall resection line intersects with the N electroplated conductive structures; perform a resection process on the side wall of the circuit board along the side wall resection line to form the N side wall conductive structures, wherein the resection process is used to resect a portion of the N electroplated conductive structures so that the conductors inside the N electroplated conductive structures are exposed to obtain a side graded packaging position; wherein the side graded packaging position is used to indicate the position at which the second component is packaged on the side of the circuit board.

6. The method according to claim 5, characterized in that The circuit board includes a plurality of circuit units; M laser blind holes are formed inside the circuit board, including: Determine a first target circuit unit among the plurality of circuit units, wherein the first target circuit unit is located at a center position of the circuit board; The M laser blind holes are formed at preset positions in the first target circuit unit, and the preset positions are located at sides of the first target circuit unit.

7. The method according to claim 6, characterized in that The circuit board includes a plurality of circuit units; N laser blind holes are formed on the side wall of the circuit board, including: Determine a second target circuit unit among the plurality of circuit units, wherein the second target circuit unit is located at an edge position of the circuit board; The N laser blind holes are formed at preset positions in the second target circuit unit, and the preset positions are located at sides of the second target circuit unit.

8. A circuit board packaging device, characterized in that: include: A processing module, for forming M internal conductive structures inside any layer of a multi-layer circuit board, and forming N side wall conductive structures on the side wall of the circuit board; a plurality of first components are arranged on the front and / or back of the circuit board, a plurality of second components are arranged on the N side wall conductive structures, and the internal conductive structures are used to connect the plurality of second components with the plurality of first components, wherein M and N are integers greater than or equal to 1 respectively; wherein any one of the internal conductive structures is connected to at least one of the plurality of first components, and any one of the side wall conductive structures is connected to at least one of the M internal conductive structures; A conducting module, used for forming a conducting hole between at least two layers of the multi-layer circuit board, wherein the conducting hole is used for connecting the at least two layers of the circuit board; The processing module is used for: Forming M laser blind holes inside the circuit board, and filling the M laser blind holes with electroplating to form the N internal conductive structures; forming N laser blind holes on the side wall of the circuit board, and filling the N laser blind holes with electroplating, and performing a cutting process on the side wall of the circuit board to form the N side wall conductive structures; The processing module is used for: Perform electroplating filling on the N laser blind holes to obtain N electroplated conductive structures; determine a side wall resection line, wherein the side wall resection line intersects with the N electroplated conductive structures; perform a resection process on the side wall of the circuit board along the side wall resection line to form the N side wall conductive structures, wherein the resection process is used to resect a portion of the N electroplated conductive structures so that the conductors inside the N electroplated conductive structures are exposed to obtain a side graded packaging position; wherein the side graded packaging position is used to indicate the position at which the second component is packaged on the side of the circuit board.

9. A circuit board packaging device, characterized in that: include: Memory, used to store programs; A processor, configured to execute the program stored in the memory; when the program is executed, the processor is configured to execute the method according to any one of claims 5 to 7.

10. A computer-readable storage medium, characterized in that: The method comprises instructions which, when executed on a computer, cause the computer to perform the method as claimed in any one of claims 5 to 7.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 5 to 7 is implemented.

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