Hardware accelerator with reconfigurable instruction set

Abstract

In one example, a hardware accelerator includes: a programmable hardware instruction decoder programmed to store a plurality of opcodes; a programmable instruction pattern mapping table implemented as a content addressable memory (CAM) and programmed to map the plurality of opcodes to a plurality of definitions of operands in a plurality of instructions; a hardware execution engine; and a controller configured to: receive an instruction containing a first opcode of the plurality of opcodes; control the hardware instruction decoder to extract the first opcode from the instruction; obtain a first definition of a first operand from the instruction pattern mapping table and based on the first opcode; and forward the instruction and the first definition to the hardware execution engine to control the hardware execution engine to extract the first operand from the instruction based on the first definition and to execute the instruction based on the first operand.

Description

BACKGROUND

[0001] An artificial neural network is a computing system having an architecture based on biological neural networks. An artificial neural network can be trained using training data to learn how to perform a certain computing task for an application.

[0002] A hardware accelerator, such as a neural network processor, can implement an artificial neural network by performing various operations associated with the artificial neural network. The operations can include, for example, compute operations, memory access operations, and the like. The hardware accelerator typically includes hardware components specifically configured to perform and accelerate these operations. Often, these hardware components can be programmed by instructions to support, for example, different neural network topologies, different applications of neural networks, and the like. BRIEF DESCRIPTION OF DRAWINGS

[0003] Various embodiments according to the present disclosure will be described with reference to the drawings, in which:

[0004] Figure 1 An example of a classifier apparatus that processes data using the techniques disclosed herein is shown;

[0005] Figures 2A-2D is a simplified block diagram showing a prediction model and computations using the techniques disclosed herein according to certain aspects of the present disclosure;

[0006] Figure 3 An example sequence of neural network operations in a computing environment is shown;

[0007] Figures 4A-4D An example neural network processor and its operations according to certain aspects of the present disclosure are shown;

[0008] Figures 5A-5D An example of the internal components of the neural network processor of Figures 4A-4D is shown;

[0009] Figure 6 Instruction pattern programs of various forms according to certain aspects of the present disclosure are shown;

[0010] Figures 7A-7C Examples of instructions for different memory access patterns supported by the neural network processor of Figures 4A-4D are shown according to certain aspects of the present disclosure;

[0011] Figure 8A and Figure 8B An example method of performing computations at a hardware accelerator according to certain aspects of the present disclosure is shown;

[0012] Figure 9 includes a neural network processor that can use the techniques disclosed herein according to certain aspects of the present disclosure; Figures 4A-4Da block diagram of a host system of a neural network processor; and

[0013] Figure 10 A diagram including an example network. DETAILED DESCRIPTION

[0014] Examples of the present disclosure relate to hardware accelerators, and more specifically to neural network hardware accelerators with reconfigurable instruction sets.

[0015] Hardware accelerators, such as neural network processors, can implement artificial neural networks by performing various operations associated with the artificial neural networks. The operations can include computational operations, such as convolution operations, post-processing operations, such as pooling, activation function processing, etc., as well as memory access operations to support these computational operations. Hardware accelerators typically include hardware components specifically configured to perform and / or accelerate these operations. For example, a hardware accelerator can include circuitry specifically designed to perform certain arithmetic operations (e.g., convolution operations), circuitry specifically designed to perform certain pooling operations, circuitry specifically designed to perform certain activation function processing operations, circuitry specifically designed to perform memory access operations, computational operations, etc.

[0016] These hardware components are typically programmable by instructions to support different neural network topologies and / or different applications for the neural networks. The instructions can include, for example, indications of input data and selections of weights for convolution operations, activation functions and / or pooling operations to be performed by the hardware accelerator, memory access operations to control data flow between different neural network layers, etc. The hardware components can extract this information from the instructions and perform operations based on the extracted information.

[0017] The instruction set supported by the hardware components can form an instruction set. The instruction set also has a predefined instruction format that defines bit offsets and bit sizes of opcode and individual operands in each instruction of the instruction set. The opcode can define a specific operation to be performed (e.g., a convolution operation, an activation function processing, a pooling operation, a memory access operation, etc.), as well as operands for those operations (e.g., input data and weights, addresses to be accessed by memory access operations, etc.). The hardware components can extract the opcode and operands from the instructions based on the predefined instruction format and perform operations based on the extracted opcode and operands.

[0018] Instructions in the instruction set can define a range of operations supported by the hardware accelerator, and the instruction set can define a range of neural network topologies and applications thereof supported by the hardware accelerator. However, as neural network topologies and applications thereof evolve, new operations can be needed to support these new topologies and applications. Hardware accelerators that only support a fixed instruction set can not be able to support those new operations, and can not be able to support new neural network topologies and / or new applications.

[0019] Examples of the present disclosure relate to hardware accelerators, and more specifically to neural network hardware accelerators with a reconfigurable instruction set. A neural network hardware accelerator includes a programmable hardware instruction decoder, a programmable instruction pattern mapping table, a hardware execution engine, and a controller. The hardware instruction decoder can be programmed to store a first mapping between a plurality of opcodes and a plurality of definitions of bit length and bit offset for the opcodes. The instruction pattern mapping table can be programmed to store a second mapping between a plurality of opcodes and a plurality of definitions of bit offset and bit length of an operand of an instruction that includes the opcode. The controller can forward a first instruction to each of the hardware instruction decoder and the execution engine. The hardware instruction decoder can find a first opcode from the first instruction based on the first mapping and output the first opcode to the instruction pattern mapping table. The instruction pattern mapping table can output a first definition of bit offset and bit length of an operand to the execution engine based on the second mapping and the first opcode. The execution engine can extract a first operand from the first instruction based on the first definition and operate based on the first operand.

[0020] Both the hardware instruction decoder and the instruction pattern mapping table can be programmed based on an instruction pattern program. The instruction pattern program can define an instruction set supported by the hardware accelerator and can define bit offset and bit length of opcodes and one or more operands for each instruction in the instruction set. The opcodes of the instruction set can have the same bit length or different bit lengths between instructions. For example, some of the opcodes can have a bit length of one byte or less, while others of the opcodes can have a bit length of more than one byte. Further, some of the opcodes can span two or more bytes of an instruction. Further, the bit offset and bit length of operands between instructions can also differ. Such an arrangement can provide flexibility in allocating opcodes and operands for different instructions to support different aspects of operations, which in turn can increase the number of instructions and operations supported by the hardware accelerator.

[0021] The definitions of opcodes and operands stored in the hardware instruction decoder and the instruction pattern mapping table can correspond to an instruction set supported by the hardware accelerator. To enable the hardware accelerator to support operations not defined in the instruction set, the hardware instruction decoder and the instruction pattern mapping table can be programmed according to a second instruction pattern program to store different definitions of opcodes and operands.

[0022] A hardware accelerator can include multiple execution engines to perform different types of operations of a neural network. An execution engine can include, for example, a systolic array to perform arithmetic operations to generate partial sums (e.g., of weight data products), a summing buffer to accumulate partial sums from the systolic array, a pooling engine to perform pooling operations, an activation function engine to perform activation function processing operations, etc. Based on an opcode, the hardware accelerator can route an instruction, along with a definition of operands, to a target execution engine, which can then extract the operands from the instruction and perform a computational operation based on the operands. The operands can indicate, for example, a configuration of an arithmetic operation (e.g., a type of input data, a precision of the arithmetic operation, etc.), a configuration of a post-processing operation (e.g., a selection of a pooling operation, a selection of an activation function, etc.), or other configurations. The opcodes and the definitions of the operands stored in the hardware instruction decoder and the instruction pattern mapping table can thus define a range of arithmetic operation configurations and a range of post-processing operations supported by the hardware accelerator.

[0023] A hardware accelerator can also include on-chip memory to provide temporary data storage for the execution engines. Each execution engine can be allocated memory access circuitry to access the memory. The memory access circuitry can perform memory access operations based on instructions received by the execution engine. The instructions can include operands that indicate a computational operation to be performed by the execution engine, as well as a specific memory access pattern that defines a series of specific memory access operations to be performed by the memory controller of the execution engine to support the computational operation. The series of memory access operations can include, for example, accessing input data stored in the memory to create input data streams for the systolic array, the activation function engine, and / or the pooling engine, storing output data from the systolic array, the activation engine, and / or the pooling engine at the memory, etc.

[0024] The memory access circuitry of the hardware accelerator can support different sequences of memory access operations for different computational operations. For example, the memory access circuitry can be programmed by an instruction to read input data that is organized into a tensor of a particular dimension (e.g., a one-dimensional vector, a multi-dimensional matrix, etc.) and provide the data to the systolic array for a convolution operation. Depending on the dimension of the input data, the instruction can include an operand for each of the single dimension or multiple dimensions. The operand can include, for example, a stride parameter based on the stride of the convolution operation, an element parameter number for defining the number of input data elements to fetch / provide to the systolic array, etc. In the case of the systolic array performing a convolution operation on multi-dimensional input data, the instruction can include an operand defining the stride and the number of elements for each of the multiple dimensions. The memory access circuitry can be designed to handle memory access operations up to a certain maximum dimension (e.g., 4D). The instruction can include an operand up to the maximum dimension or a lower dimension (e.g., ID, 2D, 3D, etc.) to control the memory access circuitry to fetch / provide input data to the systolic array according to the dimension of the input data.

[0025] Additionally, the memory access circuitry can be programmed by an instruction to perform a write operation to the memory only when a predetermined condition is satisfied. For example, the computational operation can include a summation of data elements of a particular dimension of a tensor as part of a tensor reduction operation to compute a total sum of data elements across the tensor dimension. The instruction can define the memory access circuitry of a summation buffer to write the total sum of data elements of the vector / matrix to the memory. Another instruction can define the memory access circuitry to write each partial sum received from the systolic array to the memory as part of an accumulation operation.

[0026] The dimension of the input data to be read from the memory, and the condition for storing the output data in the memory, can be defined in a particular instruction set for a particular neural network / application. The hardware instruction decoder and instruction mode mapping table can be programmed based on a first instruction mode program to support memory access operations for input data of a particular dimension (e.g., ID) and / or for a particular condition of storing the output data (e.g., storing only the sum of ID vectors) for a particular neural network and / or a particular application. The hardware instruction decoder and instruction mode mapping table can then be programmed based on a second instruction mode program to support memory access operations for input data of a different dimension (e.g., 2D, 3D, 4D, etc.) and / or for a different condition of storing the output data (e.g., storing different partial sums as part of an accumulation operation) for a different neural network and / or a different application.

[0027] Examples of the present disclosure can increase the number of instructions supported by a hardware accelerator. Specifically, the instructions supported by the hardware accelerator are no longer limited to the definitions of those instructions currently stored in the hardware instruction decoder and instruction mode mapping table, and can be extended by programming the hardware instruction decoder and instruction mode mapping table with different instruction mode programs. Along with the flexibility of opcodes and operands having variable bit lengths and / or bit offsets, and the ability to select different memory access modes, the capabilities of the hardware accelerator can thus be extended to enable the hardware accelerator to support new operations associated with new neural network topologies and / or new applications. This capability can be extended without changing the accelerator design.

[0028] In the following description, various examples will be described. For the purpose of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the examples. However, it will also be apparent to one skilled in the art that the examples can be practiced without the specific details. Furthermore, well-known features can be omitted or simplified in order not to obscure the embodiment being described.

[0029] Figure 1 An example classifier device 100 that processes data using the techniques disclosed herein is shown. The classifier device 100 can be, for example, a computing device that operates a software application 102 and a prediction model 103 to predict information contained in a sequence of data and perform a predetermined function based on the prediction. For example, the classifier device 100 can be part of an image recognition service that provides for recognizing certain objects (e.g., text, people, etc.) from images. It should be understood that the image recognition service is provided merely as an illustrative example, and that the techniques disclosed herein can be used for other data processing applications, including, for example, text-based data processing (e.g., processing of search queries), audio data processing, etc. Furthermore, the classifier device 100 can operate multiple different prediction models to process different input data in parallel or at different times.

[0030] In some instances, an image recognition service can be provided in a multi-tenant computing service system. A multi-tenant computing service system can generally include a plurality of servers that can host data and be used by a plurality of clients or organizations to run instances, such as virtual machine instances or bare metal instances (e.g., operating systems running directly on server hardware). In most instances, such as in bare metal or virtual machine instances, a multi-tenant computing service system can be allocated to a client when needed by the client and stopped when no longer needed by the client, such that resources can be reallocated to other clients. In this disclosure, the terms "tenant," "client," and "customer" can be used interchangeably, although such terms do not necessarily imply that there is any particular business arrangement. The term "instance" can refer to, for example, an instance executing directly on server hardware or as a virtual machine. Different types of instances generally correspond to different hardware capabilities and / or hardware arrangements (e.g., different amounts of available memory and / or processing hardware). In Figure 1 In instances of the foregoing, a multi-tenant computing service system can provide an image recognition service when needed by a client and stop using the service when no longer needed by the client, such that resources supporting the image recognition service (e.g., access to the software application 102 and underlying hardware resources used to process the software application 102) can be reallocated to other clients. Different clients (or one client) can require the application 102 to process different input data using the same or different predictive models including the predictive model 103.

[0031] In Figure 1 In instances of the foregoing, the software application 102 can receive pixel data of an image 104 from a user. The image 104 can include an array of pixels. The software application 102 can analyze the pixel data and predict one or more objects 106 depicted in the image 104. The analysis can include, for example, comparing the pixel data to a set of predetermined feature data. The predetermined feature data can include data associated with a set of predetermined visual image features, such as a nose object, a mouth object, etc. The predetermined feature data can also include data associated with non-visual image features or a combination of visual and non-visual image features. As will be discussed in greater detail below, the software application 102 can employ a predictive model 103 to compute a set of scores based on the pixel data of the image 104. The set of scores can represent, for example, a likelihood that the image 104 includes an image feature represented by the feature data. The software application 102 can then determine other information about the content of the image 104 based on the scores. For example, based on the scores, the software application 102 can determine that the image 104 is an image of, for example, a panda, a cat, or other object.

[0032] The prediction model 103 can be in the form of an artificial neural network. The artificial neural network can include a plurality of processing nodes, where each processing node is configured to process a portion of the input pixel data or is configured to further process an intermediate output from other processing nodes. Figure 1 Examples of the prediction model 103 using the techniques disclosed herein are demonstrated. In Figure 1 , the prediction model 103 can be a multi-layer neural network, such as a deep neural network (DNN), a convolutional neural network (CNN), etc. The prediction model 103 can include an input layer 207, a set of intermediate layers including intermediate layers 209 and 211, and an output layer (not shown in Figure 2A ). It is to be understood that the prediction model 103 can also include other different types of neural networks, including, for example, long short-term memory (LSTM), multilayer perceptron (MLP), multi-scale dense network (MSDNET), etc.

[0033] The layer 207 can process pixel data representing different portions of the image 104. For example, in the example of Figure 2A , the layer 207 can process pixel data of the image 204. Each processing node of the layer 207 is assigned to receive pixel values (e.g., x0, x1, x2,..., x n ) corresponding to predetermined pixels within the image 104 and transmit one or more weights having the received pixel values to the layer 209. In the case that the prediction model 203 is a DNN, each processing node of the layer 207 can be assigned a set of weights defined based on a matrix W1. Each processing node of the layer 207 can send the received pixel values and the assigned weights to each processing node of the layer 209. In the case that the prediction model 103 is a CNN, groups of processing nodes of the layer 207 can share a set of weights, and each group can send the set of weights and pixel values received by the group of processing nodes to a single processing node of the layer 209. Different neural network models can include different topologies (e.g., including different numbers of layers, different connections between layers, etc.) and / or a different set of weights for each layer.

[0034] The layer 209 can process the scaled outputs from the layer 207 to generate a set of intermediate outputs. For example, assuming that a processing node 210a of the layer 209 is connected to n processing nodes in the layer 207, the processing node 210a can generate a sum of the scaled outputs received from the layer 207 based on the following equation:

[0035] (Equation 1)

[0036] Here, represents an intermediate output generated by the processing node 210a. represents the scaling of a particular pixel value (e.g., x0) by an associated weight (e.g., W10) by a processing node of layer 207. In the case where prediction model 103 is a DNN, each processing node of layer 209 can generate a sum based on the scaling of the pixel values from each processing node of layer 207, and subsequently generate the sum (e.g., ) by summing the scaled pixel values. The sum can also represent a dot product between an input vector comprising a plurality of elements (e.g., pixel values) and a weight vector (e.g., W1). In some instances, a bias can also be added to the scaled output to generate an intermediate output.

[0037] In the case where prediction model 103 is a CNN, each processing node of layer 209 can generate an intermediate output based on the scaling of the pixel values from a group of processing nodes of layer 207. The intermediate output can represent a convolution result between a group of pixel values and a filter comprising weight values. Figure 2B An example of a convolution operation that layer 209 can perform is illustrated. In Figure 2B filter 230 can contain a two-dimensional array of weights. The weights in filter 230 can represent a spatial distribution of pixels of certain features to be detected from an image. The two-dimensional array can have a height of R rows and a width of S columns, and is typically smaller than an input image having a height of H pixels and a width of W pixels. Each weight can be mapped to a pixel in a rectangular block of pixel values having the same R rows and S columns. A processing node (e.g., processing node 210a) of layer 209 can receive a group 240 of pixel values from a group of processing nodes of input layer 207 corresponding to a first rectangular block of pixels from an input image corresponding to a first stride position of filter 230, and generate a convolution output 242 based on a sum of multiplication results between each weight of filter 230 and each corresponding pixel in group 240 according to Equation 1, thereby generating a dot product between a matrix represented by filter 230 and a matrix represented by group 240. Another processing node of layer 209 can also receive a group 244 of pixel values from another group of processing nodes of input layer 207 corresponding to a second rectangular block of pixels from the input image corresponding to a second stride position of filter 230, and generate a convolution output 246 based on a sum of multiplication results between each weight of filter 230 and each corresponding pixel in group 244 according to Equation 1, thereby generating a dot product between the matrix of filter 230 and a matrix represented by group 240. In some instances, Figure 2BEach convolutional output (e.g., convolutional output 242, convolutional output 346, etc.) can correspond to the output of a processing node in layer 209. In some instances, pixel data in the input image can be referred to as an input feature map indicating that the pixels have been processed by the same filter (or the same filter bank) corresponding to certain features. Convolutional outputs can be referred to as output feature maps indicating the result of processing the input feature map with filters.

[0038] As in Figure 2B As shown, the convolution operation can be arranged in a sliding window such that the second rectangular block overlaps with or is otherwise adjacent to the first rectangular block in the input image. For example, in Figure 2B In this example, D can be the stride distance (in pixels) of the sliding window for each convolution operation, such that the pixel block corresponding to group 244 can be located at a distance D (in pixels) from the pixel block corresponding to group 240, and the next pixel block can also be located at the same distance D from group 244. Other processing nodes of layer 209 can also receive pixel groups corresponding to other rectangular blocks and generate other intermediate outputs. The convolution output can be part of a convolution output array. Compared to the input image, the convolution output array can have a smaller height and a smaller width. The rectangular blocks of the convolution output can be further grouped, and convolution operations can be performed at layer 211 between the convolution output group and another set of filter weights to generate another set of convolution outputs.

[0039] In some instances, convolution operations can be performed between multiple images and multiple filters. For example, see reference... Figure 2C A set of C filters 260 can correspond to multiple (C) images 270, and a convolution operation can be performed on the corresponding image of image 270 between each filter in the set of filters 260 and a pixel block. Each image in image 270 can correspond to an input channel. The convolution results of each filter image pair can be summed to generate the following convolution output:

[0040] (Equation 2)

[0041] Here, the convolution operation involves an image (or an array of pixels). This can refer to the pixel value at index c of an image within a plurality of (C) images, where the row coordinate is eD+r and the column coordinate is fD+s. For the remainder of this disclosure, elements... The coordinates can be expressed in the form of (eD+r, fD+s). The index c can represent a particular input channel. D is a sliding window stride distance, and e and f correspond to positions of data elements in a convolution output array, which can also correspond to a particular sliding window. Further, r and s correspond to particular positions within the sliding window. The pixel at the (r, s) position and the pixel of the image of index c can also correspond to a weight in the corresponding filter of the same index c at the same (r, s) position . Equation 2 indicates that to compute a convolution output , each pixel within a sliding window (indexed by (e, f)) can be multiplied by a corresponding weight . A partial sum of the multiplied products within each sliding window in each image within the image group can be computed. And then a sum of the partial sums of all images of the image group can be computed.

[0042] Further, in some instances, a set of images can be convolved using multiple sets of filters to generate a set of convolution output arrays, where each convolution output array corresponds to a set of filters. Each set of filters can correspond to an output channel. For example, the multiple sets of filters can correspond to multiple features to be detected from the set of images, and each convolution output array can correspond to a detection result for each feature from the set of images. For example, in the case that M sets of filters are applied to C images to generate M convolution output arrays, Equation 2 can be updated as follows:

[0043] (Equation 3)

[0044] Here, the convolution output and the weight have an index m corresponding to one of the M sets of filters. The index m can represent a particular output channel.

[0045] Figure 2D An example of C sets of input data (where C = 3) to be convolved with M sets of filters (where M = 2) is shown. Each set of input data corresponds to an entry of a pixel array. Each set of filters in the M sets of filters contains a set of C filters corresponding to the C sets of input pixel arrays. The convolution operation generates M sets of output data elements, where each set of output data elements corresponds to a convolution output array. Each convolution output array corresponds to convolving a set of filters (in the M sets) with an input pixel array. For example, can be generated by a sum of a dot product between a set of pixels 282 and a filter array 284, a dot product between a set of pixels 286 and a filter array 288, and a dot product between a set of pixels 289 and a filter array 292. .

[0046] Referring back to Figure 2AA processing node in layer 209 can be configured to generate convolutional output elements of a convolutional output array, and a set of M processing nodes in layer 209 can correspond to a set of M convolutional output arrays. The processing nodes in layer 209 can also process each convolutional output with an activation function to generate an activation output. The activation function can transform the convolutional output into a decision on whether to forward the convolutional output to the intermediate layer 211 to influence the classifier's decision (similar to triggering biological neurons). An instance of the activation function can be the rectified linear unit (ReLU) defined according to the following equation:

[0047] (Equation 4)

[0048] Besides ReLU, other activation functions can be used, including softplus (which is a smooth approximation of ReLU), hyperbolic tangent (tanh), arctangent (arctan), sigmoid, and Gaussian function.

[0049] The processing nodes of layer 209 (e.g., processing node 210a) can use the ReLU function to process the sum to generate the first output of layer 209 based on the following equation:

[0050] (Equation 5)

[0051] Layer 211 can further process the scaled intermediate output from layer 209 by performing additional convolution operations, for example, based on different groups of filters. The output from each processing node of layer 211 can be forwarded to other higher intermediate layers, or forwarded to the output layer. Figure 2A (Not shown in the image). The output layer can form an output vector representing, for example, the probability that image 104 contains certain features and / or the probability that image 204 contains an image of a panda. For example, the output vector can be compared with a reference vector associated with a panda's nose or a reference vector associated with a panda. A decision about whether image 104 is an image of a panda can be determined based on the comparison result.

[0052] Figure 3 Example sequence 300 demonstrates implementing neural network operations in a computing environment. (e.g.) Figure 3As shown, sequence 300 can start at step 302, where input data and weights for a neural network layer are fetched from memory. The input data can contain, for example, pixel values of an image, audio data, etc., or output data from a previous neural network layer. In step 304, arithmetic operations can be performed based on the input data and weights to generate an intermediate output. The arithmetic operations can include, for example, summations and multiplications as described above in Equations 1-3. The arithmetic operations can be performed by, for example, a systolic array of hardware accelerators, a general-purpose hardware processor, etc. In step 306, post-processing operations can be performed on the intermediate output to generate a final output for the neural network layer. The post-processing operations can include, for example, pooling operations, activation function processing, etc., as described above in Equations 4 and 5. In step 308, the final output can be stored in memory as a final output, which can represent an overall output for the neural network or as an input for a next neural network layer.

[0053] Each of steps 302, 304, 306, and 308 can involve different operations for different neural network topologies and / or different applications. Specifically, in step 302, the input data and weights can be fetched that are organized into tensors of different dimensions (e.g., ID, 2D, 3D, 4D, etc.), sizes, etc. For example, an audio processing application can access one-dimensional input data (e.g., a time series of an audio signal), while an image processing application can access multi-dimensional input data (e.g., a two-dimensional image of different spectral channels). Further, the arithmetic operations in step 304 can vary. For example, a convolutional neural network (CNN) can implement convolution operations as described in Equations 3 and 4, while a fully-connected neural network does not. Different convolution operations can also be implemented (e.g., transpose convolution operations, dilated convolution operations, etc.). Further, other types of arithmetic operations can also be performed, such as tensor reduction operations, to compute a sum of data elements across a tensor dimension. Different post-processing operations can be implemented in step 306 for different neural network topologies and / or different applications, such as different activation functions, different pooling operations, etc. Finally, storing the output data in memory in step 308 can involve different modes of write operations for different applications. For example, some applications can require that the output be written to memory only after the arithmetic operations in step 304 are completed, while some other applications can need to write partial sums to memory and update in memory as the arithmetic operations in step 304 are ongoing.

[0054] In a computing environment, each of steps 302, 304, 306, and 308 can be represented by one or more instructions to be executed to perform a neural network operation. The instructions can represent different operations for each of steps 302, 304, 306, and 308. For example, reading memory for input data and weights of different dimensions and sizes can be represented by different instructions. Further, different instructions can represent different arithmetic operations in step 304, different post-processing operations in step 306, and different modes of write operations in step 308. To implement different neural network topologies for different applications, a computing environment can need to support a large number of instructions to cover different operations in each of steps 302, 304, 306, and 308.

[0055] Figure 4A is a block diagram illustrating an example of an integrated circuit device that can be configured to perform various types of neural network operations. Figure 4A Examples of illustrate an accelerator 402. In various examples, for a set of input data (e.g., input data 450), accelerator 402 can perform computations using a compute circuit including processing engine array 410 and post-processing engine 415, which includes activation engine 416 and / or pooling engine 418. In some examples, example accelerator 402 can be an integrated circuit component of a processor, such as a neural network processor. The processor can have other integrated circuit components, including additional accelerator engines. Accelerator 402 can include a controller 422 to control operation of the compute circuit including processing engine array 410 and post-processing engine 415.

[0056] In various implementations, memory sub-system 404 can include multiple banks 414. In these implementations, each bank 414 can be independently accessible, meaning that a read of one bank does not depend on a read of another bank. Similarly, a write to one bank does not affect or limit a write to a different bank. In some cases, each bank can be read from and written to simultaneously. Various techniques can be used to have independently accessible banks 414. For example, each bank can be a physically separate memory component with an address space that is separate and independent of the address space of each other bank. In this example, each bank can have at least one read channel and can have at least one separate write channel that can be used simultaneously. In these examples, memory sub-system 404 can allow simultaneous access to read channels or write channels of multiple banks. As another example, memory sub-system 404 can include arbitration logic such that arbitration between outputs of, for example, multiple banks 414 can be such that more than one bank’s output is used. In these and other examples, each bank can operate independently of any other bank, although globally managed by memory sub-system 404.

[0057] Making the banks 414 independently accessible can improve the efficiency of the accelerator 402. For example, multiple values can be read simultaneously and provided to each row of the processing engine array 410 so that the entire processing engine array 410 can be used in one clock cycle. As another example, the banks 414 can be read while results computed by the processing engine array 410 are written to the memory subsystem 404. In contrast, a single memory can only service one read or write at a time. With a single memory, multiple clock cycles can be needed, e.g., to read input data for each row of the processing engine array 410 before the processing engine array 410 can be started.

[0058] In various embodiments, the memory subsystem 404 can be configured to service multiple clients simultaneously, including the processing engine array 410, the activation engine 416, the pooling engine 418, and any external clients that access the memory subsystem 404 through the communication fabric 420. In some embodiments, being able to service multiple clients can mean that the memory subsystem 404 has at least as many banks as clients. In some cases, each row of the processing engine array 410 can count as a separate client. In some cases, each column of the processing engine array 410 can output results so that each column can count as a separate write client. In some cases, output from the processing engine array 410 can be written to the banks 414, which can then subsequently provide input data for the processing engine array 410. As another example, the activation engine 416 and the pooling engine 418 can include multiple execution lanes, each of which can be a separate memory client. For example, the banks 414 can be implemented using static random access memory (SRAM).

[0059] In various embodiments, the memory subsystem 404 can include control logic. The control logic can, for example, track the address space of each of the banks 414, identify the banks 414 to read from or write to, and / or move data between the banks 414. In some embodiments, the banks 414 can be hardwired to particular clients. For example, a set of banks 414 can be hardwired to provide values to rows of the processing engine array 410, with one bank servicing each row. As another example, a set of banks can be hardwired to receive values from columns of the processing engine array 410, with one bank receiving data for each column.

[0060] The processing engine array 410 is a computational matrix of the example accelerator 402. The processing engine array 410 can, for example, perform parallel integration, convolution, correlation, and / or matrix multiplication, among other operations. The processing engine array 410 contains a plurality of processing engines 411 arranged in rows and columns such that the output from one processing engine 411 can be input directly into another processing engine 411. Thus, processing engines 411 that are not on the outer edges of the processing engine array 410 can receive data from other processing engines 411 rather than from the memory subsystem 404 for operations.

[0061] In various examples, the processing engine array 410 can contain a systolic array and use systolic execution in which data arrives at each processing engine 411 from different directions at regular intervals. In some examples, input data can flow in from the left into the processing engine array 410, and weight values can be loaded at the top. In some examples, weights and input data can flow from the left, and partial sums can flow from top to bottom. In these and other examples, multiplication and accumulation operations move through the processing engine array 410 in diagonal wavefronts, with data moving right and down across the array. Control signals can be input at the left side along with the weights, and can flow through and down with the computations.

[0062] In various implementations, the number of columns in the processing engine array 410 determines the computational power of the processing engine array 410, and the number of rows determines the memory bandwidth required to achieve maximum utilization of the processing engine array 410. The processing engine array 410 can, for example, have 64 columns and 428 rows, or some other number of columns and rows.

[0063] An example of a processing engine 411 is shown in an inset in FIG. 4. As shown in this example, the processing engine 411 can contain a multiplier-accumulator circuit. Input from the left can contain, for example, input data i and a weight value w, where the input data is a value taken from a set of input data or a set of intermediate results, and the weight value is from a set of weight values that connect one layer of a neural network to the next layer. For example, a set of input data can be an image submitted for recognition or object recognition, a piece of audio provided for speech recognition, a string of text for natural language processing or machine translation, or a current state of a game that needs to be analyzed to determine a next move, among others. In some examples, the input data and weight value are output to the right for input to the next processing engine 411.

[0064] In the illustrated example, the input from above can include partial sums and p_in, which are provided by another processing engine 411 or by a previous round of computation by the processing engine array 410. When starting computation on a new set of input data, the top row of the processing engine array 410 can receive a fixed value for p_in, such as zero. As illustrated by this example, i and w are multiplied, and the result is summed with p_in to produce a new partial sum, p_out, which can be input into another processing engine 411. Various other implementations of the processing engine 411 are possible.

[0065] The output from the last row in the processing engine array 410 can be temporarily stored in the sum buffer 412. The result can be an intermediate result, which can be written to the memory bank 414 for provision to the processing engine array 410 for additional computation. Alternatively, the result can be a final result, which can be read from the memory sub-system 404 by the communication structure 420 once written to the memory bank 414, to be output by the system.

[0066] In some implementations, the accelerator 402 includes a post-processing engine 415, which can include an activation engine 416 and a pooling engine 418. In these implementations, the activation engine 416 can combine the results from the processing engine array 410 into one or more output activations. For example, for a convolutional neural network, the convolution sums from multiple channels can be combined to produce an output activation for a single channel. In other examples, the results from one or more columns in the processing engine array 410 can need to be accumulated to produce an output activation for a single node in the neural network. In some examples, the activation engine 416 can be bypassed.

[0067] In various examples, the activation engine 416 can include multiple separate execution lanes. In these examples, the execution lanes can correspond to columns of the processing engine array 410, and can operate on the outputs of the columns, the results of which can be stored in the memory sub-system 404. In these examples, the activation engine 416 can be capable of between 1 and n parallel computations, where n is equal to the number of columns in the processing engine array 410. In some cases, one or more of the computations can be performed simultaneously. Examples of computations that each execution lane can perform include, among others, exponential, square, square root, identity, binary step, bipolar step, sigmoid, and tanh.

[0068] In some embodiments, accelerator 402 can include a pooling engine 418. Pooling is a combination of the outputs of a column of processing engine array 410. The combination can include, for example, computing a maximum, a minimum, an average, a median, a sum, a multiplication, or another logical or mathematical combination. In various instances, pooling engine 418 can include a plurality of execution lanes that can operate on values of a corresponding column of processing engine array 410. In these instances, pooling engine 418 can be capable of between 1 and n parallel computations, where n equals the number of columns in processing engine array 410. In various instances, the execution lanes of pooling engine 418 can operate in parallel and / or simultaneously. In some instances, pooling engine 418 can be bypassed.

[0069] In this document, activation engine 416 and pooling engine 418 can be collectively referred to as execution engines. Processing engine array 410 is another instance of an execution engine. Another instance of an execution engine is a direct memory access (DMA) engine that can be located outside of accelerator 402.

[0070] Input data 450 can arrive through communication fabric 420. Communication fabric 420 can connect accelerator 402 to other components of a processor, such as a DMA engine that can obtain input data 450 from an input / output (I / O) device, a storage drive, or a network interface. Input data 450 can be, for example, one-dimensional data, such as a string or a sequence of numbers, or two-dimensional data, such as an array of pixel values of an image or frequency and amplitude values of an audio signal over time. In some instances, input data 450 can be three-dimensional, for example, as can be the case for situational information used by an autonomous vehicle or virtual reality data. In some embodiments, memory subsystem 404 can include a separate buffer for input data 450. In some embodiments, when accelerator 402 receives input data 450, input data 450 can be stored in memory bank 414.

[0071] In some instances, accelerator 402 can implement a neural network processing engine. In these instances, for a set of input data 450, accelerator 402 can run a neural network to perform a task, where the neural network has been trained for the task. Performing a neural network on a set of input data can be referred to as inference or performing inference.

[0072] The weights of the neural network can be stored in the memory sub-system 404 along with the input data 450 on which the neural network will operate. The addresses of the weights and input data 450 in the memory sub-system 404 can be based on or mapped to the coordinates of the weights and input data 450 in the weight data array and input data array, respectively, which allows the weights and input data to be retrieved based on the addresses derived from their coordinates. The neural network can also contain instructions that can be executed by the controller 422 to control the processing engine array 410 to perform various computations on the weights and input data. The instructions can be generated by a compiler and can also be stored in the memory sub-system 404, the storage 414, or a separate instruction buffer. The processing engine array 410 can output intermediate results that represent the outputs of the various layers of the neural network. In some cases, the activation engine 416 and / or the pooling engine 418 can be enabled to perform the computations required by certain layers of the neural network. The accelerator 402 can store the intermediate results in the memory sub-system 404 to be input into the processing engine array 410 to compute the results of the next layer of the neural network. The processing engine array 410 can further output a final result from the last layer of the neural network. The final result can be stored in the memory sub-system 404 and subsequently copied to a host processor memory or to another location.

[0073] Figure 4B and Figure 4C An example of the operation of the accelerator 402 is shown. As shown in Figure 4B , the memory sub-system 404 can be organized into multiple rows, such as memory rows 425, 426, etc. In one example, the input data can be organized into a three-dimensional (2D) matrix of image data having a first dimension represented by height H, a second dimension represented by width W, and a third dimension represented by channel C. In the example shown in Figure 4B , each memory row can store two-dimensional (2D) input data elements of a particular input channel C (across height H and width W). The memory sub-system 404 can also store higher dimensional input data, such as a 4D matrix. In one example, the memory sub-system 404 can store input data belonging to different fourth dimensions at different times in each row and / or at different locations within each row. The memory sub-system 404 can sequentially fetch the input data of different fourth dimensions. For example, the memory sub-system 404 can first fetch the three-dimensional input data of a particular fourth dimension (e.g., different channels C across different rows) to the processing engine array 410, followed by the input data of another fourth dimension, and so on.

[0074] The memory access circuitry (e.g., memory access circuitry 427) that is part of the processing engine array 410 can be controlled to fetch input data elements to the processing engine array 410 in sequence based on a set of memory fetch parameters 430 that include a starting address of the elements, a stride, and a number of elements. The starting address parameter can define the location of the first input data element to be read from a memory row, the stride parameter can define the number of input data elements to skip between fetched input data elements, which can correspond to the stride distance of the convolution operation (parameter D in Equations 1-3), and the number of elements parameter can define the total number of input data elements to fetch. Since the input data elements are stored in a strided space, the access circuitry 427 can determine the addresses of the fetched input data elements and update a counter based on the stride. For example, the access circuitry 427 can start fetching the first input data element from the starting address, add an address offset based on the stride to the starting address to fetch the next input data element while skipping a number of input data elements, and repeat until the number of fetched elements is reached.

[0075] As described below, the parameters 430 can include a stride parameter and a number of elements to fetch parameter for each dimension of the input data stored in the memory subsystem 404. The memory fetch parameters 430 can be included in instructions to the processing engine array 410 to compute a set of partial sums. The instructions can be generated by a compiler and forwarded to the processing engine array 410 by the controller 422, which includes a decoder (not shown in FIG. 4) to extract the memory fetch parameters 430 from the instructions. Figure 4B

[0076] The processing engines 411 of the processing engine array 410 can be organized into rows like row 431 and columns like column 432. In one example, each row of processing engines 411 can be mapped to an input channel (C) and can receive input data elements from a memory row of the memory system 404 that is mapped to the input channel in sequence, while each column of processing engines 411 can be mapped to an output channel (parameter m in Equation 3). The input data elements are stored in a contiguous address space and follow an order based on their coordinates in the input data array. Each processing engine 411 can store weight data elements for the input channel and the output channel that the processing engine is mapped to. Each column of processing engines 411. Referring to Figure 4A and Figure 4B , a processing engine 411 within the engine can receive an input data element (e.g., input data i of Figure 4A ) for the input channel, multiply it with the stored weights (e.g., weights w of Figure 4A ​the product with the input partial sum p_in to generate a new partial sum p_out, and pass the new partial sum p_out to the processing engines 411 under the same column. The bottom processing engine 411 of the column can generate a partial sum representing a sum of the products between the weight data elements stored in the column of processing engines 411 and the input data elements of different input channels received from the memory substation 404.

[0077] In the case where the memory fetch parameters 430 indicate that the starting address is at the right-most input data element of each row, a stride of one (which in this example can indicate a skip), and a number of input data elements are fetched, the first partial sums in the first iteration column 432 of processing engines 411 can be generated as follows based on the stored weight data elements and input data elements provided by the memory substation 404:

[0078] The first partial sum ... (Equation 6)

[0079] In the second iteration, the columns 432 of processing engines 411 can generate second partial sums as follows based on the stored weight data elements and input data elements provided by the memory substation 404:

[0080] The second partial sum ... (Equation 7)

[0081] Each column of processing engines 411 can provide the partial sums generated in the iteration to a column sum buffer, such as column sum buffers 442, 443, etc., which are both part of the sum buffer 412. The partial sums are generated based on weight data elements at the same coordinates of different filter arrays associated with different input channels and output channels, and the partial sums correspond to different output data elements.

[0082] Each column sum buffer can continue to accumulate the partial sums received from each column of processing engines 411 until the arithmetic operations on all input data elements are complete. The accumulated partial sums can correspond to, for example, the . Figure 4C Example internal components of the column sum buffers are shown, such as column sum buffers 442 and 443. As shown in Figure 4C , the column sum buffers can contain a number of entries, such as E 0,0 , E 0,1 , E 0,2etc. Each entry can have coordinates that map to coordinates of an output tile, which can represent a region of the output array. Each entry has an adder (not shown in Figure 4C ) that allows the entry to add the received partial sum and to the stored partial sum and to generate an accumulated partial sum and. The entry can then store the accumulated partial sum and. The operations at column sum buffers 442 and 443 can be controlled by a set of buffer write parameters 452 that includes a destination offset, a step, and a number of write elements. The destination offset parameter can indicate the entry to which the first partial sum (of the first iteration) is to be added.

[0083] After computing partial sums from a first set of weight data elements (whose coordinates in the respective filter array are the same but whose input channels and output channels are different), processing engine array 410 can load a new set of weight data elements from a different coordinate and repeat the partial sum computation. The new partial sums can be added to the partial sums computed from the first set of weight data elements and stored in sum buffer 412. The computation and accumulation of partial sums for the remaining weight data elements can continue to generate the output data elements of the output tile.

[0084] After generating the data elements of the output tile, sum buffer 412 can provide the data elements of the output tile to post-processing engine 415, which includes activation function engine 416 and pooling engine 418 to post-process the output data elements and write the post-processed output back to memory sub-system 404. The post-processing operations performed by post-processing engine 415 can be programmable. In some instances, post-processing engine 415 can be programmed to forward the output data elements to one of activation function engine 416 or pooling engine 418 for post-processing. In some instances, post-processing engine 415 can be programmed to forward the output data elements to one of activation function engine 416 or pooling engine 418 for a first stage post-processing operation, write the first stage post-processed output back to sum buffer 412, forward the first stage post-processed output from sum buffer 412 to the other one of activation function engine 416 or pooling engine 418 for a second stage post-processing operation, and then write the second stage post-processed output back to memory sub-system 404.

[0085] Figure 4D Example internal components of post-processing engine 415 are shown. As Figure 4DAs shown, in addition to the activation function engine 416 and the pooling engine 418, the post-processing engine 415 also includes a sum buffer access circuit 462 and a memory subsystem access circuit 464. The sum buffer access circuit 462 provides read and write access to the sum buffer 412 to the activation function engine 416 and the pooling engine 418, while the memory subsystem access circuit 464 provides read and write access to the memory subsystem 404 to the activation function engine 416 and the pooling engine 418. Each of the sum buffer access circuit 462 and the memory subsystem access circuit 464 can be programmed by a buffer write parameter 468 and a memory write parameter 470, respectively. Both parameters 468 and 470 can be generated by a compiler and forwarded to the post-processing engine 416 by the controller 422, which includes a decoder that extracts parameters from instructions Figure 4D (not shown in the middle).

[0086] Each of the buffer write parameter 468 and the memory write parameter 470 can include a starting address or destination offset, a stride indicating a number of elements of the post-processing to skip between each write element, a number of elements to write into the buffer / memory subsystem, and a condition for performing a write operation to the sum buffer / memory subsystem. The parameters can define a series of write operations to write the number of elements into different locations of the buffer / memory. The condition for performing a write operation can apply to the pooling engine 418, which can perform a summation of output data elements of a particular dimension as part of a tensor reduction operation, and the write condition can indicate whether the pooling engine 418 stores a final output of the summation operation of the sum buffer 412 or the memory subsystem 404, or writes partial sums of the output data elements generated during the summation operation to the sum buffer 412 or the memory subsystem 404 as part of an accumulation operation. In the case that the output data elements have multiple dimensions, the buffer write parameter 468 and the memory write parameter 470 can include a stride, a number of elements for each dimension, and a write condition for each dimension. The output data of the post-processing can be sent from the memory subsystem 404 to the communication fabric 420 and / or fetched to the processing engine array 410 as input data for a subsequent neural network layer processing.

[0087] Figures 5A-5D Another example of internal components of the processing circuit 500 is shown, such as the processing engine array 410 and the post-processing engine 415. As Figure 5AAs shown, processing circuitry 500 includes programmable hardware instruction decoder 502, programmable instruction pattern mapping table 504, hardware execution engine 506, memory access circuitry 508, and controller 509. Hardware execution engine 506 can include, for example, processing engine 411, activation function engine 416, pooling engine 418, etc. Memory access circuitry 508 can include, for example, memory access circuitry 427, sum buffer access circuitry 462, memory subsystem access circuitry 464, etc. Each of hardware execution engine 506 and memory access circuitry 508 further includes operand extraction circuitry 510 (e.g., 510a in hardware execution engine 506, 510b in memory access circuitry 508). Figure 4B

[0088] Processing circuitry 500 can receive instructions 520, which can include opcode 522 that can uniquely identify instructions 520 and / or operations performed by hardware execution engine 506. Instructions 520 can also include one or more operands 524, which can include configuration parameters to configure operations at hardware execution engine 506 and memory access circuitry 508. Operands can define, for example, input data type for processing engine 411, arithmetic operation precision at processing engine 411, type of activation function used by activation function engine 416, pooling operation performed by pooling engine 418, etc. Operands can include, for example, memory fetch parameters 430 to configure memory access circuitry 427 of Figure 4B Figure 4C buffer write parameters 468 and memory write parameters 470 to configure memory access circuitry 508 to perform a series of specific access operations at memory (e.g., memory subsystem 404) to support operations at hardware execution engine 506. The series of access operations can include, for example, a series of read / write operations to fetch / store a set of input data elements (e.g., from a certain destination address, skipping a number of input data elements between each data element that is read or written, etc.). The series of memory access operations can also include, for example, a write operation at memory / buffer when a certain condition is met, such as when a sum operation is completed or a partial sum is generated during a sum operation. Memory access operations can be performed to support operations at hardware execution engine 506 associated with instructions 520. In some instances, if execution of an instruction at hardware execution engine 506 requires both a read access operation and a write access operation from memory, the instruction can define both a read access operation and a write access operation.

[0089] ​​Controller 509 can control hardware instruction decoder 502 and programmable instruction pattern mapping table 504 to decode instruction 520 and provide the results of the decoding to memory access circuitry 508 and hardware execution engine 506 to enable both to extract operands 524 from instruction 520. Figure 5B and Figure 5C Example internal components of hardware instruction decoder 502 and programmable instruction pattern mapping table 504 are shown, respectively. In particular, with reference to Figure 5B Hardware instruction decoder 502 can include a memory device (e.g., a register) programmed to store a plurality of opcodes 542, which can include opcode 522. Hardware instruction decoder 502 can search instruction 520 for an opcode that matches any of the plurality of opcodes and output the matching opcode (e.g., opcode 522). Hardware instruction decoder 502 can include a plurality of byte comparators, including 540a, 540b, 540n, etc., to conduct the search. To conduct the search, instruction 520 can be segmented into a plurality of bytes 543 (e.g., 543a, 543b, 543n), where each byte is fed to one of the byte comparators 540 for comparison to each of the plurality of opcodes 542 to search for a matching opcode. In the case where an opcode spans one or more segmented bytes 543, a subset of bits of each opcode can be provided to each byte comparator to search for a matching subset of bits of the opcode. Hardware instruction decoder 502 further includes a merging circuit 544, which can include a multiplexer or other logic circuitry to output the matching opcode. In the case where an opcode is wholly contained in one of the segmented bytes, merging circuit 544 can select the output from one of the byte comparators as the matching opcode based on an indication from the byte comparator that the opcode was found in the byte handled by the byte comparator. Further, in the case where an opcode spans one or more segmented bytes 543, merging circuit 544 can merge the outputs from the byte comparators that indicate that a subset of bits of the opcode was found in the bytes handled by those byte comparators.

[0090] Controller 509 can control programmable hardware instruction decoder 502 to forward the matching opcode (e.g., opcode 522) to programmable instruction pattern mapping table 504, which can be programmed to store a mapping between the plurality of opcodes and a plurality of definitions of bit offsets and bit lengths of operands of instructions. Figure 5C Example internal components of programmable instruction pattern mapping table 504 are shown. As Figure 5CAs shown, the programmable instruction pattern mapping table 504 can include a memory device (e.g., a register) programmed to store mappings between a plurality of opcodes 542 and a plurality of definitions 554. Each definition can define a bit offset and a bit length of one or more operands. A subset of the definitions 554 (e.g., definitions 554a) can define some operands that are targeted for the hardware execution engine 506, while another subset of the definitions 554 (e.g., definitions 554b) can define some operands that are targeted for the memory access circuit 508. Referring back to Figure 5A The programmable instruction pattern mapping table 504 can receive an opcode (e.g., opcode 522) from the programmable hardware instruction decoder 502 and determine a definition 554 that is mapped to the opcode 522. The controller 509 can also identify a subset of the definitions 554 (e.g., definitions 554a) that are targeted for the hardware execution engine 506 and another subset of the definitions 554 (e.g., definitions 554b) that are targeted for the memory access circuit 508. The controller 509 can then control the programmable instruction pattern mapping table 504 to forward the definitions 544b to the operand extraction circuit 510a of the memory access circuit 508 and the definitions 544a to the operand extraction circuit 510b of the hardware execution engine 506. Based on the received definitions, the operand extraction circuit 510a and the operand extraction circuit 510b can extract respective subsets of the operands 524 for the memory access circuit 508 and the hardware execution engine 506.

[0091] The plurality of opcodes stored in the programmable hardware instruction decoder 502 and the programmable instruction pattern mapping table 504 can represent the instruction set currently supported by the processing circuit 500 and the accelerator 402. In some instances, the opcodes can have different bit lengths in at least one subset of the instructions. For example, some of the opcodes can have a bit length of one byte or less, while others of the opcodes can have a bit length of more than one byte. The bit positions and bit lengths of the operands, as well as the number of operands, can also vary between instructions. The flexibility in the length and position of the opcodes and operands allows for a large number of instructions defined and supported by the accelerator 402. As a result, a greater variety of operations can be encoded in the instructions to support different neural network topologies and / or applications, which can expand the capabilities of the accelerator 402.

[0092] On the other hand, the programmable hardware instruction decoder 502 and the programmable instruction mode map 504 do not need to store all opcodes and operand definitions of the instructions supported by the accelerator 402. Instead, the programmable hardware instruction decoder 502 and the programmable instruction mode map 504 can be programmed via an instruction mode program to store only a subset of the opcodes and definitions. This subset can be used by the processing circuitry 500 (and the accelerator 402) as the instruction set currently supported by the accelerator 402. Instructions associated with the subset of opcodes and definitions can control the processing circuitry 500 to perform operations on specific neural networks and / or applications, including, for example, accessing input data of a specific dimension, performing a specific set of pooling operations, using a specific set of activation functions, etc. After the operation of the neural network and / or application is completed, the programmable hardware instruction decoder 502 and the programmable instruction mode map 504 can be programmed via an instruction mode program to store another instruction mode program to store another subset of opcodes and definitions to provide another instruction set to the accelerator 402. This arrangement reduces the number of opcodes and definitions stored in the programmable hardware instruction decoder 502 and the programmable instruction mode mapping table 504. This not only reduces the storage capacity required for the memory device to store the opcodes and definitions, but also improves the search speed of the opcodes and definitions to accelerate the decoding operation.

[0093] The search speed of the opcodes and definitions in the programmable instruction mode mapping table 504 can be further improved by other techniques, such as using content-addressable memory (CAM), which can compare the input search data with the stored data table and return the address of the matching data. Figure 5D An example of the internal structure of the programmable instruction mode map 504 is shown. For example... Figure 5D As shown, the programmable instruction mode map 504 may contain a CAM 560. In CAM 560, each opcode may be associated with an address 564, which in turn is associated with a definition. To perform an opcode-based definition lookup, CAM 560 may search for an input opcode (e.g., opcode 522). Based on a matching opcode, the corresponding address and definition can then be found. Compared to conventional memory devices that only allow address-based access, Figure 5D The arrangement allows for faster searching and retrieval of opcodes and definitions, which can further accelerate decoding operations.

[0094] As described above, the hardware instruction decoder 502 and the programmable instruction mode map 504 can be programmed based on the instruction mode program to store opcodes and definitions. The instruction mode program can be in the form of a bitstream that can be generated from the instruction mode document.

[0095] Figure 6An example of an instruction schema document 600 is shown, which lists the opcode ("opcode_1") of instruction X, as well as the bit offset and bit length of each operand of instruction X, such as the input data type ("input_data_type"), the number of element parameters and step parameters of the input data for each dimension (e.g., step_x, step_y, step_z, num_element_x, num_element_y, num_element_z, etc.), and the like. A bitstream of an instruction schema program defining the bit offset and bit length of the operands can then be generated from the instruction schema document 600 by, for example, a compiler and based on the keywords "bit_offset" and "bit_length".

[0096] In some examples, the instruction schema document 600 can be generated from a more human-readable instruction definition document 602, which can list the order of the opcode and operands, as well as the type of each operand, which can define the bit length of each operand. A script can be employed to generate the instruction schema document 600 from the instruction definition document 602 by, for example, looking up the type and order of the operands listed in the instruction definition document 602 and filling in the bit offset and bit length fields of the operands in the instruction schema document 600. With such an arrangement, the instruction definition can be edited in the more human-readable instruction definition document 602 to reduce the likelihood of human error, while the edits can be automatically and efficiently propagated to the instruction schema document 600 with low risk of error.

[0097] Figures 7A-7C Further examples of instructions for different memory access patterns are shown. As shown in Figure 7A and Figure 7B Two different instructions (Y and X) can include memory access operands for different dimensional data. Figure 7A An instruction definition document 702 for instruction Y and its corresponding instruction schema document 700 are shown, while Figure 7B An instruction definition document 712 for instruction X and its corresponding instruction schema document 710 are shown for Figure 6

[0098] As shown in Figure 7A ​As shown, instruction Y contains operand 722, "Mem_access_4D," for a series of memory access operations on 4D data. The "Mem_access_4D" operand includes address operands, step operands, and multiple element operands for each dimension of the 4D data, such as step_x and num_element_x for the first dimension, step_y and num_element_y for the second dimension, step_z and num_element_z for the third dimension, and step_t and num_element_t for the fourth dimension. The instruction may also include one or more addresses defining the starting position for accessing the 4D data. The address, step, and num_element parameters can define the mode of accessing memory (e.g., memory subsystem 404, summation buffer 412) for each dimension. For example, the "step_x" parameter can define the number of data elements to skip between two accessed data elements along the x-axis, while the "num_element_x" parameter can define the number of data elements to access along the x-axis. Furthermore, the "step_y" parameter defines the number of data elements to skip between two accessed data elements along the x-axis (e.g., rows of a 2D tensor), while "num_element_y" defines the number of data elements to access along the y-axis. The "step_y" parameter can define which data element starts a new row based on the "step_x" and "num_element_x" parameters, while the "num_element_y" element can correspond to the row number in the 2D tensor. The "step_z" parameter defines the number of channels to skip between each element in the 2D tensor (e.g., by skipping rows of memory subsystem 404), while the "num_element_z" parameter defines the total number of channels (e.g., the total number of 2D tensors). Finally, the "step_t" parameter defines the groups of 3D tensors to skip between two accessed groups of 3D tensors (e.g., based on determining address offsets between different locations in memory subsystem 404 storing the groups of 3D tensors), while the "num_element_t" parameter defines the total number of groups of 3D tensors to access. The bit offset and bit length of the Mem_access_4D operand are listed in the instruction mode document 700. After the Mem_access_4D operand is extracted by the operand extraction circuit 510a, the memory access circuit 508 can perform a series of memory access operations to obtain a set of 4D data based on the step size and num_element operand for each dimension.

[0099] On the other hand, Figure 7B In the example, instruction X contains, for instance, in... Figure 6The operand 732 of "Mem_access_3D" in the instruction definition document 750 can be a series of memory access operations for 3D data. The "Mem_access_3D" operand includes a step operand and a plurality of element operands for each dimension of the 3D data, such as step_x and num_element_x for the first dimension, step_y and num_element_y for the second dimension, and step_z and num_element_z for the third dimension. In addition, as shown in the corresponding instruction mode document 710, a step_t and num_element_t operand 734 for the fourth dimension can be padded with zero values. Based on the zero values in the bit length and bit offset, the controller 509 can skip sending the bit length and bit offset of the step_t and num_element_t operand 734 to the memory access circuit 508. Figure 7B

[0100] Figure 7C Examples of sum instructions that can be supported by the programmable hardware instruction decoder 502 and the programmable instruction mode mapping table 504 are shown. As shown in the instruction definition document 752 of Figure 7C The sum instructions can include an operand 754 of "mem_write_mode" that can define conditions to be satisfied by the memory access circuit 508 for write operations, as shown in the instruction definition document 752. The sum instructions can be executed by, for example, the pooling engine 418 to perform a series of write operations to perform a tensor reduction operation. As shown in the instruction file 756 of Figure 7C The sum instruction 762 sets the mem_write_mode operand 754 to a first value (e.g., a zero value) to instruct the pooling engine 418 to only write back the final output of the sum operation to the memory sub-system 404, while the sum instruction 764 sets the mem_write_mode operand 754 to a second value (e.g., a one value) to instruct the pooling engine 418 to write each partial sum of the sum operation to the memory sub-system 404 and / or to perform a write operation at each clock cycle as the partial sum is generated at the pooling engine 418. As an illustrative example, assuming the pooling engine 418 receives a set of input data [1, 2, 3, 4], execution of the instructions 756 can cause the memory access circuit 508 to only store the sum output (10) in the memory sub-system 404, while execution of the instructions 764 can cause the memory access circuit 508 to store the partial sums 1, 3 (sum of 1 and 2), 6 (sum of 1, 2, and 3), and 10 in the memory sub-system 404.

[0101] Figure 8A Examples of operating a hardware accelerator, such as the pooling engine 418, are shown. As shown in the instruction definition document 750, the pooling engine 418 can be configured to perform a sum operation on a set of input data to generate a sum output. The sum operation can be performed by the pooling engine 418 using a sum instruction, such as the sum instruction 762 of the instruction file 756. Figure 4A ​The method 800 can be performed by an accelerator 402. The accelerator 402 can include one or more compute circuits including a processing engine array 410, a sum buffer 412, a post-processing engine 415, and the like. Each compute circuit can include Figure 5A The components of the processing circuit 500 can perform the method 800. The processing circuit 500 includes a programmable hardware instruction decoder 502, a programmable instruction pattern mapping table 504, a hardware execution engine 506, a memory access circuit 508, and a controller 509. The hardware execution engine 506 can include, for example, a processing engine 411, an activation function engine 416, a pooling engine 418, and the like. The memory access circuit 508 can include, for example, a memory access circuit 427, a sum buffer access circuit 462, a memory subsystem access circuit 464, and the like. Each of the hardware execution engine 506 and the memory access circuit 508 further include an operand extraction circuit 510 (e.g., 510a in the hardware execution engine 506, 510b in the memory access circuit 508, and the like). Figure 4B The components of the processing circuit 500 can perform the method 800. The processing circuit 500 includes a programmable hardware instruction decoder 502, a programmable instruction pattern mapping table 504, a hardware execution engine 506, a memory access circuit 508, and a controller 509. The hardware execution engine 506 can include, for example, a processing engine 411, an activation function engine 416, a pooling engine 418, and the like. The memory access circuit 508 can include, for example, a memory access circuit 427, a sum buffer access circuit 462, a memory subsystem access circuit 464, and the like. Each of the hardware execution engine 506 and the memory access circuit 508 further include an operand extraction circuit 510 (e.g., 510a in the hardware execution engine 506, 510b in the memory access circuit 508, and the like).

[0102] The method 800 begins at step 802, where the processing circuit 500 receives an instruction (e.g., instruction 520) including a first opcode (e.g., opcode 522). The opcode 522 can uniquely identify the instruction 520 and / or an operation performed by the hardware execution engine 506. The instruction 520 can also include one or more operands 524, which can include configuration parameters to configure operations at the hardware execution engine 506 and the memory access circuit 508. The operands can define, for example, an input data type for the processing engine 411, a precision of an arithmetic operation at the processing engine 411, a type of activation function used by the activation function engine 416, a pooling operation performed by the pooling engine 418, and the like.

[0103] In step 804, the hardware instruction decoder 502 extracts a first opcode from the instruction. The hardware instruction decoder 502 can include a memory device (e.g., a register) programmed to store a plurality of opcodes 542, which can include the opcode 522. The hardware instruction decoder 502 can search the instruction 520 for an opcode that matches any of the plurality of opcodes and output the matching opcode (e.g., the opcode 522). The hardware instruction decoder 502 can include a plurality of byte comparators, including 540a, 540b, 540n, etc., to perform the search. To perform the search, the instruction 520 can be segmented into a plurality of bytes 543 (e.g., 543a, 543b, 543n), where each byte is fed to one of the byte comparators 540 to compare to each of the plurality of opcodes 542 to search for a matching opcode. In cases where an opcode spans one or more segmented bytes 543, a subset of bits of each opcode can be provided to each byte comparator to search for a matching subset of bits of the opcode. The hardware instruction decoder 502 further includes a merge circuit 544, which can include a multiplexer or other logic circuitry to output the matching opcode. In cases where an opcode is entirely contained in one of the segmented bytes, the merge circuit 544 can select the output from one of the byte comparators as the matching opcode based on an indication from the byte comparator that the opcode was found in the byte handled by the byte comparator. Further, in cases where an opcode spans one or more segmented bytes 543, the merge circuit 544 can merge the outputs from the byte comparators that indicate that a subset of bits of the opcode was found in the bytes handled by those byte comparators.

[0104] In step 806, the controller 509 obtains a first definition of a first operand from the instruction pattern mapping table 504 and based on the first opcode, which maps the plurality of opcodes to a plurality of definitions of operands in a plurality of instructions. The programmable instruction pattern mapping table 504 can include a memory device (e.g., a register) programmed to store mappings between the plurality of opcodes 542 and a plurality of definitions 554. Each definition can define a bit offset and a bit length of one or more operands. A subset of the definitions 554 (e.g., the definitions 554a) can define some operands for the hardware execution engine 506, while another subset of the definitions 554 (e.g., the definitions 554b) can define some operands for the memory access circuit 508. In some instances, the programmable instruction pattern table 504 can be implemented as a content addressable memory (CAM) to improve the speed of retrieving the operand definitions based on the opcode.

[0105] The programmable hardware instruction decoder 502 and the programmable instruction pattern mapping table 504 need not store all of the operation codes and operand definitions for the instructions supported by the accelerator 402. Instead, the programmable hardware instruction decoder 502 and the programmable instruction pattern mapping table 504 can be programmed by the instruction pattern program to store only a subset of the operation codes and definitions. The subset can be used by the processing circuitry 500 (and the accelerator 402) as the instruction set currently supported by the accelerator 402. The instructions associated with the subset of operation codes and definitions can control the processing circuitry 500 to perform the operations of a particular neural network and / or application, including, for example, accessing input data of a particular dimension, performing a particular set of pooling operations, using a particular set of activation functions, etc. After the operations of the neural network and / or application are completed, the programmable hardware instruction decoder 502 and the programmable instruction pattern mapping table 504 can be programmed by the instruction pattern program to store another instruction pattern program to store another subset of operation codes and definitions to provide another instruction set to the accelerator 402. With such an arrangement, the number of operation codes and definitions stored in the programmable hardware instruction decoder 502 and the programmable instruction pattern mapping table 504 can be reduced, which not only can reduce the storage capacity required to store the operation codes and definitions in the memory device, but also can improve the search speed of the operation codes and definitions to speed up the decoding operations.

[0106] In step 808, the controller 509 forwards the instruction and the first definition to a hardware execution engine (e.g., one of the processing engine 411, the activation function engine 416, the pooling engine 418) to enable the hardware execution engine 506 to extract the operands from the instruction based on the first definition and perform operations (e.g., arithmetic operations, activation function processing, pooling operations, etc.) based on the operands. The controller 509 can also forward the second definition of the instruction and the operands for the memory access instruction to the memory access circuitry 508 to perform the memory access instruction to support the operations at the hardware execution engine 506.

[0107] In step 810, the hardware execution engine can extract the operands from the instruction based on the first definition and then, in step 812, execute the instruction by performing operations based on the operands. The operations can include, for example, arithmetic operations based on the precision specified by the operands, activation function processing using the activation function specified by the operands, pooling operations specified by the operands, etc.

[0108] Figure 8B A method 850 of operating a hardware accelerator, such as the accelerator 402, to perform a memory access operation at a memory is shown. Figure 4A The memory can be an on-chip memory, such as the memory subsystem 404, the sum buffer 412, etc. The method 850 can be performed by the memory access circuitry 508 of the processing circuitry 500.

[0109] Method 850 begins with step 852, in which memory access circuit 508 receives an instruction. The instruction can be forwarded by controller 509. The instruction is also decoded by hardware instruction decoder 502 to obtain an opcode, and can also obtain a definition of operands from instruction pattern mapping table 504 to memory access circuit 508.

[0110] In step 854, memory access circuit 508 extracts from the instruction information indicating a first memory access pattern of a plurality of memory access patterns supported by the memory access circuit. In some instances, the plurality of memory access patterns includes accessing different dimensions of data, such as ID, 2D, 3D, and 4D data. The instruction can also contain operands / parameters for each dimension of the plurality of dimensions of data, such as a number of data elements to skip, a number of data elements to access, etc. In cases where the memory access pattern only accesses a subset of the plurality of dimensions, the parameters for the dimensions not accessed can be zeroed out in the instruction.

[0111] In some instances, the instruction is associated with a sum operation of a plurality of data elements at the hardware execution engine. In one memory access pattern, the memory access circuit can perform a write operation to store the sum of the plurality of data elements upon completion of the sum operation, while in another memory access pattern, the memory access circuit can perform a write operation to store each partial sum of the plurality of data elements during the sum operation.

[0112] In step 856, the memory access circuit accesses the memory in the first memory access pattern to support the hardware execution engine in executing the instruction. For example, the memory access circuit can access memory subsystem 404 to fetch input data to the systolic array for computation based on the instruction, and can store output data of the systolic array at sum buffer 412.

[0113] Embodiments of the present disclosure can also be described in terms of the following clauses:

[0114] 1. A hardware accelerator, comprising:

[0115] a programmable hardware instruction decoder programmed to store a plurality of opcodes;

[0116] a programmable instruction pattern mapping table implemented as a content addressable memory (CAM) and programmed to map the plurality of opcodes to a plurality of definitions of operands in a plurality of instructions;

[0117] a hardware execution engine; and

[0118] a controller configured to:

[0119] receiving an instruction containing a first opcode of the plurality of opcodes;

[0120] controlling the hardware instruction decoder to extract the first opcode from the instruction;

[0121] obtaining a first definition of a first operand from the instruction pattern mapping table and based on the first opcode; and

[0122] forwarding the instruction and the first definition to the hardware execution engine to control the hardware execution engine:

[0123] extracting the first operand from the instruction based on the first definition; and

[0124] executing the instruction based on the first operand.

[0125] 2. The hardware accelerator of clause 1, wherein the hardware instruction decoder is programmed based on an opcode programming file specifying locations and sizes of bits of the first opcode in the instruction.

[0126] 3. The hardware accelerator of clause 1 or 2, wherein each definition of the plurality of definitions specifies locations and sizes of bits of an operand in a respective instruction.

[0127] 4. The hardware accelerator of clause 3, wherein the instruction pattern mapping table is programmable based on an instruction pattern programming file specifying bit locations and bit offsets of the operands in the instruction.

[0128] 5. The hardware accelerator of any of clauses 1 to 4, wherein the CAM maps the opcodes to addresses defined in the CAM; and

[0129] wherein the mapping enables retrieval of the first definition from the CAM based on the opcode.

[0130] 6. A hardware accelerator comprising:

[0131] an instruction decoder;

[0132] an instruction pattern mapping table;

[0133] a hardware execution engine; and

[0134] a controller configured to:

[0135] receive an instruction;

[0136] extract an opcode from the instruction using the instruction decoder;

[0137] obtaining an instruction mode of the instruction from the instruction mode mapping table and based on the opcode; and

[0138] forwarding the instruction and the instruction mode to the hardware execution engine to enable the hardware execution engine to extract operands from the instruction and execute the instruction based on the operands.

[0139] 7. The hardware accelerator of clause 6, wherein the hardware instruction decoder is programmable based on an opcode programming file to extract bits of the opcode from a single byte of the instruction or from multiple bytes of the instruction; and

[0140] wherein the opcode programming file specifies locations and sizes of the bits of the opcode in the instruction.

[0141] 8. The hardware accelerator of clause 7, wherein the opcode programming file specifies locations and sizes of multiple sets of bits of the opcode in multiple bytes of the instruction; and

[0142] wherein the hardware instruction decoder is programmed based on the opcode programming file to extract the multiple sets of bits of the opcode from the multiple bytes of the instruction and combine the multiple sets of bits to extract the opcode.

[0143] 9. The hardware accelerator of any one of clauses 6 to 8, wherein the instruction mode mapping table is programmable based on an instruction mode programming file that specifies bit positions and bit offsets of operands in the instruction.

[0144] 10. The hardware accelerator of clause 9, wherein the instruction mode mapping table is programmable during execution of an instruction file comprising first instructions and second instructions by the hardware execution engine;

[0145] wherein the instruction mode mapping table is programmed based on a first instruction mode programming file to provide a first instruction mode of the first instructions to the hardware execution engine; and

[0146] wherein the instruction mode mapping table is programmed based on a second instruction mode programming file to provide a second instruction mode of the second instructions to the hardware execution engine.

[0147] 11. The hardware accelerator of any one of clauses 6 to 10, wherein the instruction mode mapping table is implemented using a content addressable memory (CAM) that maps the opcode to addresses of multiple instruction modes in the CAM and enables retrieval of the instruction mode from the CAM based on the opcode.

[0148] 12. The hardware accelerator of any of clauses 6-11,

[0149] wherein the operand is a first operand;

[0150] wherein the hardware accelerator further comprises a memory access circuit; and

[0151] wherein the controller is configured to:

[0152] obtain, from the instruction pattern mapping table and based on the operation code, a first definition of the first operand and a second definition of a second operand; and

[0153] forward the instruction and the second definition to the memory access circuit to control the memory access circuit to extract the second operand from the instruction and to perform a memory access operation based on the second operand to support the execution of the instruction by the hardware execution engine.

[0154] 13. The hardware accelerator of clause 12, further comprising an on-chip memory;

[0155] wherein the hardware execution engine comprises a systolic array;

[0156] wherein the operation code controls the systolic array to perform a computation to generate an intermediate output; and

[0157] wherein the memory access operation fetches input data elements and weight elements from the on-chip memory to the systolic array for the computation.

[0158] 14. The hardware accelerator of clause 13, wherein the instruction is a first instruction;

[0159] wherein the hardware accelerator further comprises a post-processing engine;

[0160] wherein the controller is configured to:

[0161] receive a second instruction;

[0162] extract, using the instruction decoder, a second operation code from the second instruction;

[0163] obtain, from the instruction pattern mapping table and based on the second operation code, a third definition of a third operand and a fourth definition of a fourth operand;

[0164] forward the second instruction and the third definition to the post-processing engine to enable the post-processing engine to extract the third operand from the second instruction and to perform a post-processing operation on the intermediate output of the systolic array based on the third operand to generate an output; and

[0165] forwarding the second instruction and the fourth definition to the memory access circuit to store the output at the on-chip memory.

[0166] 15. The hardware accelerator of clause 13 or 14, wherein the systolic array is programmable by a first instruction set to perform the computations of the first neural network and programmable by a second instruction set to perform the computations of the second neural network;

[0167] wherein the instruction pattern mapping table is programmed based on a first instruction pattern programming file to provide instruction patterns to the systolic array to control the systolic array to perform the computations of the first neural network; and

[0168] wherein the instruction pattern mapping table is programmed based on a second instruction pattern programming file to provide instruction patterns to the systolic array to control the systolic array to perform the computations of the second neural network.

[0169] 16. A method of operating a hardware accelerator, the method comprising:

[0170] receiving an instruction containing a first operation code;

[0171] extracting, by a hardware instruction decoder of the hardware accelerator that stores a plurality of operation codes, the first operation code from the instruction;

[0172] obtaining, from an instruction pattern mapping table of the hardware accelerator and based on the first operation code, a first definition of a first operand, the instruction pattern mapping table mapping the plurality of operation codes to a plurality of definitions of operands in a plurality of instructions;

[0173] forwarding the instruction and the first definition to a hardware execution engine of the hardware accelerator;

[0174] extracting, by the hardware execution engine, the first operand from the instruction based on the first definition; and

[0175] executing, by the hardware execution engine, the instruction based on the first operand.

[0176] 17. The method of clause 16, further comprising:

[0177] programming the hardware instruction decoder based on an operation code programming file to extract bits of the operation code from a single byte of the instruction or from a plurality of bytes of the instruction; and

[0178] wherein the operation code programming file specifies locations and sizes of the bits of the operation code in the instruction.

[0179] 18. The method of clause 17, wherein the opcode programming file specifies locations and sizes of multiple sets of bits of the opcode in multiple bytes of the instruction; and

[0180] wherein the hardware instruction decoder is programmed based on the programming file to extract the multiple sets of bits of the opcode from the multiple bytes of the instruction and combine the multiple sets of bits to extract the opcode.

[0181] 19. The method of any one of clauses 16-18, further comprising:

[0182] programming the instruction pattern mapping table based on an instruction pattern programming file that specifies bit positions and bit offsets of operands in the instruction.

[0183] 20. The method of clause 19, further comprising:

[0184] programming the instruction pattern mapping table during execution of an instruction file, the instruction file including a first instruction and a second instruction and executed by the hardware execution engine,

[0185] wherein the instruction pattern mapping table is programmed based on a first instruction pattern programming file to provide a first instruction pattern of the first instruction to the hardware execution engine; and

[0186] wherein the instruction pattern mapping table is programmed based on a second instruction pattern programming file to provide a second instruction pattern of the second instruction to the hardware execution engine.

[0187] 21. A hardware accelerator, comprising:

[0188] a hardware instruction decoder programmed to store multiple opcodes;

[0189] an instruction pattern mapping table that maps the multiple opcodes to multiple definitions of operands in multiple instructions;

[0190] a hardware execution engine;

[0191] memory access circuitry programmed to access a memory in multiple memory access patterns, each memory access pattern defining a specific series of access operations in the memory;

[0192] a controller configured to:

[0193] receive an instruction that includes a first opcode of the multiple opcodes;

[0194] controlling the hardware instruction decoder to extract the first opcode from the instruction;

[0195] obtaining, from the instruction pattern mapping table and based on the first opcode, a first definition of a first operand and a second definition of a second operand, the first operand defining a computation operation at the hardware execution engine, the second operand setting a memory access mode of the plurality of memory access modes at the memory access circuit to support the computation operation at the hardware execution engine;

[0196] forwarding the instruction and the first definition to the hardware execution engine to control the hardware execution engine:

[0197] extracting the first operand from the instruction based on the first definition; and

[0198] performing the computation operation based on the first operand; and

[0199] forwarding the instruction and the second definition to the memory access circuit to control the memory access circuit:

[0200] extracting the second operand from the instruction based on the second definition; and

[0201] performing a series of memory access operations at the memory based on the second operand to support the computation operation at the hardware execution engine.

[0202] 22. The hardware accelerator of clause 21, wherein the memory access circuit is configured to perform the series of memory access operations of at least one of: providing input data of the computation operation to the hardware execution engine, or storing output data of the computation operation at the memory.

[0203] 23. The hardware accelerator of clause 21 or 22, wherein the plurality of memory access modes comprises a first memory access mode and a second memory access mode;

[0204] wherein in the first memory access mode, the memory access circuit is programmed to access the memory for one-dimensional first data;

[0205] wherein in the second memory access mode, the memory access circuit is programmed to access the memory for multi-dimensional second data; and

[0206] wherein the accessing the memory for the multi-dimensional second data comprises a series of access operations of data elements of the second data at the memory based on a dimension of the data elements.

[0207] 24. The hardware accelerator of clause 23, wherein in the second memory access mode, the memory access circuit is programmed to access the memory for four-dimensional (4D) second data.

[0208] 25. The hardware accelerator of any one of clauses 21-24, wherein the instruction is associated with a sum operation of a plurality of data elements at the hardware execution engine;

[0209] wherein the plurality of memory access modes comprises a first memory access mode and a second memory access mode;

[0210] wherein in the first memory access mode, the memory access circuit is programmed to perform a write operation to store a sum of the plurality of data elements upon completion of the sum operation; and

[0211] wherein in the second memory access mode, the memory access circuit is programmed to perform a write operation to store each partial sum of the plurality of data elements during the sum operation.

[0212] 26. A hardware accelerator, comprising:

[0213] a hardware execution engine; and

[0214] a memory access circuit, the memory access circuit configured to:

[0215] receive an instruction;

[0216] extract from the instruction information indicative of a first memory access mode of a plurality of memory access modes supported by the memory access circuit; and

[0217] access a memory in the first memory access mode to support execution of the instruction by the hardware execution engine.

[0218] 27. The hardware accelerator of clause 26, wherein the instruction includes:

[0219] an opcode specifying a computational operation at the hardware execution engine;

[0220] a first operand specifying the first memory access mode; and

[0221] a second operand specifying parameters of one or more memory access operations in the first memory access mode.

[0222] 28. The hardware accelerator of clause 27, wherein the second operand specifies at least one of: a read operation on the memory in the first memory access mode to fetch input data for the compute operation to the hardware execution engine, or a write operation on the memory in the first memory access mode to store output data for the compute operation.

[0223] 29. The hardware accelerator of clause 27 or 28, wherein the plurality of memory access modes includes the first memory access mode and a second memory access mode;

[0224] wherein in the first memory access mode, the memory access circuitry is programmed to access the memory for one-dimensional first data having a first dimension;

[0225] wherein in the second memory access mode, the memory access circuitry is programmed to access the memory for multi-dimensional second data having a plurality of dimensions; and

[0226] wherein the accessing the memory for the multi-dimensional second data comprises a series of access operations on data elements of the second data at the memory based on a dimension of the data elements.

[0227] 30. The hardware accelerator of clause 29, wherein in the second memory access mode, the memory access circuitry is programmed to access the memory for four-dimensional second data.

[0228] 31. The hardware accelerator of clause 30, wherein the four-dimensional second data is stored in groups of three-dimensional second data, each group corresponding to a different fourth dimension; and

[0229] wherein the memory access circuitry is programmed to access one or more of the groups of three-dimensional second data based on the second operand.

[0230] 32. The hardware accelerator of any one of clauses 29 to 31, wherein for each dimension of the plurality of dimensions, the second operand includes at least one of: a first parameter indicating a number of data elements to skip between two accessed data elements, or a second parameter indicating a total number of data elements to access.

[0231] 33. The hardware accelerator of clause 32, wherein in the first memory access mode, the first parameter and the second parameter for dimensions other than the first dimension are zero.

[0232] 34. The hardware accelerator of any of clauses 27-33, wherein the compute operation includes a sum operation of a plurality of elements at the hardware execution engine;

[0233] wherein the plurality of memory access modes includes the first memory access mode and a second memory access mode;

[0234] wherein in the first memory access mode, the memory access circuitry is programmed to perform a write operation to store a sum of the plurality of data elements when the sum operation is complete; and

[0235] wherein in the second memory access mode, the memory access circuitry is programmed to perform a write operation to store each partial sum of the plurality of data elements during the sum operation.

[0236] 35. The hardware accelerator of any of clauses 27-34, further comprising an on-chip memory;

[0237] wherein the hardware execution engine comprises a systolic array;

[0238] wherein the opcode controls the systolic array to perform a computation to generate an intermediate output; and

[0239] wherein the one or more memory access operations provide input data elements and weight elements from the on-chip memory to the systolic array for the computation.

[0240] 36. A method of operating a hardware accelerator, the method comprising:

[0241] receiving an instruction;

[0242] extracting, by a memory access circuitry of the hardware accelerator and from the instruction, information indicative of a first memory access mode of a plurality of memory access modes supported by the memory access circuitry; and

[0243] accessing a memory in the first memory access mode to support execution of the instruction by a hardware execution engine of the hardware accelerator.

[0244] 37. The method of clause 36, wherein the instruction includes:

[0245] an opcode specifying a compute operation at the hardware execution engine;

[0246] a first operand specifying the first memory access mode; and

[0247] a second operand that specifies parameters for one or more memory access operations in the first memory access mode.

[0248] 38. The method of clause 37, wherein the plurality of memory access modes includes the first memory access mode and a second memory access mode;

[0249] wherein in the first memory access mode, the memory access circuitry accesses the memory for one-dimensional first data having a first dimension;

[0250] wherein in the second memory access mode, the memory access circuitry accesses the memory for multi-dimensional second data having a plurality of dimensions; and

[0251] wherein the accessing the memory for the multi-dimensional second data comprises a series of access operations for data elements of the second data at the memory based on dimensions of the data elements.

[0252] 39. The method of clause 38, wherein for each dimension of the plurality of dimensions, the second operand includes a first parameter indicating a number of data elements to skip between two accessed data elements, and a second parameter indicating a total number of data elements to access; and

[0253] wherein in the first memory access mode, the first parameter and the second parameter for dimensions other than the first dimension are zero.

[0254] 40. The method of any of clauses 37-39, wherein the compute operation includes a sum operation of a plurality of elements at the hardware execution engine;

[0255] wherein the plurality of memory access modes includes a first memory access mode and a second memory access mode;

[0256] wherein in the first memory access mode, the memory access circuitry performs a write operation to store a sum of the plurality of data elements when the sum operation is complete; and

[0257] wherein in the second memory access mode, the memory access circuitry performs a write operation to store each partial sum of the plurality of data elements during the sum operation.

[0258] Figure 9 includes a block diagram illustrating an example of a host system 900 in which an acceleration engine 960 can be used. Figure 9 The acceleration engine 960 is an example of a device that can include one or more accelerators, as in Figure 4Aas shown in the middle. Figure 9 The example host system 900 includes an acceleration engine 960, a host processor 972, DRAM 930 or processor memory, I / O devices 932, and support systems 974. In various embodiments, the host system 900 can include other hardware not shown here.

[0259] The host processor 972 is a general-purpose integrated circuit capable of executing program instructions. In some examples, the host processor 972 can include multiple processing cores. A multi-core processor can include multiple processing units within the same processor. In some examples, the host system 900 can include more than one host processor 972. In some examples, the host processor 972 and the acceleration engine 960 can be one chip, such as one or more integrated circuits within the same package.

[0260] In various examples, the host processor 972 can communicate with other components in the host system 900 through one or more communication channels. For example, the host system 900 can include a host processor bus that the host processor 972 can use to communicate with, for example, the DRAM 930. As another example, the host system 900 can include an I / O bus, such as a PCI-based bus, that the host processor 972 can use to communicate with, for example, the acceleration engine 960 and / or the I / O devices 932. In various examples, the host system 900 can alternatively or additionally include other communication channels or buses, such as a serial bus, a power management bus, a storage bus, and the like.

[0261] In some examples, a software program executed by the host processor 972 can receive or generate input to be processed by the acceleration engine 960. In some examples, the program can select an appropriate neural network to execute for a given input. For example, the program can be for language translation and can select one or more neural networks capable of speech recognition and / or machine translation. In these and other examples, the program can configure the acceleration engine 960 through a neural network to be executed, and / or can select a neural network processing engine on the acceleration engine 960 that has previously been configured to execute a desired neural network. In some examples, once the acceleration engine 960 has started inference on input data, the host processor 972 can manage data (such as weights, instructions, intermediate results, results of conditional layers, and / or final results) moving into or out of the acceleration engine 960.

[0262] In some instances, a software program using the inference of the acceleration engine 960 can read the results from the condition layer from the acceleration engine 960 and / or from a storage location, such as in the DRAM 930. In these instances, the program can determine what action the neural network should take next. For example, the program can decide to terminate the inference. As another example, the program can determine to change the direction of the inference, which can be translated to the next layer for execution by lower level code and / or neural network processors. In these and other instances, the flow of execution of the neural network can be coordinated by software.

[0263] The DRAM 930 is a memory used by the host processor 972 for storing program code that the host processor 972 is executing and values to operate on. In some instances, data of a neural network (e.g., weight values, instructions, and other data) can be stored in whole or in part in the DRAM 930. DRAM is a general term for processor memory, and while DRAM is volatile memory, processor memory can be volatile and / or non-volatile. Although not illustrated here, the host system 900 can include other volatile and non-volatile memory for other purposes. For example, the host system 900 can include read-only memory (ROM) that stores boot code and / or basic input / output system (BIOS) code that boots the host system 900 upon power up.

[0264] Although not shown here, the DRAM 930 can store instructions of various programs that can be loaded into and executed by the host processor 972. For example, the DRAM 930 can store instructions for an operating system, one or more data stores, one or more application programs, one or more drivers, and / or a service for implementing features disclosed herein.

[0265] The operating system can manage and orchestrate the overall operation of the host system 900, such as scheduling tasks, executing applications, and / or controlling the overall operation of peripheral devices and other operations. In some instances, the host system 900 can host one or more virtual machines. In these instances, each virtual machine can be configured to execute its own operating system. Examples of operating systems include Unix, Linux, Windows, Mac OS, iOS, Android, and the like. Alternatively or additionally, the operating system can be a proprietary operating system.

[0266] The data store can include permanent data or temporary data used and / or operated on by the operating system, applications, or drivers. Examples of such data include web pages, video data, audio data, images, user data, etc. In some examples, information in the data store can be provided to user devices over a network. In some cases, the data store can additionally or alternatively include stored applications and / or drivers. Additionally or alternatively, the data store can store standard and / or proprietary software libraries, and / or standard and / or proprietary application programming interface (API) libraries. Information stored in the data store can be machine-readable object code, source code, interpreted code, or intermediate code.

[0267] Drivers can include programs that provide communication between components in the host system 900. For example, some drivers can provide communication between the operating system and peripheral or I / O devices 932. Alternatively or additionally, some drivers can provide communication between applications and the operating system, and / or between applications accessible to the host system 900 and peripheral devices. In many cases, drivers can include drivers that provide readily understood functionality (e.g., printer drivers, display drivers, hard disk drivers, solid state device drivers, etc.). In other cases, drivers can provide proprietary or specialized functionality.

[0268] I / O devices 932 can include hardware that connects to user input and output devices, such as a keyboard, mouse, pen, tablet, voice input device, touch input device, display or monitor, speaker, and printer, among other devices. I / O devices 932 can also include storage drives and / or network interfaces for connecting to network 980. For example, in various examples, host system 900 can use a network interface to communicate with storage devices, user terminals, other computing devices or servers, and / or other networks.

[0269] In various examples, one or more of the I / O devices 932 can be storage devices. In these examples, the storage devices include non-volatile memory and can store program instructions and / or data. Examples of storage devices include magnetic storage devices, optical discs, solid state disks, flash memory, and / or tape storage devices, among others. Storage devices can be housed in the same chassis as host system 900, or can be in an external enclosure. Storage devices can be fixed (e.g., connected by screws) or removable (e.g., with a physical release mechanism and possibly a hot plug mechanism).

[0270] Any other memory components in the storage device, DRAM 930, and host system 900 are examples of computer-readable storage media. Computer-readable storage media is physical media that can store data in a format that can be read by an apparatus such as host processor 972. Computer-readable storage media can be non-transitory. Non-transitory computer-readable media can retain data stored thereon when the media is not powered on. Examples of non-transitory computer-readable media include ROM devices, magnetic disks, magnetic tapes, optical disks, flash memory devices, and solid-state drives, among others. As used herein, computer-readable storage media does not include computer-readable communication media.

[0271] In various examples, data stored on computer-readable storage media can include program instructions, data structures, program modules, libraries, other software program components, and / or other data that can be transmitted within a data signal, such as a carrier wave or other transmission. Additionally or alternatively, computer-readable storage media can include documents, images, videos, audio, and other data that can be operated or manipulated using software programs.

[0272] In various examples, one or more of the I / O devices 932 can be PCI-based devices. In these examples, a PCI-based I / O device includes a PCI interface that communicates with host system 900. The term "PCI" or "PCI-based" can be used to describe any of the family of PCI bus protocols, including the original PCI standard, PCI-X, Accelerated Graphics Port (AGP), and PCI-Express (PCIe), or any other improvement or derivative protocol based on the PCI protocols discussed herein. A PCI-based protocol is a standard bus protocol for connecting devices such as local peripheral devices to host devices. A standard bus protocol is a data transfer protocol whose specification has been adopted by various manufacturers for correspondence and adoption. Manufacturers ensure that compatible devices are compatible with computing systems that implement the bus protocol, and vice versa. As used herein, a PCI-based device also includes devices that use Non-Volatile Memory Express (NVMe) communication. NVMe is a device interface specification for accessing non-volatile storage media connected to a computing system using PCIe.

[0273] A PCI-based device can include one or more functions. A "function" describes a hardware and / or software operation that can be provided by a PCI-based device. Examples of functions include mass storage controllers, network controllers, display controllers, memory controllers, serial bus controllers, wireless controllers, and encryption and decryption controllers, among others. In some cases, a PCI-based device can include more than one function. For example, a PCI-based device can provide a mass storage controller and a network adapter. As another example, a PCI-based device can provide two storage controllers to control two different storage resources. In some embodiments, a PCI-based device can have up to eight functions.

[0274] In some examples, a PCI-based device can include Single Root Input / Output Virtualization (SR-IOV). SR-IOV is an extended function that can be included in a PCI-based device. SR-IOV allows a physical resource (e.g., a single network interface controller) to appear as multiple virtual resources (e.g., sixty-four network interface controllers). Thus, a PCI-based device that provides a certain function (e.g., a network interface controller) can appear to a device that uses the PCI-based device as multiple devices that provide the same function. The functions of a storage adapter device that supports SR-IOV can be classified as a physical function (PF) or a virtual function (VF). A physical function refers to a function in a device that can be discovered, managed, and manipulated with full features. A physical function has configuration resources that can be used to configure or control the storage adapter device. A physical function includes the same configuration address space and memory address space as a non-virtualized device. A physical function can have multiple virtual functions associated with it. A virtual function is similar to a physical function, but is a lightweight function that can typically lack configuration resources and is typically controlled by the configuration of its underlying physical function. Each of the physical function and / or virtual functions can be assigned to a respective execution thread (e.g., a virtual machine) running on a host device.

[0275] In various embodiments, the support system 974 can include hardware to coordinate the operation of the acceleration engine 960. For example, the support system 974 can include a microprocessor that coordinates the activities of the acceleration engine 960, including moving data around on the acceleration engine 960. In this example, the microprocessor can be an integrated circuit that can execute microcode. Microcode is program code that can give an integrated circuit a certain degree of flexibility in the operations that the integrated circuit can perform, but because the program code uses a limited instruction set, the microprocessor can have more limited capabilities than the host processor 972. In some examples, the program executed by the microprocessor is stored on the hardware of the microprocessor, or on a non-volatile memory chip in the host system 900. In some examples, the microprocessor and the acceleration engine 960 can be on a chip, such as on the same die and in the same package as one integrated circuit.

[0276] In some examples, when a program executing on the host processor 972 requests execution of a neural network, the support system 974 can be responsible for obtaining the instructions from the host processor 972. For example, the host processor 972 can provide a set of input data to the support system 974 along with a task to be performed on the set of input data. In this example, the support system 974 can identify a neural network that can perform the task, and can program the acceleration engine 960 to execute the neural network on the set of input data. In some examples, the support system 974 need only select an appropriate neural network processing engine of the neural network processor. In some examples, the support system 974 can need to load data for the neural network onto the acceleration engine 960 before the acceleration engine 960 can begin executing the neural network. In these and other examples, the support system 974 can further receive an output of the execution of the neural network, and provide the output back to the host processor 972.

[0277] In some examples, the operations of the support system 974 can be handled by the host processor 972. In these examples, the support system 974 can not be needed, and can be omitted from the host system 900.

[0278] In various examples, the host system 900 can include a combination of host systems, processor nodes, storage subsystems, and I / O racks representing user devices, service provider computers, or third party computers.

[0279] A user device can include a computing device for accessing an application (e.g., a web browser or mobile device application). In some examples, the application can be hosted, managed, and / or provided by a computing resource service or service provider. The application can enable a user to interact with a service provider computer to, for example, access web content (e.g., web pages, music, videos, etc.). The user device can be a computing device such as a mobile phone, a smart phone, a personal digital assistant (PDA), a laptop computer, a netbook computer, a desktop computer, a thin terminal device, a tablet computer, an electronic book (e-book) reader, a gaming console, etc. In some examples, the user device can communicate with the service provider computer over one or more networks. Additionally, the user device can be part of a distributed system managed, controlled, or otherwise part of a service provider computer (e.g., a console device integrated with the service provider computer).

[0280] The host system 900 can also represent one or more service provider computers. The service provider computers can provide a native application configured to run on a user device with which a user can interact. In some examples, the service provider computers can provide computing resources such as, but not limited to, client entities, low-latency data storage, persistent data storage, data access, management, virtualization, cloud-based software solutions, electronic content performance management, etc. The service provider computers can also be operable to provide web hosting, databases, computer application development and / or implementation platforms, combinations of the foregoing, etc. In some examples, the service provider computers can provide as one or more virtual machines implemented in a hosted computing environment. The hosted computing environment can include one or more computing resources that are quickly provisioned and released. These computing resources can include computing, networking, and / or storage. The hosted computing environment can also be referred to as a cloud computing environment. The service provider computers can include one or more servers, possibly arranged in a cluster, as a server farm, or as separate servers that are not related to each other, and can host applications and / or cloud-based software services. These servers can be configured as part of an integrated distributed computing environment. In some examples, additionally or alternatively, the service provider computers can include a computing device such as a mobile phone, a smart phone, a personal digital assistant (PDA), a laptop computer, a desktop computer, a netbook computer, a server computer, a thin terminal device, a tablet computer, a gaming console, etc. In some examples, the service provider computers can communicate with one or more third party computers.

[0281] Figure 10 A diagram including an example network 1000 can include one or more host systems, such as Figure 9 the host system shown in FIG. 1. For example, Figure 10The example network 1000 includes a plurality of nodes 1002a-1002h, one or more of which can be host systems as shown in Figure 9

[0282] In various instances, the network 1000 can be used to process data. For example, input data can be received at one of the nodes 1002a-1002h or from another network 1008 with which the network 1000 can communicate. In this instance, the input data can be directed to a node in the network 1000 that includes an acceleration engine for the acceleration engine to operate on and produce a result. The result can then be transmitted to the node that received the input data or to the other network. In various instances, input data can be accumulated from a variety of sources, including one or more of the nodes 1002a-1002h and / or computing devices located in the other network 1008, and the accumulated input data can be directed to one or more host systems in the network 1000. Results from the host systems can then be distributed back to the sources that collected the input data.

[0283] In various instances, one or more of the nodes 1002a-1002h can be responsible for operations such as accumulating input data for host systems to operate on, tracking which host systems are busy and which host systems can accept more work, determining whether host systems are operating correctly and / or most efficiently, monitoring network security, and / or other management operations.

[0284] In instances of Figure 10 The nodes 1002a-1002h are connected to each other using a switched architecture with point-to-point links in the example. The switched architecture includes a plurality of switches 1004a-1004d, which can be arranged in a multi-tier network such as a Clos network. A network device that filters and forwards packets between segments of a local-area network (LAN) is called a switch. Switches operate at the data link layer (Layer 2) and sometimes at the network layer (Layer 3) of the Open Systems Interconnection (OSI) reference model, and can support several packet protocols. Figure 10 The switches 1004a-1004d of the example can be connected to the nodes 1002a-1002h and provide multiple paths between any two nodes.

[0285] ​The network 1000 can also include one or more network devices that are used to connect with other networks 1008, such as routers 1006. Routers use headers and forwarding tables to determine the best path for forwarding packets, and communicate with each other and configure the best routes between any two devices using protocols such as Internet Control Message Protocol (ICMP). Figure 10 The routers 1006 can be used to connect to other networks 1008, such as subnets, LANs, wide area networks (WANs), and / or the Internet.

[0286] In some instances, the network 1000 can include any one or a combination of many different types of networks, such as wired networks, the Internet, wireless networks, cellular networks, and other private and / or public networks. If present, the interconnected switches 1004a-1004d and routers 1006 can be referred to as a switch fabric 1010, fabric, network fabric, or simply network. In the context of computer networks, the terms "fabric" and "network" can be used interchangeably herein.

[0287] The nodes 1002a-1002h can be any combination of host systems, processor nodes, storage subsystems, and I / O racks representing user devices, service provider computers, or third party computers.

[0288] A user device can include a computing device for accessing an application 1032 (e.g., a web browser or mobile device application). In some aspects, the application 1032 can be hosted, managed, and / or provided by a computing resource service or service provider. The application 1032 can allow a user to be able to interact with a service provider computer to, for example, access network content (e.g., webpages, music, videos, etc.). The user device can be a computing device such as a mobile phone, a smart phone, a personal digital assistant (PDA), a laptop computer, a netbook computer, a desktop computer, a thin terminal device, a tablet computer, an electronic book (e-book) reader, a gaming console, etc. In some instances, the user device can communicate with the service provider computer through other networks 1008. Additionally, the user device can be part of a distributed system that is managed, controlled, or otherwise part of the service provider computer (e.g., a console device integrated with the service provider computer).

[0289] Figure 10The nodes can also represent one or more service provider computers. The one or more service provider computers can provide a native application configured to run on a user device with which a user can interact. In some instances, the service provider computers can provide computing resources such as, but not limited to, client entities, low-latency data storage, persistent data storage, data access, management, virtualization, cloud-based software solutions, electronic content performance management, and the like. The service provider computers can also be operable to provide network hosting, databases, computer application development and / or implementation platforms, combinations of the foregoing, and the like, to users. In some instances, the service provider computers can provide as one or more virtual machines implemented in a hosted computing environment. The hosted computing environment can include one or more computing resources that are rapidly provisioned and released. These computing resources can include computing, network, and / or storage resources. The hosted computing environment can also be referred to as a cloud computing environment. The service provider computers can include one or more servers, possibly arranged in a cluster, as a server farm, or as separate servers that are not related to each other and can host the application 1032 and / or cloud-based software services. These servers can be configured as part of an integrated, distributed computing environment. In some aspects, additionally or alternatively, the service provider computers can include computing devices such as mobile phones, smart phones, personal digital assistants (PDAs), laptop computers, desktop computers, netbook computers, server computers, thin terminal devices, tablet computers, gaming devices, and the like. In some cases, the service provider computers can communicate with one or more third party computers.

[0290] In one example configuration, the nodes 1002a-1002h can include at least one memory 1018 and one or more processing units (or processors) 1020. The processors 1020 can be implemented in hardware, computer-executable instructions, firmware, or combinations thereof. Computer-executable instruction or firmware implementations of the processors 1020 can include computer-executable or machine-executable instructions written in any suitable programming language to perform the various functions described.

[0291] In some cases, the hardware processors 1020 can be single-core or multi-core processors. Multi-core processors can include multiple processing units within the same processor. In some instances, multi-core processors can share certain resources, such as a bus and a level two or level three cache. In some cases, each core in a single-core or multi-core processor can also include multiple execution logic processors (or execution threads). In such cores (e.g., cores with multiple logic processors), several stages of the execution pipeline and lower level caches can also be shared.

[0292] The memory 1018 can store program instructions loadable and executable on the processor 1020, as well as data generated during the execution of these programs. Depending on the configuration and type of the node 1002a-1002h, the memory 1018 can be volatile (such as RAM) and / or non-volatile (such as ROM, flash memory, etc.). The memory 1018 can include an operating system 1028, one or more data stores 1030, one or more application programs 1032, one or more drivers 1034, and / or a service for implementing the features disclosed herein.

[0293] The operating system 1028 can support basic functions of the node 1002a-1002h, such as scheduling tasks, executing applications, and / or controlling peripheral devices. In some embodiments, the service provider computer can host one or more virtual machines. In these embodiments, each virtual machine can be configured to execute its own operating system. Examples of operating systems include Unix, Linux, Windows, Mac OS, iOS, Android, and the like. The operating system 1028 can also be a proprietary operating system.

[0294] The data stores 1030 can include persistent or temporary data used and / or manipulated by the operating system 1028, the application programs 1032, or the drivers 1034. Examples of such data include web pages, video data, audio data, images, user data, and the like. In some embodiments, information in the data stores 1030 can be provided to user devices over the network 1008. In some cases, additionally or alternatively, the data stores 1030 can include stored application programs and / or drivers. Additionally or alternatively, the data stores 1030 can store standard and / or proprietary software libraries, and / or standard and / or proprietary application program interface (API) libraries. Information stored in the data stores 1030 can be machine-readable object code, source code, interpreted code, or intermediate code.

[0295] The drivers 1034 include programs that can provide communication between components in the node. For example, some drivers 1034 can provide communication between the operating system 1028 and the additional storage 1022, the network device 1024, and / or the I / O device 1026. Alternatively or additionally, some drivers 1034 can provide communication between the application programs 1032 and the operating system 1028, and / or between application programs 1032 accessible by the service provider computer and peripheral devices. In many cases, the drivers 1034 can include drivers that provide easy-to-understand functionality (e.g., printer drivers, display drivers, hard drive and solid state device drivers). In other cases, the drivers 1034 can provide proprietary or specialized functionality.

[0296] The service provider computer or server can also include additional storage 1022, which can include removable storage and / or non-removable storage. The additional storage 1022 can include magnetic storage, optical disks, solid state disks, flash memory, and / or tape storage. The additional storage 1022 can be housed in the same rack as the nodes 1002a-1002h or can be located in an external hard drive bay. The memory 1018 and / or the additional storage 1022 and their associated computer-readable media provide nonvolatile storage of computer-readable instructions, data structures, program modules, and other data for the computing devices. In some embodiments, the memory 1018 can include a variety of different types of memory, such as SRAM, DRAM, or ROM.

[0297] The removable and non-removable memory 1018 and the additional storage 1022 are examples of computer-readable storage media. For example, computer-readable storage media can include volatile or non-volatile, removable or non-removable media implemented in a method or technology for storage of information such as computer readable instructions, data structures, program modules, or other data. The memory 1018 and the additional storage 1022 are examples of computer storage media. Additional types of computer storage media that can be present in the nodes 1002a-1002h include, but are not limited to, PRAM, SRAM, DRAM, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROMs, DVDs or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, solid state drives, or some other mass storage device technology which can be used to store the desired information and which can be accessed by the nodes 1002a-1002h. Computer-readable media also includes combinations of the above-mentioned types of computer-readable media, including multiple ones of a type of media.

[0298] Alternatively, or in addition, the computer-readable media can include computer- readable instructions, program modules, or other data generated and transmitted within a data signal, such as a carrier wave or other transport. However, as used herein, computer-readable storage media does not include computer-readable communication media.

[0299] The nodes 1002a-1002h can also include I / O devices 1026, such as keyboards, mice, pens, voice input devices, touch input devices, displays, speakers, printers, etc. The nodes 1002a-1002h can also include one or more communication channels 1036. The communication channels 1036 can provide a medium through which various components of the nodes 1002a-1002h can communicate. The one or more communication channels 1036 can take the form of a bus, ring, switch, or network.

[0300] The nodes 1002a-1002h can also contain network devices 1024 that allow the nodes 1002a-1002h to communicate with stored databases, another computing device or server, user terminals, and / or other devices on the network 1000.

[0301] In some embodiments, the network devices 1024 are peripheral devices, such as PCI-based devices. In these embodiments, the network devices 1024 include a PCI interface for communicating with a host device. The term "PCI" or "PCI-based" can be used to describe any of the family of PCI bus protocols, including the original PCI standard, PCI-X, Accelerated Graphics Port (AGP), and PCI-Express (PCIe), or any other improvement or derivative protocol based on the PCI protocols discussed herein. PCI-based protocols are standard bus protocols for connecting devices, such as local peripheral devices, to host devices. A standard bus protocol is a data transfer protocol whose specification has been adopted by various manufacturers. Manufacturers ensure that compatible devices are compatible with computing systems that implement the bus protocol, and vice versa. As used herein, PCI-based devices also include devices that use Non-Volatile Memory Express (NVMe) communications. NVMe is a device interface specification for accessing non-volatile storage media connected to a computing system using PCIe. For example, a bus interface module can implement NVMe, and the network devices 1024 can connect to a computing system using a PCIe interface.

[0302] PCI-based devices can include one or more functions. A "function" describes an operation that can be provided by the network devices 1024. Examples of functions include mass storage controllers, network controllers, display controllers, memory controllers, serial bus controllers, wireless controllers, and encryption and decryption controllers, among others. In some cases, a PCI-based device can include more than one function. For example, a PCI-based device can provide a mass storage controller and a network adapter. As another example, a PCI-based device can provide two storage controllers to control two different storage resources. In some embodiments, a PCI-based device can have up to eight functions.

[0303] In some embodiments, network device 1024 can include Single Root Input / Output Virtualization (SR-IOV). SR-IOV is an extension function that can be included in PCI-based devices. SR-IOV allows a physical resource (e.g., a single network interface controller) to appear as multiple resources (e.g., sixty-four network interface controllers). Thus, a PCI-based device that provides a certain function (e.g., a network interface controller) can appear to a device that uses the PCI-based device as multiple devices that provide the same function. The functions of a storage adapter device that supports SR-IOV can be classified as a physical function (PF) or a virtual function (VF). A physical function refers to a function in a device that has full features that can be discovered, managed, and manipulated. A physical function has configuration resources that can be used to configure or control the storage adapter device. A physical function includes the same configuration address space and memory address space as a non-virtualized device. A physical function can have multiple virtual functions associated with it. A virtual function is similar to a physical function, but is a light-weight function that can typically lack configuration resources and is typically controlled by the configuration of its underlying physical function. Each of the physical functions and / or virtual functions can be assigned to a respective execution thread (e.g., a virtual machine) running on a host device.

[0304] The modules described herein can be software modules, hardware modules, or suitable combinations thereof. If a module is a software module, the module can be embodied on a non-transitory computer-readable medium and processed by a processor of any of the computer systems described herein. It should be noted that the described processes and architectures can be performed in real-time or in an asynchronous mode prior to any user interaction. The modules can be configured in the manner suggested in the foregoing figures, and / or the functionality described herein can be provided by one or more modules existing as separate modules, and / or the module functionality described herein can be distributed over multiple modules.

[0305] The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be apparent that various modifications and changes can be made thereto without departing from the broader spirit and scope of the disclosure as set forth in the claimed subject matter.

[0306] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the present disclosure to the specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the present disclosure, as defined in the appended claims.

[0307] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the disclosed examples (especially in the context of following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" are to be construed as open-ended terms (i.e., meaning "including, but not limited to,") unless otherwise noted. The term "connected" is to be construed as partly or fully inclusive, attached to, or joined together, even if there is an intervening material or some other interruption, unless otherwise indicated herein or by context. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate examples of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0308] Unless specifically stated otherwise, the use of terms such as "at least one," "one or more," "or," and "including" to link the

[0309] Various examples of the present disclosure are described herein, including the best modes known to the inventors to practice the present disclosure. Variations on those examples can become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate, and the inventors intend for the present disclosure to be practiced otherwise than specifically described herein. Accordingly, the present disclosure includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the elements set forth above can be implemented with both general and special-purpose apparatuses that are neither expressly nor implicitly disclosed above. Unless otherwise indicated herein, the procedures or methods disclosed herein can be performed in any suitable order unless otherwise indicated herein or by context. Moreover, the various elements of the disclosure can be combined in any combination, unless otherwise indicated herein or by context.

Claims

1. A hardware accelerator, comprising: Instruction decoder; Instruction mode mapping table; Hardware execution engine; as well as The controller is configured to: Receive instructions; The instruction decoder is used to extract the opcode from the instruction; The instruction pattern of the instruction is obtained from the instruction pattern map and based on the opcode, wherein the instruction pattern specifies the bit offset and bit length of the operand in the instruction, and wherein the instruction pattern map is separate from the instruction decoder. and The instruction and the instruction pattern are forwarded to the hardware execution engine so that the hardware execution engine can extract operands from the instruction based on the instruction pattern and execute the instruction based on the operands.

2. The hardware accelerator of claim 1, wherein the instruction decoder can be programmed based on an instruction mode program to extract bits of the opcode from a single byte or from multiple bytes of the instruction; The instruction mode program specifies the position and size of the bit of the opcode in the instruction.

3. The hardware accelerator of claim 2, wherein the instruction mode program specifies the position and size of a plurality of bit sets of the opcode within a plurality of bytes of the instruction; and The instruction decoder is programmed based on the instruction mode program to extract the multiple bit sets of the opcode from the multiple bytes of the instruction, and combines the multiple bit sets to extract the opcode.

4. The hardware accelerator according to any one of claims 1 to 3, wherein the instruction mode mapping table is programmable based on an instruction mode program that specifies the position and size of the bits of the operands in the instruction.

5. The hardware accelerator of claim 4, wherein the instruction mode mapping table can be programmed during the execution of an instruction file including a first instruction and a second instruction by the hardware execution engine; The instruction mode mapping table is programmed based on a first instruction mode program to provide the first instruction mode of the first instruction to the hardware execution engine; and The instruction mode mapping table is programmed based on a second instruction mode program to provide the second instruction mode of the second instruction to the hardware execution engine.

6. The hardware accelerator according to any one of claims 1 to 3, wherein the instruction mode mapping table is implemented using a content-addressable memory (CAM), the CAM mapping the opcode to addresses of a plurality of instruction modes in the CAM, and enabling retrieval of the instruction mode from the CAM based on the opcode.

7. The hardware accelerator according to any one of claims 1 to 3, The operand mentioned above is the first operand; The hardware accelerator further includes memory access circuitry; and The controller is configured to: The first definition of the first operand and the second definition of the second operand are obtained from the instruction pattern mapping table and based on the opcode, wherein... The first definition and the second definition specify the bit offset and bit length of the first operand and the second operand in the instruction, respectively; and The instruction and the second definition are forwarded to the memory access circuit to control the memory access circuit to extract the second operand from the instruction and perform memory access operations based on the second operand to support the execution of the instruction by the hardware execution engine.

8. The hardware accelerator of claim 7, further comprising on-chip memory; The hardware execution engine mentioned above includes a systolic array; The opcodes control the systolic array to perform calculations to generate intermediate outputs; and The memory access operation wherein the input data elements and weight elements are retrieved from the on-chip memory to the systolic array for the computation.

9. The hardware accelerator according to claim 8, wherein the instruction is a first instruction; The hardware accelerator further includes a post-processing engine. The controller is configured to: Receive the second instruction; The instruction decoder is used to extract the second opcode from the second instruction; The third definition of the third operand and the fourth definition of the fourth operand are obtained from the instruction pattern mapping table and based on the second opcode, wherein, The third definition and the fourth definition respectively specify the bit offset and bit length of the third operand and the fourth operand in the second instruction; The second instruction and the third definition are forwarded to the post-processing engine so that the post-processing engine can extract the third operand from the second instruction and perform post-processing operations on the intermediate output of the systolic array based on the third operand to generate an output; and The second instruction and the fourth definition are forwarded to the memory access circuitry to store the output in the on-chip memory.

10. The hardware accelerator of claim 8, wherein the systolic array can be programmed via a first instruction set to perform the computation of the first neural network, and can be programmed via a second instruction set to perform the computation of the second neural network; The instruction pattern mapping table is programmed based on a first instruction pattern program to provide instruction patterns to the systolic array to control the systolic array to perform the computation of the first neural network; and The instruction pattern mapping table is programmed based on a second instruction pattern program to provide instruction patterns to the systolic array to control the systolic array to perform the computation of the second neural network.

11. A method of operating a hardware accelerator, the method comprising: Receive an instruction containing the first opcode; The hardware instruction decoder of the hardware accelerator, which stores multiple opcodes, extracts the first opcode from the instruction. A first definition of a first operand is obtained from the instruction mode map table of the hardware accelerator and based on the first opcode. The instruction mode map table maps the plurality of opcodes to a plurality of definitions of operands in a plurality of instructions. The first definition specifies the bit offset and bit length of the first operand in the instruction. The instruction mode map table is separate from the hardware instruction decoder. The instruction and the first definition are forwarded to the hardware execution engine of the hardware accelerator; The hardware execution engine extracts the first operand from the instruction based on the first definition; as well as The hardware execution engine executes the instruction based on the first operand.

12. The method of claim 11, further comprising: The hardware instruction decoder is programmed based on the instruction mode to extract bits of the opcode from a single byte or multiple bytes of the instruction. and The instruction mode program specifies the position and size of the bit of the opcode in the instruction.

13. The method of claim 12, wherein the instruction mode program specifies the position and size of a plurality of bit sets of the opcode within a plurality of bytes of the instruction; and The hardware instruction decoder is programmed based on the instruction mode program to extract the multiple bit sets of the opcode from the multiple bytes of the instruction, and combines the multiple bit sets to extract the opcode.

14. The method according to any one of claims 11 to 13, further comprising: The instruction pattern program programs the instruction pattern mapping table based on the position and size of the bits of the specified operands in the instruction.

15. The method of claim 14, further comprising: The instruction pattern mapping table is programmed during the execution of the instruction file, which includes first and second instructions and is executed by the hardware execution engine. The instruction mode mapping table is programmed based on a first instruction mode program to provide the first instruction mode of the first instruction to the hardware execution engine; and The instruction mode mapping table is programmed based on a second instruction mode program to provide the second instruction mode of the second instruction to the hardware execution engine.

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