Multi-mode plane engine for neural processors

Abstract

The implementation relates to a neural processor comprising a plurality of neural engine circuits and one or more planar engine circuits. The plurality of neural engine circuits are capable of performing convolution operations on input data of the neural engine circuits with one or more kernels to generate an output. The planar engine circuit is coupled to the plurality of neural engine circuits. The planar engine circuit generates the output from input data corresponding to a version of the output of the neural engine circuits or the input data of the neural processor. The planar engine circuit can be configured to multiple modes. In pooling mode, the planar engine circuit reduces the spatial size of the version of the input data. In element-wise mode, the planar engine circuit performs element-wise operations on the input data. In reduction mode, the planar engine circuit reduces the rank of the tensor.

Description

Background Technology 1. Technical Field

[0002] This disclosure relates to a circuit for performing operations related to a neural network, and more specifically to a neural processor comprising a plurality of neural engine circuits and one or more multimode planar engine circuits.

[0003] 2. Relevant Technical Descriptions

[0004] Artificial neural networks (ANNs) are computational systems or models that use a set of connected nodes to process input data. ANNs are typically organized into layers, with different layers performing different types of transformations on their inputs. Extensions or variants of ANNs such as convolutional neural networks (CNNs), recurrent neural networks (RNNs), and deep belief networks (DBNs) have received considerable attention. These computational systems or models typically involve a wide range of computational operations, including multiplication and accumulation. For example, CNNs are a class of machine learning techniques that primarily use convolutions between input data and kernel data; convolutions can be decomposed into multiplication and accumulation operations.

[0005] These machine learning systems or models can be configured differently depending on the type of input data and the operations to be performed. Such varied configurations would include, for example, preprocessing operations, the number of channels in the input data, the kernel data to be used, the nonlinear functions to be applied to the convolution results, and the application of various post-processing operations. Instantiating and executing machine learning systems or models with various configurations using a central processing unit (CPU) and its main memory is relatively straightforward, as such systems or models can be instantiated simply by updating the code. However, relying solely on the CPU for the various operations of these machine learning systems or models would consume significant CPU bandwidth and increase overall power consumption. Summary of the Invention

[0006] The implementation relates to a neural processor including a plurality of neural engine circuits and a planar engine circuit capable of operating in multiple modes and coupled to the plurality of neural engine circuits. At least one of the neural engine circuits performs a convolution operation on first input data with one or more kernels to generate a first output. The planar engine circuit generates a second output from second input data corresponding to either the first output or a version of the neural processor's input data. The input data to the neural processor may be data received from a source outside the neural processor, or the output of the neural engine circuit or the planar engine circuit in a previous loop. In pooling mode, the planar engine circuit reduces the spatial size of the version of the second input data. In element-wise mode, the planar engine circuit performs element-wise operations on the second input data. In reduction mode, the planar engine circuit reduces the rank of the tensor. Attached Figure Description

[0007] Figure 1 It is a high-level diagram of an electronic device according to the implementation plan.

[0008] Figure 2 This is a block diagram illustrating components in an electronic device according to one embodiment.

[0009] Figure 3 This is a block diagram illustrating a neural processor circuit according to one embodiment.

[0010] Figure 4 This is a block diagram of a neural engine in a neural processor circuit according to one implementation scheme.

[0011] Figure 5 This is a conceptual diagram illustrating a loop for processing input data at a neural processor circuit according to one embodiment.

[0012] Figure 6A , Figure 6B and Figure 6C It is a conceptual diagram illustrating pooling, element-wise, and shrinking operations according to an implementation scheme.

[0013] Figure 7 This is a flowchart illustrating the operation of a neural processor according to an implementation scheme.

[0014] For illustrative purposes only, the accompanying drawings and detailed descriptions depict various non-limiting embodiments. Detailed Implementation

[0015] Reference will now be made in detail to the embodiments, examples of which are shown in the accompanying drawings. Numerous specific details are shown in the following detailed description to provide a full understanding of the various described embodiments. However, the embodiments described may be implemented without these specific details. In other cases, well-known methods, processes, components, circuits, and networks are not described in detail so as not to unnecessarily obscure the various aspects of the embodiments.

[0016] Embodiments of this disclosure relate to a neural processor comprising a plurality of neural engine circuits and one or more planar engine circuits that are efficient in performing different types of computations. The neural engine circuits may be efficient for performing computationally intensive operations (e.g., convolution operations), while the planar engine circuits may be efficient for performing computationally inefficient operations involving higher data input / output speeds. The neural engine circuits can operate in multiple modes, including pooling mode, element-wise mode, and reduction mode. In pooling mode, the planar engine circuits reduce the spatial size of a version of second input data. In element-wise mode, the planar engine circuits perform element-wise operations on the second input data. In reduction mode, the planar engine circuits reduce the rank of the tensor. The planar engine circuits and neural engine circuits can perform different computations in parallel, thereby accelerating the operation of the neural processor.

[0017] Exemplary electronic devices

[0018] This document describes implementations of electronic devices, user interfaces for such devices, and related processes for using such devices. In some implementations, the device is a portable communication device, such as a mobile phone, that also includes other functions such as a personal digital assistant (PDA) and / or music player functionality. Exemplary implementations of portable multi-functional devices include, but are not limited to, those from Apple Inc. (Cupertino, California). Devices, iPod Devices, Apple Equipment and Device. Alternatively, other portable electronic devices, such as wearable devices, laptops, or tablets, may be used. In some embodiments, the device is not a portable communication device, but a desktop computer or other computing device not designed for portable use. In some embodiments, the disclosed electronic device may include a touch-sensitive surface (e.g., a touchscreen display and / or touchpad). The following is combined with… Figure 1 The described example electronic device (e.g., device 100) may include a touch-sensitive surface for receiving user input. The electronic device may also include one or more other physical user interface devices, such as a physical keyboard, mouse, and / or joystick.

[0019] Figure 1This is a high-level diagram of an electronic device 100 according to one embodiment. Device 100 may include one or more physical buttons, such as a "home" button or a menu button 104. Menu button 104 is used, for example, to navigate to any application in a set of applications running on device 100. In some embodiments, menu button 104 includes a fingerprint sensor for recognizing a fingerprint on menu button 104. The fingerprint sensor can be used to determine whether the finger on menu button 104 has a fingerprint that matches a fingerprint stored for unlocking device 100. Alternatively, in some embodiments, menu button 104 is implemented as a soft key in a graphical user interface (GUI) displayed on a touchscreen.

[0020] In some embodiments, device 100 includes a touchscreen 150, a menu button 104, a push-button 106 for powering the device on / off and for locking the device, a volume control button 108, a subscriber identity module (SIM) card slot 110, a headset jack 112, and a docking / charging external port 124. The push-button 106 can be used to power the device on / off by pressing the button and holding it in the pressed state for a predefined time interval; to lock the device by pressing the button and releasing it before the predefined time interval has elapsed; and / or to unlock the device or initiate an unlocking process. In an alternative embodiment, device 100 also accepts voice input via microphone 113 for activating or deactivating certain functions. Device 100 includes various components, including but not limited to memory (which may include one or more computer-readable storage media), a memory controller, one or more central processing units (CPUs), peripheral interfaces, RF circuitry, audio circuitry, a speaker 111, a microphone 113, an input / output (I / O) subsystem, and other input or control devices. Device 100 may include one or more image sensors 164, one or more proximity sensors 166, and one or more accelerometers 168. Device 100 may include more than one type of image sensor 164. Each type may include more than one image sensor 164. For example, one type of image sensor 164 may be a camera, and another type of image sensor 164 may be an infrared sensor for facial recognition performed by one or more machine learning models stored in device 100. Device 100 may include Figure 1 Components not shown include, for example, an ambient light sensor, a dot projector, and a floodlight illuminator for supporting facial recognition.

[0021] Device 100 is merely one example of an electronic device, and device 100 may have more or fewer components than those listed above, some of which may be combined into a single component or have different configurations or arrangements. The various components of device 100 listed above are embodied in hardware, software, firmware, or combinations thereof, including one or more signal processing and / or application-specific integrated circuits (ASICs).

[0022] Figure 2 This is a block diagram illustrating components in device 100 according to one embodiment. Device 100 is capable of performing various operations, including implementing one or more machine learning models. For this and other purposes, device 100 may include an image sensor 202, a system-on-a-chip (SOC) component 204, system memory 230, permanent memory (e.g., flash memory) 228, a motion sensor 234, and a display 216, among other components. Figure 2 The components shown are merely illustrative. For example, device 100 may include... Figure 2 Other components not shown (such as speakers or microphones). Additionally, some components (such as motion sensor 234) may be omitted from device 100.

[0023] Image sensor 202 is a component for capturing image data and can be implemented as, for example, a complementary metal-oxide-semiconductor (CMOS) active pixel sensor, camera, camcorder, or other device. Image sensor 202 generates raw image data, which is sent to SOC component 204 for further processing. In some embodiments, the image data processed by SOC component 204 is displayed on display 216, stored in system memory 230, permanent memory 228, or transmitted to a remote computing device via a network connection. The raw image data generated by image sensor 202 may be a Bayer color kernel array (CFA) pattern.

[0024] Motion sensor 234 is a component or set of components used to sense the motion of device 100. Motion sensor 234 can generate sensor signals indicating the orientation and / or acceleration of device 100. The sensor signals are sent to SOC component 204 for various operations, such as turning on device 100 or rotating an image displayed on display 216.

[0025] Display 216 is a component for displaying images generated by SOC component 204. Display 216 may include, for example, a liquid crystal display (LCD) device or an organic light-emitting diode (OLED) device. Based on data received from SOC component 204, display 216 may display various images, such as menus, selected operating parameters, images captured by image sensor 202 and processed by SOC component 204, and / or other information (not shown) received from the user interface of device 100.

[0026] System memory 230 is a component used to store instructions executed by SOC component 204 and to store data processed by SOC component 204. System memory 230 can be embodied in any type of memory, including, for example, dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) RAMBUS DRAM (RDRAM), static RAM (SRAM), or combinations thereof.

[0027] Persistent memory 228 is a component used to store data in a non-volatile manner. Even when power is unavailable, persistent memory 228 retains the data. Persistent memory 228 may be embodied as read-only memory (ROM), flash memory, or other non-volatile random access memory devices. Persistent memory 228 stores the operating system and various software applications of device 100. Persistent memory 228 may also store one or more machine learning models, such as regression models, random forest models, support vector machines (SVMs) such as kernel SVMs, and artificial neural networks (ANNs) such as convolutional networks (CNNs), recurrent networks (RNNs), autoencoders, and long short-term memory (LSTMs). Machine learning models can be standalone models that work with neural processor circuitry 218 and various software applications or sensors of device 100. Machine learning models can also be part of software applications. Machine learning models can perform various tasks, such as face recognition, image classification, object, concept and information classification, speech recognition, machine translation, voice recognition, voice command recognition, text recognition, text and context analysis, other natural language processing, prediction, and suggestion.

[0028] Various machine learning models stored in device 100 can be fully trained, untrained, or partially trained to allow device 100 to enhance or continue training the machine learning models as device 100 is used. The operation of the machine learning models includes various computations, such as training the model and using the model to determine runtime results. For example, in one scenario, device 100 captures a user's facial image and uses that image to further improve the machine learning model used to lock or unlock device 100.

[0029] SOC component 204 is embodied as one or more integrated circuit (IC) chips and performs various data processing procedures. SOC component 204 may include, among other sub-components, an image signal processor (ISP) 206, a central processing unit (CPU) 208, a network interface 210, a sensor interface 212, a display controller 214, a neural processor circuit 218, a graphics processor (GPU) 220, a memory controller 222, a video encoder 224, a memory controller 226, and a bus 232 connecting these sub-components. SOC component 204 may include... Figure 2 The sub-components shown have more or fewer sub-components.

[0030] ISP 206 is a circuit that performs each stage of the image processing pipeline. In some implementations, ISP 206 may receive raw image data from image sensor 202 and process the raw image data into a form available to other sub-components of SOC component 204 or components of device 100. ISP 206 may perform various image manipulation operations, such as image panning, horizontal and vertical scaling, color space conversion, and / or image stabilization transformations.

[0031] CPU 208 can be implemented using any suitable instruction set architecture and can be configured to execute instructions defined in that instruction set architecture. CPU 208 can be a general-purpose or embedded processor using any of a variety of instruction set architectures (ISAs), such as x86, PowerPC, SPARC, RISC, ARM, or MIPS ISA, or any other suitable ISA. Although Figure 2 A single CPU is shown, but SOC component 204 may include multiple CPUs. In a multiprocessor system, each CPU may collectively implement the same ISA, but this is not required.

[0032] The graphics processing unit (GPU) 220 is a graphics processing circuit for executing graphics data. For example, the GPU 220 may render objects to be displayed in a frame buffer (e.g., a frame buffer that includes pixel data for the entire frame). The GPU 220 may include one or more graphics processors that can execute graphics software to perform some or all of the graphics operations or hardware acceleration of some graphics operations.

[0033] Neural processor circuit 218 is a circuit that performs various machine learning operations based on computations including multiplication, addition, and accumulation. Such computations can be arranged, for example, to perform various types of tensor multiplication, such as tensor products and convolutions of input data and kernel data. Neural processor circuit 218 is a configurable circuit that performs these operations in a fast and efficient manner, while alleviating the resource-intensive operations associated with CPU 208 and neural network operations. Neural processor circuit 218 can receive input data from sensor interface 212, image signal processor 206, permanent memory 228, system memory 230, or other sources such as network interface 210 or GPU 220. The output of neural processor circuit 218 can be provided to various components of device 100, such as image signal processor 206, system memory 230, or CPU 208, for various operations. The structure and operation of neural processor circuit 218 are referenced below. Figure 3 Detailed description.

[0034] Network interface 210 is a sub-component that supports the exchange of data between device 100 and other devices via one or more networks (e.g., carrier or proxy devices). For example, video or other image data may be received from other devices via network interface 210 and stored in system memory 230 for subsequent processing (e.g., via a back-end interface to image signal processor 206) and display. Networks may include, but are not limited to, local area networks (LANs) (e.g., Ethernet or corporate networks) and wide area networks (WANs). Image data received via network interface 210 may be processed by ISP 206.

[0035] Sensor interface 212 is a circuit used to communicate with motion sensor 234. Sensor interface 212 receives sensor information from motion sensor 234 and processes the sensor information to determine the orientation or movement of device 100.

[0036] Display controller 214 is a circuit used to send image data to be displayed on display 216. Display controller 214 receives image data from ISP 206, CPU 208, graphics processor or system memory 230, and processes the image data into a format suitable for display on display 216.

[0037] The memory controller 222 is circuitry for communicating with the system memory 230. The memory controller 222 can read data from the system memory 230 for processing by the ISP 206, CPU 208, GPU 220, or other sub-components of the SOC component 204. The memory controller 222 can also write data to the system memory 230 received from various sub-components of the SOC component 204.

[0038] The video encoder 224 is hardware, software, firmware, or a combination thereof used to encode video data into a format suitable for storage in permanent memory 128, or to pass data to network interface 210 for transmission over a network to another device.

[0039] In some implementations, one or more sub-components of SOC component 204, or some functions of these sub-components, may be executed by software components that run on neural processor circuitry 218, ISP 206, CPU 208, or GPU 220. Such software components may be stored in system memory 230, permanent memory 228, or in another device that communicates with device 100 via network interface 210.

[0040] Example Neural Processor Circuit

[0041] The neural processor circuit 218 is a programmable circuit that performs machine learning operations on the input data of the neural processor circuit 218. The machine learning operations may include different computations for training a machine learning model and for performing inference or prediction based on the trained machine learning model.

[0042] Taking a CNN as an example of a machine learning model, CNN training can include forward propagation and backward propagation. A neural network can include an input layer, an output layer, and one or more intermediate layers, which may be called hidden layers. Each layer can include one or more nodes, which may be fully or partially connected to other nodes in adjacent layers. In forward propagation, the neural network performs computations in the forward direction based on the output of the previous layer. The operations of a node can be defined by one or more functions. Functions defining node operations can include various computational operations, such as data convolution using one or more kernels, layer pooling, tensor multiplication, etc. Functions can also include activation functions that adjust the weights of the node's output. Nodes in different layers can be associated with different functions. For example, a CNN may include one or more convolutional layers mixed with pooling layers and followed by one or more fully connected layers.

[0043] Each function (including the kernel) in a machine learning model can be associated with different coefficients that can be adjusted during training. Additionally, individual nodes in a neural network can also be associated with activation functions that determine the weights of the node's output during forward propagation. Common activation functions include step functions, linear functions, sigmoid functions, hyperbolic tangent functions (tanh), and rectified linear unit functions (ReLU). After a batch of training sample data passes through the neural network in forward propagation, the result is compared to the training labels of the training samples to calculate the network's loss function, which represents the network's performance. Furthermore, the neural network performs backpropagation by adjusting the coefficients in the individual functions using coordinate descent techniques such as stochastic coordinate descent (SGD) to improve the value of the loss function.

[0044] During training, device 100 may use neural processor circuitry 218 to perform all or some of the operations in forward and backward propagation. Multiple rounds of forward and backward propagation may be performed by neural processor circuitry 218 alone or in coordination with other processors such as CPU 208, GPU 220, and ISP 206. Training may be completed when the loss function no longer improves (e.g., the machine learning model has converged) or after a predetermined number of rounds for a specific training sample. While using device 100, it may continue to collect additional training samples for the neural network.

[0045] To make predictions or inferences, device 100 may receive one or more input samples. Neural processor circuitry 218 may take the input samples and perform forward propagation to determine one or more results. Input samples may be images, speech, text files, sensor data, or other data.

[0046] In machine learning, data and functions (e.g., input data, kernels, functions, layer outputs, gradient data) can be stored and represented by one or more tensors. Common operations related to the training and runtime of machine learning models can include tensor product, tensor transpose, element-wise tensor operations, convolution, application of activation functions, automatic differentiation to determine gradients of values ​​in tensors, statistics and aggregations (e.g., mean, variance, standard deviation), tensor rank and size manipulation, etc.

[0047] While the training and runtime of neural networks have been discussed as examples, the neural processor circuit 218 can also be used to operate other types of machine learning models, such as kernel SVMs.

[0048] See Figure 3 The exemplary neural processor circuitry 218 may include, among other components, a neural task manager 310, a plurality of neural engines 314A to 314N (collectively referred to below as "a plurality of neural engines 314" and also individually as "neural engine 314"), kernel direct memory access (DMA) 324, data processor circuitry 318, data processor DMA 320, and planar engine 340. The neural processor circuitry 218 may include fewer components or Figure 3 Additional components not shown.

[0049] Each neural engine in neural engine 314 performs machine learning computational operations in parallel. Depending on the workload, the entire group of neural engines 314 may be operating, or only a subset of neural engines 314 may be operating, while the remaining neural engines 314 are placed in a power-saving mode to conserve power. Each neural engine in neural engine 314 includes components for storing one or more kernels, for performing multiplication and accumulation operations, and for post-processing to generate output data 328, as described below. Figure 4 Detailed description. The Neural Engine 314 is specifically designed to perform computationally intensive operations, such as convolution and tensor product operations. Convolution operations can include different types of convolution, such as cross-channel convolution (convolution that sums values ​​from different channels), communication-by-communication convolution, and transposed convolution.

[0050] Planar engine 340 can specialize in performing simpler computational operations, and its speed may depend primarily on the input and output (I / O) speed of data transfer rather than the computational speed within planar engine 340. These computational operations may be referred to as I / O-constrained computations. In contrast, neural engine 314 can focus on complex computations, and its speed may depend primarily on the computational speed within each neural engine 314. For example, planar engine 340 is efficient for performing operations within a single channel, while neural engine 314 is efficient for performing operations across multiple channels that may involve heavy data accumulation. Computations using neural engine 314 to perform I / O-constrained computations cannot be efficient in both speed and power consumption. In one implementation, the input data may be a tensor with a rank greater than three (e.g., having three or more dimensions). One set of dimensions (two or more) in the tensor may be referred to as a plane, and another dimension as a channel. Neural engine 314 may utilize kernels to convolve the plane data in the tensor and accumulate the results of different plane convolutions across different channels. On the other hand, planar engine 340 can specialize in in-plane operations.

[0051] The circuitry of the planar engine 340 can be programmed to operate in one of several modes, including pooling mode, element-wise mode, and shrinking mode. In pooling mode, the planar engine 340 shrinks the spatial size of the input data. In element-wise mode, the planar engine 340 generates the output derived from element-wise operations on one or more inputs. In shrinking mode, the planar engine 340 shrinks the rank of a tensor. For example, a rank-5 tensor can be shrunk to a rank-2 tensor, or a rank-3 tensor can be shrunk to a rank-0 tensor (e.g., a scalar). See below for reference. Figure 5 The operation of the planar engine 340 will be discussed in further detail.

[0052] The neural task manager 310 manages the overall operation of the neural processor circuitry 218. The neural task manager 310 may receive a list of tasks from a compiler executed by the CPU 208, store tasks in its task queue, select tasks to be executed, and send task commands to other components of the neural processor circuitry 218 for executing the selected tasks. Data may be associated with task commands indicating the type of operation to be performed on the data. The data of the neural processor circuitry 218 includes input data transferred from another source, such as system memory 230, and data generated by the neural processor circuitry 218 in previous operating cycles. Each dataset may be associated with a task command specifying the type of operation to be performed on the data. The neural task manager 310 may also perform task switching upon detecting events such as receiving instructions from the CPU 208. In one or more embodiments, the neural task manager 310 sends raster information to components of the neural processor circuitry 218 to enable each of these components to track, retrieve, or process appropriate portions of the input data and kernel data. For example, the neural task manager 310 may include registers storing information about the size and rank of the datasets for processing by the neural processor circuitry 218. Although in Figure 3 The neural task manager 310 is shown as part of the neural processor circuitry 218, but the neural task manager 310 may be a component external to the neural processor circuitry 218.

[0053] Kernel DMA 324 is a read circuit that retrieves kernel data from a source (e.g., system memory 230) and sends kernel data 326A to 326N to each neural engine in neural engine 314. Kernel data represents information from which kernel elements can be extracted. In one embodiment, the kernel data may be a compressed format that is decompressed at each neural engine in neural engine 314. Although in some cases the kernel data provided to each neural engine in neural engine 314 may be the same, in most cases the kernel data provided to each neural engine in neural engine 314 is different. In one embodiment, the direct memory access nature of kernel DMA 324 allows kernel DMA 324 to directly retrieve and write data from the source without the involvement of CPU 208.

[0054] Data processor circuitry 318 manages the data flow and task performance of neural processor circuitry 218. Data processor circuitry 318 may include flow control circuitry 332 and buffer 334. Buffer 334 is a temporary storage device for storing data associated with the operation of neural processor circuitry 218 and planar engine 340, such as input data transferred from system memory 230 (e.g., data from a machine learning model) and other data generated within neural processor circuitry 218 or planar engine 340. The data stored in data processor circuitry 318 may include different subsets that are sent to various downstream components, such as neural engine 314 and planar engine 340.

[0055] In one embodiment, buffer 334 is implemented as a non-transitory memory accessible to neural engine 314 and planar engine 340. Buffer 334 may store input data 322A to 322N for feeding to corresponding neural engines 314A to 314N or planar engine 340, and output data 328A to 328N from each of neural engines 314A to 314N or planar engine 340 for feedback to one or more neural engines 314 or planar engine 340, or for transmission to target circuitry (e.g., system memory 230). Buffer 334 may also store input data 342 and output data 344 of planar engine 340, and allows data exchange between neural engine 314 and planar engine 340. For example, one or more output data 328A to 328N of neural engine 314 may be used as input 342 to planar engine 340. Similarly, the output 344 of planar engine 340 may be used as input data 322A to 322N of neural engine 314. The input to the neural engine 314 or the planar engine 340 can be any data stored in the buffer 334. For example, in each operation loop, the source dataset from which one of the engines draws input can be different. The input to an engine can be the output of the same engine in a previous loop, the output of a different engine, or any other suitable source dataset stored in the buffer 334. Furthermore, the dataset in the buffer 334 can be partitioned and sent to different engines for different operations in the next operation loop. Two datasets in the buffer 334 can also be combined for the next operation.

[0056] The flow control circuit 332 of the data processor circuit 318 controls the data exchange between the neural engine 314 and the planar engine 340. The operation of the data processor circuit 318 and other components of the neural processor circuit 218 is coordinated so that input data and intermediate data stored in the data processor circuit 318 can be reused across multiple operations at the neural engine 314 and the planar engine 340, thereby reducing the data transfer to and from the system memory 230. The flow control circuit 332 may perform one or more of the following operations: (i) monitor the size and rank of the data being processed by the neural engine 314 and the planar engine 340 (e.g., the data may be one or more tensors), (ii) determine which subsets of data are transmitted to the neural engine 314 or the planar engine 340 based on task commands associated with different subsets of data, (iii) determine the manner in which data is transmitted to the neural engine 314 and the planar engine 340 (e.g., the data processor circuit 318 may operate in a broadcast mode, in which the same data is fed to multiple input channels of the neural engine 314 such that multiple or all neural engines 314 receive the same data, or may operate in a unicast mode, in which different neural engines 314 receive different data), and (iv) transmit configuration commands to the planar engine 340 to instruct the planar engine 340 to program itself for operation in one of a number of operating modes.

[0057] The data stored in the buffer 334 of the neural processor circuit 218 may be a portion of image data, histograms of orientation gradient (HOG) data, audio data, metadata, output data 328 of the previous loop of the neural engine 314, and other processed data received from other components of the SOC component 204.

[0058] The data processor DMA 320 includes read circuitry that receives segments of input data from a source (e.g., system memory 230) for storage in a buffer 334, and write circuitry that forwards the data from the buffer 334 to a target component (e.g., system memory). In one embodiment, the direct memory access nature of the data processor DMA 320 allows the data processor DMA 320 to directly acquire and write data from a source (e.g., system memory 230) without the involvement of the CPU 208. The buffer 334 may be a direct memory access buffer that stores data of the machine learning model of device 100 without the involvement of the CPU 208.

[0059] Example Neural Engine Architecture

[0060] Figure 4This is a block diagram of a neural engine 314 according to one implementation. The neural engine 314 performs various operations to facilitate machine learning, such as convolution, tensor product, and other operations that may involve large computational loads. To this end, the neural engine 314 receives input data 322, performs a multiplication-accumulation operation (e.g., a convolution operation) on the input data 322 based on stored kernel data, performs further post-processing operations on the result of the multiplication-accumulation operation, and generates output data 328. The input data 322 and / or output data 328 of the neural engine 314 can be single-channel or span multiple channels.

[0061] The neural engine 314 may include, among other components, an input buffer circuit 402, a computational core 416, a neural engine (NE) control 418, a kernel extraction circuit 432, an accumulator 414, and an output circuit 424. The neural engine 314 may include... Figure 4 The fewer components shown or including Figure 4 Other components not shown.

[0062] Input buffer circuit 402 is a circuit that stores a subset of data received from a source when a subset of data for neural processor circuit 218 is received. The source may be data processor circuit 318, planar engine 340, or another suitable component. Input buffer circuit 402 sends an appropriate segment 408 of data for the current task or processing loop to computation core 416 for processing. Input buffer circuit 402 may include a shifter 410 that shifts the read position of input buffer circuit 402 to change the segment 408 of data sent to computation core 416. By changing the segment of input data provided to computation core 416 via shifting, neural engine 314 can perform multiplication and accumulation on different segments of input data based on a smaller number of read operations. In one or more embodiments, the data for neural processor circuit 218 includes differential convolution groups and / or input channel data.

[0063] Kernel extraction circuit 432 is a circuit that receives kernel data 326 from kernel DMA 324 and extracts kernel coefficients 422. In one embodiment, kernel extraction circuit 432 references a lookup table (LUT) and uses a mask to reconstruct the kernel from compressed kernel data 326 based on the LUT. The mask indicates the locations of unfilled zeros and the remaining locations of unfilled numbers in the reconstructed kernel. The kernel coefficients 422 of the reconstructed kernel are sent to compute core 416 to populate registers in the multiply-accumulate (MAD) circuitry of compute core 416. In other embodiments, kernel extraction circuit 432 receives kernel data in uncompressed format and determines the kernel coefficients without referencing a LUT or using a mask.

[0064] The computational core 416 is a programmable circuit that performs computational operations. For this purpose, the computational core 416 may include MAD circuits MAD0 to MADN and a post-processor 428. Each of the MAD circuits MAD0 to MADN may store an input value in a segment 408 of input data and a corresponding kernel coefficient in kernel coefficient 422. In each of the MAD circuits, the input value and the corresponding kernel coefficient are multiplied to generate a processed value 412.

[0065] Accumulator 414 is a memory circuit that receives and stores processed values ​​412 from the MAD circuit. The processed values ​​stored in accumulator 414 can be sent back as feedback information 419 for further multiplication and addition operations at the MAD circuit, or sent to post-processor 428 for post-processing. Accumulator 414, combined with the MAD circuit, forms multiplication accumulator (MAC) 404. In one or more embodiments, accumulator 414 may have sub-units, each of which sends data to a different part of neural engine 314. For example, during a processing cycle, data stored in a first sub-unit of accumulator 414 is sent to the MAC circuit, while data stored in a second sub-unit of accumulator 414 is sent to post-processor 428.

[0066] Postprocessor 428 is circuitry that performs further processing on the value 412 received from accumulator 414. Postprocessor 428 may perform operations including, but not limited to, applying linear functions (e.g., rectified linear unit (ReLU)), normalizing cross-correlation (NCC), combining the results of neural operations on 8-bit data into 16-bit data, and local response normalization (LRN). The result of such operations is output from postprocessor 428 as a processed value 417 to output circuitry 424. In some embodiments, processing at postprocessor 428 is bypassed. For example, data in accumulator 414 may be sent directly to output circuitry 414 for access by other components of neural processor circuitry 218.

[0067] The NE control 418 controls the operation of other components of the neural engine 314 based on the operating mode and parameters of the neural processor circuit 218. Depending on different operating modes (e.g., group convolution mode or non-group convolution mode) or parameters (e.g., the number of input channels and the number of output channels), the neural engine 314 can operate on different input data in different sequences, return different values ​​from the accumulator 414 to the MAC circuit, and perform different types of post-processing operations at the post-processor 428. To configure the components of the neural engine 314 to operate in a desired manner, the NE control 418 sends task commands, which can be included in the information 419, to the components of the neural engine 314. The NE control 418 may include a raster 430 that tracks the current task or processing loop being processed at the neural engine 314.

[0068] Input data is typically divided into smaller data slices for parallel processing across multiple neural engines 314 or between neural engine 314 and planar engine 340. A set of data used for convolution operations may be called a convolution group, which can be divided into multiple smaller units. The hierarchical structure of these smaller units (slices) can be convolution groups, slices, blocks, working units, output channel groups, input channels (Cin), sub-Cin for input strides, etc. For example, a convolution group can be divided into slices; slices can be divided into blocks; blocks can be divided into working units; and so on. In the context of neural engine 314, a working unit can be a slice of input data, such as data processed by planar engine 340 or data processed in a previous loop of neural engine 314, having a size that generates the output value of accumulator 414 suitable for neural engine 314 during a single loop of computation kernel 416. In one case, the size of each working unit is 256 bytes. In such implementations, for example, a working unit may be shaped into one of a 16×16, 32×8, 64×4, 128×2, or 256×1 dataset. In the context of the planar engine 340, a working unit may be (i) a fragment of input data, (ii) data from the neural engine 314, or (iii) data from a previous loop of the planar engine 340, which can be processed simultaneously at the planar engine 340.

[0069] Rasterizer 430 performs operations associated with dividing input data into smaller units (segments) and regulates the processing of these smaller units via MAC 404 and accumulator 414. Rasterizer 430 keeps track of the size and rank (e.g., group, working unit, input channel, output channel) of the input / output data segments and instructs components of neural processor circuitry 218 to correctly process the segments of input data. For example, rasterizer 430 operates shifter 410 in input buffer circuitry 402 to forward the correct segment 408 of input data to MAC 404 and send the completed output data 328 to data buffer 334. Other components of neural processor circuitry 218 (e.g., kernel DMA 324, buffer DMA 320, data buffer 334, planar engine 340) may also have corresponding rasterizers for monitoring the partitioning of input data and the parallel computation of individual segments of input data in different components.

[0070] The output circuit 424 receives the processed value 417 from the post-processor 428 and interacts with the data processor circuit 318 to store the processed value 417 in the data processor circuit 318. For this purpose, the output circuit 424 may issue output data 328 in an order or format different from the order or format in which the processed value 417 is processed in the post-processor 428.

[0071] Components in the Neural Engine 314 can be configured by the NE control 418 and the Neural Task Manager 310 during the configuration cycle. To this end, the Neural Task Manager 310 sends configuration information to the Neural Engine 314 during the configuration cycle. Configurable parameters and modes may include, but are not limited to, the mapping between input data elements and kernel elements, the number of input channels, the number of output channels, the execution of output strides, and enabling / selecting post-processing operations at the post-processor 428.

[0072] Exemplary plane engine

[0073] Figure 5This is a block diagram of a planar engine 340 according to one embodiment. The planar engine 340 is a separate circuit from the plurality of neural engines 314 and can be programmed to perform in different operating modes. For example, the planar engine 340 can operate in a pooling mode, a shrinking mode, a gain-biased mode, and an element-wise mode, where the pooling mode shrinks the spatial size of the data, the shrinking mode shrinks the rank of the tensor, the gain-biased mode provides a one-way addition of bias and scaling by a scaling factor, and the element-wise mode includes element-wise operations. For this purpose, the planar engine 340 may include, among other components, a first format converter 502, a first filter 506 (also referred to herein as a "multimode horizontal filter 506"), a line buffer 510, a second filter 514 (also referred to herein as a "multimode vertical filter 514"), a post-processor 518, a second format converter 522, and a planar engine (PE) control 530 (including a rasterizer 540). The planar engine 340 may include fewer components or may include... Figure 5 Other components not shown. Each component in the planar engine 340 may be implemented as a circuit or a circuit combined with firmware or software.

[0074] Input data 342 for the planar engine 340 can be obtained from one or more source datasets stored in the data processor circuitry 318. If the dataset to be processed by the planar engine 340 is larger than the working unit of data that the planar engine 340 can process simultaneously, such a dataset can be segmented into multiple working units for use as input data 342 to be read into the planar engine 340. Depending on the mode of the planar engine 340, the input data 342 may include data from one or more source datasets. The source datasets described herein refer to different data stored in the neural processor circuitry 218 for processing. Different components of the neural processor circuitry 218 can generate or transfer data stored in the data processor circuitry 318. For example, the neural engine 314, the planar engine 340 (which generated data in a previous operating loop), and the system memory 230 can generate or transfer different datasets stored in different memory locations of the data processor circuitry 318. Each source dataset can represent a different tensor. During the operating loop of the planar engine 340, different source datasets can be obtained together as input data 342. For example, in element-wise mode involving the addition of two different tensors to derive the tensor, input data 342 may include data from two different source datasets, each providing a separate tensor. In other modes, a single source dataset may provide input data 342. For example, in pooling mode, input data 342 may be obtained from a single source dataset.

[0075] The first format converter 502 is a circuit that performs one or more format conversions on input data 342 in one format (e.g., a format for use in the buffer 334) to another form for processing in subsequent parts of the planar engine 340. Such format conversions may include, etc., applying a ReLU function to one or more values ​​of input data 342, converting one or more values ​​of input data 342 to their absolute values, transposing a tensor included in the source, applying a gain to one or more values ​​of input data 342, biasing one or more values ​​of input data 342, normalizing or denormalizing one or more values ​​of input data 342, converting floating-point numbers to signed or unsigned numbers (or vice versa), logarithmicizing, and changing the size of a tensor, such as by broadcasting the tensor's values ​​in one or more dimensions to expand the tensor's rank. The converted input data 342 and the unconverted input data 342 to the planar engine 340 are collectively referred to herein as "versions of input data".

[0076] The first filter 506 is a circuit that performs a filtering operation in one direction. For this purpose, the first filter 506 may include an adder, a comparator, and a multiplier, among other components. The filtering performed by the first filter 506 may be, for example, averaging, selecting a maximum value, or selecting a minimum value. When averaging, an adder is used to sum the values ​​of the input data 342, and a weighting factor may be applied to the sum using a multiplier to obtain an average value. When selecting a maximum or minimum value, a comparator may be used instead of an adder and a multiplier to select the value.

[0077] Row buffer 510 is a memory circuit for storing results, such as one or more intermediate data obtained from the first filter 506 or the second filter 514. Row buffer 510 can store values ​​from different rows and allows access from the second filter 514 or other downstream components to obtain intermediate data for further processing. In some modes, row buffer 510 is bypassed. Row buffer 510 may also include logic circuitry for performing additional operations beyond simply storing intermediate data. For example, row buffer 510 includes adder circuitry 512, which, combined with memory components, enables row buffer 510 to act as an accumulator that aggregates data generated from the results of the first filter 506 or the second filter 514 to store aggregated data in a separate, non-reduced dimension.

[0078] Similar to the first filter 506, the second filter 514 performs a filtering operation, but in a different direction than the first filter 506. For this purpose, the second filter 514 may include adders, comparators, and multipliers, among other components. In pooling mode, the first filter 506 performs the filtering operation in the first dimension, while the second filter 514 performs the filtering operation in the second dimension. In other modes, the first filter 506 and the second filter 514 may operate differently. In reduction mode, for example, the second filter 514 performs an element-wise operation, while the first filter 506 acts as a reduction tree to aggregate data values.

[0079] Postprocessor 518 is circuitry that performs further processing on values ​​obtained from other upstream components. Postprocessor 518 may include dedicated circuitry that is efficient for performing certain types of mathematical calculations that might be inefficient using general-purpose computing circuitry. The operations performed by postprocessor 518 may include, among others, performing square root operations and reciprocals of values ​​in reduction mode. Postprocessor 518 may be bypassed in other operating modes.

[0080] The second format converter 522 is circuitry that converts the results of previous components in the planar engine 340 from one format to another format for output data 344. Such format conversions may include, for example, applying a ReLU function to the results, transposing the resulting tensor, normalizing or denormalizing one or more values ​​of the results, and other digital format conversions. Output data 344 may be stored in the data processor circuitry 318 as output of the neural processor circuitry 218 or as input to other components of the neural processor circuitry 218 (e.g., the neural engine 314).

[0081] The PE control 530 is a circuit that controls the operation of other components in the planar engine 340 based on the operating modes of the planar engine 340. Depending on the operating mode, the PE control 530 programs registers associated with different components in the planar engine 340, causing the programmed components to operate in a certain way. The pipeline of connections between components or between components in the planar engine 340 can also be reconfigured. In pooling mode, for example, data processed by the first filter 506 can be stored in the row buffer 510 and then read by the second filter 514 for further filtering. However, in reduction mode, the data is processed by the second filter 514, reduced at the first filter 506, and then accumulated in the row buffer 510, which is programmed as an accumulator. In element-wise mode, the row buffer 510 can be bypassed.

[0082] The PE control 530 also includes a rasterizer 540 that tracks the current task or processing loop being processed at the planar engine 340. The rasterizer 540 is circuitry that tracks units or segments of input data and / or loops used to process input data in the planar engine 340. The rasterizer 540 controls the acquisition of segments to the planar engine 340 in each operating cycle and monitors the size and rank of each segment processed by the planar engine 340. For example, smaller segments of the dataset may be acquired as input data 342 in rasterizer order for processing at the planar engine 340 until all segments of the source dataset have been processed. While acquiring segments, the rasterizer 540 monitors the coordinates of the segments in the dataset. The way the dataset is segmented into input data 342 for processing at the planar engine 340 can be different from how the dataset is segmented into input data 328 for processing at the neural engine 314.

[0083] The dataset to be processed at the planar engine 340 may be larger than the capacity of the planar engine 340, which can process data in a single operation loop. In this case, the planar engine 340 acquires different segments of the dataset as input data 342 in multiple operation loops. The acquired segments may partially overlap with previously acquired segments and / or the next segment to be acquired. In one embodiment, portions of the overlapping data are acquired only once and reused to reduce the time and power consumption costs of the planar engine 340 in acquiring data.

[0084] Figure 6A , Figure 6B and Figure 6C This is a conceptual diagram illustrating the operation of different example modes of the planar engine 340 according to the implementation scheme. Two-dimensional 5x5 input data 342 (e.g., a rank-2 tensor) is shown for illustrative purposes only. The input data 342 can have any suitable size and rank. The input data 342 can be data stored in a buffer 334 of the data processor circuitry 318. For example, in some cases, the data stored in the buffer 334 acquired as input data 342 is the output of the neural engine 314. In other cases, the data stored in the buffer 334 acquired as input data 342 can be the output of the planar engine 340 in a previous loop. In still other cases, the data acquired and stored in the buffer 334 can be a fragment of data received from the system memory 230.

[0085] Exemplary pooling patterns

[0086] exist Figure 6AIn the pooling operation shown, the planar engine 340 reduces the spatial size of the input data 342 to generate the output. The pooling operation can depend on the filter size, stride factor, and type of filtering operation. The filter size determines the size of the filter applied in the pooling operation. Figure 6A The example is filter 610, which has a size of 3×3, but other sizes such as 5×5, 7×7 and 9×9 filters can be used. Figure 6A A stride factor of 2 is also illustrated, which causes the center of filter 610 to skip one pixel in both the horizontal and vertical directions. Based on a 3×3 filter with a stride factor of 2, the spatial size of the 5×5 input data will be reduced to 2×2 output data because the center of filter 610 will only cover four pixels of the 5×5 input data.

[0087] The filtering types performed by the planar engine 340 in pooling mode may include averaging, selecting the maximum value, and selecting the minimum value. In averaging, the values ​​of the pixels covered by the filter are averaged. The first filter circuit 506 and the second filter circuit 514 include adders and multipliers to perform the averaging operation. In one embodiment, the pixel values ​​(or a horizontal or vertical subset) covered by the filter may first be added by adders, and then a reduction factor may be applied using multipliers to achieve averaging. The reduction factor may correspond to the size of the filter. For example, for a 3×3 filter, the reduction factor for each dimension may be 1 / 3.

[0088] In the operation of selecting the maximum or minimum value, the adders and multipliers in the first filter circuit 506 and the second filter circuit 514 can be bypassed. Instead, the comparators in the first filter circuit 506 and the second filter circuit 514 are used to select the maximum or minimum value among the values ​​of the input data covered by the filter.

[0089] To reduce the amount of redundant calculations, the filtering operation for the input data versions can be performed separately by the first filter 506 and the second filter 514. Figure 6A As an example, a first filter of size 1×3 can be applied horizontally first to reduce the first dimension and generate intermediate data. For example, after applying the horizontal filter, the size of the intermediate data could be 5×2. The intermediate data is then stored in a row buffer 510 for use in sending to a vertical filter 514. Next, a second filter 514 applies a vertical filter of size 3×1 to further reduce the second dimension of the intermediate data. The second filter 514 may include one or more multipliers for applying weighting factors to the calculated values ​​when performing an averaging. Although the terms "horizontal" and "vertical" are used, the first dimension and the second dimension can each represent either of two different dimensions in the dataset, such as a tensor.

[0090] In pooling mode, the post-processor 518 can be bypassed. The second format converter 522 can perform the functions described in the reference above. Figure 5 The described format conversions (one or more).

[0091] Exemplary element-by-element pattern

[0092] exist Figure 6B In the element-wise mode shown, one or both of the first filter 506 and the second filter 514 can be used to perform one or more element-wise operations, while the line buffer 510 and the post-processor 518 can be bypassed. In element-wise mode, the planar engine 340 performs element-wise operations on the input data.

[0093] If the input data 342 in element-wise mode is received from a single source dataset, the operation is called a unary operation. For example, the planar engine 340 may obtain only a fragment of a single tensor from the data processor circuitry 318. In an exemplary unary operation, each value in the input data 342 may be squared to produce an output. If the input data 342 is received from two source datasets (e.g., from two datasets stored in the data processor circuitry 318), the operation used to combine the two source datasets is called a binary operation. If two tensors are added, the addition operation is a binary operation because the input data 342 includes values ​​representing the two tensors from the two source datasets. In one embodiment, the planar engine 340 may support up to ternary operations in one operation loop.

[0094] In element-wise mode, the first format converter 502 can perform various tasks, including but not limited to transposing one or more input tensors (e.g., width-to-channel transpose), broadcasting the values ​​of input tensors to expand the size and rank of the input tensors, and performing other format conversions on the input data 342. Transposing input tensors can be advantageous, among other reasons, because it allows per-channel gain or bias to be stored in a vector format. This can be more efficient in terms of hardware footprint, bandwidth, and operational performance for element-wise operations. Broadcasting values ​​can be performed to expand the size of the input data 342 in one or more dimensions by copying the values ​​of the tensors in one or more dimensions. For example, the first format converter 502 can copy the data values ​​of a column vector (a vector with a size equal to 1 in one dimension) to expand that size to another dimension. When the input data 342 includes two tensors from two sources, the values ​​of one or both of the tensors can be broadcast such that the sizes and ranks of the two tensors are matched for downstream element-wise operations.

[0095] One or both of the first filter 506 and the second filter 514 can be reconfigured to perform element-wise operations. In a binary operation involving two sources, the data values ​​of the two sources can first be interleaved (e.g., A1, B1, A2, B2, etc., where A...).i and B i These are data values ​​from these two sources, respectively. For example... Figure 6B As shown, the value 620 of the first source is combined with the corresponding value 630 of the second source to generate the value 640. The first filter 506 and the second filter 514 perform this operation element by element.

[0096] The planar engine 340 supports different types of element-wise operations, including but not limited to addition, subtraction, element-wise maximization (e.g., comparing values ​​620 and 630), element-wise minimization, element-wise multiplication, and element-wise summation followed by squaring. The adders in filters 506 and 514 can be configured to operate in parallel with each other, where data values ​​from two sources are interleaved and passed through the adders to produce an element-wise result. If the element-wise operation is element-wise multiplication, element-wise maximization, or element-wise minimization, the multipliers or digital comparators in filters 506 and 514 can be configured to perform the element-wise operation on the interleaved data values. In binary element-wise mode, two tensors are combined to generate an output tensor as a version of output 344.

[0097] In element-wise mode, the function and operation of the second format converter 522 are essentially the same as those in pooling mode, except that transpose can be applied to the output 344 at the second format converter 522. The transpose at the second format converter 522 may or may not be related to the transpose operation at the first format converter 502. For example, in one case, a reverse transpose can be applied to the output 344 at the second format converter 522 for a transposed tensor, but in another case, a transpose can be applied at the second format converter 522 that is independent of how the tensor was transposed at the first format converter 502. Similarly, a transpose can be applied to the output 344 at the second format converter 522 even if no transpose is applied at the first format converter 502.

[0098] Exemplary ternary pattern

[0099] Ternary mode is a specific type of element-wise operation that performs element-wise operations on three source tensors within an operation loop. Ternary mode can be used to perform element-wise per-channel gain-bias operations within an operation loop. In ternary mode, three source datasets are acquired from data processor circuitry 318. The tensor to be gained and biased is the first source dataset. The scaling factor used for the gain is the second source dataset. The bias value is the third source dataset. When acquiring the source datasets, planar engine 340 acquires the first source dataset as the first tensor, as part of input data 342. Planar engine 340 acquires the second and third source datasets together as the second tensor, as another part of input data 342. For example, the values ​​from the second and third sources can be arranged in the dimensions of the second tensor (e.g., an unused dimension). The index position of a value in that dimension can identify whether it comes from the second or third source.

[0100] In ternary mode, the first format converter 502 can perform various format conversion tasks discussed above in the element-by-element mode. In ternary mode, the first filter 506 and the second filter 514 can also perform element-by-element operations in a manner similar to that described above in the element-by-element mode, except that each filter can perform element-by-element operations on a different set of values. For example, the first filter 506 can perform element-by-element operations between a first tensor stored in input data 342 and a set of bias values ​​stored in input data 342 as a first part of a second tensor. The second filter 514 can perform element-by-element operations between a first tensor stored in input data 342 and a set of scaling factors stored in input data 342 as a second part of a second tensor.

[0101] Exemplary reduction mode

[0102] exist Figure 6C In the reduction mode shown, the planar engine 340 can perform a rank reduction operation on the tensor. After processing, the planar engine 340 provides an output representing the reduced tensor. For example, in one case, a rank 5 tensor can be reduced to a rank 2 tensor. In another case, a rank 3 tensor can be reduced to a rank 1 tensor (e.g., a vector). The planar engine 340 can support different types of reduction, including average, global maximum (e.g., the highest value in the tensor), and global minimum.

[0103] In reduction mode, the planar engine 340 aggregates the values ​​in the dimensions that need to be reduced to generate an aggregated value, while maintaining the size of the dimensions that do not need to be reduced. This aggregated value can be a scalar value. In this context, a scalar value can encompass scalars (e.g., a rank-0 tensor) and tensors with a size of 1 in all dimensions. For ease of reference, the dimensions to be reduced can be referred to as width and height, while the dimensions not to be reduced can be referred to as channels. However, the names of the dimensions are for illustrative purposes only. In various reduction operations, the dimensions to be reduced can be different, and the number of dimensions to be reduced can also be different (e.g., in one case, one dimension is reduced while the size of the other two dimensions is maintained). Moreover, in some cases, all dimensions of the tensor can be reduced.

[0104] In reduction mode, the tensor to be reduced can be larger than the working unit, which corresponds to the capacity of the planar engine 340 in an operation loop. The planar engine 340 performs reduction operations in multiple operation loops and stores intermediate values ​​corresponding to different channel locations in the line buffer 510. In reduction mode, the planar engine 340 can be programmed as a sequence of a second filter 514, a first filter 506, a line buffer 510, and a post-processor 518. For each operation loop, the second filter 514 can perform an element-wise operation to at least adjust a subset of the values ​​in the working unit acquired as input 342. This subset of values ​​can correspond to the width and height values ​​in the working unit. For each operation loop, the first filter 506 acts as a reduction tree operation, which reduces the values ​​in the subset to an aggregated value. The planar engine 340 may include registers (e.g., positioned as part of the first filter 506) for accumulating the aggregated values ​​corresponding to different working units of the same channel to generate a single aggregated value. The line buffer 510 includes memory locations for separately storing the aggregated values ​​of different channels because the channel dimensions are not reduced. For example, in Figure 6C In the middle, because there are three channels, three separate aggregate values ​​are stored in row buffer 510.

[0105] In one implementation, the operation and functions of the first format converter 502 in reduction mode are similar to those described above with reference to the pooling mode, except that the first format converter 502 in reduction mode can obtain data from a second source dataset. The data from the second source can be used at the first filter 506 in element-wise mode, such as for subtraction.

[0106] To perform certain types of reduction, such as determining variance or standard deviation, one of the first filter 506 or the second filter 514 can operate in the same manner as in element-wise mode. In one embodiment, one of the two filters 506 and 514 may include additional multiplier circuitry for performing averaging in pooling mode. Filters with additional multiplier circuitry can be used for element-wise operations. For example, in one embodiment, the second filter 514 can be used to perform element-wise operations. If the reduction involves subtraction (e.g., in determining variance or standard deviation), a binary element-wise operation corresponding to subtraction can be performed by the second filter 514. For other types of reduction, no element-wise operation is performed on the values ​​of the input data, and the second filter 514 can be bypassed.

[0107] The first filter 506 serves as a reduction tree to aggregate values ​​in a version of the input data 342 to reduce those values ​​to a single value. In one embodiment, using the first filter 506 instead of the second filter 514 as the reduction tree reduces the number of paths that need to be connected to the row buffer 510, since the row buffer 510 is also programmed to receive values ​​from the first filter 506 in pooling mode. However, in another embodiment, the roles of the first filter 506 and the second filter 514 are interchangeable in reduction mode. The reduction tree may include multiple layers of computational units that progressively aggregate values ​​in or derived from the input data 342. Different computational units in the first filter 506 may be used depending on the type of reduction operation. For example, if the reduction operation is to determine the mean, variance, or standard deviation of values ​​in a tensor, an adder may be the computational unit used. If the reduction operation is to determine a maximum or minimum value, a comparator may be the computational unit used. The input layer of the reduction tree may include the maximum number of computational units, and the number of computational units in each subsequent layer progressively decreases. For example, if each work unit includes 64 data values, the input layer may include 32 computation units, the second layer may include half that number of computation units (e.g., 16 units), the third layer may have a further reduced number of computation units (e.g., 8 units), and so on. The shrinking tree continues to aggregate values ​​until a single computation unit is reached at the output layer to compute a single value.

[0108] In reduction mode, row buffer 510 is downstream of the first filter 506 and the second filter 514. For this purpose, row buffer 510 may include adder 512. In some cases, the tensor to be reduced may include multiple source datasets stored in buffer 334. For example, the tensor may be large enough that it is segmented into multiple source datasets in buffer 334. The source datasets may also be referred to as “patches”. Each patch includes multiple channels, and a subset of data in a single channel of a patch includes multiple working units. Since values ​​across different channels are not further reduced, row buffer 510 uses adder 512 to accumulate the aggregated value per channel in different memory locations of row buffer 510. For example, if the tensor has N channels, N memory locations are used to store the reduced values ​​of the N channels. The channel values ​​may be stored across different patches, and row buffer 510 accumulates the values ​​in different patches in its memory locations. The reduced tensor may be a vector that maintains the size of the channels. For example, in Figure 6C In this process, each plane, including its width and height, is reduced to a single value, but the values ​​across different channels are processed separately.

[0109] During reduction, post-processor 518 may perform certain mathematical calculations that might be inefficient using general computing circuitry. Such operations may involve determining the square root of a value. For this purpose, post-processor 518 may include circuitry for calculating the square root of a floating-point number. Post-processor 518 may also include circuitry for performing an inversion of a number in a format with higher precision than the format of output 344. In another example, post-processor 518 may include a multiplier for scaling accumulated values ​​to generate an average. Post-processor 518 may include additional circuitry for performing various operations associated with the reduction operation.

[0110] The operations and functions of the second format converter 522 in the reduction mode are similar to those described above in the reference pooling mode, except that the aggregated values ​​can be repeated along one or more dimensions and the resulting reduced tensor can be shaped. For example, the reduced tensor can be shaped into another tensor with a different size or rank. The output 344 can be a scalar value, a reduced tensor, or a shaped reduced tensor.

[0111] Exemplary process of operating a neural processor

[0112] Figure 7This is a flowchart depicting an exemplary process of operating neural processor circuitry 218 according to an embodiment. Data processor circuitry 318 transmits 710 first input data to at least one of neural engine circuitry 314. The first input data may include values ​​from multiple channels. The first input data may be an input to neural processor circuitry 218 derived from a machine learning model instantiated and stored in system memory 230. The first input data may also be the output of neural engine 314 or planar engine 340 from a previous operating loop.

[0113] At neural engine circuit 314, a 720 convolution operation is performed on the first input data with one or more kernels to generate a first output. In some cases, the same first input data may be transmitted to more than one neural engine circuit 314. In other cases, each neural engine circuit 314 receives different first input data. For each neural engine circuit 314, the kernel may be the same or different.

[0114] The second input data is sent 730 from the data processor circuit 318 to the planar engine circuit 340. In response, the planar engine circuit 340 generates a second output 740 from the second input data. The input data of the planar engine circuit 340 may correspond to a first output from the neural engine circuit 314 or a processed version of the input data from the neural processor circuit 218.

[0115] The process of generating input data for the 740-dimensional planar engine circuit 340 can vary depending on the operating mode of the planar engine circuit 340. In pooling mode, the planar engine circuit 340 reduces the spatial size of a version of the 740A input data. For example, the planar engine circuit 340 includes a first filter circuit, a second filter circuit, and a row buffer circuit. Using the first filter circuit, the planar engine circuit 340 reduces the size of the input data in the first dimension to generate intermediate data. The intermediate data can be stored at the row buffer circuit for later transmission to the second filter circuit. Using the second filter circuit, the planar engine circuit 340 reduces the size of the intermediate data in the second dimension to generate the output.

[0116] In element-wise mode, the planar engine circuit 340 performs a 740B element-wise operation on its input data. For example, at least the first or second filter circuit performs the element-wise operation. The planar engine circuit can also perform in other modes, such as a reduction mode. In reduction mode, the planar engine reduces the rank of the tensor.

[0117] Figure 7The exemplary process shown is merely one of the processes for operating neural processor circuitry 218. The engines in neural processor circuitry 218 can operate in any order. For example, in another process, the dataset may be processed by planar engine circuitry 340 before being processed by neural engine circuitry 314. In yet another process, the dataset may be processed repeatedly by the same type of engine.

[0118] While specific implementations and applications have been described and illustrated, it should be understood that the invention is not limited to the precise constructions and components disclosed herein, and that various modifications, alterations, and variations that will be apparent to those skilled in the art may be made to the arrangement, operation, and details of the methods and apparatus disclosed herein without departing from the spirit and scope of this disclosure.

Claims

1. A neural processor, comprising: Multiple neural engine circuits, each of which is configured to perform a convolution operation on a first input data with one or more kernels to generate a first output; as well as A planar engine circuit, coupled to and configured to operate in parallel with the plurality of neural engine circuits, is capable of operating in one of two or more modes to generate a second output, the two or more modes including a pooling mode and an element-wise mode. The planar engine circuit includes a programmable row buffer circuit, wherein the programmable row buffer circuit is configured to store intermediate results generated by the planar engine circuit in the pooling mode, wherein the planar engine circuit is configured to bypass the storage of results generated by the planar engine circuit in the element-wise mode within the programmable row buffer circuit, and wherein: In the pooling mode, the planar engine circuit is configured to reduce the spatial size of a version of the second input data received by the planar engine circuit, the second input data corresponding to a version of the first output or the input data of the neural processor, and In the element-wise mode, the planar engine circuit is configured to perform an element-wise operation on the second input data, which corresponds to the first output or a version of the input data of the neural processor. as well as A data processor circuit coupled to the plurality of neural engine circuits and the planar engine circuit, the data processor circuit being configured to buffer the second output for sending to the plurality of neural engine circuits.

2. The neural processor of claim 1, wherein the planar engine circuitry comprises: A first filter circuit, configured to reduce the first dimension of the first dimension of the second input data in the pooling mode to generate intermediate data, and A second filter circuit is configured to reduce the second dimension of the intermediate data to a second size in the pooling mode to generate the version of the second output.

3. The neural processor of claim 2, wherein the programmable row buffer circuit is coupled to the first filter circuit and the second filter circuit, and wherein the intermediate result is provided to the second filter circuit.

4. The neural processor of claim 2, wherein at least one of the first filter circuit or the second filter circuit is configured to perform the element-wise operation on the version of the second input data in the element-wise mode.

5. The neural processor of claim 2, wherein the planar engine circuitry further comprises a format converter coupled to the first filter circuitry, the format converter being configured to perform one or more format conversions on the second input data to generate the version of the second input data.

6. The neural processor of claim 1, wherein the convolution operation is one of a plurality of operations for implementing a machine learning model.

7. The neural processor of claim 1, wherein the plurality of modes includes a reduced mode, and wherein the planar engine circuitry is further configured to: In the reduction mode, the rank of the tensor based on the first input data is reduced.

8. The neural processor of claim 7, wherein the planar engine circuitry includes a filter circuitry configured to: Reduce the spatial size of the second input data received in the pooling mode. Execute one or more tensor versions of the element-wise operation in the element-wise mode, and A scalar value is generated in the reduced mode.

9. The neural processor of claim 1, wherein the first input data represents data across multiple channels, and the second input data represents data in one of the multiple channels.

10. The neural processor of claim 1, wherein the element-wise operation includes one or more of tensor addition, element-wise maximum value, element-wise minimum value, or element-wise multiplication.

11. The neural processor of claim 1, wherein the circuitry of the planar engine circuit is reconfigured when switching from the pooling mode to the element-wise mode.

12. A method for operating a neural processor, the method comprising: Transmitting first input data to at least one of the plurality of neural engine circuits of the neural processor; The first input data is convolved with one or more kernels using at least one of the plurality of neural engine circuits to generate a first output; A planar engine circuit that transmits second input data to the neural processor, the planar engine circuit being coupled to the plurality of neural engine circuits and configured to operate in parallel with the plurality of neural engine circuits, the planar engine circuit including a programmable row buffer circuit. A second output is generated from the second input data at the planar engine circuit, the planar engine circuit being capable of operating in one of two or more modes, the two or more modes including a pooling mode and an element-wise mode, wherein: In the pooling mode, the planar engine circuit is configured to reduce the spatial size of the version of the second input data and store the intermediate results generated by the planar engine circuit, the second input data corresponding to the version of the first output or the input data of the neural processor; and In the element-wise mode, the planar engine circuit is configured to perform an element-wise operation on the second input data and is configured to bypass the storage of the result generated in the element-wise mode in the programmable row buffer circuit, the second input data corresponding to the first output or a version of the input data of the neural processor; and The second output is buffered by a data processor circuit for transmission to the plurality of neural engine circuits, the data processor circuit being coupled to the plurality of neural engine circuits and the planar engine circuit.

13. The method of claim 12, wherein reducing the spatial size of the version of the second input data received by the planar engine circuit in the pooling mode comprises: The first filter circuit is used to reduce the first dimension of the first dimension of the second version of the second input data to generate intermediate data; as well as The second filter circuit is used to reduce the second dimension of the intermediate data to a second size to generate the version of the second output.

14. The method of claim 13, wherein the programmable row buffer circuit is coupled to the first filter circuit and the second filter circuit, the method further comprising: The intermediate results are then provided to the second filter circuit.

15. The method of claim 13, wherein the element-wise operation of performing the second input data in the element-wise mode comprises performing the element-wise operation using at least one of the first filter circuit or the second filter circuit.

16. The method of claim 12, wherein the convolution operation is one of a plurality of operations for implementing a machine learning model.

17. The method of claim 12, wherein the more plurality of modes includes a reduction mode, and wherein the method further includes reducing the rank of the tensor based on the first input data in the reduction mode.

18. An electronic device comprising: Memory for storing machine learning models; as well as A neural processor, the neural processor comprising: Multiple neural engine circuits, each of which is configured to perform a convolution operation on a first input data with one or more kernels to generate a first output; and A planar engine circuit, coupled to and configured to operate in parallel with the plurality of neural engine circuits, is capable of operating in one of two or more modes to generate a second output, the two or more modes including a pooling mode and an element-wise mode. The planar engine circuit includes a programmable row buffer circuit, wherein the programmable row buffer circuit is configured to store intermediate results generated by the planar engine circuit in the pooling mode, wherein the planar engine circuit is configured to bypass the storage of results generated by the planar engine circuit in the element-wise mode within the programmable row buffer circuit, and wherein: In the pooling mode, the planar engine circuit is configured to reduce the spatial size of a version of the second input data received by the planar engine circuit, the second input data corresponding to a version of the first output or the input data of the neural processor, and In the element-wise mode, the planar engine circuit is configured to perform an element-wise operation on the second input data, the second input data corresponding to the first output or a version of the input data of the neural processor; and A data processor circuit coupled to the plurality of neural engine circuits and the planar engine circuit, the data processor circuit being configured to buffer the second output for sending to the plurality of neural engine circuits.

19. The electronic device of claim 18, wherein the convolution operation is one of a plurality of operations for implementing the machine learning model.

20. A computer program product comprising a computer program that, when executed by a processor, causes the processor to perform the method according to any one of claims 12-17.

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