Memory cell and method of manufacturing the same

Abstract

A memory unit comprises an active component (10), electrodes (20a, 20b), a heating unit (30), and a phase change unit (40). The electrodes (20a, 20b) are coupled to the active component (10), and the electrodes (20a, 20b) and the active component (10) are located in the same layer. The heating unit (30) is formed above the electrodes (20a, 20b), and the heating unit (30) is coupled to the electrodes (20a, 20b). The phase change unit (40) is coupled to the heating unit (30), wherein the phase change unit (40) is formed above the active component (10), and the phase change unit (40) and the active component (10) are connected in parallel.

Description

Technical Field

[0001] The invention relates to a memory unit and a method for manufacturing the memory unit. Background Art

[0002] Flash memory is a non-volatile memory that retains its contents even when it lacks external power. Flash memory is composed of many memory cells. Conventional flash memory uses floating gate transistors as data storage cells, with the amount of charge stored on the floating gate determining the data storage state.

[0003] However, conventional flash memory has disadvantages such as high operating voltage, complex structure and difficulty in manufacturing, slow programming and reading speed, and low cycle life. Therefore, the industry is in urgent need of a novel flash memory that does not have the above disadvantages.

[0004] In recent years, memory devices that use phase change materials to store data have been developed. These memory devices store information by changing the resistance of the phase change material (e.g., high resistance to low resistance). Phase change material refers to a material that can transition between different phases (e.g., crystalline and amorphous). These different phases give the phase change material different resistance states, which are used to represent different values ​​of the stored data. When operating a memory cell, an electric current can be applied to increase the temperature of the memory device, thereby changing the phase of the phase change material. Summary of the Invention

[0005] In view of the above problems, the present invention discloses a memory unit and a method for manufacturing the memory unit. The memory unit can be used to prepare a flash memory with high density, simple structure, fast writing and reading speed and long cycle life.

[0006] The memory cell disclosed in the present invention includes an active component, two electrodes, two heating units, and a phase change unit. The electrodes are coupled to the active component and are located on the same layer as the active component. The heating units are coupled to the two electrodes, respectively. The phase change unit is coupled to the two heating units, wherein the phase change unit is formed above the active component and is connected in parallel with the active component.

[0007] The flash memory disclosed in the present invention includes a plurality of the above-mentioned memory units connected in series.

[0008] The present invention also discloses a method for manufacturing a memory unit, including: forming an active component; forming two electrodes coupled to the active component, with the electrodes and the active component located on the same layer; forming two heating units respectively located above the two electrodes, with the two heating units respectively coupled to the two electrodes; and forming a phase change unit above the active component, with the phase change unit coupled to the heating unit, and the phase change unit and the active component connected in parallel.

[0009] According to the memory cell manufacturing method disclosed in the present invention, the electrodes and active components are formed in the same dielectric layer, thereby simplifying the structure and manufacturing process of the memory cell. The phase change unit is connected in parallel with the active component, so the memory cell disclosed in the present invention can be applied to NAND type memory. The present invention further discloses a NAND type memory comprising a plurality of memory cells connected in series, which has a lower operating voltage and a higher write and read speed. In addition, in the flash memory of the prior art, floating gate transistors are mostly used, which are easily damaged by a larger operating voltage; in comparison, since the flash memory of the present invention has a lower operating voltage, it is less likely to damage the components in the memory, thereby increasing the service life of the memory.

[0010] The above description of the contents of the present disclosure and the following description of the embodiments are intended to demonstrate and explain the spirit and principles of the present invention, and to provide further explanation of the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 1 is a circuit diagram of a flash memory according to an embodiment of the present invention.

[0012] Figure 2 FIG. 1 is a schematic cross-sectional view of a memory cell according to a first embodiment of the present invention.

[0013] Figures 3 to 5 To form Figure 2 A cross-sectional diagram of the switches in a memory cell.

[0014] Figure 6 and Figure 7 To form Figure 2 Schematic cross-section of the heater in the memory cell.

[0015] Figure 8 and Figure 9 To form Figure 2 Schematic cross-section of the phase change cell in the memory cell.

[0016] Figure 10 A schematic cross-sectional view of a memory cell according to a second embodiment of the present invention.

[0017] Figure 11 and Figure 12 To form Figure 10Schematic cross-section of the heater in the memory cell.

[0018] Figure 13 and Figure 14 To form Figure 10 Schematic cross-section of the phase change cell in the memory cell.

[0019] Wherein, the reference numerals:

[0020] Memory unit 1, 1-1, 1-2, 1"

[0021] Switching transistors 11 and 12

[0022] Word lines WL0 to WL7

[0023] bit lines BL1 to BL3

[0024] Select control line CS

[0025] Switch control lines SSG, DSG

[0026] Substrate 100

[0027] Active Components 10

[0028] Source / drain 110, 120

[0029] Gate 130

[0030] Channel 140

[0031] Gate conductive layer 131

[0032] Gate metal layer 132

[0033] Gate spacer 133

[0034] First electrode 20a

[0035] Second electrode 20b

[0036] Heating material HM

[0037] Heating unit 30

[0038] Phase Change Material PCM

[0039] Phase change unit 40

[0040] Thermal insulation material IM

[0041] Thermal insulation unit 50

[0042] Dielectric layer DL, ILD

[0043] Through hole TH

[0044] First through groove G1

[0045] Second through groove G2

[0046] Horizontal width W1, W2 DETAILED DESCRIPTION

[0047] The following detailed description of the features and advantages of the present invention is provided in the following embodiments. The details are sufficient to enable any person skilled in the art to understand the technical content of the present invention and implement it accordingly. Furthermore, based on the disclosure of this specification, the claims, and the accompanying drawings, any person skilled in the art can readily understand the relevant objects and advantages of the present invention. The following examples further illustrate the concepts of the present invention but are not intended to limit the scope of the present invention in any way.

[0048] Spatially relative terms, such as "below," "above," "beneath," "over," and the like, are used to simplify describing the relationship of one component or structure to another component (or components) or structure (or structures) illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0049] Figure 1 This is a circuit diagram of a NAND type memory according to an embodiment of the present invention. The NAND type memory includes a plurality of memory cells 1, two switch transistors 11, 12, a plurality of word lines WL0 to WL7, a plurality of bit lines BL1 to BL3, a plurality of selection control lines CS, and two switch control lines SSG and DSG. These memory cells 1 are connected in series, and each memory cell includes an active component (such as a transistor) and a phase change component connected in parallel. The plurality of memory cells 1 connected in series are coupled to the drain / source of the control transistors 11 and 12. The above-mentioned control transistors and active components include N-type or P-type metal oxide semiconductor transistors MOS, but are not limited thereto. As long as the component can act as a switch, it can be the above-mentioned control transistor or active component.

[0050] The drain / source of switch transistor 11 is coupled to one of the select control lines CS, while the drain / source of switch transistor 12 is coupled to one of the bit lines (e.g., BL1). The gate of switch transistor 11 is coupled to switch control line SSG, while the gate of switch transistor 12 is coupled to switch control line DSG. The switching transistors 11 and 12 can be turned on or off by voltage signals on switch control lines SSG and DSG, thereby controlling the flow of current into and out of the multiple memory cells 1 connected in series. The active element of each memory cell 1 includes a gate, which is coupled to one of the multiple word lines WL0-WL7. Therefore, the voltage signals on each word line WL0-WL7 can be used to control whether current flows through the phase change element to write to and read from the memory cell 1.

[0051] Please refer to Figure 2 , is a schematic cross-sectional view of a memory cell according to a first embodiment of the present invention. In this embodiment, the memory cell 1 includes an active component 10, a first electrode 20a, a second electrode 20b, two heating units 30, and a phase change unit 40.

[0052] An active device 10 is formed on a substrate 100. The active device 10 is, for example, a transistor and includes a source / drain 110, a source / drain 120, and a gate 130. The source / drain 110 and 120 are located in doped regions of the substrate, while the gate 130 is disposed on the substrate 100 and located between the source / drain 110 and the source / drain 120. In some embodiments of the present invention, the substrate 100 further includes a shallow trench isolation (STI) structure to electrically isolate adjacent active devices 10. The substrate 100 may be made of, but not limited to, silicon or other semiconductor elements such as germanium or Group III-V elements. The STI structure may be made of, for example, silicon oxide, silicon nitride, silicon oxynitride, or other suitable electrically insulating materials.

[0053] In this embodiment, the gate 130 includes a gate conductive layer 131, a gate metal layer 132, and a gate spacer 133. Figure 2As shown, the gate metal layer 132 is disposed above the gate conductive layer 131, and the gate spacer 133 is disposed on the opposite side walls of the gate conductive layer 131 and on the opposite side walls of the gate metal layer 132. The gate conductive layer 131, for example, includes doped polysilicon. The gate metal layer 132, for example, includes titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi) or cobalt silicide (CoSi). By providing the gate metal layer 132 in contact with the gate conductive layer 131, the resistive load effect of the gate can be reduced, thereby improving the RC (resistance-capacitance) delay problem. The gate spacer 133 can be a single-layer structure or a multi-layer structure. In some embodiments, the gate spacer 133 includes oxide, nitride, oxynitride or a combination thereof. For example, in this embodiment, the gate spacer 133 includes a single layer of silicon oxide and a single layer of silicon nitride.

[0054] The first electrode 20a is coupled to the source / drain 110 of the active device 10, and the second electrode 20b is coupled to the source / drain 120 of the active device 10. The material of the first electrode 20a and the second electrode 20b includes tungsten (W), for example. The first electrode 20a and the second electrode 20b are located in the same layer as the gate 130 of the active device 10. Specifically, Figure 2 As shown, the gate 130 , the first electrode 20 a and the second electrode 20 b are all located in the same dielectric layer DL.

[0055] Two heating units 30 are formed on the first electrode 20a and the second electrode 20b, respectively, and are coupled to the first electrode 20a and the second electrode 20b, respectively. The heating units 30 may be made of, for example, titanium, tungsten (W), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), or tantalum aluminum nitride (TaAlN).

[0056] The phase change unit 40 is formed on the top surface of the dielectric layer DL and is located above the gate 130 of the active device 10. The phase change unit 40 is coupled to the two heating units 30. Specifically, the phase change unit 40 is located between the two heating units 30 and is coupled to the side surfaces of each of the two heating units 30. The material of the phase change unit 40 includes, for example, germanium antimony telluride (GST), nitrogen-doped germanium antimony telluride (nitrogen-doped GST), antimony telluride (Sb2Te), antimony germanium (GeSb), or indium-doped antimony telluride (In-doped Sb2Te).

[0057] Please refer to Figure 1 and Figure 2Whether current flows through the phase-change cell 40 for writing and reading can be controlled by controlling the voltage signals of the word lines WL0-WL7. Specifically, when an appropriate bias is applied to the gate conductive layer 131 via the word line, a channel 140 is formed between the source / drain 110 and the source / drain 120. As a result, the resistance of the active device 10 is lower than the resistance of the phase-change cell 40, and current can flow from the source / drain 110 to the source / drain 120 through the channel 140. Conversely, when no appropriate bias is applied to the gate conductive layer 131, no channel exists between the source / drain 110 and the source / drain 120. As a result, the resistance of the active device 10 is much higher than the resistance of the phase-change cell 40. At this time, current flows from the source / drain 110 through the first electrode 20a, the heating unit 30, the phase-change cell 40, the other heating unit 30, and the second electrode 20b to the source / drain 120. Accordingly, during writing, the phase change unit 40 is heated by ohmic heating, and the phase of the phase change unit 40 is switched between the crystalline state and the amorphous state by adjusting the current passing through the phase change layer and the cooling speed, thereby storing different values ​​of data.

[0058] The following instructions Figure 2 The manufacturing method of the memory cell 1 is described first. The formation of the electrode of the memory cell is described first. Please refer to Figures 3 to 5 , to form Figure 2 Schematic diagram of a cross section of the electrodes of the memory cell. A plurality of memory cells 1 connected in series are shown below.

[0059] First, the active device 10 is formed on the substrate 100 by conventional semiconductor processing. Figure 3 As shown, a dielectric layer DL is formed on the substrate 100 to cover the active device 10. The material of the dielectric layer DL includes, for example, an electrically insulating material such as silicon oxide, silicon carbide or silicon nitride. Figure 4 As shown, a portion of the dielectric layer DL is removed to form a plurality of through holes TH. Specifically, the dielectric layer DL can be removed by etching to form the through holes TH. The through holes TH expose the source / drain 110 or the source / drain 120 of the active device 10. Figure 3 and Figure 4 The two active components 10 on the left and right can be used as Figure 1 Switching transistors 11 and 12 of the NAND type memory.

[0060] like Figure 5As shown, a conductive material is filled in the through hole TH to form a first electrode 20a and a second electrode 20b. Specifically, a titanium film or a titanium nitride film can be first deposited on the sidewalls of the through hole TH as an adhesion layer, and then tungsten is deposited to fill the through hole TH. The conductive material filled in the through hole TH that exposes the source / drain 110 serves as the first electrode 20a of one of the memory cells, and the conductive material filled in the through hole TH that exposes the source / drain 120 serves as the second electrode 20b of the one of the memory cells. After the conductive material is filled, an additional chemical mechanical polishing process can be used to remove excess conductive material to flatten the top surfaces of the dielectric layer DL, the first electrode 20a, and the second electrode 20b.

[0061] In the case where multiple memory cells are connected in series, the first electrode 20a of one memory cell can share the second electrode 20b of another adjacent memory cell. Figure 5 The second electrode 20b of the leftmost memory cell 1-1 also serves as the first electrode 20a of the adjacent memory cell 1-2. In addition, the source / drain 120 of one memory cell can also serve as the source / drain 110 of another adjacent memory cell 1, for example Figure 5 The source / drain 120 of the leftmost memory cell 1 - 1 also serves as the source / drain 110 of the adjacent memory cell 1 - 2 .

[0062] Figure 6 and Figure 7 To form Figure 2 Schematic diagram of the cross section of the heating unit 30 of the memory unit. The heating material HM is formed above the first electrode 20a and the second electrode 20b. Specifically, as Figure 6 As shown, a heating material HM (such as titanium, titanium nitride, tantalum nitride, titanium aluminum nitride or aluminum nitride) may be deposited on the top surface of the dielectric layer DL and the top surfaces of the first electrode 20a and the second electrode 20b. Figure 7 As shown, the heating material HM may be patterned by using a lithography process and an etching process. After patterning, a portion of the heating material HM located on the top surface of the dielectric layer DL is removed, thereby forming a plurality of heating units 30.

[0063] Figure 8 and Figure 9 To form Figure 2 The phase change unit 40 is formed above the gate 130 of the active device 10. Specifically, as shown in FIG. Figure 8 As shown in FIG, a phase change material PCM is formed on the top surface of the dielectric layer DL. Figure 8As shown, the phase change material PCM can be patterned into a plurality of phase change units 40 by using lithography and etching. Alternatively, a chemical mechanical polishing method can be used to remove part of the phase change material PCM to form the phase change unit 40. Figure 9 As shown, the phase change unit 40 is formed between two adjacent heating units 30. The phase change unit 40 contacts the side of the heating unit 30, that is, the top surface of the phase change unit 40 and the top surface of the heating unit 30 are at the same level. Figure 9 In the embodiment, the active device 10 and the phase change unit 40 are connected to two nodes at both ends, and the first electrode 20a and the second electrode 20b serve as the two nodes, thereby implementing the parallel connection of the phase change unit 40 and the active device 10.

[0064] After forming the phase-change cell 40, another dielectric layer can be further formed over the dielectric layer ILD to cover the heating unit 30 and the phase-change cell 40. Subsequently, a through-hole can be formed in the dielectric layer through an etching process, and a metal material can be filled in the through-hole to form a conductive pillar. Aluminum or copper can also be further deposited over the dielectric layer to serve as a bit line.

[0065] Figure 10 A schematic cross-sectional view of a memory cell according to a second embodiment of the present invention. Since the second embodiment is similar to the first embodiment, the differences will be described below. In this embodiment, the memory cell 1" further includes two thermal insulation units 50, wherein the heating unit 30 may be a titanium nitride layer, and the thermal insulation unit 50 may be a tantalum nitride layer. The two thermal insulation units 50 are respectively formed above the two heating units 30, and the phase change unit 40 contacts the side surfaces of each of the two thermal insulation units 50. The maximum line width of the thermal insulation unit 50 is smaller than the minimum line width of the heating unit 30, and the phase change unit 40 contacts the top surface and side surfaces of the heating unit 30. The thermal insulation unit 50 helps to prevent heat energy from escaping from the side of the phase change unit 40 into the dielectric layer DL when the heating unit 30 heats the phase change unit 40.

[0066] The following instructions Figure 10 A method for manufacturing a memory cell 1". Figure 11 and Figure 12 To form Figure 10 Schematic diagram of the cross section of the thermal insulation unit 50 of the memory cell. Below, a plurality of memory cells 1 are shown to be connected in series. Figures 2 to 7 The active element 10, the first electrode 20a, the second electrode 20b and the heating unit 30 of the memory cell 1 are formed by the steps. Figure 11 As shown, a thermal insulation material IM is formed on the top surface of the dielectric layer DL and the top surface of the heating unit 30. Figure 12As shown, the thermal insulation material IM can be patterned by using a lithography process and an etching process. After patterning, excess thermal insulation material IM on the top surface of the dielectric layer DL is removed, thereby forming a plurality of thermal insulation units 50.

[0067] In addition, if Figure 12 As shown, in each memory cell 1″, the heating material HM is patterned to form not only the heating unit 30 but also a first through-groove G1 between the two heating units 30. The first through-groove G1 is located above the gate 130 of the active component 10, and the first through-groove G1 exposes the dielectric layer DL. Furthermore, after patterning, the thermal insulation material IM is patterned to form not only the thermal insulation unit 50 but also a second through-groove G2 above the first through-groove G1. The second through-groove G2 is connected to the first through-groove G1, and the horizontal width W2 of the second through-groove G2 is greater than the horizontal width W1 of the first through-groove G1. In this way, the first through-groove G1 and the second through-groove G2 together form a receiving space that is wide at the top and narrow at the bottom.

[0068] Figure 13 and Figure 14 To form Figure 10 Schematic diagram of the cross section of the phase change unit 40 of the memory cell. Phase change material PCM is formed on the top surface of the dielectric layer DL. Figure 13 As shown in FIG, the phase change material PCM can be patterned into a plurality of phase change units 40 by using lithography and etching. Figure 14 As shown, for example, chemical mechanical polishing is used to remove a portion of the phase change material (PCM) to form a phase change unit 40 between two adjacent heating units 30, with the top surface of the phase change unit 40 being flush with the top surface of the thermal insulation unit 50. Because the phase change unit 40 is filled within the first through-groove G1 and the second through-groove G2, the phase change unit 40 also has a shape that is wide at the top and narrow at the bottom.

[0069] When the PCM is planarized by chemical mechanical polishing, the thermal insulation unit 50 can serve as a stop layer of the chemical mechanical polishing process, thereby preventing the heating unit 30 from being over-polished by the polishing pad and becoming too thin.

[0070] In summary, according to the manufacturing method of the memory cell disclosed in the present invention, the electrodes and the active components are formed in the same dielectric layer, thereby simplifying the structure and manufacturing process of the memory cell. The phase change unit is connected in parallel with the active component, so the memory cell disclosed in the present invention can be applied to NAND type memory. The present invention further discloses a NAND type memory comprising a plurality of memory cells connected in series, which has a lower operating voltage and a higher write and read speed. In addition, floating gate transistors are mostly used in flash memories of the prior art, which are easily damaged by higher operating voltages; in comparison, since the flash memory of the present invention has a lower operating voltage, it is less likely to damage the components in the memory, thereby increasing the service life of the memory.

Claims

1. A memory unit comprising: Active components; Two electrodes are coupled to the active component, and the two electrodes and the active component are located on the same layer; Two heating units, wherein the two heating units are respectively coupled to the two electrodes, and the top surfaces of the two heating units are located at the same horizontal height; A phase change unit is coupled to the two heating units, the phase change unit is formed above the active component, the phase change unit is connected in parallel with the active component, and the phase change unit is coupled to the side surfaces of the two heating units; as well as Two heat insulation units are respectively formed above the two heating units, and the phase change unit contacts respective sides of the two heat insulation units.

2. The memory cell as claimed in claim 1, wherein the two electrodes are respectively coupled to the source and drain of the active device, the two electrodes and the gate of the active device are located in the same layer, and the phase change unit is formed above the gate of the active device. 3 . The memory cell according to claim 1 , wherein the phase change unit has a shape that is wide at the top and narrow at the bottom.

4. A NAND memory comprising a plurality of memory cells as claimed in claim 1 connected in series.

5. A method for manufacturing a memory cell, comprising: forming active components; forming two electrodes coupled to the active component, wherein the two electrodes and the active component are located on the same layer; forming two heating units respectively located above the two electrodes, and the two heating units are respectively coupled to the two electrodes, with top surfaces of the two heating units being located at the same level; and forming a phase change unit above the active component, wherein the phase change unit is coupled to the two heating units, and the phase change unit is connected in parallel with the active component; The forming of the two electrodes includes: forming a dielectric layer covering the active component; removing a portion of the dielectric layer to form two through holes to expose the source and drain of the active component respectively; and forming the two electrodes in the two through holes respectively; forming the two heating units and the phase change unit above the dielectric layer, with the phase change unit contacting respective side surfaces of the two heating units; Before forming the phase change unit, forming two thermal insulation units respectively located above the two heating units; and The phase change unit is formed above the dielectric layer, and the phase change unit contacts the top surface and side surface of each of the two heating units and contacts the side surface of each of the two thermal insulation units.

6. The method for manufacturing a memory cell as described in claim 5, wherein a first through-groove is formed between the two heating units, the first through-groove being located above the active component and exposing the dielectric layer, a second through-groove communicating with the first through-groove is formed between the two thermal insulation units, the second through-groove being located above the first through-groove, the horizontal width of the second through-groove being greater than the horizontal width of the first through-groove, and the phase change unit is formed within the first through-groove and the second through-groove.

7. The method for manufacturing a memory cell as claimed in claim 5, wherein the two electrodes are respectively coupled to the source and drain of the active device, the two electrodes and the gate of the active device are located in the same layer, and the phase change unit is formed above the gate of the active device.

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