Method and apparatus for processing a substrate

Abstract

The present invention provides methods and apparatus for processing substrates. For example, the method may include depositing a first metal layer on a first substrate; depositing a second metal layer on top of the first metal layer; depositing a third metal layer on the second substrate; depositing a fourth metal layer on top of the third metal layer; and contacting the second material layer with the fourth material layer under conditions sufficient to bond the first substrate to the second substrate through a diffusion layer, the diffusion layer being formed by diffusion of the first metal layer through a portion of the second metal layer and diffusion of the third metal layer through a portion of the fourth metal layer.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to methods and apparatus for processing substrates, and more particularly to methods and apparatus for high performance chip-level thermally conductive interface formation.

[0002] Related technical notes

[0003] Methods and apparatus are known for connecting a cooling system to a chip (an integrated chip (IC)) such as a high-power chip, a system on chip (SoC), or a chiplet. For example, during package-level assembly of the chip, heat can be conducted from the chip to the cooling system using several layers of one or more suitable thermal interface materials (TIMs) such as solder or indium-based materials, heat spreaders, cooling plates (heat sinks), and / or spacers (metals). Conventional cooling systems can include, for example, remote cooling chips such as thermoelectrically cooled ICs or microelectromechanical systems (MEMS) microfluidic conduits to improve heat dissipation capabilities.

[0004] However, the inventors have discovered that methods and apparatus for high performance chip-level thermally conductive interface formation during substrate (wafer) assembly can improve thermal conductivity from the chip to the cooling system. Summary of the invention

[0005] Methods and apparatus for processing substrates are provided herein. In some embodiments, the method may include depositing a first metal layer on a first substrate; depositing a second metal layer on top of the first metal layer; depositing a third metal layer on the second substrate; depositing a fourth metal layer on top of the third metal layer; and contacting the second metal layer with the fourth metal layer under conditions sufficient to bond the first substrate to the second substrate through a diffusion layer, the diffusion layer being formed by diffusion of the first metal layer through a portion of the second metal layer and diffusion of the third metal layer through a portion of the fourth metal layer.

[0006] According to at least some embodiments, a non-transitory computer-readable storage medium is provided having instructions stored thereon, which, when executed by a processor, perform a method for processing a substrate, the method comprising depositing a first metal layer on a first substrate; depositing a second metal layer on top of the first metal layer; depositing a third metal layer on the second substrate; depositing a fourth metal layer on top of the third metal layer; and contacting the second metal layer with the fourth metal layer under conditions sufficient to bond the first substrate to the second substrate via a diffusion layer, the diffusion layer being formed by diffusion of the first metal layer through a portion of the second metal layer and diffusion of the third metal layer through a portion of the fourth metal layer.

[0007] According to at least some embodiments, an integrated circuit is provided, the integrated circuit having a first metal layer disposed thereon; a second metal layer, the second metal layer being disposed on the first metal layer and different from the first metal layer; a substrate having a third metal layer disposed thereon; a fourth metal layer, the fourth metal layer being disposed on the third metal layer and different from the third metal layer; and an interlayer comprising a portion of the first metal layer disposed between the second metal layer and the fourth metal layer and a portion of the third metal layer disposed between the second metal layer and the fourth metal layer.

[0008] Other and further embodiments of the disclosure are described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The embodiments of the present disclosure briefly summarized above and discussed in more detail below can be understood with reference to the illustrative embodiments of the present disclosure depicted in the accompanying drawings. However, the accompanying drawings illustrate only typical embodiments of the present disclosure and therefore should not be considered to limit the scope of the present disclosure, as the present disclosure may admit to other equally effective embodiments.

[0011] Figure 1 is a flow chart of a method for processing a substrate according to at least some embodiments of the present disclosure.

[0012] Figure 2 is a schematic diagram of an apparatus for processing a substrate according to at least some embodiments of the present disclosure.

[0013] FIG. 3A to FIG. 3C For the purpose of describing at least some embodiments of the present disclosure Figure 1 An illustration of the processing order of the method.

[0014] FIG. 4A to FIG. 4D For the purpose of describing at least some embodiments of the present disclosure Figure 1 An illustration of the processing order of the method.

[0015] FIG. 5A to FIG. 5C For the purpose of describing at least some embodiments of the present disclosure Figure 1 An illustration of the processing order of the method.

[0016] Figure 6 is an illustration of a substrate according to at least some embodiments of the present disclosure.

[0017] To facilitate understanding, the same reference numerals have been used, where possible, to designate the same elements common to the drawings. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation. DETAILED DESCRIPTION

[0018] Embodiments of methods and apparatus for processing substrates, thermal module assemblies, or the like are provided herein. For example, the methods described herein can be used for high-performance chip-level thermal conductive interface formation. More specifically, one or more suitable metals (e.g., copper) can be used, for example, to bond two substrates, such as bonding a cooling module substrate to a chiplet and / or a chip system (SoC) to form a metal interlayer. The copper can be covered by (e.g.) one or more suitable passivation metals. Copper atoms infiltrate the passivation metal under the bonding conditions described herein to form a copper interlayer to bond the two substrates. Compared to conventional bonding methods using one or more thermal interface materials (TIMs), the bonding methods described herein can provide about ten times (or more) of thermal conduction, can significantly reduce θJc (thermal resistance from junction to housing), can have a relatively small footprint, can have an extremely thin bond line thickness (BLT), and can be at relatively low temperatures (e.g., <250°C) and at relatively low pressures (e.g., (~0.1 kg / cm 2 )) and is executed in a relatively short time (~5 minutes).

[0019] According to at least some embodiments of the present disclosure, Figure 1 is a flow chart of a method 100 for processing a substrate, and Figure 2 A tool 200 (or device) can be used to perform the method 100 .

[0020] The method 100 may be performed in a tool 200 including any suitable process chamber configured to perform one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), and / or atomic layer deposition (ALD) such as plasma enhanced atomic layer deposition (ALD) or thermal ALD (e.g., without plasma formation). Exemplary processing systems that may be used to perform the inventive methods disclosed herein may include, but are not limited to, or Line processing system and Plus or SIP Those processing systems in PVD process chambers, such processing systems and process chambers are available from Applied Materials, Inc., of Santa Clara, Calif. Other process chambers, including those from other manufacturers, may also be used as appropriate in conjunction with the teachings provided herein.

[0021] The tool 200 may be implemented in a single process chamber, which may be provided in a standalone configuration or as part of a cluster tool, such as described below with reference to Figure 2 An integrated tool (hereinafter referred to as tool 200) is described. Examples of integrated tools include those available from Applied Materials, Inc. of Santa Clara, California. and and The methods described herein may be practiced using other cluster tools with suitable process chambers coupled thereto, or in other suitable process chambers. For example, in some embodiments, the inventive methods discussed above may be performed in an integrated tool such that there are limited or no vacuum breaks between processing steps. For example, reducing vacuum breaks may limit or prevent contamination (e.g., oxidation) of the tungsten liner layer or other portions of the substrate.

[0022] The integrated tool includes a vacuum sealed processing platform (processing platform 201), a factory interface 204, and a system controller 202. The processing platform 201 includes a plurality of process chambers such as 214A, 214B, 214C, and 214D, which are operatively coupled to a vacuum substrate transfer chamber (transfer chamber 203). The factory interface 204 is connected to a vacuum substrate transfer chamber (transfer chamber 203) through one or more load lock chambers such as Figure 2 Two load lock chambers 206A and 206B) shown in FIG. 1 are operatively coupled to the transfer chamber 203 .

[0023] In some embodiments, the factory interface 204 includes at least one docking station 207 and at least one factory interface robot 238 to facilitate the transfer of one or more semiconductor substrates (wafers). The docking station 207 is configured to accommodate one or more front opening unified pods (FOUPs). Figure 2 205A, 205B, 205C, and 205D. The factory interface robot 238 is configured to transfer substrates from the factory interface 204 to the processing platform 201 through load lock chambers such as 206A and 206B. Each of the load lock chambers 206A and 206B has a first port coupled to the factory interface 204 and a second port coupled to the transfer chamber 203. The load lock chambers 206A and 206B are coupled to a pressure control system (not shown) that pumps down and vents the load lock chambers 206A and 206B to facilitate the transfer of substrates between the vacuum environment of the transfer chamber 203 and the substantially ambient (e.g., atmospheric) environment of the factory interface 204. The transfer chamber 203 has a vacuum robot 242 disposed within the transfer chamber 203. The vacuum robot 242 can transfer the substrate 221 between the load lock chambers 206A and 206B and the process chambers 214A, 214B, 214C, and 214D.

[0024] In some embodiments, process chambers 214A, 214B, 214C, and 214D are coupled to transfer chamber 203. Process chambers 214A, 214B, 214C, and 214D include at least ALD chambers, CVD chambers, PVD chambers, electron beam deposition chambers, and / or electroplating, electroless (EEP) deposition chambers.

[0025] In some embodiments, one or more optional maintenance chambers (shown as 216A and 216B) may be coupled to the transfer chamber 203. The maintenance chambers 216A and 216B may be configured to perform other substrate processes such as degassing, bonding, chemical mechanical polishing (CMP), wafer dicing, etching, plasma dicing, orientation, substrate metrology, cooling, etc.

[0026] The system controller 202 controls the operation of the tool 200 using direct control of the process chambers 214A, 214B, 214C, and 214D, or alternatively by controlling computers (or controllers) associated with the process chambers 214A, 214B, 214C, and 214D and the tool 200. In operation, the system controller 202 enables data to be collected from the various chambers and systems and obtains feedback to optimize the performance of the tool 200. The system controller 202 generally includes a central processing unit (CPU) 230, a memory 234, and support circuits 232. The CPU 230 can be any form of general-purpose computer processor that can be used in an industrial environment. The support circuits 232 are conventionally coupled to the CPU 230 and can include caches, clock circuits, input / output subsystems, power supplies, etc. Software routines such as the processing methods described above may be stored in memory 234 (e.g., a non-transitory computer-readable storage medium) and, when executed by CPU 230, transform the CPU into a special-purpose computer (system controller 202). Software routines may also be stored and / or executed by a second controller (not shown) located remotely from tool 200.

[0027] Continue to refer Figure 1 , one or more substrates may be initially loaded into, for example, 205A, 205B, 205C, and 205D ( Figure 3A) in one or more of the four FOUPs of the FOUP 205A. For example, in at least some embodiments, a cooling module substrate 300 (wafer) can be loaded into the FOUP 205A. The substrate 300 can include a layer 302, and a chip-level cooling system 304 (or a thermoelectric cooling module) can be disposed on the layer 302. The layer 302 can be made of one or more materials suitable for disposing the chip-level cooling system 304 on it. For example, in at least some embodiments, the layer 302 can be formed of silicon, glass, or a metal substrate made of copper, stainless steel, and / or aluminum.

[0028] Once loaded, the factory interface robot 238 may transfer the substrate 300 from the factory interface 204 through, for example, the load lock chamber 206A to the processing platform 201. The vacuum robot 242 may transfer the substrate 300 from the load lock chamber 206A to and from one or more of the process chambers 214A to 214D and / or the maintenance chambers 216A and 216B.

[0029] For example, in at least some embodiments, an optional dielectric material layer (eg, dielectric layer 306) may be deposited on chip-level cooling system 304 ( Figure 3B ). The dielectric layer 306 is configured to prevent copper from diffusing into the chip-level cooling system 304 (or other adjacent IC layers). The dielectric layer 306 may be deposited using one or more suitable deposition processes (e.g., CVD, ALD, PVD, and / or other suitable deposition processes). For example, in at least some embodiments, the dielectric layer 306 may be deposited using CVD and / or ALD. The dielectric layer 306 may be formed using one or more suitable dielectric materials, including but not limited to oxides, silicon oxides, silicon nitrides, silicon carbonitrides, or similar dielectric materials. For example, in at least some embodiments, the dielectric layer 306 may be formed using silicon oxide. The dielectric layer 306 may have a thickness of about 0.05 μm to about 1 μm.

[0030] Subsequently, at 102, a first layer 308 ( Figure 3B) may be deposited on a substrate 300 (e.g., a first substrate). More specifically, in at least some embodiments, when used, the first metal layer 308 may be deposited on the dielectric layer 306. Alternatively, in at least some embodiments, the first metal layer 308 may be deposited directly on the chip-level cooling system 304 (e.g., when the dielectric layer 306 is not used). One or more suitable metals that may be deposited on the substrate 300 may include, but are not limited to, copper, nickel, and the like. For example, in at least some embodiments, the first metal layer 308 may be copper. The first metal layer 308 may be deposited using one or more suitable deposition processes, including, but not limited to, PVD, ALD, CVD, electroplating, electroless (EEP) deposition, and / or other suitable deposition processes. For example, in at least some embodiments, the first metal layer 308 may be deposited using PVD, CVD, and / or EEP deposition. The first metal layer 308 may have a thickness of about 0.05 μm to about 10 μm.

[0031] Subsequently, at 104, a second layer 310 of one or more suitable metals may be deposited on top of the first metal layer 308 and may be configured as a passivation layer. The one or more suitable metals may include, but are not limited to, silver, palladium, platinum, gold, and / or other suitable metals. The inventors have found that when such metals are used, conventional TIM materials such as solder or indium-based materials are not required, but such conventional TIM materials may also be used if desired. For example, in at least some embodiments, palladium may be used to form the second layer 310. The second metal layer 310 may be formed using one or more suitable deposition processes, including, but not limited to, ALD, PVD, CVD, electron beam deposition, EEP, and / or other suitable deposition processes. For example, in at least some embodiments, a passivation layer may be formed using PVD, CVD, electron beam deposition, and / or EEP. The second metal layer 310 may have a thickness of about 0.001 μm to about 0.05 μm.

[0032] One or more additional substrates may be loaded onto the substrates such as 205A, 205B, 205C, and 205D ( Figure 4A ) in one or more of the four FOUPs of 205B. For example, in at least some embodiments, a substrate 400 (wafer) can be loaded into FOUP 205B. Substrate 400 can include layer 402, and chiplets 404 (or SoCs or high-power ICs) can be disposed on layer 402. Similar to layer 302, layer 402 can be made of one or more materials suitable for disposing chiplets 404 thereon. For example, in at least some embodiments, layer 402 can be formed using silicon.

[0033] Once loaded, the factory interface robot 238 may transfer the substrate 400 from the factory interface 204 through, for example, the load lock chamber 206B to the processing platform 201. The vacuum robot 242 may transfer the substrate 400 from the load lock chamber 206B to and from one or more of the process chambers 214A to 214D and / or the maintenance chambers 216A and 216B.

[0034] In at least some embodiments, one or more hybrid bonding interfaces 412 such as copper oxide (or other conventional bonding interfaces) are formed on the chiplet 404 ( Figure 4B ).

[0035] Subsequently, layer 402 ( Figure 4C ). Suitable removal processes that can be used to remove layer 402 may include, but are not limited to, substrate cutting processes including hydrogen or invisible laser processing or vector field mapping (VFM), CMP processes, or etching processes. For example, in at least some embodiments, substrate 400 may be transferred to maintenance chamber 216A, which may be configured as an etching chamber and may be configured to remove layer 402.

[0036] After removing layer 402, a carrier substrate 414 may be deposited on hybrid bonding interface 412 using, for example, one or more of process chambers 214A-214D (eg, PVD, CVD, ALD, etc.). Figure 4C ). The carrier substrate 414 may be formed using one or more suitable materials configured to protect the chiplets 404 when the substrate 400 is transferred to or removed from the process chambers 214A to 214D and / or the maintenance chambers 216A and 216B for processing. For example, in at least some embodiments, the carrier substrate 414 may be made of silicon with an adhesive, a passive silicon interposer or a functional silicon interposer, glass with an adhesive, etc.

[0037] Then, as mentioned above Figure 3B As described, in at least some embodiments, an optional dielectric layer 406 may be deposited on the chiplet 404 ( Figure 4D). As noted above, dielectric layer 406 is configured to prevent copper from diffusing into chiplet 404 (or other adjacent IC layers). Dielectric layer 406 may be deposited using one or more suitable deposition processes (e.g., CVD, ALD, PVD, and / or other suitable deposition processes). For example, in at least some embodiments, dielectric layer 406 may be deposited using CVD and / or ALD. Dielectric layer 406 may be formed using one or more suitable dielectric materials, including, but not limited to, silicon oxide, silicon nitride, or similar dielectric materials. For example, in at least some embodiments, dielectric layer 406 may be formed using silicon oxide. Dielectric layer 406 may have a thickness of about 0.05 μm to about 1 μm.

[0038] Subsequently, in a manner similar to 102, at 106, a third layer 408 of one or more suitable metals may be deposited on substrate 400 (e.g., a second substrate). More specifically, in at least some embodiments, when used, third metal layer 408 may be deposited on dielectric layer 406. Alternatively, in at least some embodiments, third metal layer 408 may be deposited directly on chiplet 404 (e.g., when dielectric layer 406 is not used). One or more suitable metals that may be deposited on substrate 400 may include, but are not limited to, copper, nickel, and the like. For example, in at least some embodiments, third metal layer 408 may be copper. Third metal layer 408 may be deposited using one or more suitable deposition processes, including, but not limited to, PVD, ALD, CVD, electroplating, electroless (EEP) deposition, and / or other suitable deposition processes. For example, in at least some embodiments, third metal layer 408 may be deposited using PVD, CVD, and / or EEP deposition. Third metal layer 408 may have a thickness of about 0.05 μm to about 10 μm.

[0039] Subsequently, at 108, a fourth layer 410 of one or more suitable metals may be deposited on top of the third metal layer 408 and may be configured as a passivation layer. The one or more suitable metals may include, but are not limited to, silver, palladium, platinum, gold, and / or other suitable metals. As noted above, the inventors have found that when such metals are used, conventional TIM materials such as solder or indium-based materials are not required, but such conventional TIM materials may also be used if desired. For example, in at least some embodiments, palladium may be used to form the fourth layer 410. The fourth metal layer 410 may be formed using one or more suitable deposition processes, including, but not limited to, ALD, PVD, CVD, electron beam deposition, EEP, and / or other suitable deposition processes. For example, in at least some embodiments, a passivation layer may be formed using PVD, CVD, electron beam deposition, and / or EEP. The fourth metal layer 410 may have a thickness of about 0.001 μm to about 0.05 μm.

[0040] Subsequently, at 110, the second metal layer 310 (e.g., the second metal layer) is brought into contact with the fourth metal layer 410 (e.g., the fourth metal layer) under conditions sufficient to bond the substrate 300 (e.g., the first substrate) to the substrate 400 (e.g., the second substrate) through the diffusion layer 500 (e.g., Figure 5A ). More specifically, diffusion layer 500 is formed by diffusion of first metal layer 308 through (indicated by directional arrow 502) a portion of second metal layer 310 and diffusion of third metal layer 408 through a portion of fourth metal layer 410. Thermocompression bonding, fusion bonding, and / or post-annealing processes are suitable processes for diffusing a portion of first metal layer 308 through second metal layer 310 and diffusing a portion of third metal layer 408 through fourth layer 410, thereby bonding substrate 300 to substrate 400.

[0041] In at least some embodiments, the substrate 300 and the substrate 400 may be transferred to one or more of the process chambers 214A to 241D and / or one or more of the maintenance chambers 216A and / or 216B. For example, in at least some embodiments, the maintenance chamber 216B may be configured to bond the substrates to each other. Alternatively or additionally, the substrate 300 and the substrate 400 may be transferred from the tool 200 and transferred to another process chamber or multiple process chambers configured to bond the substrate 300 to the substrate 400.

[0042] The inventors have found that using the aforementioned metals for the first metal layer 308 and the second metal layer 310 (e.g., copper or nickel for diffusion metal) and for the third metal layer 408 and the fourth metal layer 410 (e.g., palladium for passivation metal) can allow the substrate 300 and the substrate 400 to be bonded at a relatively low temperature, at a relatively low pressure, and in a relatively short time. For example, in at least some embodiments (e.g., the first metal layer and the third metal layer are copper and the second metal layer and the fourth metal layer are one of silver, palladium, platinum, and gold), the temperature at which the substrate 300 and the substrate 400 can be bonded to each other can be about 250° C. Similarly, in such embodiments, the pressure at which the substrate 300 and the substrate 400 can be bonded to each other can be about 0.1 kg / cm 2 Likewise, in such embodiments, the time required for the substrate 300 and the substrate 400 to be bonded to each other may be about 1 minute to about 30 minutes. For example, in some embodiments, the time required for the substrate 300 to be bonded to the substrate 400 may be about 5 minutes.

[0043] Subsequently, in at least some embodiments, layer 302 may be removed using, for example, one of a substrate cutting process including hydrogen or invisible laser processing or VFM, a CMP process, or an etching process. Figure 5B). For example, in at least some embodiments, layer 302 can be transferred to maintenance chamber 216A, which can be configured as an etching chamber and can be configured to remove layer 302. In addition, carrier substrate 414 can be removed using one or more suitable removal processes ( Figure 5C ). For example, in at least some embodiments, the carrier substrate 414 may be removed using laser and blade cutting and / or plasma cutting.

[0044] After removing the layer 302 and the carrier substrate 414 from the substrate 300 and the substrate 400, respectively, the chip-level cooling system 304 and the chiplet 404 may be connected to one or more other modules ( Figure 6 ). For example, in at least some embodiments, the chip-level cooling system 304 of the substrate 300 can be connected to one or more suitable cooling systems 602. For example, the chip-level cooling system 304 can be connected to a MEMS including one or more air-cooled exchangers. Such devices can include piezoelectric stack actuators, synthetic nozzles, stirrers, scatterers (e.g., fins), heat sinks, etc. Similarly, the hybrid bonding interface 412 connected to the chiplet 404 can be connected to an insert 604, another cooling system 606, a power delivery system 608, etc.

[0045] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.

Claims

1. A method for processing a substrate, comprising the following steps: depositing a first metal layer on a first substrate; depositing a second metal layer atop the first metal layer; depositing a third metal layer on the second substrate; depositing a fourth metal layer on top of the third metal layer; as well as bringing the second metal layer into contact with the fourth metal layer under conditions sufficient to bond the first substrate to the second substrate via a diffusion layer formed by diffusion of the first metal layer through a portion of the second metal layer and diffusion of the third metal layer through a portion of the fourth metal layer, wherein the first substrate comprises a cooling module having the first metal layer deposited thereon, wherein the second substrate comprises at least one of an integrated chip or a system on a chip having the third metal layer deposited thereon, and wherein the method further comprises: before depositing the third metal layer on the second substrate, transferring the at least one of the integrated chip or the system on chip from the second substrate to a carrier substrate; as well as After bonding the first substrate to the second substrate, the first substrate is removed from the cooling module, and the carrier substrate is removed from the at least one of the integrated chip or the system on chip.

2. The method as claimed in claim 1 further comprises: before depositing the first metal layer on the first substrate and depositing the third metal layer on the second substrate, depositing a dielectric material layer on the first substrate and the second substrate, the dielectric material layer comprising at least one of silicon oxide, silicon nitride or silicon carbonitride.

3. The method of any one of claims 1 or 2, wherein the deposition of the dielectric material layer is performed using one of chemical vapor deposition or atomic layer deposition.

4. The method of any one of claims 1 or 2, wherein the deposition of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer is performed using one of physical vapor deposition, chemical vapor deposition, electron beam deposition or electroplating, electroless deposition.

5. The method of claim 1, further comprising: wherein the first metal layer and the third metal layer are at least one of copper or nickel; and The second metal layer and the fourth metal layer are at least one of silver, palladium, platinum or gold.

6. The method of claim 1, wherein the first substrate and the second substrate are made of at least one of silicon, glass, copper, stainless steel, or aluminum.

7. The method of any one of claims 1, 2, 5, and 6, wherein removing the first substrate from the cooling module and removing the second substrate from the at least one of the integrated chip or the system on chip are performed using at least one of hydrogen or invisible laser processing, vector field mapping (VFM) substrate cutting, chemical mechanical polishing, or etching, and Wherein removing the carrier substrate from the at least one of the integrated chip or the system on chip is performed using at least one of laser and blade cutting or plasma cutting.

8. A non-transitory computer readable storage medium having stored thereon instructions which, when executed by a processor, perform a method for processing a substrate, the method comprising: depositing a first metal layer on a first substrate; depositing a second metal layer atop the first metal layer; depositing a third metal layer on the second substrate; depositing a fourth metal layer on top of the third metal layer; as well as bringing the second metal layer into contact with the fourth metal layer under conditions sufficient to bond the first substrate to the second substrate via a diffusion layer formed by diffusion of the first metal layer through a portion of the second metal layer and diffusion of the third metal layer through a portion of the fourth metal layer, wherein the first substrate comprises a cooling module having the first metal layer deposited thereon, wherein the second substrate comprises at least one of an integrated chip or a system on a chip having the third metal layer deposited thereon, and wherein the method further comprises: before depositing the third metal layer on the second substrate, transferring the at least one of the integrated chip or the system on chip from the second substrate to a carrier substrate; as well as After bonding the first substrate to the second substrate, the first substrate is removed from the cooling module, and the carrier substrate is removed from the at least one of the integrated chip or the system on chip.

9. The non-transitory computer-readable storage medium of claim 8, further comprising: before depositing the first metal layer on the first substrate and depositing the third metal layer on the second substrate, depositing a dielectric material layer on the first substrate and the second substrate, the dielectric material layer comprising at least one of silicon oxide, silicon nitride or silicon carbonitride.

10. The non-transitory computer readable storage medium of any one of claims 8 or 9, wherein the deposition of the dielectric material layer is performed using one of chemical vapor deposition or atomic layer deposition.

11. The non-transitory computer-readable storage medium of any one of claims 8 or 9, wherein the deposition of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer is performed using one of physical vapor deposition, chemical vapor deposition, electron beam deposition, or electroplating, and electroless deposition.

12. The non-transitory computer-readable storage medium of claim 8, further comprising: wherein the first metal layer and the third metal layer are at least one of copper or nickel; and The second metal layer and the fourth metal layer are at least one of silver, palladium, platinum or gold.

13. The non-transitory computer-readable storage medium of claim 8, wherein the first substrate and the second substrate are made of at least one of silicon, glass, copper, stainless steel, or aluminum.

14. The non-transitory computer readable storage medium of any one of claims 8, 9, 12, and 13, wherein removing the first substrate from the cooling module and removing the second substrate from the at least one of the integrated chip or the system on chip are performed using at least one of hydrogen or invisible laser processing, vector field mapping (VFM) substrate cutting, chemical mechanical polishing, or etching, and Wherein removing the carrier substrate from the at least one of the integrated chip or the system on chip is performed using at least one of laser and blade cutting or plasma cutting.

15. A substrate, comprising: an integrated circuit having a first metal layer disposed thereon; a second metal layer, the second metal layer being disposed on the first metal layer and being different from the first metal layer; a substrate on which a third metal layer is disposed; a fourth metal layer, the fourth metal layer being disposed on the third metal layer and being different from the third metal layer; as well as an interlayer, the interlayer comprising a portion of the first metal layer disposed between the second metal layer and the fourth metal layer and a portion of the third metal layer disposed between the second metal layer and the fourth metal layer, A layer of dielectric material is deposited on the first metal layer, and a layer of dielectric material is deposited on the integrated circuit.

16. The substrate of any one of claims 15, wherein the dielectric material layer deposited on the first metal layer and the dielectric material layer deposited on the integrated circuit are at least one of silicon oxide, silicon nitride or silicon carbonitride. 17 . The substrate of claim 15 , wherein the first metal layer and the third metal layer are at least one of copper or nickel, and the second metal layer and the fourth metal layer are at least one of silver, palladium, platinum or gold.

Images